From patchwork Tue Jul 24 18:30:02 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marcus Folkesson X-Patchwork-Id: 10542957 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 866DB1805 for ; Tue, 24 Jul 2018 18:52:59 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 677F920182 for ; Tue, 24 Jul 2018 18:52:59 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 59B9821FAD; Tue, 24 Jul 2018 18:52:59 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.8 required=2.0 tests=BAYES_00,DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED,FREEMAIL_FROM,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id B8A6820182 for ; Tue, 24 Jul 2018 18:52:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2388434AbeGXUAq (ORCPT ); Tue, 24 Jul 2018 16:00:46 -0400 Received: from mail-lj1-f194.google.com ([209.85.208.194]:40413 "EHLO mail-lj1-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2388366AbeGXUAp (ORCPT ); Tue, 24 Jul 2018 16:00:45 -0400 Received: by mail-lj1-f194.google.com with SMTP id j19-v6so4504094ljc.7; Tue, 24 Jul 2018 11:52:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id; bh=PQMcMtbMYDPgR9+wRPXfJSgsCWHFDDomSfgNo4aUlK4=; b=tvoyzAM0XFSkvaj+zuERxttL3qzkC9OFYjCUpsAhfqU2IgYILSp6bjsvZbtDlEtHHQ LDBvSz5X/MhIhZoWwyArIa1UvJhgIJNBJIc0d30wyzq8NMxrklGQpgKhdeNstbqNN3wX 5vFfd0j3Eq2O2U8KQB69vWnknDxejTUGH1Vnfwb2Uy9v5Ruen4oLY2vOlcnt4Tez0aAU xVYvSDj3Iak+CFs3aUecGkE34rePY9ACGlkWtDHbh6tBU6VRKoRa+CRuMAueC3yd8Var vGJVEgl52fRmvFPjcITYEz/nNQY/xYNWokvJURls5/p32XSFKGlxTobDCQ8f2fRlU8gF 93Dw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=PQMcMtbMYDPgR9+wRPXfJSgsCWHFDDomSfgNo4aUlK4=; b=fuCMvf3eafxG1YGLKZfq9h2RuFjqd/d4xRFPG6nVZYyATX5C0XdcebTzwt+xOLqzH5 nLswIAWIrI61n/jW6gBYIMERaJS12dFFKEyIj01WRRcJ5B1iJlbq0fs3UcD7eNNsyOls g8TUX6bwpif2lKn/XUFUmX+9AxkkYoiW4ostKiIQzSF7LJwdwmeBtr+Yp5xokIYS1Tol y3muVDHDWksYHoDj4k67bvtdtLtwO72MrtR5bBtJ0AK7SHlmUCRNG8sesX0r9CyHbLzE hmZR/TUOuCrBCD5Y583QFcAwPuIWhd610r0KCvdUBUQNWuQ19myK7/sfXqTbdMVMdGRr Ih3Q== X-Gm-Message-State: AOUpUlGvGIQNuUZJ3mfvZ+haUS541frneyJwLdGhR3QGK/dcTicUMfPu daksQ5bqNuTdrnqwuFW3eaw= X-Google-Smtp-Source: AAOMgpcmSYCKKi6sPjwJ+Oj9pVRmPUvW0TjKscm4WoK8A2LtX2Jw3Js+fs1q0SR5OVlYreRhg/bYDg== X-Received: by 2002:a2e:9e17:: with SMTP id e23-v6mr1502379ljk.14.1532458373824; Tue, 24 Jul 2018 11:52:53 -0700 (PDT) Received: from localhost.localdomain (c-2ec2f9f0-74736162.cust.telenor.se. [46.194.249.240]) by smtp.gmail.com with ESMTPSA id q14-v6sm1899287lfq.7.2018.07.24.11.52.51 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 24 Jul 2018 11:52:52 -0700 (PDT) From: Marcus Folkesson To: Marcus Folkesson , Kent Gustavsson , Jonathan Cameron , Hartmut Knaack , Lars-Peter Clausen , Peter Meerwald-Stadler , Rob Herring , Mark Rutland Cc: linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Mark Brown Subject: [PATCH v2 1/3] iio: adc: add support for mcp3911 Date: Tue, 24 Jul 2018 20:30:02 +0200 Message-Id: <20180724183004.20279-1-marcus.folkesson@gmail.com> X-Mailer: git-send-email 2.11.0.rc2 Sender: linux-iio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-iio@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP MCP3911 is a dual channel Analog Front End (AFE) containing two synchronous sampling delta-sigma Analog-to-Digital Converters (ADC). Signed-off-by: Marcus Folkesson Signed-off-by: Kent Gustavsson --- Notes: v2: - cleanups and bugfixes (thanks Peter Meerwald-Stadler) - drop hardware gain - use the presence or lack of regulator to indicate if we go for internal or external voltage reference - do not store device node in private struct - drop support to set width in devicetree - use the presence or lack of clock to indicate if we go for internal or external clock drivers/iio/adc/Kconfig | 10 ++ drivers/iio/adc/Makefile | 1 + drivers/iio/adc/mcp3911.c | 366 ++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 377 insertions(+) create mode 100644 drivers/iio/adc/mcp3911.c diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig index 15606f237480..f9a41fa96fcc 100644 --- a/drivers/iio/adc/Kconfig +++ b/drivers/iio/adc/Kconfig @@ -501,6 +501,16 @@ config MCP3422 This driver can also be built as a module. If so, the module will be called mcp3422. +config MCP3911 + tristate "Microchip Technology MCP3911 driver" + depends on SPI + help + Say yes here to build support for Microchip Technology's MCP3911 + analog to digital converter. + + This driver can also be built as a module. If so, the module will be + called mcp3911. + config MEDIATEK_MT6577_AUXADC tristate "MediaTek AUXADC driver" depends on ARCH_MEDIATEK || COMPILE_TEST diff --git a/drivers/iio/adc/Makefile b/drivers/iio/adc/Makefile index 28a9423997f3..3cfebfff7d26 100644 --- a/drivers/iio/adc/Makefile +++ b/drivers/iio/adc/Makefile @@ -47,6 +47,7 @@ obj-$(CONFIG_MAX1363) += max1363.o obj-$(CONFIG_MAX9611) += max9611.o obj-$(CONFIG_MCP320X) += mcp320x.o obj-$(CONFIG_MCP3422) += mcp3422.o +obj-$(CONFIG_MCP3911) += mcp3911.o obj-$(CONFIG_MEDIATEK_MT6577_AUXADC) += mt6577_auxadc.o obj-$(CONFIG_MEN_Z188_ADC) += men_z188_adc.o obj-$(CONFIG_MESON_SARADC) += meson_saradc.o diff --git a/drivers/iio/adc/mcp3911.c b/drivers/iio/adc/mcp3911.c new file mode 100644 index 000000000000..29aa39930ead --- /dev/null +++ b/drivers/iio/adc/mcp3911.c @@ -0,0 +1,366 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Driver for Microchip MCP3911, Two-channel Analog Front End + * + * Copyright (C) 2018 Marcus Folkesson + * Copyright (C) 2018 Kent Gustavsson + * + */ +#include +#include +#include +#include +#include +#include +#include + +#define MCP3911_REG_CHANNEL0 0x00 +#define MCP3911_REG_CHANNEL1 0x03 +#define MCP3911_REG_MOD 0x06 +#define MCP3911_REG_PHASE 0x07 +#define MCP3911_REG_GAIN 0x09 + +#define MCP3911_REG_STATUSCOM 0x0a +#define MCP3911_STATUSCOM_CH1_24WIDTH BIT(4) +#define MCP3911_STATUSCOM_CH0_24WIDTH BIT(3) +#define MCP3911_STATUSCOM_EN_OFFCAL BIT(2) +#define MCP3911_STATUSCOM_EN_GAINCAL BIT(1) + +#define MCP3911_REG_CONFIG 0x0c +#define MCP3911_CONFIG_CLKEXT BIT(1) +#define MCP3911_CONFIG_VREFEXT BIT(2) + +#define MCP3911_REG_OFFCAL_CH0 0x0e +#define MCP3911_REG_GAINCAL_CH0 0x11 +#define MCP3911_REG_OFFCAL_CH1 0x14 +#define MCP3911_REG_GAINCAL_CH1 0x17 +#define MCP3911_REG_VREFCAL 0x1a + +#define MCP3911_CHANNEL(x) (MCP3911_REG_CHANNEL0 + x * 3) +#define MCP3911_OFFCAL(x) (MCP3911_REG_OFFCAL_CH0 + x * 6) + +/* Internal voltage reference in uV */ +#define MCP3911_INT_VREF_UV 1200000 + +#define MCP3911_REG_READ(reg, id) ((((reg) << 1) | ((id) << 5) | (1 << 0)) & 0xff) +#define MCP3911_REG_WRITE(reg, id) ((((reg) << 1) | ((id) << 5) | (0 << 0)) & 0xff) + +#define MCP3911_NUM_CHANNELS 2 + +struct mcp3911 { + struct spi_device *spi; + struct mutex lock; + struct regulator *vref; + struct clk *adc_clk; + u32 dev_addr; +}; + +static int mcp3911_read(struct mcp3911 *adc, u8 reg, u32 *val, u8 len) +{ + int ret; + + reg = MCP3911_REG_READ(reg, adc->dev_addr); + ret = spi_write_then_read(adc->spi, ®, 1, val, len); + if (ret < 0) + return ret; + + be32_to_cpus(val); + *val >>= ((4 - len) * 8); + dev_dbg(&adc->spi->dev, "reading 0x%x from register 0x%x\n", *val, + reg>>1); + return ret; +} + +static int mcp3911_write(struct mcp3911 *adc, u8 reg, u32 val, u8 len) +{ + dev_dbg(&adc->spi->dev, "writing 0x%x to register 0x%x\n", val, reg); + + val <<= (3 - len) * 8; + cpu_to_be32s(&val); + val |= MCP3911_REG_WRITE(reg, adc->dev_addr); + + return spi_write(adc->spi, &val, len+1); +} + +static int mcp3911_update(struct mcp3911 *adc, u8 reg, u32 mask, + u32 val, u8 len) +{ + u32 tmp; + int ret; + + ret = mcp3911_read(adc, reg, &tmp, len); + if (ret) + return ret; + + val &= mask; + val |= tmp & ~mask; + return mcp3911_write(adc, reg, val, len); +} + +static int mcp3911_read_raw(struct iio_dev *indio_dev, + struct iio_chan_spec const *channel, int *val, + int *val2, long mask) +{ + struct mcp3911 *adc = iio_priv(indio_dev); + int ret = -EINVAL; + + mutex_lock(&adc->lock); + switch (mask) { + case IIO_CHAN_INFO_RAW: + ret = mcp3911_read(adc, + MCP3911_CHANNEL(channel->channel), val, 3); + if (ret) + goto out; + + ret = IIO_VAL_INT; + break; + + case IIO_CHAN_INFO_OFFSET: + ret = mcp3911_read(adc, + MCP3911_OFFCAL(channel->channel), val, 3); + if (ret) + goto out; + + ret = IIO_VAL_INT; + break; + + case IIO_CHAN_INFO_SCALE: + if (adc->vref) { + ret = regulator_get_voltage(adc->vref); + if (ret < 0) { + dev_err(indio_dev->dev.parent, + "failed to get vref voltage: %d\n", + ret); + goto out; + } + + *val = ret / 1000; + } else { + *val = MCP3911_INT_VREF_UV; + } + + *val2 = 24; + ret = IIO_VAL_FRACTIONAL_LOG2; + break; + } + +out: + mutex_unlock(&adc->lock); + return ret; +} + +static int mcp3911_write_raw(struct iio_dev *indio_dev, + struct iio_chan_spec const *channel, int val, + int val2, long mask) +{ + struct mcp3911 *adc = iio_priv(indio_dev); + int ret = -EINVAL; + + mutex_lock(&adc->lock); + switch (mask) { + case IIO_CHAN_INFO_OFFSET: + if (val2 != 0) { + ret = -EINVAL; + goto out; + } + + /* Write offset */ + ret = mcp3911_write(adc, MCP3911_OFFCAL(channel->channel), val, + 3); + if (ret) + goto out; + + /* Enable offset*/ + ret = mcp3911_update(adc, MCP3911_REG_STATUSCOM, + MCP3911_STATUSCOM_EN_OFFCAL, + MCP3911_STATUSCOM_EN_OFFCAL, 2); + break; + } + +out: + mutex_unlock(&adc->lock); + return ret; +} + +#define MCP3911_CHAN(idx) { \ + .type = IIO_VOLTAGE, \ + .indexed = 1, \ + .channel = idx, \ + .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ + BIT(IIO_CHAN_INFO_OFFSET) | \ + BIT(IIO_CHAN_INFO_SCALE), \ +} + +static const struct iio_chan_spec mcp3911_channels[] = { + MCP3911_CHAN(0), + MCP3911_CHAN(1), +}; + +static const struct iio_info mcp3911_info = { + .read_raw = mcp3911_read_raw, + .write_raw = mcp3911_write_raw, +}; + +static int mcp3911_config(struct mcp3911 *adc, struct device_node *of_node) +{ + u32 configreg; + int ret; + + of_property_read_u32(of_node, "device-addr", &adc->dev_addr); + if (adc->dev_addr > 3) { + dev_err(&adc->spi->dev, + "invalid device address (%i). Must be in range 0-3.\n", + adc->dev_addr); + return -EINVAL; + } + dev_dbg(&adc->spi->dev, "use device address %i\n", adc->dev_addr); + + ret = mcp3911_read(adc, MCP3911_REG_CONFIG, &configreg, 2); + if (ret) + return ret; + + if (adc->vref) { + dev_dbg(&adc->spi->dev, "use external voltage reference\n"); + configreg |= MCP3911_CONFIG_VREFEXT; + + } else { + dev_dbg(&adc->spi->dev, "use internal voltage reference (1.2V)\n"); + configreg &= ~MCP3911_CONFIG_VREFEXT; + } + + if (adc->adc_clk) { + dev_dbg(&adc->spi->dev, "use external clock as clocksource\n"); + configreg |= MCP3911_CONFIG_CLKEXT; + } else { + dev_dbg(&adc->spi->dev, "use crystal oscillator as clocksource\n"); + configreg &= ~MCP3911_CONFIG_CLKEXT; + } + + return mcp3911_write(adc, MCP3911_REG_CONFIG, configreg, 2); +} + +static int mcp3911_probe(struct spi_device *spi) +{ + struct iio_dev *indio_dev; + struct mcp3911 *adc; + int ret; + + indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*adc)); + if (!indio_dev) + return -ENOMEM; + + adc = iio_priv(indio_dev); + adc->spi = spi; + + adc->vref = devm_regulator_get_optional(&adc->spi->dev, "vref"); + if (IS_ERR(adc->vref)) { + + if (PTR_ERR(adc->vref) == -ENODEV) { + adc->vref = NULL; + } else { + dev_err(&adc->spi->dev, + "failed to get regulator (%ld)\n", + PTR_ERR(adc->vref)); + return PTR_ERR(adc->vref); + } + + } else { + ret = regulator_enable(adc->vref); + if (ret) + return ret; + } + + adc->adc_clk = devm_clk_get(&adc->spi->dev, "adc_clk"); + if (IS_ERR(adc->adc_clk)) { + if (PTR_ERR(adc->adc_clk) == -ENOENT) { + adc->adc_clk = NULL; + } else { + dev_err(&adc->spi->dev, + "failed to get adc clk (%ld)\n", + PTR_ERR(adc->adc_clk)); + ret = PTR_ERR(adc->adc_clk); + goto reg_disable; + } + } else { + ret = clk_prepare_enable(adc->adc_clk); + if (ret < 0) { + dev_err(&adc->spi->dev, + "Failed to enable adc_clk: %d\n", ret); + goto reg_disable; + } + } + + ret = mcp3911_config(adc, spi->dev.of_node); + if (ret) + goto clk_disable; + + indio_dev->dev.parent = &spi->dev; + indio_dev->dev.of_node = spi->dev.of_node; + indio_dev->name = spi_get_device_id(spi)->name; + indio_dev->modes = INDIO_DIRECT_MODE; + indio_dev->info = &mcp3911_info; + spi_set_drvdata(spi, indio_dev); + + indio_dev->channels = mcp3911_channels; + indio_dev->num_channels = ARRAY_SIZE(mcp3911_channels); + + mutex_init(&adc->lock); + + ret = iio_device_register(indio_dev); + if (ret) + goto clk_disable; + + return ret; + +clk_disable: + if (adc->adc_clk) + clk_disable_unprepare(adc->adc_clk); +reg_disable: + if (adc->vref) + regulator_disable(adc->vref); + + return ret; +} + +static int mcp3911_remove(struct spi_device *spi) +{ + struct iio_dev *indio_dev = spi_get_drvdata(spi); + struct mcp3911 *adc = iio_priv(indio_dev); + + iio_device_unregister(indio_dev); + + if (adc->vref) + regulator_disable(adc->vref); + + return 0; +} + +#if defined(CONFIG_OF) +static const struct of_device_id mcp3911_dt_ids[] = { + { .compatible = "microchip,mcp3911" }, + { } +}; +MODULE_DEVICE_TABLE(of, mcp3911_dt_ids); +#endif + +static const struct spi_device_id mcp3911_id[] = { + { "mcp3911", 0 }, + { } +}; +MODULE_DEVICE_TABLE(spi, mcp3911_id); + +static struct spi_driver mcp3911_driver = { + .driver = { + .name = "mcp3911", + .of_match_table = of_match_ptr(mcp3911_dt_ids), + }, + .probe = mcp3911_probe, + .remove = mcp3911_remove, + .id_table = mcp3911_id, +}; +module_spi_driver(mcp3911_driver); + +MODULE_AUTHOR("Marcus Folkesson "); +MODULE_AUTHOR("Kent Gustavsson "); +MODULE_DESCRIPTION("Microchip Technology MCP3911"); +MODULE_LICENSE("GPL v2"); From patchwork Tue Jul 24 18:30:03 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marcus Folkesson X-Patchwork-Id: 10542961 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id A0770112E for ; Tue, 24 Jul 2018 18:53:07 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 8F66E287C9 for ; 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[46.194.249.240]) by smtp.gmail.com with ESMTPSA id q14-v6sm1899287lfq.7.2018.07.24.11.52.53 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 24 Jul 2018 11:52:54 -0700 (PDT) From: Marcus Folkesson To: Marcus Folkesson , Kent Gustavsson , Jonathan Cameron , Hartmut Knaack , Lars-Peter Clausen , Peter Meerwald-Stadler , Rob Herring , Mark Rutland Cc: linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Mark Brown Subject: [PATCH v2 2/3] dt-bindings: iio: adc: add bindings for mcp3911 Date: Tue, 24 Jul 2018 20:30:03 +0200 Message-Id: <20180724183004.20279-2-marcus.folkesson@gmail.com> X-Mailer: git-send-email 2.11.0.rc2 In-Reply-To: <20180724183004.20279-1-marcus.folkesson@gmail.com> References: <20180724183004.20279-1-marcus.folkesson@gmail.com> Sender: linux-iio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-iio@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP MCP3911 is a dual channel Analog Front End (AFE) containing two synchronous sampling delta-sigma Analog-to-Digital Converters (ADC). Signed-off-by: Marcus Folkesson Signed-off-by: Kent Gustavsson --- Notes: v2: - drop channel width - drop `external_vref` - replace `external-clock` with proper clock bindings .../devicetree/bindings/iio/adc/mcp3911.txt | 28 ++++++++++++++++++++++ 1 file changed, 28 insertions(+) create mode 100644 Documentation/devicetree/bindings/iio/adc/mcp3911.txt diff --git a/Documentation/devicetree/bindings/iio/adc/mcp3911.txt b/Documentation/devicetree/bindings/iio/adc/mcp3911.txt new file mode 100644 index 000000000000..af5472f51a84 --- /dev/null +++ b/Documentation/devicetree/bindings/iio/adc/mcp3911.txt @@ -0,0 +1,28 @@ +* Microchip MCP3911 Dual channel analog front end (ADC) + +Required properties: + - compatible: Should be "microchip,mcp3911" + - reg: SPI chip select number for the device + +Recommended properties: + - spi-max-frequency: Definition as per + Documentation/devicetree/bindings/spi/spi-bus.txt. + Max frequency for this chip is 20MHz. + +Optional properties: + - device-addr: Device address when multiple MCP3911 chips are present on the + same SPI bus. Valid values are 0-3. Defaults to 0. + - vref-supply: Phandle to the external reference voltage supply. + - clocks: Phandle and clock identifier (see clock-names) + - clock-names: "adc_clk" for the ADC (sampling) clock + +Example: +adc@0 { + compatible = "microchip,mcp3911"; + reg = <0>; + spi-max-frequency = <20000000>; + device-addr = <0>; + vref-supply = <&vref_reg>; + clocks = <&xtal>; + clock-names = "adc_clk"; +}; From patchwork Tue Jul 24 18:30:04 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marcus Folkesson X-Patchwork-Id: 10542959 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 660A31805 for ; Tue, 24 Jul 2018 18:53:04 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 54409287A6 for ; Tue, 24 Jul 2018 18:53:04 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 4841F287BE; Tue, 24 Jul 2018 18:53:04 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.8 required=2.0 tests=BAYES_00,DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED,FREEMAIL_FROM,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id BA847287A6 for ; Tue, 24 Jul 2018 18:53:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2388619AbeGXUAt (ORCPT ); Tue, 24 Jul 2018 16:00:49 -0400 Received: from mail-lj1-f195.google.com ([209.85.208.195]:38097 "EHLO mail-lj1-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2388366AbeGXUAs (ORCPT ); Tue, 24 Jul 2018 16:00:48 -0400 Received: by mail-lj1-f195.google.com with SMTP id p6-v6so4504984ljc.5; Tue, 24 Jul 2018 11:52:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=l4DxCWcjc7EIC4KgORJCdIVTkxzo+vRhxAQxdPczEag=; b=eYdUj7nY5aUOeOjs/wkasxsmcFIioE36/XW2+iebVlq/ovU1TEMNnh9geJsIvppGah VoW3Hjg5vQWmpIen4yg50AeZ4Mde7WhBEAWW1cPy6HAQUkmPBZSxYCd8f8Hf/F5JRGe3 BU63k/Z7qLRCxc2D33+GccaL8rjH65W2OOptnLyYdJSbJLEkH2x32yQySO0PvH+874id hfiUY20LIuXrW2jeKaWRtQXvzSZQZpbLeVOof7ScCQm2o6X0jTK3wE2bLgfGuywzodVF HA5ZilHdMVYR89bMn6cMJxt086ahJTN0wJmYh8CzSXWZjtFlaJUTHwnCPG/WynpMlqjM OUdw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=l4DxCWcjc7EIC4KgORJCdIVTkxzo+vRhxAQxdPczEag=; b=FDhN3MrfsH7TyiZBe8+mjtMQncU3jhz77LhebwvSUWxHmfOLxLUVpdOXQA3z9jBsh8 VC3PBFr/I5yo85lyY5XbdDS1eBaBD/Am5tBPgW5NxQFgtdgEOwt0zdvUKitZ3/uY6lDk jrVyJxNFbzKlFjxG1+anZ/eAQkekQ1a9ElxAEd7UGvS5qgMJlA+uS2kq/rX6XvhwA19d 8FG1Yd4giXDPezJumG3KyzpALqdUQy1S7bFAFELd+1IJNBovLTt/1Q4AchW6COIHii2f Rs9/s8GJ5Vk/KIxSo2eXxQ/Fes76Bxg+62LckV/8JvRH+rcxBL7bApx3lORedb6oXlhm iwcQ== X-Gm-Message-State: AOUpUlH8KvhAYfXgqqq/ssusw08xNcIyNE8eIG29PPu4uPxzphhQwNme Xy4sGk0uk8H+BpkEUD4E8OQ= X-Google-Smtp-Source: AAOMgpdFHdPJLw6GoqPhqjIuEYbmY/k/1mT6CkK1Uu2t9UoX9c+Kxvu0VSeyVZBxE65C2NBOYMt41w== X-Received: by 2002:a2e:94d5:: with SMTP id r21-v6mr12748303ljh.126.1532458377691; Tue, 24 Jul 2018 11:52:57 -0700 (PDT) Received: from localhost.localdomain (c-2ec2f9f0-74736162.cust.telenor.se. [46.194.249.240]) by smtp.gmail.com with ESMTPSA id q14-v6sm1899287lfq.7.2018.07.24.11.52.55 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 24 Jul 2018 11:52:56 -0700 (PDT) From: Marcus Folkesson To: Marcus Folkesson , Kent Gustavsson , Jonathan Cameron , Hartmut Knaack , Lars-Peter Clausen , Peter Meerwald-Stadler , Rob Herring , Mark Rutland Cc: linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Mark Brown Subject: [PATCH v2 3/3] MAINTAINERS: Add entry for mcp3911 ADC driver Date: Tue, 24 Jul 2018 20:30:04 +0200 Message-Id: <20180724183004.20279-3-marcus.folkesson@gmail.com> X-Mailer: git-send-email 2.11.0.rc2 In-Reply-To: <20180724183004.20279-1-marcus.folkesson@gmail.com> References: <20180724183004.20279-1-marcus.folkesson@gmail.com> Sender: linux-iio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-iio@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add an entry for mcp3911 ADC driver and add myself and Kent Gustavsson as maintainers of this driver. Signed-off-by: Marcus Folkesson Signed-off-by: Kent Gustavsson --- Notes: v2: - no changes MAINTAINERS | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 79bb02ff812f..9276da915d9d 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -9271,6 +9271,14 @@ L: netdev@vger.kernel.org S: Maintained F: drivers/net/ethernet/microchip/lan743x_* +MICROCHIP / ATMEL MCP3911 ADC DRIVER +M: Marcus Folkesson +M: Kent Gustavsson +L: linux-iio@vger.kernel.org +S: Supported +F: drivers/iio/adc/mcp3911.c +F: Documentation/devicetree/bindings/iio/adc/mcp3911.txt + MICROCHIP USB251XB DRIVER M: Richard Leitner L: linux-usb@vger.kernel.org