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[90.86.218.216]) by smtp.gmail.com with ESMTPSA id u17sm5582862wmu.36.2019.04.17.07.47.14 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 17 Apr 2019 07:47:15 -0700 (PDT) From: Bartosz Golaszewski To: Sekhar Nori , Kevin Hilman , Daniel Lezcano , Thomas Gleixner , David Lechner Subject: [RFC 1/2] clocksource: davinci-timer: add support for clockevents Date: Wed, 17 Apr 2019 16:47:08 +0200 Message-Id: <20190417144709.19588-2-brgl@bgdev.pl> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190417144709.19588-1-brgl@bgdev.pl> References: <20190417144709.19588-1-brgl@bgdev.pl> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190417_074717_460749_10A22D7E X-CRM114-Status: GOOD ( 23.81 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bartosz Golaszewski , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP From: Bartosz Golaszewski Currently the clocksource and clockevent support for davinci platforms lives in mach-davinci. It hard-codes many things, uses global variables, implements functionalities unused by any platform and has code fragments scattered across many (often unrelated) files. Implement a new, modern and simplified timer driver and put it into drivers/clocksource. We still need to support legacy board files so export a config structure and a function that allows machine code to register the timer. The timer we're using is 64-bit but can be programmed in dual 32-bit mode (both chained and unchained). We're using dual 32-bit mode to have separate counters for clockevents and clocksource. This patch contains the core code and support for clockevent. The clocksource code will be included in a subsequent patch. Signed-off-by: Bartosz Golaszewski --- drivers/clocksource/Kconfig | 5 + drivers/clocksource/Makefile | 1 + drivers/clocksource/timer-davinci.c | 272 ++++++++++++++++++++++++++++ include/clocksource/timer-davinci.h | 44 +++++ 4 files changed, 322 insertions(+) create mode 100644 drivers/clocksource/timer-davinci.c create mode 100644 include/clocksource/timer-davinci.h diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig index 171502a356aa..974f9b50ebf4 100644 --- a/drivers/clocksource/Kconfig +++ b/drivers/clocksource/Kconfig @@ -42,6 +42,11 @@ config BCM_KONA_TIMER help Enables the support for the BCM Kona mobile timer driver. +config DAVINCI_TIMER + bool "Texas Instruments DaVinci timer driver" if COMPILE_TEST + help + Enables the support for the TI DaVinci timer driver. + config DIGICOLOR_TIMER bool "Digicolor timer driver" if COMPILE_TEST select CLKSRC_MMIO diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile index be6e0fbc7489..3c73d0e58b45 100644 --- a/drivers/clocksource/Makefile +++ b/drivers/clocksource/Makefile @@ -15,6 +15,7 @@ obj-$(CONFIG_SH_TIMER_TMU) += sh_tmu.o obj-$(CONFIG_EM_TIMER_STI) += em_sti.o obj-$(CONFIG_CLKBLD_I8253) += i8253.o obj-$(CONFIG_CLKSRC_MMIO) += mmio.o +obj-$(CONFIG_DAVINCI_TIMER) += timer-davinci.o obj-$(CONFIG_DIGICOLOR_TIMER) += timer-digicolor.o obj-$(CONFIG_OMAP_DM_TIMER) += timer-ti-dm.o obj-$(CONFIG_DW_APB_TIMER) += dw_apb_timer.o diff --git a/drivers/clocksource/timer-davinci.c b/drivers/clocksource/timer-davinci.c new file mode 100644 index 000000000000..d30f81a4088e --- /dev/null +++ b/drivers/clocksource/timer-davinci.c @@ -0,0 +1,272 @@ +// SPDX-License-Identifier: GPL-2.0-only +// +// TI DaVinci clocksource driver +// +// Copyright (C) 2019 Texas Instruments +// Author: Bartosz Golaszewski +// (with tiny parts adopted from code by Kevin Hilman ) + +#include +#include +#include +#include +#include +#include +#include + +#include + +#undef pr_fmt +#define pr_fmt(fmt) "%s: " fmt "\n", __func__ + +#define DAVINCI_TIMER_REG_TIM12 0x10 +#define DAVINCI_TIMER_REG_TIM34 0x14 +#define DAVINCI_TIMER_REG_PRD12 0x18 +#define DAVINCI_TIMER_REG_PRD34 0x1c +#define DAVINCI_TIMER_REG_TCR 0x20 +#define DAVINCI_TIMER_REG_TGCR 0x24 + +#define DAVINCI_TIMER_TIMMODE_MASK GENMASK(3, 2) +#define DAVINCI_TIMER_RESET_MASK GENMASK(1, 0) +#define DAVINCI_TIMER_TIMMODE_32BIT_UNCHAINED BIT(2) +#define DAVINCI_TIMER_UNRESET GENMASK(1, 0) + +#define DAVINCI_TIMER_ENAMODE_MASK GENMASK(1, 0) +#define DAVINCI_TIMER_ENAMODE_DISABLED 0x00 +#define DAVINCI_TIMER_ENAMODE_ONESHOT BIT(0) +#define DAVINCI_TIMER_ENAMODE_PERIODIC BIT(1) + +#define DAVINCI_TIMER_ENAMODE_SHIFT_TIM12 6 +#define DAVINCI_TIMER_ENAMODE_SHIFT_TIM34 22 + +#define DAVINCI_TIMER_MIN_DELTA 0x01 +#define DAVINCI_TIMER_MAX_DELTA 0xfffffffe + +#define DAVINCI_TIMER_TGCR_DEFAULT \ + (DAVINCI_TIMER_TIMMODE_32BIT_UNCHAINED | DAVINCI_TIMER_UNRESET) + +struct davinci_clockevent { + struct clock_event_device dev; + void __iomem *base; + + unsigned int tim_off; + unsigned int prd_off; + unsigned int cmp_off; + + unsigned int enamode_disabled; + unsigned int enamode_oneshot; + unsigned int enamode_periodic; + unsigned int enamode_mask; +}; + +static struct davinci_clockevent * +to_davinci_clockevent(struct clock_event_device *clockevent) +{ + return container_of(clockevent, struct davinci_clockevent, dev); +} + +static unsigned int +davinci_clockevent_read(struct davinci_clockevent *clockevent, + unsigned int reg) +{ + return readl_relaxed(clockevent->base + reg); +} + +static void davinci_clockevent_write(struct davinci_clockevent *clockevent, + unsigned int reg, unsigned int val) +{ + writel_relaxed(val, clockevent->base + reg); +} + +static void davinci_reg_update(void __iomem *base, unsigned int reg, + unsigned int mask, unsigned int val) +{ + unsigned int new, orig; + + orig = readl_relaxed(base + reg); + new = orig & ~mask; + new |= val & mask; + + writel_relaxed(new, base + reg); +} + +static void davinci_clockevent_update(struct davinci_clockevent *clockevent, + unsigned int reg, unsigned int mask, + unsigned int val) +{ + davinci_reg_update(clockevent->base, reg, mask, val); +} + +static int +davinci_clockevent_set_next_event_std(unsigned long cycles, + struct clock_event_device *dev) +{ + struct davinci_clockevent *clockevent; + unsigned int enamode; + + clockevent = to_davinci_clockevent(dev); + enamode = clockevent->enamode_disabled; + + davinci_clockevent_update(clockevent, DAVINCI_TIMER_REG_TCR, + clockevent->enamode_mask, + clockevent->enamode_disabled); + + davinci_clockevent_write(clockevent, clockevent->tim_off, 0x0); + davinci_clockevent_write(clockevent, clockevent->prd_off, cycles); + + if (clockevent_state_oneshot(&clockevent->dev)) + enamode = clockevent->enamode_oneshot; + else if (clockevent_state_periodic(&clockevent->dev)) + enamode = clockevent->enamode_periodic; + + davinci_clockevent_update(clockevent, DAVINCI_TIMER_REG_TCR, + clockevent->enamode_mask, enamode); + + return 0; +} + +static int +davinci_clockevent_set_next_event_cmp(unsigned long cycles, + struct clock_event_device *dev) +{ + struct davinci_clockevent *clockevent = to_davinci_clockevent(dev); + unsigned int curr_time; + + curr_time = davinci_clockevent_read(clockevent, clockevent->tim_off); + davinci_clockevent_write(clockevent, + clockevent->cmp_off, curr_time + cycles); + + return 0; +} + +static irqreturn_t davinci_timer_irq_timer(int irq, void *data) +{ + struct davinci_clockevent *clockevent = data; + + clockevent->dev.event_handler(&clockevent->dev); + + return IRQ_HANDLED; +} + +static void davinci_timer_init(void __iomem *base) +{ + /* Set clock to internal mode and disable it. */ + writel_relaxed(0x0, base + DAVINCI_TIMER_REG_TCR); + /* + * Reset both 32-bit timers, set no prescaler for timer 34, set the + * timer to dual 32-bit unchained mode, unreset both 32-bit timers. + */ + writel_relaxed(DAVINCI_TIMER_TGCR_DEFAULT, + base + DAVINCI_TIMER_REG_TGCR); + /* Init both counters to zero. */ + writel_relaxed(0x0, base + DAVINCI_TIMER_REG_TIM12); + writel_relaxed(0x0, base + DAVINCI_TIMER_REG_TIM34); +} + +int __init davinci_timer_register(struct clk *clk, + const struct davinci_timer_cfg *timer_cfg) +{ + struct davinci_clockevent *clockevent; + unsigned int tick_rate, shift; + void __iomem *base; + int rv; + + rv = clk_prepare_enable(clk); + if (rv) { + pr_err("Unable to prepare and enable the timer clock"); + return rv; + } + + base = request_mem_region(timer_cfg->reg.start, + resource_size(&timer_cfg->reg), + "davinci-timer"); + if (!base) { + pr_err("Unable to request memory region"); + return -EBUSY; + } + + base = ioremap(timer_cfg->reg.start, resource_size(&timer_cfg->reg)); + if (!base) { + pr_err("Unable to map the register range"); + return -ENOMEM; + } + + davinci_timer_init(base); + tick_rate = clk_get_rate(clk); + + clockevent = kzalloc(sizeof(*clockevent), GFP_KERNEL); + if (!clockevent) { + pr_err("Error allocating memory for clockevent data"); + return -ENOMEM; + } + + clockevent->dev.name = "tim12"; + clockevent->dev.features = CLOCK_EVT_FEAT_ONESHOT; + clockevent->dev.cpumask = cpumask_of(0); + + clockevent->base = base; + clockevent->tim_off = DAVINCI_TIMER_REG_TIM12; + clockevent->prd_off = DAVINCI_TIMER_REG_PRD12; + + shift = DAVINCI_TIMER_ENAMODE_SHIFT_TIM12; + clockevent->enamode_disabled = DAVINCI_TIMER_ENAMODE_DISABLED << shift; + clockevent->enamode_oneshot = DAVINCI_TIMER_ENAMODE_ONESHOT << shift; + clockevent->enamode_periodic = DAVINCI_TIMER_ENAMODE_PERIODIC << shift; + clockevent->enamode_mask = DAVINCI_TIMER_ENAMODE_MASK << shift; + + if (timer_cfg->cmp_off) { + clockevent->cmp_off = timer_cfg->cmp_off; + clockevent->dev.set_next_event = + davinci_clockevent_set_next_event_cmp; + } else { + clockevent->dev.set_next_event = + davinci_clockevent_set_next_event_std; + } + + rv = request_irq(timer_cfg->irq[DAVINCI_TIMER_CLOCKEVENT_IRQ].start, + davinci_timer_irq_timer, IRQF_TIMER, + "clockevent", clockevent); + if (rv) { + pr_err("Unable to request the clockevent interrupt"); + return rv; + } + + clockevents_config_and_register(&clockevent->dev, tick_rate, + DAVINCI_TIMER_MIN_DELTA, + DAVINCI_TIMER_MAX_DELTA); + + return 0; +} + +static int __init of_davinci_timer_register(struct device_node *np) +{ + struct davinci_timer_cfg timer_cfg = { }; + struct clk *clk; + int rv; + + rv = of_address_to_resource(np, 0, &timer_cfg.reg); + if (rv) { + pr_err("Unable to get the register range for timer"); + return rv; + } + + rv = of_irq_to_resource_table(np, timer_cfg.irq, + DAVINCI_TIMER_NUM_IRQS); + if (rv != DAVINCI_TIMER_NUM_IRQS) { + pr_err("Unable to get the interrupts for timer"); + return rv; + } + + clk = of_clk_get(np, 0); + if (IS_ERR(clk)) { + pr_err("Unable to get the timer clock"); + return PTR_ERR(clk); + } + + rv = davinci_timer_register(clk, &timer_cfg); + if (rv) + clk_put(clk); + + return rv; +} +TIMER_OF_DECLARE(davinci_timer, "ti,da830-timer", of_davinci_timer_register); diff --git a/include/clocksource/timer-davinci.h b/include/clocksource/timer-davinci.h new file mode 100644 index 000000000000..1dcc1333fbc8 --- /dev/null +++ b/include/clocksource/timer-davinci.h @@ -0,0 +1,44 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * TI DaVinci clocksource driver + * + * Copyright (C) 2019 Texas Instruments + * Author: Bartosz Golaszewski + */ + +#ifndef __TIMER_DAVINCI_H__ +#define __TIMER_DAVINCI_H__ + +#include +#include + +enum { + DAVINCI_TIMER_CLOCKEVENT_IRQ, + DAVINCI_TIMER_CLOCKSOURCE_IRQ, + DAVINCI_TIMER_NUM_IRQS, +}; + +/** + * struct davinci_timer_cfg - davinci clocksource driver configuration struct + * @reg: register range resource + * @irq: clockevent and clocksource interrupt resources + * @cmp_off: if set - it specifies the compare register used for clockevent + * + * Note: if the compare register is specified, the driver will use the bottom + * clock half for both clocksource and clockevent and the compare register + * to generate event irqs. The user must supply the correct compare register + * interrupt number. + * + * This is only used by da830 the DSP of which uses the top half. The timer + * driver still configures the top half to run in free-run mode. + */ +struct davinci_timer_cfg { + struct resource reg; + struct resource irq[DAVINCI_TIMER_NUM_IRQS]; + unsigned int cmp_off; +}; + +int __init davinci_timer_register(struct clk *clk, + const struct davinci_timer_cfg *data); + +#endif /* __TIMER_DAVINCI_H__ */ From patchwork Wed Apr 17 14:47:09 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bartosz Golaszewski X-Patchwork-Id: 10905459 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 859751515 for ; Wed, 17 Apr 2019 14:47:43 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 6A78B223B3 for ; Wed, 17 Apr 2019 14:47:43 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 5E7C328740; Wed, 17 Apr 2019 14:47:43 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 010C4223B3 for ; Wed, 17 Apr 2019 14:47:42 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=12d8LXwrbdKXHQtteQXNY9iJxLyHTyT576JRpn35HtQ=; b=E//Ag3HPLmciWw YPzQq2j5Y1iRiDdZX335IpS3L68qXIBkdXee0o3txzLqji2jw1fWZWieH+lMn6dh+ZIoxJV0SBXDx wL2rW0og9Zow4CYEGSWTKOlboUN/8YLiu19rTYDFAGa2CctIzjHU/OM7uBrBFYhJEzSpKZOCANiuD ECm+geJeboJysQipu4QGy/X0qB9Q03H+Jm6UcryG5u8AgtVse2rCrLaTr7do4DN2GAHsAYzTItpdk bpLuDUH4fygPdscOtynFQMtgY1w66x8S62C7mvPdrur46YHtqjjgDTx0CzoW9lHZvWAgw5EUPq+5b ByyXumvn9+IXr6OtvuVQ==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1hGlqc-0003XX-Qf; Wed, 17 Apr 2019 14:47:38 +0000 Received: from mail-wr1-x441.google.com ([2a00:1450:4864:20::441]) by bombadil.infradead.org with esmtps (Exim 4.90_1 #2 (Red Hat Linux)) id 1hGlqI-000378-J4 for linux-arm-kernel@lists.infradead.org; Wed, 17 Apr 2019 14:47:20 +0000 Received: by mail-wr1-x441.google.com with SMTP id k11so32352194wro.5 for ; Wed, 17 Apr 2019 07:47:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bgdev-pl.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=PkEAOEiMzCEaJhtas7PAWSYNdvyzA7yFJpIHTqreR8A=; b=gKv18u2Dcj1ZxRC0dLdKT1Cg3ih6bcMPrni8U1SZ7Mdu4PjpWH4c+LJqbXxkd3cSbp kyGFclhWJAI6xy0hriXtHZ10ptiaXleLUCjxojur3zVeikz1HAmDH/4SZmgabkTM/ggL mbQjLLAtYeh3R/OlCzzbl1rcznB88fVam46IJiANH7IDcE4zgMophKTpCYOxi2Q7AHz5 NQoIASVxckgaNmkP1fY/w5pjCD5LDV+QoLF351n1LAkbJJil5nIDbJG4Gy7S/eWq68pu DVJ8tsC9Lr/lvYwAxq5k46wh4YQRR5qIzomhcF1NfqRPprmCoZN5crnT1Yw6OrmSkAFN GlBg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=PkEAOEiMzCEaJhtas7PAWSYNdvyzA7yFJpIHTqreR8A=; b=jQwd+yb+9ZpuAQj5rw586+6Sh92zQohxEWIE92I4nl4UuhG27xNJHQOBNC+SVZ2AX+ Y8X1hEwhMFcCxTIGZQa5bStQcMS0340rzNCA7sXWLXNbYeyugn9JVPhVnKanHLRIwy8q 0Y4a3QmZETXpwvhnOrrLaMC5BU/5CHSkDJC6duMQnytkxPce96d5zstnPkztoa+0YzVM q2zZg0qECCJvUgublkaCOGga7N9PbUDOkiM6R9RDmy70A4UV3tOyh6uQ/zCNnti51qSc YnvKeu+s4Aefr3fMBPKwMoAGtKCR+Lu5r2cYDfpO0GZW2yblWOzn+5R1oX+7V3jf6d6M M3dQ== X-Gm-Message-State: APjAAAVD2Vv9cYhmi5fx8UE8s07eGBtopfettxyREfteE7VuI/n1/4iM 2BvDCVwqGDfkEDjyD7qwG+w/4w== X-Google-Smtp-Source: APXvYqwN+bSAzaX1I+kboL1bDFXatlPHaX54h5qvTFWj+vUA/ejLFp/ewmMOa6PwqUKzsP/wmF6dOw== X-Received: by 2002:a5d:6b07:: with SMTP id v7mr108084wrw.311.1555512437024; Wed, 17 Apr 2019 07:47:17 -0700 (PDT) Received: from localhost.localdomain (aputeaux-684-1-15-216.w90-86.abo.wanadoo.fr. [90.86.218.216]) by smtp.gmail.com with ESMTPSA id u17sm5582862wmu.36.2019.04.17.07.47.15 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 17 Apr 2019 07:47:16 -0700 (PDT) From: Bartosz Golaszewski To: Sekhar Nori , Kevin Hilman , Daniel Lezcano , Thomas Gleixner , David Lechner Subject: [RFC 2/2] clocksource: timer-davinci: add support for clocksource Date: Wed, 17 Apr 2019 16:47:09 +0200 Message-Id: <20190417144709.19588-3-brgl@bgdev.pl> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190417144709.19588-1-brgl@bgdev.pl> References: <20190417144709.19588-1-brgl@bgdev.pl> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190417_074718_638695_80686E7D X-CRM114-Status: GOOD ( 14.73 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bartosz Golaszewski , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP From: Bartosz Golaszewski Extend the davinci-timer driver to also register a clock source. Signed-off-by: Bartosz Golaszewski --- drivers/clocksource/timer-davinci.c | 70 +++++++++++++++++++++++++++++ 1 file changed, 70 insertions(+) diff --git a/drivers/clocksource/timer-davinci.c b/drivers/clocksource/timer-davinci.c index d30f81a4088e..d630fca98123 100644 --- a/drivers/clocksource/timer-davinci.c +++ b/drivers/clocksource/timer-davinci.c @@ -42,6 +42,8 @@ #define DAVINCI_TIMER_MIN_DELTA 0x01 #define DAVINCI_TIMER_MAX_DELTA 0xfffffffe +#define DAVINCI_TIMER_CLKSRC_BITS 32 + #define DAVINCI_TIMER_TGCR_DEFAULT \ (DAVINCI_TIMER_TIMMODE_32BIT_UNCHAINED | DAVINCI_TIMER_UNRESET) @@ -59,6 +61,16 @@ struct davinci_clockevent { unsigned int enamode_mask; }; +/* + * This must be globally accessible by davinci_timer_read_sched_clock(), so + * let's keep it here. + */ +static struct { + struct clocksource dev; + void __iomem *base; + unsigned int tim_off; +} davinci_clocksource; + static struct davinci_clockevent * to_davinci_clockevent(struct clock_event_device *clockevent) { @@ -148,6 +160,32 @@ static irqreturn_t davinci_timer_irq_timer(int irq, void *data) return IRQ_HANDLED; } +static u64 notrace davinci_timer_read_sched_clock(void) +{ + return readl_relaxed(davinci_clocksource.base + + davinci_clocksource.tim_off); +} + +static u64 davinci_clocksource_read(struct clocksource *dev) +{ + return davinci_timer_read_sched_clock(); +} + +static void davinci_clocksource_init(void __iomem *base, unsigned int tim_off, + unsigned int prd_off, unsigned int shift) +{ + davinci_reg_update(base, DAVINCI_TIMER_REG_TCR, + DAVINCI_TIMER_ENAMODE_MASK << shift, + DAVINCI_TIMER_ENAMODE_DISABLED << shift); + + writel_relaxed(0x0, base + tim_off); + writel_relaxed(UINT_MAX, base + prd_off); + + davinci_reg_update(base, DAVINCI_TIMER_REG_TCR, + DAVINCI_TIMER_ENAMODE_MASK << shift, + DAVINCI_TIMER_ENAMODE_PERIODIC << shift); +} + static void davinci_timer_init(void __iomem *base) { /* Set clock to internal mode and disable it. */ @@ -235,6 +273,38 @@ int __init davinci_timer_register(struct clk *clk, DAVINCI_TIMER_MIN_DELTA, DAVINCI_TIMER_MAX_DELTA); + davinci_clocksource.dev.rating = 300; + davinci_clocksource.dev.read = davinci_clocksource_read; + davinci_clocksource.dev.mask = + CLOCKSOURCE_MASK(DAVINCI_TIMER_CLKSRC_BITS); + davinci_clocksource.dev.flags = CLOCK_SOURCE_IS_CONTINUOUS; + davinci_clocksource.base = base; + + if (timer_cfg->cmp_off) { + davinci_clocksource.dev.name = "tim12"; + davinci_clocksource.tim_off = DAVINCI_TIMER_REG_TIM12; + davinci_clocksource_init(base, + DAVINCI_TIMER_REG_TIM12, + DAVINCI_TIMER_REG_PRD12, + DAVINCI_TIMER_ENAMODE_SHIFT_TIM12); + } else { + davinci_clocksource.dev.name = "tim34"; + davinci_clocksource.tim_off = DAVINCI_TIMER_REG_TIM34; + davinci_clocksource_init(base, + DAVINCI_TIMER_REG_TIM34, + DAVINCI_TIMER_REG_PRD34, + DAVINCI_TIMER_ENAMODE_SHIFT_TIM34); + } + + rv = clocksource_register_hz(&davinci_clocksource.dev, tick_rate); + if (rv) { + pr_err("Unable to register clocksource"); + return rv; + } + + sched_clock_register(davinci_timer_read_sched_clock, + DAVINCI_TIMER_CLKSRC_BITS, tick_rate); + return 0; }