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Fri, 19 Apr 2019 14:19:39 +0000 (GMT) From: Lukasz Luba To: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-samsung-soc@vger.kernel.org Cc: b.zolnierkie@samsung.com, krzk@kernel.org, kgene@kernel.org, cw00.choi@samsung.com, kyungmin.park@samsung.com, m.szyprowski@samsung.com, s.nawrocki@samsung.com, myungjoo.ham@samsung.com, keescook@chromium.org, tony@atomide.com, jroedel@suse.de, treding@nvidia.com, digetx@gmail.com, willy.mh.wolff.ml@gmail.com, Lukasz Luba Subject: [PATCH v6 01/10] clk: samsung: add needed IDs for DMC clocks in Exynos5420 Date: Fri, 19 Apr 2019 16:19:19 +0200 Message-Id: <1555683568-20882-2-git-send-email-l.luba@partner.samsung.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1555683568-20882-1-git-send-email-l.luba@partner.samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA0VSeUhTcRzvt3fsOZu9ZuUvE61Jh1GaUfaDDhQUX+UfYURURr70YZFT2/PI LFhKmpoa69A07b5W5jXNSaXOkZI6s2ueJI0USi3P0jBzvoX/fb+fk9+XH4XJDIQjdTwimlNG sOFyUoJXvJ4wrp9q0wVtaH3jikpyighkGu0j0E2DkUBPhswAXX6TL0JN6QqUZf6OoZaWYjFq TuwXow6VE3pfdYNEIxkGgHJaXolQoaFbjDrPPSJRXX8Kgao/7EKdf+zQeMMX4G3PjI+pcSZP 1YozutxuMVOqSSWZjKRBkqkdfCFiMrUawJQ1JjAjpc57bA5KtoVy4cdjOaXHjmDJsV/lH4mo ZrtTidUDpArcnZ8GKArSm+BUZXQakFAy+hGA5vPDQFhGAVSXvLQuIwCmpubOLDazDuPYfSvx EMDs6/o5S9JkIWbJJWl3WKk5aTEsohNgl6kas2gwul8Emyd/4xbCnt4HjTXds6k4vRKe73kw 65XSu2Byikgoc4btxlTMMtvQu2HVYy1pyYF0hxgmGzRiQeQLTZ0tuDDbw2/1WivuBKd1N61B PFRl3La+4Aw0Z+VbNVthXX0rYenFaDdYVOUhwD6wWK0jhRPZwbaBhRYYmxnVFdmYAEvhhWSZ oF4DtRffWouWwIdPr1nDGWh6/ZUQrlMAYFntEHYJuOTOld0CQAMcuBheEcbxnhFcnDvPKviY iDD3kEhFKZj5W41/64crwdi7o3pAU0A+X1qj1gXJCDaWj1foAaQw+SKpT6g2SCYNZeNPc8rI I8qYcI7Xg2UULneQJszrOSSjw9ho7gTHRXHK/6yIsnFUgevu62mfwLyCAbfCgRCvKN/VNaF+ OYm6+MAbXfuyA9yK/e9mjsQNB9heXZrjmwQ+GCsO2+L9XZ47RnvNwcv9P99zdvUr+Mku6DXl P2/45GU3vWxi1Y8rq/Qbtff5ddsn7nif3LmFc3FVBzVtfuaUXh7Ant2bt8K8uKF9/4GwPgXK lMhx/hjruRZT8uw/XDYMb1cDAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrKIsWRmVeSWpSXmKPExsVy+t/xe7p/buyMMZh+h89i44z1rBbXvzxn tZh/5ByrxeqPjxktJp+ay2RxpjvXov/xa2aL8+c3sFucbXrDbnGrQcbi8q45bBafe48wWsw4 v4/JYu2Ru+wWtxtXsFkcftPOarH/ipfF7d98Ft9OPGJ0EPb49nUSi8fshossHjtn3WX32LSq k82jt/kdm8fBd3uYPPq2rGL02Hy62uPzJrkAzig9m6L80pJUhYz84hJbpWhDCyM9Q0sLPSMT Sz1DY/NYKyNTJX07m5TUnMyy1CJ9uwS9jO9br7IWnOWraNr/lq2BcTFPFyMnh4SAicS5r0sZ QWwhgaWMEi8b9SDiYhKT9m1nh7CFJf5c62KDqPnEKPH9gGoXIwcHm4CexI5VhSBhEYF6if43 l4BKuDiYBRqYJdZsv8oKkhAWCJZ49WkqE4jNIqAq0fpgGTNIL6+Al0RbOxPEeDmJm+c6mUFs TgFviV0rt0Ct8pLYcG0v0wRGvgWMDKsYRVJLi3PTc4uN9IoTc4tL89L1kvNzNzECo2jbsZ9b djB2vQs+xCjAwajEw3tg0s4YIdbEsuLK3EOMEhzMSiK8jilbYoR4UxIrq1KL8uOLSnNSiw8x mgLdNJFZSjQ5HxjheSXxhqaG5haWhubG5sZmFkrivOcNKqOEBNITS1KzU1MLUotg+pg4OKUa GJccsJ1kuUqAR+mIw/mil49i3mlZxyo/5EqzSu5xvPpiklOlRpHy5bnfXvtdTkvPvcr2KlWi aW7JN8vVIVIBK8LzLnBIXauMXFTyI2PG10RVY8tHIrtOH5batlfZJX5yP4NMWMznPXO/WHrJ xEVz3//u+X+2IaPTCgfN5wvnx86+orPeo1A5TImlOCPRUIu5qDgRAELDPlS4AgAA X-CMS-MailID: 20190419141940eucas1p295a1130863cf2e69476ca0ba11a8a102 X-Msg-Generator: CA X-RootMTR: 20190419141940eucas1p295a1130863cf2e69476ca0ba11a8a102 X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20190419141940eucas1p295a1130863cf2e69476ca0ba11a8a102 References: <1555683568-20882-1-git-send-email-l.luba@partner.samsung.com> Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Define new IDs for clocks used by Dynamic Memory Controller in Exynos5422 SoC. Acked-by: Rob Herring Signed-off-by: Lukasz Luba --- include/dt-bindings/clock/exynos5420.h | 18 +++++++++++++++++- 1 file changed, 17 insertions(+), 1 deletion(-) diff --git a/include/dt-bindings/clock/exynos5420.h b/include/dt-bindings/clock/exynos5420.h index 355f469..abb1842 100644 --- a/include/dt-bindings/clock/exynos5420.h +++ b/include/dt-bindings/clock/exynos5420.h @@ -60,6 +60,7 @@ #define CLK_MAU_EPLL 159 #define CLK_SCLK_HSIC_12M 160 #define CLK_SCLK_MPHY_IXTAL24 161 +#define CLK_SCLK_BPLL 162 /* gate clocks */ #define CLK_UART0 257 @@ -195,6 +196,18 @@ #define CLK_ACLK432_CAM 518 #define CLK_ACLK_FL1550_CAM 519 #define CLK_ACLK550_CAM 520 +#define CLK_CLKM_PHY0 521 +#define CLK_CLKM_PHY1 522 +#define CLK_ACLK_PPMU_DREX0_0 523 +#define CLK_ACLK_PPMU_DREX0_1 524 +#define CLK_ACLK_PPMU_DREX1_0 525 +#define CLK_ACLK_PPMU_DREX1_1 526 +#define CLK_PCLK_PPMU_DREX0_0 527 +#define CLK_PCLK_PPMU_DREX0_1 528 +#define CLK_PCLK_PPMU_DREX1_0 529 +#define CLK_PCLK_PPMU_DREX1_1 530 +#define CLK_CDREX_PAUSE 531 +#define CLK_CDREX_TIMING_SET 532 /* mux clocks */ #define CLK_MOUT_HDMI 640 @@ -217,6 +230,8 @@ #define CLK_MOUT_EPLL 657 #define CLK_MOUT_MAU_EPLL 658 #define CLK_MOUT_USER_MAU_EPLL 659 +#define CLK_MOUT_SCLK_SPLL 660 +#define CLK_MOUT_MX_MSPLL_CCORE_PHY 661 /* divider clocks */ #define CLK_DOUT_PIXEL 768 @@ -248,8 +263,9 @@ #define CLK_DOUT_CCLK_DREX0 794 #define CLK_DOUT_CLK2X_PHY0 795 #define CLK_DOUT_PCLK_CORE_MEM 796 +#define CLK_FF_DOUT_SPLL2 797 /* must be greater than maximal clock id */ -#define CLK_NR_CLKS 797 +#define CLK_NR_CLKS 798 #endif /* _DT_BINDINGS_CLOCK_EXYNOS_5420_H */ From patchwork Fri Apr 19 14:19:20 2019 Content-Type: text/plain; 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Fri, 19 Apr 2019 14:19:41 +0000 (GMT) From: Lukasz Luba To: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-samsung-soc@vger.kernel.org Cc: b.zolnierkie@samsung.com, krzk@kernel.org, kgene@kernel.org, cw00.choi@samsung.com, kyungmin.park@samsung.com, m.szyprowski@samsung.com, s.nawrocki@samsung.com, myungjoo.ham@samsung.com, keescook@chromium.org, tony@atomide.com, jroedel@suse.de, treding@nvidia.com, digetx@gmail.com, willy.mh.wolff.ml@gmail.com, Lukasz Luba Subject: [PATCH v6 02/10] clk: samsung: add new clocks for DMC for Exynos5422 SoC Date: Fri, 19 Apr 2019 16:19:20 +0200 Message-Id: <1555683568-20882-3-git-send-email-l.luba@partner.samsung.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1555683568-20882-1-git-send-email-l.luba@partner.samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA0WSe0hTYRjG+3bO2Y6jyWmafpkYLKNcqJVFHyqSVHCw/ggikDJq5fFCTm1H TTNwOrG82yw1zTIivC5Lh6iE90t5m6LivOWtrNQU80KmSB4367/f97zP+7wvLx+JiZsJK9I/ MIRRBMoCJHwhXtGyprPf1Fd5HYtpPozeZ5USaGD5G4FeNnURqHhxCqD0tlwe6kiUo9SpWQzp dO8EqDNmToCGlNaot/o5Hy0lNwGUpavhIU3TqAANRxfwUePcQwLV9nmg4XVTtPpxEpwxo1dX 1Dido+zB6arsUQFdVhTPp5NV83y6fv4Dj07RFgG6vD2SXiqzuWRyVejqzQT4hzEKR7ebQr++ +g5+8Lg0XPOmjlACvW0CMCEhdRKqFquwBCAkxVQBgKl1scbHMoATymTAucTUEoAd6+KdjuLB H4TBlA/g6/li4l/H97QveAIgST7lACuL7nIN5lQkHBmo3U7FqDke7PzzG+cKZtRlOBTdvs04 dQi2NMXzOBZRHlBdqcIN02zgYFc8xrEJdQFWF2r5XBCkJgVwdrhPYDCdg9NrGiObwZlWrZGt YXt6kjGIhcrkV8DAD+BUaq7R4wIbW3sIbmmMsoOl1Y4G2R3q9dM8ToaUKdT/3MPJ2BaqKzIx gyyCj+KMNzkCtUndPANbwPySDGM4DdcWCozneQFgnm4epIED2f+H5QFQBCyZUFbuy7BOgcw9 B1YmZ0MDfR1uB8nLwNbnat9sXakENRu3GgBFAsluUZ26yktMyMLYCHkDgCQmMRe5e2u9xCJv WcR9RhF0QxEawLANYD+JSyxFkbvGr4kpX1kIc4dhghnFTpVHmlgpQYm5SJp71H7jYLfwxPX1 swuo9Ep/ytd8f2uyc3Ci3GWo95SgTWzat4LPOO17GukWlZihclSpLEcsHg/Xa9Q+7vGnpRr/ t3sXYp5kZ6aO/RoLCffsH4pzTu/RS7QTsbZ2F5+1tPmN5BR6Oie4O414TI165EV/alMLzrta fI4q9nGQ4Kyf7LgUU7CyvyGVi4BYAwAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrBIsWRmVeSWpSXmKPExsVy+t/xe7p/b+yMMTg/08xi44z1rBbXvzxn tZh/5ByrxeqPjxktJp+ay2RxpjvXov/xa2aL8+c3sFucbXrDbnGrQcbi8q45bBafe48wWsw4 v4/JYu2Ru+wWtxtXsFkcftPOarH/ipfF7d98Ft9OPGJ0EPb49nUSi8fshossHjtn3WX32LSq k82jt/kdm8fBd3uYPPq2rGL02Hy62uPzJrkAzig9m6L80pJUhYz84hJbpWhDCyM9Q0sLPSMT Sz1DY/NYKyNTJX07m5TUnMyy1CJ9uwS9jCsHz7AVPNCqWLv0AGsD4w2VLkZODgkBE4nVN1+y djFycQgJLGWUOHTqEDNEQkxi0r7t7BC2sMSfa11sEEWfGCWWnD4PlODgYBPQk9ixqhCkRkSg XqL/zSWwGmaBBmaJNduvsoIkhAUCJTqXzgEbxCKgKnHsSCcTiM0r4CUxaUczC8QCOYmb5zrB FnMKeEvsWrmFDcQWAqrZcG0v0wRGvgWMDKsYRVJLi3PTc4uN9IoTc4tL89L1kvNzNzECY2nb sZ9bdjB2vQs+xCjAwajEw3tg0s4YIdbEsuLK3EOMEhzMSiK8jilbYoR4UxIrq1KL8uOLSnNS iw8xmgIdNZFZSjQ5HxjneSXxhqaG5haWhubG5sZmFkrivOcNKqOEBNITS1KzU1MLUotg+pg4 OKUaGBN/R8jr/ZB6Nyv++wK/nea2apvTEmfq3lkR/3fu/J9Zp/p/33m+xuXE5EsPhW7bHDST eRd/aGbgp+OZ78KVfx0rSXQ2axW8bilQ+dRpQ/uuKWZyep/rWdckHGe5cqW0beL/Pb/E9W0+ xcVeZtukITxZrSC2IGf3bcXsyEWRm78pHvq95EjV/FNKLMUZiYZazEXFiQAmsgS3uwIAAA== X-CMS-MailID: 20190419141942eucas1p2eaa1d17d785a27632b214a2da011a9fb X-Msg-Generator: CA X-RootMTR: 20190419141942eucas1p2eaa1d17d785a27632b214a2da011a9fb X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20190419141942eucas1p2eaa1d17d785a27632b214a2da011a9fb References: <1555683568-20882-1-git-send-email-l.luba@partner.samsung.com> Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch provides support for clocks needed for Dynamic Memory Controller in Exynos5422 SoC. It adds CDREX base register addresses, new DIV, MUX and GATE entries. Signed-off-by: Lukasz Luba --- drivers/clk/samsung/clk-exynos5420.c | 46 ++++++++++++++++++++++++++++++++---- 1 file changed, 42 insertions(+), 4 deletions(-) diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c index 34cce3c..d9e6653 100644 --- a/drivers/clk/samsung/clk-exynos5420.c +++ b/drivers/clk/samsung/clk-exynos5420.c @@ -134,6 +134,8 @@ #define SRC_CDREX 0x20200 #define DIV_CDREX0 0x20500 #define DIV_CDREX1 0x20504 +#define GATE_BUS_CDREX0 0x20700 +#define GATE_BUS_CDREX1 0x20704 #define KPLL_LOCK 0x28000 #define KPLL_CON0 0x28100 #define SRC_KFC 0x28200 @@ -248,6 +250,8 @@ static const unsigned long exynos5x_clk_regs[] __initconst = { DIV_CDREX1, SRC_KFC, DIV_KFC0, + GATE_BUS_CDREX0, + GATE_BUS_CDREX1, }; static const unsigned long exynos5800_clk_regs[] __initconst = { @@ -425,6 +429,9 @@ PNAME(mout_group13_5800_p) = { "dout_osc_div", "mout_sw_aclkfl1_550_cam" }; PNAME(mout_group14_5800_p) = { "dout_aclk550_cam", "dout_sclk_sw" }; PNAME(mout_group15_5800_p) = { "dout_osc_div", "mout_sw_aclk550_cam" }; PNAME(mout_group16_5800_p) = { "dout_osc_div", "mout_mau_epll_clk" }; +PNAME(mout_mx_mspll_ccore_phy_p) = { "sclk_bpll", "mout_sclk_dpll", + "mout_sclk_mpll", "ff_dout_spll2", + "mout_sclk_spll", "mout_sclk_epll"}; /* fixed rate clocks generated outside the soc */ static struct samsung_fixed_rate_clock @@ -450,7 +457,7 @@ static const struct samsung_fixed_factor_clock static const struct samsung_fixed_factor_clock exynos5800_fixed_factor_clks[] __initconst = { FFACTOR(0, "ff_dout_epll2", "mout_sclk_epll", 1, 2, 0), - FFACTOR(0, "ff_dout_spll2", "mout_sclk_spll", 1, 2, 0), + FFACTOR(CLK_FF_DOUT_SPLL2, "ff_dout_spll2", "mout_sclk_spll", 1, 2, 0), }; static const struct samsung_mux_clock exynos5800_mux_clks[] __initconst = { @@ -472,11 +479,14 @@ static const struct samsung_mux_clock exynos5800_mux_clks[] __initconst = { MUX(0, "mout_aclk300_disp1", mout_group5_5800_p, SRC_TOP2, 24, 2), MUX(0, "mout_aclk300_gscl", mout_group5_5800_p, SRC_TOP2, 28, 2), + MUX(CLK_MOUT_MX_MSPLL_CCORE_PHY, "mout_mx_mspll_ccore_phy", + mout_mx_mspll_ccore_phy_p, SRC_TOP7, 0, 3), + MUX(CLK_MOUT_MX_MSPLL_CCORE, "mout_mx_mspll_ccore", - mout_mx_mspll_ccore_p, SRC_TOP7, 16, 2), + mout_mx_mspll_ccore_p, SRC_TOP7, 16, 3), MUX_F(CLK_MOUT_MAU_EPLL, "mout_mau_epll_clk", mout_mau_epll_clk_5800_p, SRC_TOP7, 20, 2, CLK_SET_RATE_PARENT, 0), - MUX(0, "sclk_bpll", mout_bpll_p, SRC_TOP7, 24, 1), + MUX(CLK_SCLK_BPLL, "sclk_bpll", mout_bpll_p, SRC_TOP7, 24, 1), MUX(0, "mout_epll2", mout_epll2_5800_p, SRC_TOP7, 28, 1), MUX(0, "mout_aclk550_cam", mout_group3_5800_p, SRC_TOP8, 16, 3), @@ -648,7 +658,7 @@ static const struct samsung_mux_clock exynos5x_mux_clks[] __initconst = { MUX(0, "mout_sclk_mpll", mout_mpll_p, SRC_TOP6, 0, 1), MUX(CLK_MOUT_VPLL, "mout_sclk_vpll", mout_vpll_p, SRC_TOP6, 4, 1), - MUX(0, "mout_sclk_spll", mout_spll_p, SRC_TOP6, 8, 1), + MUX(CLK_MOUT_SCLK_SPLL, "mout_sclk_spll", mout_spll_p, SRC_TOP6, 8, 1), MUX(0, "mout_sclk_ipll", mout_ipll_p, SRC_TOP6, 12, 1), MUX(0, "mout_sclk_rpll", mout_rpll_p, SRC_TOP6, 16, 1), MUX_F(CLK_MOUT_EPLL, "mout_sclk_epll", mout_epll_p, SRC_TOP6, 20, 1, @@ -817,6 +827,8 @@ static const struct samsung_div_clock exynos5x_div_clks[] __initconst = { DIV(CLK_DOUT_CLK2X_PHY0, "dout_clk2x_phy0", "dout_sclk_cdrex", DIV_CDREX0, 3, 5), + DIV(0, "dout_pclk_drex0", "dout_cclk_drex0", DIV_CDREX0, 28, 3), + DIV(CLK_DOUT_PCLK_CORE_MEM, "dout_pclk_core_mem", "mout_mclk_cdrex", DIV_CDREX1, 8, 3), @@ -1170,6 +1182,32 @@ static const struct samsung_gate_clock exynos5x_gate_clks[] __initconst = { GATE_TOP_SCLK_ISP, 12, CLK_SET_RATE_PARENT, 0), GATE(CLK_G3D, "g3d", "mout_user_aclk_g3d", GATE_IP_G3D, 9, 0, 0), + + /* CDREX */ + GATE(CLK_CLKM_PHY0, "clkm_phy0", "dout_sclk_cdrex", + GATE_BUS_CDREX0, 0, 0, 0), + GATE(CLK_CLKM_PHY1, "clkm_phy1", "dout_sclk_cdrex", + GATE_BUS_CDREX0, 1, 0, 0), + GATE(0, "mx_mspll_ccore_phy", "mout_mx_mspll_ccore_phy", + SRC_MASK_TOP7, 0, CLK_IGNORE_UNUSED, 0), + + GATE(CLK_ACLK_PPMU_DREX1_1, "aclk_ppmu_drex1_1", "dout_aclk_cdrex1", + GATE_BUS_CDREX1, 12, CLK_IGNORE_UNUSED, 0), + GATE(CLK_ACLK_PPMU_DREX1_0, "aclk_ppmu_drex1_0", "dout_aclk_cdrex1", + GATE_BUS_CDREX1, 13, CLK_IGNORE_UNUSED, 0), + GATE(CLK_ACLK_PPMU_DREX0_1, "aclk_ppmu_drex0_1", "dout_aclk_cdrex1", + GATE_BUS_CDREX1, 14, CLK_IGNORE_UNUSED, 0), + GATE(CLK_ACLK_PPMU_DREX0_0, "aclk_ppmu_drex0_0", "dout_aclk_cdrex1", + GATE_BUS_CDREX1, 15, CLK_IGNORE_UNUSED, 0), + + GATE(CLK_PCLK_PPMU_DREX1_1, "pclk_ppmu_drex1_1", "dout_pclk_cdrex", + GATE_BUS_CDREX1, 26, CLK_IGNORE_UNUSED, 0), + GATE(CLK_PCLK_PPMU_DREX1_0, "pclk_ppmu_drex1_0", "dout_pclk_cdrex", + GATE_BUS_CDREX1, 27, CLK_IGNORE_UNUSED, 0), + GATE(CLK_PCLK_PPMU_DREX0_1, "pclk_ppmu_drex0_1", "dout_pclk_cdrex", + GATE_BUS_CDREX1, 28, CLK_IGNORE_UNUSED, 0), + GATE(CLK_PCLK_PPMU_DREX0_0, "pclk_ppmu_drex0_0", "dout_pclk_cdrex", + GATE_BUS_CDREX1, 29, CLK_IGNORE_UNUSED, 0), }; static const struct samsung_div_clock exynos5x_disp_div_clks[] __initconst = { From patchwork Fri Apr 19 14:19:21 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lukasz Luba X-Patchwork-Id: 10909599 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id EE09614DB for ; Fri, 19 Apr 2019 19:10:04 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id E240C28A3A for ; Fri, 19 Apr 2019 19:10:04 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id D636B28AC6; Fri, 19 Apr 2019 19:10:04 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 7B56828A3A for ; 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Fri, 19 Apr 2019 14:19:42 +0000 (GMT) From: Lukasz Luba To: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-samsung-soc@vger.kernel.org Cc: b.zolnierkie@samsung.com, krzk@kernel.org, kgene@kernel.org, cw00.choi@samsung.com, kyungmin.park@samsung.com, m.szyprowski@samsung.com, s.nawrocki@samsung.com, myungjoo.ham@samsung.com, keescook@chromium.org, tony@atomide.com, jroedel@suse.de, treding@nvidia.com, digetx@gmail.com, willy.mh.wolff.ml@gmail.com, Lukasz Luba Subject: [PATCH v6 03/10] clk: samsung: add BPLL rate table for Exynos 5422 SoC Date: Fri, 19 Apr 2019 16:19:21 +0200 Message-Id: <1555683568-20882-4-git-send-email-l.luba@partner.samsung.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1555683568-20882-1-git-send-email-l.luba@partner.samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA0WSe0hTcRTH/d27u92NZrcZ+cOGwUCoJM3Q+EUliRUXRXr8EVGGrrzozE3d dZUtYSpZzpk2H5mvHv9oy9LmEjXJnK/Ix3yBmVmRpWBTMx9kL3PeRf99zvec8z2HwyFxiZXw IBWqJEatksfJ+CJeXceybYfLSEP4zor7ruhJUTWBhhcmCXSnrZdAD+fGAcp7VYah7iwlyhn/ giObrUaAetLsAvRGJ0WDjaV8NJ/dBlCR7TmGHrWNCdBoaiUftdqvEah5KASN/nRFSy8/ggNu 9NKikUeX6Pp5dEPxmIA2mzL5dHb6DJ9umWnC6BsWE6Bru7T0vNnzqPCUaF8UE6e4wKh9AyNF MakFsQktrpc6K5eBDjxdpwckCSl/mFVA64GIlFCVAJbM5WNcsADg5wErzgXzAF5NsxN6IFzr aLqZs8YSqgLA9v4Ajlc7JtpCHK58ygfWmxId8kZKC98ON6/54JQdgz0/vvMcCTfqGMzQmTAH 8ygvaL76B3ewmAqBhh91gJvlCUd6M9d0IRUKGx9Y+A4jSL0TwIlBI8YVHYSZn/r4HLvBqU6L gGMp7Moz8DhmoS77ntP0ChzPKXPW7IWtnf2EY2mc2garG305OQg+flaFcxdyha+nNzhkfBWN dbecshhez5Bw1VuhxdDnXGYTrKgqdJrTcLx9WsCdsBzAxpVaPBdsKf4/7C4AJuDOaFhlNMP6 qZiLPqxcyWpU0T7n4pVmsPpZXX86v9WDxYGzVkCRQLZO/MLYEC4h5BfYZKUVQBKXbRQHRVnC JeIoefJlRh0fodbEMawVbCZ5Mnex1uXDaQkVLU9izjNMAqP+l8VIoYcOqDNSAoe7+3OhX/tx vboq4lCY5oxUteilIA8XTmUvbQ/KvX9ScXteNZfeEVw6uHviKyb6FdpksPuHlRWEzq4sa39H TtpSY+XC0HKjxxF/9yqFsr5wSHoxpyOA2LMLS3zlnT/THbx+1oh90O7XTqU0iTGb1VswO1Iz 8f5T8AmVjMfGyP2242pW/hcOyRqYVQMAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrOIsWRmVeSWpSXmKPExsVy+t/xe7r/b+yMMTj7VMRi44z1rBbXvzxn tZh/5ByrxeqPjxktJp+ay2RxpjvXov/xa2aL8+c3sFucbXrDbnGrQcbi8q45bBafe48wWsw4 v4/JYu2Ru+wWtxtXsFkcftPOarH/ipfF7d98Ft9OPGJ0EPb49nUSi8fshossHjtn3WX32LSq k82jt/kdm8fBd3uYPPq2rGL02Hy62uPzJrkAzig9m6L80pJUhYz84hJbpWhDCyM9Q0sLPSMT Sz1DY/NYKyNTJX07m5TUnMyy1CJ9uwS9jMapWQUH+SqOr/jJ2MC4laeLkZNDQsBEYs/EftYu Ri4OIYGljBKL1x1jhUiISUzat50dwhaW+HOtiw2i6BOjxP72JYxdjBwcbAJ6EjtWFYLUiAjU S/S/uQRWwyzQwCyxZvtVsEHCAv4Sd+ZPYASxWQRUJTa1/mMGsXkFvCR6fm1jhFggJ3HzXCdY nFPAW2LXyi1sILYQUM2Ga3uZJjDyLWBkWMUoklpanJueW2yoV5yYW1yal66XnJ+7iREYSduO /dy8g/HSxuBDjAIcjEo8vAcm7YwRYk0sK67MPcQowcGsJMLrmLIlRog3JbGyKrUoP76oNCe1 +BCjKdBRE5mlRJPzgVGeVxJvaGpobmFpaG5sbmxmoSTOe96gMkpIID2xJDU7NbUgtQimj4mD U6qBUUrktX+uxkfHVXNE1JufSrKZ5DW6VunG7z/Eld8Sf2Xmb4WfEzcEqu3f2+HJkSVVE2pZ 9fTjqxp2zoyWi0LT1+7X3fdmzkOT7Ya1vRuWBPzuN3OcYnxaIiKw5snuZzv+yy6L0zpjH1Ex f96Hpd5Oln1vmBquPmGZKvpsTgvrRqsCqdBy7W2MSizFGYmGWsxFxYkAntM8UboCAAA= X-CMS-MailID: 20190419141943eucas1p220d77bacfc4fcba8ec6a10f540e1a27d X-Msg-Generator: CA X-RootMTR: 20190419141943eucas1p220d77bacfc4fcba8ec6a10f540e1a27d X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20190419141943eucas1p220d77bacfc4fcba8ec6a10f540e1a27d References: <1555683568-20882-1-git-send-email-l.luba@partner.samsung.com> Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add new table rate for BPLL for Exynos5422 SoC supporting Dynamic Memory Controller frequencies for driver's DRAM timings. Signed-off-by: Lukasz Luba --- drivers/clk/samsung/clk-exynos5420.c | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c index d9e6653..ddee8bd 100644 --- a/drivers/clk/samsung/clk-exynos5420.c +++ b/drivers/clk/samsung/clk-exynos5420.c @@ -1323,6 +1323,17 @@ static const struct samsung_pll_rate_table exynos5420_pll2550x_24mhz_tbl[] __ini PLL_35XX_RATE(24 * MHZ, 200000000, 200, 3, 3), }; +static const struct samsung_pll_rate_table exynos5422_bpll_rate_table[] = { + PLL_35XX_RATE(24 * MHZ, 825000000, 275, 4, 1), + PLL_35XX_RATE(24 * MHZ, 728000000, 182, 3, 1), + PLL_35XX_RATE(24 * MHZ, 633000000, 211, 4, 1), + PLL_35XX_RATE(24 * MHZ, 543000000, 181, 2, 2), + PLL_35XX_RATE(24 * MHZ, 413000000, 413, 6, 2), + PLL_35XX_RATE(24 * MHZ, 275000000, 275, 3, 3), + PLL_35XX_RATE(24 * MHZ, 206000000, 206, 3, 3), + PLL_35XX_RATE(24 * MHZ, 165000000, 110, 2, 3), +}; + static const struct samsung_pll_rate_table exynos5420_epll_24mhz_tbl[] = { PLL_36XX_RATE(24 * MHZ, 600000000U, 100, 2, 1, 0), PLL_36XX_RATE(24 * MHZ, 400000000U, 200, 3, 2, 0), @@ -1465,7 +1476,7 @@ static void __init exynos5x_clk_init(struct device_node *np, exynos5x_plls[apll].rate_table = exynos5420_pll2550x_24mhz_tbl; exynos5x_plls[epll].rate_table = exynos5420_epll_24mhz_tbl; exynos5x_plls[kpll].rate_table = exynos5420_pll2550x_24mhz_tbl; - exynos5x_plls[bpll].rate_table = exynos5420_pll2550x_24mhz_tbl; + exynos5x_plls[bpll].rate_table = exynos5422_bpll_rate_table; } samsung_clk_register_pll(ctx, exynos5x_plls, ARRAY_SIZE(exynos5x_plls), From patchwork Fri Apr 19 14:19:22 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lukasz Luba X-Patchwork-Id: 10909563 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 6372A1515 for ; Fri, 19 Apr 2019 19:07:45 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 53CC928DFA for ; Fri, 19 Apr 2019 19:07:45 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 46F9B28DFC; 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Fri, 19 Apr 2019 14:19:45 +0000 (GMT) Received: from eusmgms1.samsung.com (unknown [182.198.249.179]) by eusmtrp1.samsung.com (KnoxPortal) with ESMTP id 20190419141944eusmtrp1dfa37bfa4f1f85a58af6bab1b495a033~W5fpf8l8O1759317593eusmtrp1a; Fri, 19 Apr 2019 14:19:44 +0000 (GMT) X-AuditID: cbfec7f2-f2dff700000010ca-1f-5cb9d9017813 Received: from eusmtip2.samsung.com ( [203.254.199.222]) by eusmgms1.samsung.com (EUCPMTA) with SMTP id 8B.02.04146.009D9BC5; Fri, 19 Apr 2019 15:19:44 +0100 (BST) Received: from AMDC3778.DIGITAL.local (unknown [106.120.51.20]) by eusmtip2.samsung.com (KnoxPortal) with ESMTPA id 20190419141943eusmtip24b293dda9237ad973e6b4f13ad4de701~W5fouhMCN3043830438eusmtip2A; Fri, 19 Apr 2019 14:19:43 +0000 (GMT) From: Lukasz Luba To: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-samsung-soc@vger.kernel.org Cc: b.zolnierkie@samsung.com, krzk@kernel.org, kgene@kernel.org, cw00.choi@samsung.com, kyungmin.park@samsung.com, m.szyprowski@samsung.com, s.nawrocki@samsung.com, myungjoo.ham@samsung.com, keescook@chromium.org, tony@atomide.com, jroedel@suse.de, treding@nvidia.com, digetx@gmail.com, willy.mh.wolff.ml@gmail.com, Lukasz Luba Subject: [PATCH v6 04/10] Documentation: dt: device tree bindings for LPDDR3 memories Date: Fri, 19 Apr 2019 16:19:22 +0200 Message-Id: <1555683568-20882-5-git-send-email-l.luba@partner.samsung.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1555683568-20882-1-git-send-email-l.luba@partner.samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA0WSa0hTYRjHe3cuO1uuTlPyTcVqYFSUGgS9YYVCHw5WkH1ISMmWHlRyU3c0 Mw1mRd61NMqWl9RCM8PbELV0upZGU+cl85KWl5FaZuWNtKhcZ9W33/N//s/lfXgpTGogHKhQ ZRSrUsrDZKQYr21dNu0Gg/X+7rWjW1BVTgWB+hcmCVRg6CTQo68TAGW/zBOg9lQFypz4iCGT qVKIOi7PCNGQ2gn1NuSSaD7dAFCOqUmAHhtGhOhNQimJns0kEkj3yhu9+b4OLb0YB562zNJi Fs7cVXfjTL1mRMhUlyWTTPqVWZJpmX0qYDK0ZYCpMcYx89XOx0WnxAeC2LDQ86zK7dAZcUhf 1QIeoXO5sJjTB9TghnMKoChI74V9+SdTgJiS0qUA9hT0AT5YAHAgtQXng3kAl/vnVjOiPxUJ vTNWVwmApqEG4l9Jt7lIYOlL0q6wrizSUmBHx8Hhfh1m8WD0jAB2rHzDLQlb2hcaP2f86YrT LnA6/b3QwhLaG3ZnNBL8NGc42JmMWVhEH4END7Ukr78VwoHnDM+H4Wt9odVvCz+0aYU8O0Fj dhrOMwfV6YXWF8TDicw8q8cDPmvrJiw7Y/QOWNHgxstecKi1lORPtA4OfNpgkbFVzKq9jfGy BCZdk/Lu7VCb1iXgeSMsKb9lbc5AzZRRyF8nH8Ca4nLyOtis+T/sHgBlwJ6N5hTBLLdHyca4 cnIFF60Mdg0MV1SD1b9l/Nk2VwcWe87qAU0BmY2kOaveX0rIz3OxCj2AFCazk3gFaf2lkiB5 7EVWFR6gig5jOT1wpHCZvSRuzaiflA6WR7HnWDaCVf3NCiiRgxoUTeU0bbvz0rx4887dsUHO QZ60Il67b3ociw81b41qjpJNjkUefeId2G7rGaDUb/KpC9IWG5QMsIkV+PwaUNyfNb8OTP6y a9qxyfX0dKVfQJvvXLjG+CNGmejH5R/UTeQ+6PLZf5VsHXavXn/i2HDL0uZ3antHj0bfNZRO dEnTIcO5EPmenZiKk/8G6wiKPFcDAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrOIsWRmVeSWpSXmKPExsVy+t/xe7oMN3fGGOzv17PYOGM9q8X1L89Z LeYfOcdqsfrjY0aLyafmMlmc6c616H/8mtni/PkN7BZnm96wW9xqkLG4vGsOm8Xn3iOMFjPO 72OyWHvkLrvF7cYVbBaH37SzWuy/4mVx+zefxbcTjxgdhD2+fZ3E4jG74SKLx85Zd9k9Nq3q ZPPobX7H5nHw3R4mj74tqxg9Np+u9vi8SS6AM0rPpii/tCRVISO/uMRWKdrQwkjP0NJCz8jE Us/Q2DzWyshUSd/OJiU1J7MstUjfLkEv4+rGLywF+1Urvs64ytjAOFGui5GTQ0LARKLx8htG EFtIYCmjxNxOQYi4mMSkfdvZIWxhiT/Xuti6GLmAaj4xSlzYsBwowcHBJqAnsWNVIUiNiEC9 RP+bS2A1zAINzBJrtl9lBUkIC4RKrHrbzwxiswioSrzsfQY2lFfAS+Ji315WiAVyEjfPdYLV cAp4S+xauYUN4iAviQ3X9jJNYORbwMiwilEktbQ4Nz232FCvODG3uDQvXS85P3cTIzCSth37 uXkH46WNwYcYBTgYlXh4D0zaGSPEmlhWXJl7iFGCg1lJhNcxZUuMEG9KYmVValF+fFFpTmrx IUZToKMmMkuJJucDozyvJN7Q1NDcwtLQ3Njc2MxCSZz3vEFllJBAemJJanZqakFqEUwfEwen VAOjo7PW89WM31pnT3qiZHvELerCzluO0W9dqnZu0XwRwb1l0/sdUrWZAgKdL/y3Kt5P/F/1 97r+Lq5dR1sDxY00XLVy2pqO9iV/ezV31+fGoJypBkdP6bytW+o3oWAR48GJCafnavvz+Nz+ 5/r6ygah71v3GR/uuqeaFNkqfoDxie7efM1Hr1pilFiKMxINtZiLihMBvG/z/boCAAA= X-CMS-MailID: 20190419141945eucas1p1c95d65f261f82da5c856c0f2fcf1ce87 X-Msg-Generator: CA X-RootMTR: 20190419141945eucas1p1c95d65f261f82da5c856c0f2fcf1ce87 X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20190419141945eucas1p1c95d65f261f82da5c856c0f2fcf1ce87 References: <1555683568-20882-1-git-send-email-l.luba@partner.samsung.com> Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The device tree bindings for LPDDR3 SDRAM memories. For specifying the AC timing parameters of the memory device the 'lpddr3' binding uses binding 'lpddr2-timings'. Signed-off-by: Lukasz Luba --- .../devicetree/bindings/lpddr3/lpddr3-timings.txt | 57 +++++++++++++ .../devicetree/bindings/lpddr3/lpddr3.txt | 93 ++++++++++++++++++++++ 2 files changed, 150 insertions(+) create mode 100644 Documentation/devicetree/bindings/lpddr3/lpddr3-timings.txt create mode 100644 Documentation/devicetree/bindings/lpddr3/lpddr3.txt diff --git a/Documentation/devicetree/bindings/lpddr3/lpddr3-timings.txt b/Documentation/devicetree/bindings/lpddr3/lpddr3-timings.txt new file mode 100644 index 0000000..ebf3e00 --- /dev/null +++ b/Documentation/devicetree/bindings/lpddr3/lpddr3-timings.txt @@ -0,0 +1,57 @@ +* AC timing parameters of LPDDR3 memories for a given speed-bin. +* The structures are based on LPDDR2 and extended where needed. + +Required properties: +- compatible : Should be "jedec,lpddr3-timings" +- min-freq : minimum DDR clock frequency for the speed-bin. Type is +- max-freq : maximum DDR clock frequency for the speed-bin. Type is + +Optional properties: + +The following properties represent AC timing parameters from the memory +data-sheet of the device for a given speed-bin. All these properties are +of type and the default unit is ps (pico seconds). +- tRFC +- tRRD +- tRPab +- tRPpb +- tRCD +- tRC +- tRAS +- tWTR +- tWR +- tRTP +- tW2W-C2C +- tR2R-C2C +- tFAW +- tXSR +- tXP +- tCKE +- tCKESR +- tMRD + +Example: + +timings_samsung_K3QF2F20DB_800mhz: lpddr3-timings@0 { + compatible = "jedec,lpddr3-timings"; + min-freq = <100000000>; + max-freq = <800000000>; + tRFC = <65000>; + tRRD = <6000>; + tRPab = <12000>; + tRPpb = <12000>; + tRCD = <10000>; + tRC = <33750>; + tRAS = <23000>; + tWTR = <3750>; + tWR = <7500>; + tRTP = <3750>; + tW2W-C2C = <0>; + tR2R-C2C = <0>; + tFAW = <25000>; + tXSR = <70000>; + tXP = <3750>; + tCKE = <3750>; + tCKESR = <3750>; + tMRD = <7000>; +}; diff --git a/Documentation/devicetree/bindings/lpddr3/lpddr3.txt b/Documentation/devicetree/bindings/lpddr3/lpddr3.txt new file mode 100644 index 0000000..fc7875c --- /dev/null +++ b/Documentation/devicetree/bindings/lpddr3/lpddr3.txt @@ -0,0 +1,93 @@ +* LPDDR3 SDRAM memories compliant to JEDEC JESD209-2 + +Required properties: +- compatible : Should be - "jedec,lpddr3" +- density : representing density in Mb (Mega bits) +- io-width : representing bus width. Possible values are 8, 16, 32, 64 + +Optional properties: + +The following optional properties represent the minimum value of some AC +timing parameters of the DDR device in terms of number of clock cycles. +These values shall be obtained from the device data-sheet. +- tRFC-min-tck +- tRRD-min-tck +- tRPab-min-tck +- tRPpb-min-tck +- tRCD-min-tck +- tRC-min-tck +- tRAS-min-tck +- tWTR-min-tck +- tWR-min-tck +- tRTP-min-tck +- tW2W-C2C-min-tck +- tR2R-C2C-min-tck +- tWL-min-tck +- tDQSCK-min-tck +- tRL-min-tck +- tFAW-min-tck +- tXSR-min-tck +- tXP-min-tck +- tCKE-min-tck +- tCKESR-min-tck +- tMRD-min-tck + +Child nodes: +- The lpddr3 node may have one or more child nodes of type "lpddr3-timings". + "lpddr3-timings" provides AC timing parameters of the device for + a given speed-bin. Please see Documentation/devicetree/ + bindings/lpddr3/lpddr3-timings.txt for more information on "lpddr3-timings" + +Example: + +samsung_K3QF2F20DB: lpddr3 { + compatible = "Samsung,K3QF2F20DB","jedec,lpddr3"; + density = <16384>; + io-width = <32>; + + tRFC-min-tck = <17>; + tRRD-min-tck = <2>; + tRPab-min-tck = <2>; + tRPpb-min-tck = <2>; + tRCD-min-tck = <3>; + tRC-min-tck = <6>; + tRAS-min-tck = <5>; + tWTR-min-tck = <2>; + tWR-min-tck = <7>; + tRTP-min-tck = <2>; + tW2W-C2C-min-tck = <0>; + tR2R-C2C-min-tck = <0>; + tWL-min-tck = <8>; + tDQSCK-min-tck = <5>; + tRL-min-tck = <14>; + tFAW-min-tck = <5>; + tXSR-min-tck = <12>; + tXP-min-tck = <2>; + tCKE-min-tck = <2>; + tCKESR-min-tck = <2>; + tMRD-min-tck = <5>; + + timings_samsung_K3QF2F20DB_800mhz: lpddr3-timings@0 { + compatible = "jedec,lpddr3-timings"; + min-freq = <100000000>; + max-freq = <800000000>; + tRFC = <65000>; + tRRD = <6000>; + tRPab = <12000>; + tRPpb = <12000>; + tRCD = <10000>; + tRC = <33750>; + tRAS = <23000>; + tWTR = <3750>; + tWR = <7500>; + tRTP = <3750>; + tW2W-C2C = <0>; + tR2R-C2C = <0>; + tFAW = <25000>; + tXSR = <70000>; + tXP = <3750>; + tCKE = <3750>; + tCKESR = <3750>; + tMRD = <7000>; + }; +} From patchwork Fri Apr 19 14:19:23 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lukasz Luba X-Patchwork-Id: 10909587 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 465561515 for ; Fri, 19 Apr 2019 19:09:58 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 3A98D28A3A for ; Fri, 19 Apr 2019 19:09:58 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 2EF4028AA2; Fri, 19 Apr 2019 19:09:58 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 62EA528A3A for ; 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Fri, 19 Apr 2019 14:19:45 +0000 (GMT) From: Lukasz Luba To: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-samsung-soc@vger.kernel.org Cc: b.zolnierkie@samsung.com, krzk@kernel.org, kgene@kernel.org, cw00.choi@samsung.com, kyungmin.park@samsung.com, m.szyprowski@samsung.com, s.nawrocki@samsung.com, myungjoo.ham@samsung.com, keescook@chromium.org, tony@atomide.com, jroedel@suse.de, treding@nvidia.com, digetx@gmail.com, willy.mh.wolff.ml@gmail.com, Lukasz Luba Subject: [PATCH v6 05/10] drivers: memory: extend of_memory by LPDDR3 support Date: Fri, 19 Apr 2019 16:19:23 +0200 Message-Id: <1555683568-20882-6-git-send-email-l.luba@partner.samsung.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1555683568-20882-1-git-send-email-l.luba@partner.samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA0WSe0hTYRjG/XbOzs5Ws9OMfLFhMQqyyO71VVJGBSf7o0goqIGuPGi0qe2k VkbNisrlJVRaWJZS4FqatZaoXSyvkemUWl7WRfSPaM5FeMk0I09n1X+/73ue531ePj6aUDVK Q+hDiUc5Y6JOr6EUZGXTD+cSortau2xweAZ+cLVCijuHP0vxzYY2Kb77rR/h/FdFEvz6kgHn 9g8Q2Om8L8OtZ7wy3GNS4zc11yk8lN2A8FXnMwkub/ggw+4MK4XrvRekuPZtFHZPBOLRl30o MogdHckj2WumDpKtLvwgY+22TIrNPuuj2Be+JxI2x2FD7MOWdHbIHrpLvk8REcfpD6VyxqUb YxUJX8p9RHJ35LG2PgtlQplrzEhOA7MKzOceycxIQasYK4LWnkEkHoYRfCp46VeGEFhz7dTf iPtrDiUKpQgslizqX2SkqmAqQtMUEw5VtiNCYBaTDu87awnBQzBeCbSOj5GCEMTshNpsr0Rg klkAbYPDUoGVTBSYO9z+tlDobsskBJYzO6DmjuNPGTAfZTBe7CJE01Zwdtb7OQg8zQ6ZyGpo yc8iRebBlF2CRD4J/blFfs8GqG/ukApLE0wYVNQsFRCYzeCZiBYxELoGZwpmYgrzKi2EeK2E i+dV4oyF4Mhql4g8G0rLrvhnszDwvd7/oDcQtLy9jS6juYX/u4oRsqFgLoU3xHP8ykQuLZzX GfiUxPjwg0kGO5r6XC2/mkeq0LOfB+oQQyPNdOXzvGqtSqpL5Y8b6hDQhGaWcnOcQ6tSxumO n+CMSTHGFD3H16E5NKkJVqYH9O5XMfG6o9xhjkvmjH9VCS0PMaG9gRp9OJt/d70qZjueF6bq SoJX7oHKAEXJxO7V83voU0TvEu3ZpqEt+9e5YjOeRqWFJvXa7lU0le1VL8jaectXIo9ob/VM Pq3dU6Ze4eqK3NO+9qM+fZuh0LY6Z9rk4gfRn9c6rdqw8prk4ghbhOW0q+8CuanS07hm+Zgt 9fHCdxqST9AtX0QYed1vPwl1bFgDAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrOIsWRmVeSWpSXmKPExsVy+t/xe7pMN3fGGMxZzWWxccZ6VovrX56z Wsw/co7VYvXHx4wWk0/NZbI4051r0f/4NbPF+fMb2C3ONr1ht7jVIGNxedccNovPvUcYLWac 38dksfbIXXaL240r2CwOv2lntdh/xcvi9m8+i28nHjE6CHt8+zqJxWN2w0UWj52z7rJ7bFrV yebR2/yOzePguz1MHn1bVjF6bD5d7fF5k1wAZ5SeTVF+aUmqQkZ+cYmtUrShhZGeoaWFnpGJ pZ6hsXmslZGpkr6dTUpqTmZZapG+XYJexsu175gLbjpUnHs0na2BsdOsi5GTQ0LAROL2+z62 LkYuDiGBpYwSPc9eMkMkxCQm7dvODmELS/y51gVV9IlR4vmNaUxdjBwcbAJ6EjtWFYLUiAjU S/S/uQRWwyzQwCyxZvtVVpAaYQFfiSuNyiA1LAKqEufefmEFsXkFvCS6Lt5mg5gvJ3HzXCfY Xk4Bb4ldK7eAxYWAajZc28s0gZFvASPDKkaR1NLi3PTcYkO94sTc4tK8dL3k/NxNjMBI2nbs 5+YdjJc2Bh9iFOBgVOLhPTBpZ4wQa2JZcWXuIUYJDmYlEV7HlC0xQrwpiZVVqUX58UWlOanF hxhNgY6ayCwlmpwPjPK8knhDU0NzC0tDc2NzYzMLJXHe8waVUUIC6YklqdmpqQWpRTB9TByc Ug2MielHljzaOK1ohV1PmMjpzeIzej9dnLrmVsiZ/hTvFx2N3+4r1N3trTmRlcCze/GJ/3lJ E7JtVALnCqRsUeTUFd2zdUPGUQPGFMZjHEysHEJXU0Wm1ft82Xn8iFCIvUfmuhNmD98+Vb6s 1JF2gEHwVLX2lwn1Cl+68twMDDaU6a13nbcx5A2/EktxRqKhFnNRcSIA0dcLtboCAAA= X-CMS-MailID: 20190419141946eucas1p2fffda29e18080fd3573f625f0cf2b7f8 X-Msg-Generator: CA X-RootMTR: 20190419141946eucas1p2fffda29e18080fd3573f625f0cf2b7f8 X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20190419141946eucas1p2fffda29e18080fd3573f625f0cf2b7f8 References: <1555683568-20882-1-git-send-email-l.luba@partner.samsung.com> Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The patch adds AC timings information needed to support LPDDR3 and memory controllers. The structure is used in of_memory and currently in Exynos 5422 DMC. Add parsing data needed for LPDDR3 support. It is currently used in Exynos5422 Dynamic Memory Controller. Signed-off-by: Lukasz Luba --- drivers/memory/of_memory.c | 125 +++++++++++++++++++++++++++++++++++++++++++++ drivers/memory/of_memory.h | 20 +++++++- include/memory/jedec_ddr.h | 62 ++++++++++++++++++++++ 3 files changed, 206 insertions(+), 1 deletion(-) diff --git a/drivers/memory/of_memory.c b/drivers/memory/of_memory.c index 2f5ed73..7a77174 100644 --- a/drivers/memory/of_memory.c +++ b/drivers/memory/of_memory.c @@ -152,3 +152,128 @@ const struct lpddr2_timings *of_get_ddr_timings(struct device_node *np_ddr, return lpddr2_jedec_timings; } EXPORT_SYMBOL(of_get_ddr_timings); + + +const struct lpddr3_min_tck *of_lpddr3_get_min_tck(struct device_node *np, + struct device *dev) +{ + int ret = 0; + struct lpddr3_min_tck *min; + + min = devm_kzalloc(dev, sizeof(*min), GFP_KERNEL); + if (!min) + goto default_min_tck; + + ret |= of_property_read_u32(np, "tRFC-min-tck", &min->tRFC); + ret |= of_property_read_u32(np, "tRRD-min-tck", &min->tRRD); + ret |= of_property_read_u32(np, "tRPab-min-tck", &min->tRPab); + ret |= of_property_read_u32(np, "tRPpb-min-tck", &min->tRPpb); + ret |= of_property_read_u32(np, "tRCD-min-tck", &min->tRCD); + ret |= of_property_read_u32(np, "tRC-min-tck", &min->tRC); + ret |= of_property_read_u32(np, "tRAS-min-tck", &min->tRAS); + ret |= of_property_read_u32(np, "tWTR-min-tck", &min->tWTR); + ret |= of_property_read_u32(np, "tWR-min-tck", &min->tWR); + ret |= of_property_read_u32(np, "tRTP-min-tck", &min->tRTP); + ret |= of_property_read_u32(np, "tW2W-C2C-min-tck", &min->tW2W_C2C); + ret |= of_property_read_u32(np, "tR2R-C2C-min-tck", &min->tR2R_C2C); + ret |= of_property_read_u32(np, "tWL-min-tck", &min->tWL); + ret |= of_property_read_u32(np, "tDQSCK-min-tck", &min->tDQSCK); + ret |= of_property_read_u32(np, "tRL-min-tck", &min->tRL); + ret |= of_property_read_u32(np, "tFAW-min-tck", &min->tFAW); + ret |= of_property_read_u32(np, "tXSR-min-tck", &min->tXSR); + ret |= of_property_read_u32(np, "tXP-min-tck", &min->tXP); + ret |= of_property_read_u32(np, "tCKE-min-tck", &min->tCKE); + ret |= of_property_read_u32(np, "tCKESR-min-tck", &min->tCKESR); + ret |= of_property_read_u32(np, "tMRD-min-tck", &min->tMRD); + + if (ret) { + dev_warn(dev, "%s: errors while parsing min-tck values\n", + __func__); + devm_kfree(dev, min); + goto default_min_tck; + } + + return min; + +default_min_tck: + dev_warn(dev, "%s: using default min-tck values\n", __func__); + return NULL; +} +EXPORT_SYMBOL(of_lpddr3_get_min_tck); + +static int of_lpddr3_do_get_timings(struct device_node *np, + struct lpddr3_timings *tim) +{ + int ret; + + ret = of_property_read_u32(np, "max-freq", &tim->max_freq); + ret |= of_property_read_u32(np, "min-freq", &tim->min_freq); + ret |= of_property_read_u32(np, "tRFC", &tim->tRFC); + ret |= of_property_read_u32(np, "tRRD", &tim->tRRD); + ret |= of_property_read_u32(np, "tRPab", &tim->tRPab); + ret |= of_property_read_u32(np, "tRPpb", &tim->tRPpb); + ret |= of_property_read_u32(np, "tRCD", &tim->tRCD); + ret |= of_property_read_u32(np, "tRC", &tim->tRC); + ret |= of_property_read_u32(np, "tRAS", &tim->tRAS); + ret |= of_property_read_u32(np, "tWTR", &tim->tWTR); + ret |= of_property_read_u32(np, "tWR", &tim->tWR); + ret |= of_property_read_u32(np, "tRTP", &tim->tRTP); + ret |= of_property_read_u32(np, "tW2W-C2C", &tim->tW2W_C2C); + ret |= of_property_read_u32(np, "tR2R-C2C", &tim->tR2R_C2C); + ret |= of_property_read_u32(np, "tFAW", &tim->tFAW); + ret |= of_property_read_u32(np, "tXSR", &tim->tXSR); + ret |= of_property_read_u32(np, "tXP", &tim->tXP); + ret |= of_property_read_u32(np, "tCKE", &tim->tCKE); + ret |= of_property_read_u32(np, "tCKESR", &tim->tCKESR); + ret |= of_property_read_u32(np, "tMRD", &tim->tMRD); + + return ret; +} + +const struct lpddr3_timings *of_lpddr3_get_ddr_timings(struct device_node *np_ddr, + struct device *dev, u32 device_type, u32 *nr_frequencies) +{ + struct lpddr3_timings *timings = NULL; + u32 arr_sz = 0, i = 0; + struct device_node *np_tim; + char *tim_compat = NULL; + + switch (device_type) { + case DDR_TYPE_LPDDR3: + tim_compat = "jedec,lpddr3-timings"; + break; + default: + dev_warn(dev, "%s: un-supported memory type\n", __func__); + } + + for_each_child_of_node(np_ddr, np_tim) + if (of_device_is_compatible(np_tim, tim_compat)) + arr_sz++; + + if (arr_sz) + timings = devm_kcalloc(dev, arr_sz, sizeof(*timings), + GFP_KERNEL); + + if (!timings) + goto default_timings; + + for_each_child_of_node(np_ddr, np_tim) { + if (of_device_is_compatible(np_tim, tim_compat)) { + if (of_lpddr3_do_get_timings(np_tim, &timings[i])) { + devm_kfree(dev, timings); + goto default_timings; + } + i++; + } + } + + *nr_frequencies = arr_sz; + + return timings; + +default_timings: + dev_warn(dev, "%s: using default timings\n", __func__); + *nr_frequencies = 0; + return NULL; +} +EXPORT_SYMBOL(of_lpddr3_get_ddr_timings); diff --git a/drivers/memory/of_memory.h b/drivers/memory/of_memory.h index ef2514f..8cf2ce6 100644 --- a/drivers/memory/of_memory.h +++ b/drivers/memory/of_memory.h @@ -18,6 +18,11 @@ extern const struct lpddr2_min_tck *of_get_min_tck(struct device_node *np, extern const struct lpddr2_timings *of_get_ddr_timings(struct device_node *np_ddr, struct device *dev, u32 device_type, u32 *nr_frequencies); +extern const struct lpddr3_min_tck + *of_lpddr3_get_min_tck(struct device_node *np, struct device *dev); +extern const struct lpddr3_timings + *of_lpddr3_get_ddr_timings(struct device_node *np_ddr, + struct device *dev, u32 device_type, u32 *nr_frequencies); #else static inline const struct lpddr2_min_tck *of_get_min_tck(struct device_node *np, struct device *dev) @@ -31,6 +36,19 @@ static inline const struct lpddr2_timings { return NULL; } -#endif /* CONFIG_OF && CONFIG_DDR */ + +static inline const struct lpddr3_min_tck + *of_lpddr3_get_min_tck(struct device_node *np, struct device *dev) +{ + return NULL; +} + +static inline const struct lpddr3_timings + *of_lpddr3_get_ddr_timings(struct device_node *np_ddr, + struct device *dev, u32 device_type, u32 *nr_frequencies) +{ + return NULL; +} +#endif #endif /* __LINUX_MEMORY_OF_REG_ */ diff --git a/include/memory/jedec_ddr.h b/include/memory/jedec_ddr.h index ddad0f8..3601825 100644 --- a/include/memory/jedec_ddr.h +++ b/include/memory/jedec_ddr.h @@ -32,6 +32,7 @@ #define DDR_TYPE_LPDDR2_S4 3 #define DDR_TYPE_LPDDR2_S2 4 #define DDR_TYPE_LPDDR2_NVM 5 +#define DDR_TYPE_LPDDR3 6 /* DDR IO width */ #define DDR_IO_WIDTH_4 1 @@ -172,4 +173,65 @@ extern const struct lpddr2_timings lpddr2_jedec_timings[NUM_DDR_TIMING_TABLE_ENTRIES]; extern const struct lpddr2_min_tck lpddr2_jedec_min_tck; + +/* + * Structure for timings for LPDDR3 based on LPDDR2 plus additional fields. + * All parameters are in pico seconds(ps) unless explicitly indicated + * with a suffix like tRAS_max_ns below + */ +struct lpddr3_timings { + u32 max_freq; + u32 min_freq; + u32 tRFC; + u32 tRRD; + u32 tRPab; + u32 tRPpb; + u32 tRCD; + u32 tRC; + u32 tRAS; + u32 tWTR; + u32 tWR; + u32 tRTP; + u32 tW2W_C2C; + u32 tR2R_C2C; + u32 tWL; + u32 tDQSCK; + u32 tRL; + u32 tFAW; + u32 tXSR; + u32 tXP; + u32 tCKE; + u32 tCKESR; + u32 tMRD; +}; + +/* + * Min value for some parameters in terms of number of tCK cycles(nCK) + * Please set to zero parameters that are not valid for a given memory + * type + */ +struct lpddr3_min_tck { + u32 tRFC; + u32 tRRD; + u32 tRPab; + u32 tRPpb; + u32 tRCD; + u32 tRC; + u32 tRAS; + u32 tWTR; + u32 tWR; + u32 tRTP; + u32 tW2W_C2C; + u32 tR2R_C2C; + u32 tWL; + u32 tDQSCK; + u32 tRL; + u32 tFAW; + u32 tXSR; + u32 tXP; + u32 tCKE; + u32 tCKESR; + u32 tMRD; +}; + #endif /* __LINUX_JEDEC_DDR_H */ From patchwork Fri Apr 19 14:19:24 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lukasz Luba X-Patchwork-Id: 10909579 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id BE74D1515 for ; Fri, 19 Apr 2019 19:09:40 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id AF7E028DFB for ; Fri, 19 Apr 2019 19:09:40 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id A307828DFD; Fri, 19 Apr 2019 19:09:40 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 3723028DFB for ; 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Fri, 19 Apr 2019 14:19:46 +0000 (GMT) From: Lukasz Luba To: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-samsung-soc@vger.kernel.org Cc: b.zolnierkie@samsung.com, krzk@kernel.org, kgene@kernel.org, cw00.choi@samsung.com, kyungmin.park@samsung.com, m.szyprowski@samsung.com, s.nawrocki@samsung.com, myungjoo.ham@samsung.com, keescook@chromium.org, tony@atomide.com, jroedel@suse.de, treding@nvidia.com, digetx@gmail.com, willy.mh.wolff.ml@gmail.com, Lukasz Luba Subject: [PATCH v6 06/10] dt-bindings: memory-controllers: add Exynos5422 DMC device description Date: Fri, 19 Apr 2019 16:19:24 +0200 Message-Id: <1555683568-20882-7-git-send-email-l.luba@partner.samsung.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1555683568-20882-1-git-send-email-l.luba@partner.samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA0WSe0hTURzHO7uPXa3JbUr+UElaCBW1HhYcMHpAyMUgQghkCTX1opGbtqvm K5pKj2nTsrKYmqnE1LTMRrURPVRaZGqStcykVMrXtHQmvbC63Fn/fX+f3/f3Pb9zOAyhbKOC mEP6NN6g1yaraF/yzpPvXevIPnvsBttQML51+SaFXbMjFK5q76Lw9elhhM8/q5Th50U6XDI8 QeDu7mY57sx3y/FbYwh+6aigscfcjvDl7gcy3NQ+IMf9eXU0bnOfovDD3ijc/9MPzz0dQjv8 ubmvpSRXbuwhObtlQM61NJhozlwwRXOPp+7LuGJbA+Jud+Rwnpble300vlsT+ORDGbxh/baD vkm1eS4qtTM4s6DXLTeikWWFiGGA3Qwus6YQ+TJKtg7B9FezTCpmEbjGTKRUeBDUOKvohYmX ZUkStyKYryon/030eppJ0USzarjXcKQQ+TABbA68cz0kRA/BumXQ+eMbKTb82Tj4/PiWXPST bBg0FkWKWMFGQdfAC5mogV0OfV0mQtQ+7G5w1NtoMQfYITk8cg/KJdMuOOcopSXtD+NOm5eH wG97lTdIAKO5Gkk6F4ZLKr2eCGhz9lDiDgS7Gm461kt4J4y9uOC9rx+8mVwqYuKvLL1ziZCw Ak6fVEruVWA7s7DxMrA2lnnDOZis7aCk17mCoL7mBn0WhVr+H3YVoQYUyKcLukRe2KTnj6oF rU5I1yeq41N0Lejv1+qYd87eQ45fca2IZZBqieJRqT1WSWkzhCxdKwKGUAUodibYYpWKBG1W Nm9IOWBIT+aFVhTMkKpARc6iD/uVbKI2jT/M86m8YaErY3yCjCghZl9T84nwiz1BprXZoZ8a LZEjafV3r1lmtl/iRn+ordawRSsD/HMr5q2a2V+CenyF7Ism6FUyrKyIKo5+kLm7pbbEFJoV 3xlizz+/hYf3g6OuvXmTzo85hwviv83EvI7wHO9+Tb2pjHbfz5gQjs3tmZ7TlIeXDRAbLbi6 uGyxihSStBvXEAZB+wf2G0+sVgMAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrGIsWRmVeSWpSXmKPExsVy+t/xe7rMN3fGGMx9qGaxccZ6VovrX56z Wsw/co7VYvXHx4wWk0/NZbI4051r0f/4NbPF+fMb2C3ONr1ht7jVIGNxedccNovPvUcYLWac 38dksfbIXXaL240r2CwOv2lntdh/xcvi9m8+i28nHjE6CHt8+zqJxWN2w0UWj52z7rJ7bFrV yebR2/yOzePguz1MHn1bVjF6bD5d7fF5k1wAZ5SeTVF+aUmqQkZ+cYmtUrShhZGeoaWFnpGJ pZ6hsXmslZGpkr6dTUpqTmZZapG+XYJexuLG66wFZ6Urmq+8YW9gfC7WxcjBISFgInF5WkYX IxeHkMBSRok/N/awdTFyAsXFJCbt284OYQtL/LnWxQZR9IlR4tKFSYwgzWwCehI7VhWC1IgI 1Ev0v7kEVsMs0MAssWb7VVaQhLBAgsT27klMIPUsAqoSa7rdQMK8Al4S5+5eYIKYLydx81wn M4jNKeAtsWvlFrAbhIBqNlzbyzSBkW8BI8MqRpHU0uLc9NxiI73ixNzi0rx0veT83E2MwDja duznlh2MXe+CDzEKcDAq8fAemLQzRog1say4MvcQowQHs5IIr2PKlhgh3pTEyqrUovz4otKc 1OJDjKZAN01klhJNzgfGeF5JvKGpobmFpaG5sbmxmYWSOO95g8ooIYH0xJLU7NTUgtQimD4m Dk6pBsYtwlceC64KnBUz8/Ex2zMCRU9KDbpSOLcmSUlXvWJfd3EOm3Gn9PY7K2PnXWYuXF3N InWvWo5/p2q8X6DqqtVdvT9ezv3W05ngovTAb5vr7bRyqaX3Fm9nKPLxSbrv8M1NddEtj89T OcqC7hSvPZx8O99FeVWGhaW7mkf9vO1BqRocdft/XFViKc5INNRiLipOBADuAmQ9uQIAAA== X-CMS-MailID: 20190419141947eucas1p13a27605e04169ab528ef5bfb385eddbc X-Msg-Generator: CA X-RootMTR: 20190419141947eucas1p13a27605e04169ab528ef5bfb385eddbc X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20190419141947eucas1p13a27605e04169ab528ef5bfb385eddbc References: <1555683568-20882-1-git-send-email-l.luba@partner.samsung.com> Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The patch adds description for DT binding for a new Exynos5422 Dynamic Memory Controller device. Signed-off-by: Lukasz Luba --- .../bindings/memory-controllers/exynos5422-dmc.txt | 73 ++++++++++++++++++++++ 1 file changed, 73 insertions(+) create mode 100644 Documentation/devicetree/bindings/memory-controllers/exynos5422-dmc.txt diff --git a/Documentation/devicetree/bindings/memory-controllers/exynos5422-dmc.txt b/Documentation/devicetree/bindings/memory-controllers/exynos5422-dmc.txt new file mode 100644 index 0000000..133b3cc --- /dev/null +++ b/Documentation/devicetree/bindings/memory-controllers/exynos5422-dmc.txt @@ -0,0 +1,73 @@ +* Exynos5422 frequency and voltage scaling for Dynamic Memory Controller device + +The Samsung Exynos5422 SoC has DMC (Dynamic Memory Controller) to which the DRAM +memory chips are connected. The driver is to monitor the controller in runtime +and switch frequency and voltage. To monitor the usage of the controller in +runtime, the driver uses the PPMU (Platform Performance Monitoring Unit), which +is able to measure the current load of the memory. +When 'userspace' governor is used for the driver, an application is able to +switch the DMC and memory frequency. + +Required properties for DMC device for Exynos5422: +- compatible: Should be "samsung,exynos5422-bus". +- clock-names : the name of clock used by the bus, "bus". +- clocks : phandles for clock specified in "clock-names" property. +- devfreq-events : phandles for PPMU devices connected to this DMC. +- vdd-supply : phandle for voltage regulator which is connected. +- reg : registers of two CDREX controllers, chip information, clocks subsystem. +- operating-points-v2 : phandle for OPPs described in v2 definition. +- device-handle : phandle of the connected DRAM memory device. For more + information please refer to Documentation +- devfreq-events : phandles of the PPMU events used by the controller. + +Example: + + ppmu_dmc0_0: ppmu@10d00000 { + compatible = "samsung,exynos-ppmu"; + reg = <0x10d00000 0x2000>; + clocks = <&clock CLK_PCLK_PPMU_DREX0_0>; + clock-names = "ppmu"; + status = "okay"; + events { + ppmu_event_dmc0_0: ppmu-event3-dmc0_0 { + event-name = "ppmu-event3-dmc0_0"; + }; + }; + }; + + dmc: memory-controller@10c20000 { + compatible = "samsung,exynos5422-dmc"; + reg = <0x10c20000 0x10000>, <0x10c30000 0x10000>, + <0x10000000 0x1000>, <0x10030000 0x1000>; + clocks = <&clock CLK_FOUT_SPLL>, + <&clock CLK_MOUT_SCLK_SPLL>, + <&clock CLK_FF_DOUT_SPLL2>, + <&clock CLK_FOUT_BPLL>, + <&clock CLK_MOUT_BPLL>, + <&clock CLK_SCLK_BPLL>, + <&clock CLK_MOUT_MX_MSPLL_CCORE>, + <&clock CLK_MOUT_MX_MSPLL_CCORE_PHY>, + <&clock CLK_MOUT_MCLK_CDREX>, + <&clock CLK_DOUT_CLK2X_PHY0>, + <&clock CLK_CLKM_PHY0>, + <&clock CLK_CLKM_PHY1>; + clock-names = "fout_spll", + "mout_sclk_spll", + "ff_dout_spll2", + "fout_bpll", + "mout_bpll", + "sclk_bpll", + "mout_mx_mspll_ccore", + "mout_mx_mspll_ccore_phy", + "mout_mclk_cdrex", + "dout_clk2x_phy0", + "clkm_phy0", + "clkm_phy1"; + status = "okay"; + operating-points-v2 = <&dmc_opp_table>; + devfreq-events = <&ppmu_event3_dmc0_0>, <&ppmu_event3_dmc0_1>, + <&ppmu_event3_dmc1_0>, <&ppmu_event3_dmc1_1>; + operating-points-v2 = <&dmc_opp_table>; + device-handle = <&samsung_K3QF2F20DB>; + vdd-supply = <&buck1_reg>; + }; From patchwork Fri Apr 19 14:19:25 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lukasz Luba X-Patchwork-Id: 10909601 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id A681A1850 for ; Fri, 19 Apr 2019 19:10:05 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 9990F28A3A for ; Fri, 19 Apr 2019 19:10:05 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 8C98028A73; Fri, 19 Apr 2019 19:10:05 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id BA66428AA2 for ; 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Fri, 19 Apr 2019 14:19:48 +0000 (GMT) From: Lukasz Luba To: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-samsung-soc@vger.kernel.org Cc: b.zolnierkie@samsung.com, krzk@kernel.org, kgene@kernel.org, cw00.choi@samsung.com, kyungmin.park@samsung.com, m.szyprowski@samsung.com, s.nawrocki@samsung.com, myungjoo.ham@samsung.com, keescook@chromium.org, tony@atomide.com, jroedel@suse.de, treding@nvidia.com, digetx@gmail.com, willy.mh.wolff.ml@gmail.com, Lukasz Luba Subject: [PATCH v6 07/10] drivers: memory: add DMC driver for Exynos5422 Date: Fri, 19 Apr 2019 16:19:25 +0200 Message-Id: <1555683568-20882-8-git-send-email-l.luba@partner.samsung.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1555683568-20882-1-git-send-email-l.luba@partner.samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA0VSa0hTYRj227nsbLY6baIfti4MjAqaRYEfFZFRdCiioCBWQq12cJKbtZOa WTGLvKVdHJVoZTdymc1mY20W5tSceWkzE9MSzSFFWaBTyVWS86z697zP87zP+34vH4VJ3UQ0 laQ/xhr06mQFKcbtTZOe5WSPM2FFb5YIWYurCNQ99olAZY2vCfRwxAeQqeWGALWd16GLvq8Y 8ngeC1H7mWEh6jXKUWfNdRL5CxsBKvbUCtCjxj4hep9lJlHDcA6BXrzdit7/nI0mmgfBBhkz MV6EM6XGDpxxlvQJmeqKPJIpPPudZFzfnwuYC7YKwDxpzWT81Qt2ivaK12nY5KQ01hC7/oBY ezPbgR1pcGLHvaYu3AjahwT5QERBejVsCvwG+UBMSWkzgF+u2DG+GAPQZR8IFX4AL9us5N8W 793bBC+UA9jdHyD+tVicWdPBFEXSSuioOBpsiKAz4YfuFzNJGD0sgO2BH3hQkNEMHBlqEQYx TsfAZ5VnsCCW0Fvhx647OD9tAex5nTfDi+htsOaBjQwGQXpQCH0el5A3bYJD/VOh9WTwi9sW 4uWw1VQQCuKgsfA24PFJ6Lt4I+RZCxvcHURwaYxeCqtqYnk6Hp6rejTzFkjPhu++zQ3S2DQs sl/DeFoCc7OlvHsJtBV4QyeNhOWVV4W8hYGdgWj+OjcBtP94Ci6BhSX/Z90CoAJEsamcLpHl VunZdCWn1nGp+kTloRRdNZj+Xq1T7nEHqP11sB7QFFDMktQVOROkhDqNy9DVA0hhighJvMaW IJVo1BknWEPKfkNqMsvVg3kUroiSZIYN7JPSiepj7GGWPcIa/qoCShRtBCW6UwL0ak9zjlXO OaoL7ls3jbo6QGnYjgFxeNwutMRStuhe3mJsXcA99rlWZOV6FLo4S++UarMv/OX2Dq2lSdz5 daPXnC6vv566pfj0mznNKvOkKMbfdj6l2DWqVc6/dFS1MruLWqPaLfLPymW9GlOfrG6biil/ G6m+ZVymwDmteuUyzMCp/wDZBuAgWgMAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrFIsWRmVeSWpSXmKPExsVy+t/xe7qsN3fGGNzcxmKxccZ6VovrX56z Wsw/co7VYvXHx4wWk0/NZbI4051r0f/4NbPF+fMb2C3ONr1ht7jVIGNxedccNovPvUcYLWac 38dksfbIXXaL240r2CwOv2lntdh/xcvi9m8+i28nHjE6CHt8+zqJxWN2w0UWj52z7rJ7bFrV yebR2/yOzePguz1MHn1bVjF6bD5d7fF5k1wAZ5SeTVF+aUmqQkZ+cYmtUrShhZGeoaWFnpGJ pZ6hsXmslZGpkr6dTUpqTmZZapG+XYJexry2HcwFh3cyV1yYfJWlgfHsU6YuRk4OCQETiQuL F7J2MXJxCAksZZR4/mIiI0RCTGLSvu3sELawxJ9rXWwQRZ8YJR42fgLq5uBgE9CT2LGqEKRG RKBeov/NJbAaZoEGZok126+ygiSEBTwkPj49BTaIRUBVYveaJmYQm1fAS+Lh1UUsEAvkJG6e 6wSLcwp4S+xauYUNxBYCqtlwbS/TBEa+BYwMqxhFUkuLc9Nziw31ihNzi0vz0vWS83M3MQLj aduxn5t3MF7aGHyIUYCDUYmH98CknTFCrIllxZW5hxglOJiVRHgdU7bECPGmJFZWpRblxxeV 5qQWH2I0BTpqIrOUaHI+MNbzSuINTQ3NLSwNzY3Njc0slMR5zxtURgkJpCeWpGanphakFsH0 MXFwSjUwiuf/tE/TjlkiGjclJfr8f+FrZz9M3+WVY+62cP/9r6dFosQM5yTm8izRC9686VaR b+5F579fz/RzdmY0yNdOYQzVUvkVp/lod5bMhlOqPfu2/Fg7w9Y8ZOUL3zcrmJ49uRNnmcos up97+XuOmP1snufXTdWzucz6V0RScN+1CWqrd3wyTOmPU2Ipzkg01GIuKk4EAJJkZk69AgAA X-CMS-MailID: 20190419141949eucas1p2a3ca13166210b6bc5741808055650e04 X-Msg-Generator: CA X-RootMTR: 20190419141949eucas1p2a3ca13166210b6bc5741808055650e04 X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20190419141949eucas1p2a3ca13166210b6bc5741808055650e04 References: <1555683568-20882-1-git-send-email-l.luba@partner.samsung.com> Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch adds driver for Exynos5422 Dynamic Memory Controller. The driver provides support for dynamic frequency and voltage scaling for DMC and DRAM. It supports changing timings of DRAM running with different frequency. There is also an algorithm to calculate timigns based on memory description provided in DT. The patch also contains needed MAINTAINERS file update. Signed-off-by: Lukasz Luba --- MAINTAINERS | 8 + drivers/memory/samsung/Kconfig | 17 + drivers/memory/samsung/Makefile | 1 + drivers/memory/samsung/exynos5422-dmc.c | 1793 +++++++++++++++++++++++++++++++ 4 files changed, 1819 insertions(+) create mode 100644 drivers/memory/samsung/exynos5422-dmc.c diff --git a/MAINTAINERS b/MAINTAINERS index 1ba4b9b..07e257d 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -3395,6 +3395,14 @@ S: Maintained F: drivers/devfreq/exynos-bus.c F: Documentation/devicetree/bindings/devfreq/exynos-bus.txt +DMC FREQUENCY DRIVER FOR SAMSUNG EXYNOS5422 +M: Lukasz Luba +L: linux-pm@vger.kernel.org +L: linux-samsung-soc@vger.kernel.org +S: Maintained +F: drivers/memory/samsung/exynos5422-dmc.c +F: Documentation/devicetree/bindings/memory-controllers/exynos5422-dmc.txt + BUSLOGIC SCSI DRIVER M: Khalid Aziz L: linux-scsi@vger.kernel.org diff --git a/drivers/memory/samsung/Kconfig b/drivers/memory/samsung/Kconfig index 79ce7ea..202972b 100644 --- a/drivers/memory/samsung/Kconfig +++ b/drivers/memory/samsung/Kconfig @@ -5,6 +5,23 @@ config SAMSUNG_MC Support for the Memory Controller (MC) devices found on Samsung Exynos SoCs. +config ARM_EXYNOS5422_DMC + tristate "ARM EXYNOS5422 Dynamic Memory Controller driver" + depends on ARCH_EXYNOS || COMPILE_TEST + select DDR + select PM_DEVFREQ + select DEVFREQ_GOV_SIMPLE_ONDEMAND + select DEVFREQ_GOV_USERSPACE + select PM_DEVFREQ_EVENT + select PM_OPP + help + This adds driver for Exynos5422 DMC (Dynamic Memory Controller). + The driver provides support for Dynamic Voltage and Frequency Scaling in + DMC and DRAM. It also supports changing timings of DRAM running with + different frequency. The timings are calculated based on DT memory + information. + + if SAMSUNG_MC config EXYNOS_SROM diff --git a/drivers/memory/samsung/Makefile b/drivers/memory/samsung/Makefile index 00587be..4f6e438 100644 --- a/drivers/memory/samsung/Makefile +++ b/drivers/memory/samsung/Makefile @@ -1,2 +1,3 @@ # SPDX-License-Identifier: GPL-2.0 +obj-$(CONFIG_ARM_EXYNOS5422_DMC) += exynos5422-dmc.o obj-$(CONFIG_EXYNOS_SROM) += exynos-srom.o diff --git a/drivers/memory/samsung/exynos5422-dmc.c b/drivers/memory/samsung/exynos5422-dmc.c new file mode 100644 index 0000000..fa4cd4c --- /dev/null +++ b/drivers/memory/samsung/exynos5422-dmc.c @@ -0,0 +1,1793 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2019 Samsung Electronics Co., Ltd. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "../of_memory.h" + +#define EXYNOS5_DREXI_TIMINGAREF (0x0030) +#define EXYNOS5_DREXI_TIMINGROW0 (0x0034) +#define EXYNOS5_DREXI_TIMINGDATA0 (0x0038) +#define EXYNOS5_DREXI_TIMINGPOWER0 (0x003C) +#define EXYNOS5_DREXI_TIMINGROW1 (0x00E4) +#define EXYNOS5_DREXI_TIMINGDATA1 (0x00E8) +#define EXYNOS5_DREXI_TIMINGPOWER1 (0x00EC) +#define CDREX_PAUSE (0x91c) +#define CDREX_LPDDR3PHY_CON3 (0xa20) +#define EXYNOS5_TIMING_SET_SWI (1UL << 28) +#define USE_MX_MSPLL_TIMINGS (1) +#define USE_BPLL_TIMINGS (0) + +#define EXYNOS5_AREF_NORMAL (0x2e) + +#define IS_MEM_2GB(val) \ + ( \ + (((val) & 0xf0) & 0x20) ? 1 : \ + (((val) & 0xf0) & 0x30) ? 1 : 0 \ + ) + +#define EXYNOS5_POP_OPTIONS(val) (((val >> 4) & 0x3UL) << 4) +#define EXYNOS5_DDR_TYPE(val) (((val >> 14) & 0x1UL)) + +#define EXYNOS5_CHIP_PROD_ID (0) +#define EXYNOS5_CHIP_PKG_ID (4) + +#define PPMU_PMCNT_CONST_RATIO_MUL 15 +#define PPMU_PMCNT_CONST_RATIO_DIV 10 + +#define AXI_BUS_WIDTH_BYTES (128 >> 3) + +/** + * enum dmc_slot_id - An enum with slots in DMC + */ +enum dmc_slot_id { + DMC0_0, + DMC0_1, + DMC1_0, + DMC1_1, + DMC_SLOTS_END +}; + +/** + * struct dmc_slot_info - Describes DMC's slot + * + * The structure holds DMC's slot name which is part of the device name + * provided in DT. Each slot has particular share of the DMC bandwidth. + * To abstract the model performance and values in performance counters, + * fields 'ratio_mul' and 'ratio_div' are used in calculation algorithm + * for each slot. Please check the corresponding function with the algorithm, + * to see how these variables are used. + */ +struct dmc_slot_info { + char *name; + int id; + int ratio_mul; + int ratio_div; +}; + +/** + * struct dmc_opp_table - Operating level desciption + * + * Covers frequency and voltage settings of the DMC operating mode. + */ +struct dmc_opp_table { + u32 freq_hz; + u32 volt_uv; +}; + +/** + * struct exynos5_dmc - main structure describing DMC device + * + * The main structure for the Dynamic Memory Controller which covers clocks, + * memory regions, HW information, parameters and current operating mode. + */ +struct exynos5_dmc { + struct device *dev; + struct devfreq *df; + struct devfreq_simple_ondemand_data gov_data; + void __iomem *base_drexi0; + void __iomem *base_drexi1; + void __iomem *chip_id; + struct regmap *clk_regmap; + struct mutex lock; + unsigned long curr_rate; + unsigned long curr_volt; + unsigned long bypass_rate; + struct dmc_opp_table *opp; + struct dmc_opp_table opp_bypass; + int opp_count; + u32 timings_arr_size; + u32 *timing_row; + u32 *timing_data; + u32 *timing_power; + const struct lpddr3_timings *timings; + const struct lpddr3_min_tck *min_tck; + u32 bypass_timing_row; + u32 bypass_timing_data; + u32 bypass_timing_power; + unsigned int prod_rev; + unsigned int pkg_rev; + unsigned int mem_info; + struct regulator *vdd_mif; + struct clk *fout_spll; + struct clk *fout_bpll; + struct clk *mout_spll; + struct clk *mout_bpll; + struct clk *mout_mclk_cdrex; + struct clk *dout_clk2x_phy0; + struct clk *mout_mx_mspll_ccore; + struct clk *mx_mspll_ccore_phy; + struct clk *mout_mx_mspll_ccore_phy; + struct devfreq_event_dev **counter; + int num_counters; + bool counters_enabled; +#ifdef CONFIG_DEBUG_FS + struct dentry *dbg_root; +#endif +}; + +#define TIMING_FIELD(t_name, t_bit_beg, t_bit_end) \ + { .name = t_name, .bit_beg = t_bit_beg, .bit_end = t_bit_end } + +#define TIMING_VAL(timing_array, id, t_val) \ +({ \ + u32 __val; \ + __val = t_val << timing_array[id].bit_beg; \ + __val; \ +}) + +#define TIMING_VAL2REG(timing, t_val) \ +({ \ + u32 __val; \ + __val = t_val << timing->bit_beg; \ + __val; \ +}) + +#define TIMING_REG2VAL(reg, timing) \ +({ \ + u32 __val; \ + reg <<= (31 - timing->bit_end); \ + reg >>= (31 - timing->bit_end); \ + __val = reg >> timing->bit_beg; \ + __val; \ +}) + +struct timing_reg { + char *name; + int bit_beg; + int bit_end; + unsigned int val; +}; + +static struct timing_reg timing_row[] = { + TIMING_FIELD("tRFC", 24, 31), + TIMING_FIELD("tRRD", 20, 23), + TIMING_FIELD("tRP", 16, 19), + TIMING_FIELD("tRCD", 12, 15), + TIMING_FIELD("tRC", 6, 11), + TIMING_FIELD("tRAS", 0, 5), +}; + +static struct timing_reg timing_data[] = { + TIMING_FIELD("tWTR", 28, 31), + TIMING_FIELD("tWR", 24, 27), + TIMING_FIELD("tRTP", 20, 23), + TIMING_FIELD("tW2W-C2C", 14, 14), + TIMING_FIELD("tR2R-C2C", 12, 12), + TIMING_FIELD("WL", 8, 11), + TIMING_FIELD("tDQSCK", 4, 7), + TIMING_FIELD("RL", 0, 3), +}; + +static struct timing_reg timing_power[] = { + TIMING_FIELD("tFAW", 26, 31), + TIMING_FIELD("tXSR", 16, 25), + TIMING_FIELD("tXP", 8, 15), + TIMING_FIELD("tCKE", 4, 7), + TIMING_FIELD("tMRD", 0, 3), +}; + +#define TIMING_COUNT (ARRAY_SIZE(timing_row) + ARRAY_SIZE(timing_data) + \ + ARRAY_SIZE(timing_power)) + +/** + * exynos5_counters_fname() - Macro generating function for event devices + * @f: function name suffix + * + * Macro which generates needed function for manipulation of event devices. + * It aims to avoid code duplication relaying on similar prefix and function + * parameters in the devfreq event device framework functions. + */ +#define exynos5_counters_fname(f) \ +static int exynos5_counters_##f(struct exynos5_dmc *dmc) \ +{ \ + int i, ret; \ + \ + for (i = 0; i < dmc->num_counters; i++) { \ + if (!dmc->counter[i]) \ + continue; \ + ret = devfreq_event_##f(dmc->counter[i]); \ + if (ret < 0) \ + return ret; \ + } \ + return 0; \ +} + +/* Declarations for the function generated by the macro above. */ +static int exynos5_counters_set_event(struct exynos5_dmc *dmc); +static int exynos5_counters_enable_edev(struct exynos5_dmc *dmc); +static int exynos5_counters_disable_edev(struct exynos5_dmc *dmc); + +/* Generate needed functions for managing event device. */ +exynos5_counters_fname(set_event); +exynos5_counters_fname(enable_edev); +exynos5_counters_fname(disable_edev); + +/* Event names to DMC channel and slot with proper data count type */ +static const char *event_name[] = { + /* Counters for DMC0 slot 0 */ + "ppmu-event0-dmc0_0", + "DMC0_0-Read", + "ppmu-event1-dmc0_0", + "DMC0_0-Write", + "ppmu-event3-dmc0_0", + "DMC0_0-Read+Write", + /* Counters for DMC0 slot 1 */ + "ppmu-event0-dmc0_1", + "DMC0_1-Read", + "ppmu-event1-dmc0_1", + "DMC0_1-Write", + "ppmu-event3-dmc0_1", + "DMC0_1-Read+Write", + /* Counters for DMC1 slot 0 */ + "ppmu-event0-dmc1_0", + "DMC1_0-Read", + "ppmu-event1-dmc1_0", + "DMC1_0-Write", + "ppmu-event3-dmc1_0", + "DMC1_0-Read+Write", + /* Counters for DMC1 slot 0 */ + "ppmu-event0-dmc1_1", + "DMC1_1-Read", + "ppmu-event1-dmc1_1", + "DMC1_1-Write", + "ppmu-event3-dmc1_1", + "DMC1_1-Read+Write", +}; + +/** + * find_target_freq_id() - Finds requested frequency in local DMC configuration + * @dmc: device for which the information is checked + * @target_rate: requested frequency in KHz + * + * Seeks in the local DMC driver structure for the requested frequency value + * and returns index or error value. + */ +static int find_target_freq_idx(struct exynos5_dmc *dmc, + unsigned long target_rate) +{ + int i; + + for (i = dmc->opp_count - 1; i >= 0; i--) + if (dmc->opp[i].freq_hz <= target_rate) + return i; + + return -EINVAL; +} + +/** + * exynos5_dmc_chip_revision_settings() - Chooses proper DMC's configuration + * @dmc: device for which is going to be checked and configured + * + * Function checks the HW product information in order to choose proper + * configuration for DMC frequency, voltage and DRAM timings. + */ +static int exynos5_dmc_chip_revision_settings(struct exynos5_dmc *dmc) +{ + unsigned int val; + + val = readl(dmc->chip_id + EXYNOS5_CHIP_PROD_ID); + dmc->prod_rev = val; + + val = readl(dmc->chip_id + EXYNOS5_CHIP_PKG_ID); + dmc->pkg_rev = val; + + dmc->mem_info = EXYNOS5_POP_OPTIONS(val); + dmc->mem_info |= EXYNOS5_DDR_TYPE(val); + + if (!IS_MEM_2GB(dmc->mem_info)) { + dev_warn(dmc->dev, "DRAM memory type not supported\n"); + return -EINVAL; + } + + return 0; +} + +/** + * exynos5_switch_timing_regs() - Changes bank register set for DRAM timings + * @dmc: device for which the new settings is going to be applied + * @set: boolean variable passing set value + * + * Changes the register set, which holds timing parameters. + * There is two register sets: 0 and 1. The register set 0 + * is used in normal operation when the clock is provided from main PLL. + * The bank register set 1 is used when the main PLL frequency is going to be + * changed and the clock is taken from alternative, stable source. + * This function switches between these banks according to the + * currently used clock source. + */ +static void exynos5_switch_timing_regs(struct exynos5_dmc *dmc, bool set) +{ + unsigned int reg; + int ret; + + ret = regmap_read(dmc->clk_regmap, CDREX_LPDDR3PHY_CON3, ®); + + if (set) + reg |= EXYNOS5_TIMING_SET_SWI; + else + reg &= ~EXYNOS5_TIMING_SET_SWI; + + regmap_write(dmc->clk_regmap, CDREX_LPDDR3PHY_CON3, reg); +} + +/** + * exynos5_init_freq_table() - Initialized PM OPP framework + * @dev: devfreq device for which the OPP table is going to be + * initialized + * @dmc: DMC device for which the frequencies are used for OPP init + * @profile: devfreq device's profile + * + * Populate the devfreq device's OPP table based on current frequency, voltage. + */ +static int exynos5_init_freq_table(struct device *dev, struct exynos5_dmc *dmc, + struct devfreq_dev_profile *profile) +{ + int i, ret; + int idx; + unsigned long freq; + + ret = dev_pm_opp_of_add_table(dev); + if (ret < 0) { + dev_err(dev, "Failed to get OPP table\n"); + return ret; + } + + dmc->opp_count = dev_pm_opp_get_opp_count(dev); + + dmc->opp = devm_kmalloc_array(dmc->dev, dmc->opp_count, + sizeof(struct dmc_opp_table), GFP_KERNEL); + if (!dmc->opp) + goto err_opp; + + idx = dmc->opp_count - 1; + for (i = 0, freq = ULONG_MAX; i < dmc->opp_count; i++, freq--) { + struct dev_pm_opp *opp; + + opp = dev_pm_opp_find_freq_floor(dev, &freq); + if (IS_ERR(opp)) + goto err_free_tables; + + dmc->opp[idx - i].freq_hz = freq; + dmc->opp[idx - i].volt_uv = dev_pm_opp_get_voltage(opp); + + dev_pm_opp_put(opp); + } + + return 0; + +err_free_tables: + kfree(dmc->opp); +err_opp: + dev_pm_opp_of_remove_table(dev); + + return -EINVAL; +} + +/** + * exynos5_set_bypass_dram_timings() - Low-level changes of the DRAM timings + * @dmc: device for which the new settings is going to be applied + * @param: DRAM parameters which passes timing data + * + * Low-level function for changing timings for DRAM memory clocking from + * 'bypass' clock source (fixed frequency @400MHz). + * It uses timing bank registers set 1. + */ +static void exynos5_set_bypass_dram_timings(struct exynos5_dmc *dmc) +{ + writel(EXYNOS5_AREF_NORMAL, + dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGAREF); + + writel(dmc->bypass_timing_row, + dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGROW1); + writel(dmc->bypass_timing_row, + dmc->base_drexi1 + EXYNOS5_DREXI_TIMINGROW1); + writel(dmc->bypass_timing_data, + dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGDATA1); + writel(dmc->bypass_timing_data, + dmc->base_drexi1 + EXYNOS5_DREXI_TIMINGDATA1); + writel(dmc->bypass_timing_power, + dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGPOWER1); + writel(dmc->bypass_timing_power, + dmc->base_drexi1 + EXYNOS5_DREXI_TIMINGPOWER1); +} + +/** + * exynos5_dram_change_timings() - Low-level changes of the DRAM final timings + * @dmc: device for which the new settings is going to be applied + * @target_rate: target frequency of the DMC + * + * Low-level function for changing timings for DRAM memory operating from main + * clock source (BPLL), which can have different frequencies. Thus, each + * frequency must have corresponding timings register values in order to keep + * the needed delays. + * It uses timing bank registers set 0. + */ +static int exynos5_dram_change_timings(struct exynos5_dmc *dmc, + unsigned long target_rate) +{ + int idx; + + for (idx = dmc->opp_count - 1; idx >= 0; idx--) + if (dmc->opp[idx].freq_hz <= target_rate) + break; + + if (idx < 0) + return -EINVAL; + + writel(EXYNOS5_AREF_NORMAL, + dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGAREF); + + writel(dmc->timing_row[idx], + dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGROW0); + writel(dmc->timing_row[idx], + dmc->base_drexi1 + EXYNOS5_DREXI_TIMINGROW0); + writel(dmc->timing_data[idx], + dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGDATA0); + writel(dmc->timing_data[idx], + dmc->base_drexi1 + EXYNOS5_DREXI_TIMINGDATA0); + writel(dmc->timing_power[idx], + dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGPOWER0); + writel(dmc->timing_power[idx], + dmc->base_drexi1 + EXYNOS5_DREXI_TIMINGPOWER0); + + return 0; +} + +/** + * exynos5_dmc_align_target_voltage() - Sets the final voltage for the DMC + * @dmc: device for which it is going to be set + * @target_volt: new voltage which is chosen to be final + * + * Function tries to align voltage to the safe level for 'normal' mode. + * It checks the need of higher voltage and changes the value. The target + * voltage might be lower that currently set and still the system will be + * stable. + */ +static int exynos5_dmc_align_target_voltage(struct exynos5_dmc *dmc, + unsigned long target_volt) +{ + int ret = 0; + + if (dmc->curr_volt > target_volt) { + ret = regulator_set_voltage(dmc->vdd_mif, target_volt, + target_volt); + if (!ret) + dmc->curr_volt = target_volt; + } + + return ret; +} + +/** + * exynos5_dmc_align_bypass_voltage() - Sets the voltage for the DMC + * @dmc: device for which it is going to be set + * @target_volt: new voltage which is chosen to be final + * + * Function tries to align voltage to the safe level for the 'bypass' mode. + * It checks the need of higher voltage and changes the value. + * The target voltage must not be less than currently needed, because + * for current frequency the device might become unstable. + */ +static int exynos5_dmc_align_bypass_voltage(struct exynos5_dmc *dmc, + unsigned long target_volt) +{ + int ret = 0; + unsigned long bypass_volt = dmc->opp_bypass.volt_uv; + + target_volt = max(bypass_volt, target_volt); + + if (dmc->curr_volt >= target_volt) + return 0; + + ret = regulator_set_voltage(dmc->vdd_mif, target_volt, + target_volt); + if (!ret) + dmc->curr_volt = target_volt; + + return ret; +} + +/** + * exynos5_dmc_align_bypass_dram_timings() - Chooses and sets DRAM timings + * @dmc: device for which it is going to be set + * @target_rate: new frequency which is chosen to be final + * + * Function changes the DRAM timings for the temporary 'bypass' mode. + */ +static int exynos5_dmc_align_bypass_dram_timings(struct exynos5_dmc *dmc, + unsigned long target_rate) +{ + int idx = find_target_freq_idx(dmc, target_rate); + + if (idx < 0) + return -EINVAL; + + exynos5_set_bypass_dram_timings(dmc); + + return 0; +} + +/** + * exynos5_dmc_switch_to_bypass_configuration() - Switching to temporary clock + * @dmc: DMC device for which the switching is going to happen + * @target_rate: new frequency which is going to be set as a final + * @target_volt: new voltage which is going to be set as a final + * + * Function configures DMC and clocks for operating in temporary 'bypass' mode. + * This mode is used only temporary but if required, changes voltage and timings + * for DRAM chips. It switches the main clock to stable clock source for the + * period of the main PLL reconfiguration. + */ +static int exynos5_dmc_switch_to_bypass_configuration(struct exynos5_dmc *dmc, + unsigned long target_rate, + unsigned long target_volt) +{ + int ret; + + /* + * Having higher voltage for a particular frequency does not harm + * the chip. Use it for the temporary frequency change when one + * voltage manipulation might be avoided. + */ + ret = exynos5_dmc_align_bypass_voltage(dmc, target_volt); + if (ret) + return ret; + + /* + * Longer delays for DRAM does not cause crash, the opposite does. + */ + ret = exynos5_dmc_align_bypass_dram_timings(dmc, target_rate); + if (ret) + return ret; + + /* + * Delays are long enough, so use them for the new coming clock. + */ + exynos5_switch_timing_regs(dmc, USE_MX_MSPLL_TIMINGS); + + /* + * Voltage is set at least to a level needed for this frequency, + * so switching clock source is safe now. + */ + clk_prepare_enable(dmc->fout_spll); + clk_prepare_enable(dmc->mout_spll); + clk_prepare_enable(dmc->mout_mx_mspll_ccore); + + ret = clk_set_parent(dmc->mout_mclk_cdrex, dmc->mout_mx_mspll_ccore); + + return ret; +} + +/** + * exynos5_dmc_change_freq_and_volt() - Changes voltage and frequency of the DMC + * using safe procedure + * @dmc: device for which the frequency is going to be changed + * @target_rate: requested new frequency + * @target_volt: requested voltage which corresponds to the new frequency + * + * The DMC frequency change procedure requires a few steps. + * The main requirement is to change the clock source in the clk mux + * for the time of main clock PLL locking. The assumption is that the + * alternative clock source set as parent is stable. + * The second parent's clock frequency is fixed to 400MHz, it is named 'bypass' + * clock. This requires alignment in DRAM timing parameters for the new + * T-period. There is two bank sets for keeping DRAM + * timings: set 0 and set 1. The set 0 is used when main clock source is + * chosen. The 2nd set of regs is used for 'bypass' clock. Switching between + * the two bank sets is part of the process. + * The voltage must also be aligned to the minimum required level. There is + * this intermediate step with switching to 'bypass' parent clock source. + * if the old voltage is lower, it requires an increase of the voltage level. + * The complexity of the voltage manipulation is hidden in low level function. + * In this function there is last alignment of the voltage level at the end. + */ +static int +exynos5_dmc_change_freq_and_volt(struct exynos5_dmc *dmc, + unsigned long target_rate, + unsigned long target_volt) +{ + int ret; + + ret = exynos5_dmc_switch_to_bypass_configuration(dmc, target_rate, + target_volt); + if (ret) + return ret; + + /* We are safe to increase the timings for current bypass frequency. + * Thanks to this the settings we be ready for the upcoming clock source + * change. + */ + exynos5_dram_change_timings(dmc, target_rate); + + clk_set_rate(dmc->fout_bpll, target_rate); + + exynos5_switch_timing_regs(dmc, USE_BPLL_TIMINGS); + + ret = clk_set_parent(dmc->mout_mclk_cdrex, dmc->mout_bpll); + if (ret) + return ret; + + clk_disable_unprepare(dmc->mout_mx_mspll_ccore); + clk_disable_unprepare(dmc->mout_spll); + clk_disable_unprepare(dmc->fout_spll); + /* Make sure if the voltage is not from 'bypass' settings and align to + * the right level for power efficiency. + */ + ret = exynos5_dmc_align_target_voltage(dmc, target_volt); + + return ret; +} + +/** + * exynos5_dmc_get_volt_freq() - Gets the frequency and voltage from the OPP + * table. + * @dev: device for which the frequency is going to be changed + * @freq: requested frequency in KHz + * @target_rate: returned frequency which is the same or lower than + * requested + * @target_volt: returned voltage which corresponds to the returned + * frequency + * + * Function gets requested frequency and checks OPP framework for needed + * frequency and voltage. It populates the values 'target_rate' and + * 'target_volt' or returns error value when OPP framework fails. + */ +static int exynos5_dmc_get_volt_freq(struct device *dev, unsigned long *freq, + unsigned long *target_rate, + unsigned long *target_volt, u32 flags) +{ + struct dev_pm_opp *opp; + + opp = devfreq_recommended_opp(dev, freq, flags); + if (IS_ERR(opp)) + return PTR_ERR(opp); + + *target_rate = dev_pm_opp_get_freq(opp); + *target_volt = dev_pm_opp_get_voltage(opp); + dev_pm_opp_put(opp); + + return 0; +} + +/** + * exynos5_dmc_target() - Function responsible for changing frequency of DMC + * @dev: device for which the frequency is going to be changed + * @freq: requested frequency in KHz + * @flags: flags provided for this frequency change request + * + * An entry function provided to the devfreq framework which provides frequency + * change of the DMC. The function gets the possible rate from OPP table based + * on requested frequency. It calls the next function responsible for the + * frequency and voltage change. In case of failure, does not set 'curr_rate' + * and returns error value to the framework. + */ +static int exynos5_dmc_target(struct device *dev, unsigned long *freq, + u32 flags) +{ + struct exynos5_dmc *dmc = dev_get_drvdata(dev); + unsigned long target_rate = 0; + unsigned long target_volt = 0; + int ret; + + ret = exynos5_dmc_get_volt_freq(dev, freq, &target_rate, &target_volt, + flags); + + if (ret) + return ret; + + if (target_rate == dmc->curr_rate) + return 0; + + mutex_lock(&dmc->lock); + + ret = exynos5_dmc_change_freq_and_volt(dmc, target_rate, target_volt); + + if (ret) { + mutex_unlock(&dmc->lock); + return ret; + } + + dmc->curr_rate = target_rate; + + mutex_unlock(&dmc->lock); + return 0; +} + +/** + * exynos5_counters_get() - Gets the performance counters values. + * @dmc: device for which the counters are going to be checked + * @load_count: variable which is populated with counter value + * @total_count: variable which is used as 'wall clock' reference + * + * Function which provides performance counters values. It sums up counters for + * two DMC channels. The 'total_count' is used as a reference and max value. + * The ratio 'load_count/total_count' shows the busy percentage [0%, 100%]. + */ +static int exynos5_counters_get(struct exynos5_dmc *dmc, + unsigned long *load_count, + unsigned long *total_count) +{ + unsigned long total = 0; + struct devfreq_event_data event; + int ret, i; + + *load_count = 0; + + /* Take into account only read+write counters, but stop all */ + for (i = 0; i < dmc->num_counters; i++) { + if (!dmc->counter[i]) + continue; + + ret = devfreq_event_get_event(dmc->counter[i], &event); + if (ret < 0) + return ret; + + if (i % 3 != 2) + continue; + + *load_count += event.load_count; + + if (total < event.total_count) + total = event.total_count; + } + + *total_count = total; + + return 0; +} + +/** + * exynos5_dmc_get_status() - Read current DMC performance statistics. + * @dev: device for which the statistics are requested + * @stat: structure which has statistic fields + * + * Function reads the DMC performance counters and calculates 'busy_time' + * and 'total_time'. To protect from overflow, the values are shifted right + * by 10. After read out the counters are setup to count again. + */ +static int exynos5_dmc_get_status(struct device *dev, + struct devfreq_dev_status *stat) +{ + struct exynos5_dmc *dmc = dev_get_drvdata(dev); + unsigned long load, total; + int ret; + bool cnt_en; + + mutex_lock(&dmc->lock); + cnt_en = dmc->counters_enabled; + mutex_unlock(&dmc->lock); + if (!cnt_en) { + dev_warn(dev, "performance counters needed, but not present\n"); + return -EAGAIN; + } + + ret = exynos5_counters_get(dmc, &load, &total); + if (ret < 0) + return -EINVAL; + + /* To protect from overflow in calculation ratios, divide by 1024 */ + stat->busy_time = load >> 10; + stat->total_time = total >> 10; + + ret = exynos5_counters_set_event(dmc); + if (ret < 0) { + dev_err(dmc->dev, "could not set event counter\n"); + return ret; + } + + return 0; +} + +/** + * exynos5_dmc_get_cur_freq() - Function returns current DMC frequency + * @dev: device for which the framework checks operating frequency + * @freq: returned frequency value + * + * It returns the currently used frequency of the DMC. The real operating + * frequency might be lower when the clock source value could not be divided + * to the requested value. + */ +static int exynos5_dmc_get_cur_freq(struct device *dev, unsigned long *freq) +{ + struct exynos5_dmc *dmc = dev_get_drvdata(dev); + + mutex_lock(&dmc->lock); + *freq = dmc->curr_rate; + mutex_unlock(&dmc->lock); + + return 0; +} + +/** + * exynos5_dmc_df_profile - Devfreq governor's profile structure + * + * It provides to the devfreq framework needed functions and polling period. + */ +static struct devfreq_dev_profile exynos5_dmc_df_profile = { + .polling_ms = 500, + .target = exynos5_dmc_target, + .get_dev_status = exynos5_dmc_get_status, + .get_cur_freq = exynos5_dmc_get_cur_freq, +}; + +/** + * exynos5_dmc_align_initial_frequency() - Align initial frequency value + * @dmc: device for which the frequency is going to be set + * @bootloader_init_freq: initial frequency set by the bootloader in KHz + * + * The initial bootloader frequency, which is present during boot, might be + * different that supported frequency values in the driver. It is possible + * due to different PLL settings or used PLL as a source. + * This function provides the 'initial_freq' for the devfreq framework + * statistics engine which supports only registered values. Thus, some alignment + * must be made. + */ +unsigned long +exynos5_dmc_align_init_freq(struct exynos5_dmc *dmc, + unsigned long bootloader_init_freq) +{ + unsigned long aligned_freq; + int idx; + + idx = find_target_freq_idx(dmc, bootloader_init_freq); + if (idx >= 0) + aligned_freq = dmc->opp[idx].freq_hz; + else + aligned_freq = dmc->opp[dmc->opp_count - 1].freq_hz; + + return aligned_freq; +} + +/** + * create_timings_aligned() - Create register values and align with standard + * @dmc: device for which the frequency is going to be set + * @idx: speed bin in the OPP table + * @clk_period_ps: the period of the clock, known as tCK + * + * The function calculates timings and creates a register value ready for + * a frequency transition. The register contains a few timings. They are + * shifted by a known offset. The timing value is calculated based on memory + * specyfication: minimal time required and minimal cycles required. + */ +static int create_timings_aligned(struct exynos5_dmc *dmc, u32 *reg_timing_row, + u32 *reg_timing_data, u32 *reg_timing_power, + u32 clk_period_ps) +{ + u32 val; + struct timing_reg *reg; + + if (clk_period_ps == 0) + return -EINVAL; + + *reg_timing_row = 0; + *reg_timing_data = 0; + *reg_timing_power = 0; + + val = dmc->timings->tRFC / clk_period_ps; + val += dmc->timings->tRFC % clk_period_ps ? 1 : 0; + val = max(val, dmc->min_tck->tRFC); + reg = &timing_row[0]; + *reg_timing_row |= TIMING_VAL2REG(reg, val); + + val = dmc->timings->tRRD / clk_period_ps; + val += dmc->timings->tRRD % clk_period_ps ? 1 : 0; + val = max(val, dmc->min_tck->tRRD); + reg = &timing_row[1]; + *reg_timing_row |= TIMING_VAL2REG(reg, val); + + val = dmc->timings->tRPab / clk_period_ps; + val += dmc->timings->tRPab % clk_period_ps ? 1 : 0; + val = max(val, dmc->min_tck->tRPab); + reg = &timing_row[2]; + *reg_timing_row |= TIMING_VAL2REG(reg, val); + + val = dmc->timings->tRCD / clk_period_ps; + val += dmc->timings->tRCD % clk_period_ps ? 1 : 0; + val = max(val, dmc->min_tck->tRCD); + reg = &timing_row[3]; + *reg_timing_row |= TIMING_VAL2REG(reg, val); + + val = dmc->timings->tRC / clk_period_ps; + val += dmc->timings->tRC % clk_period_ps ? 1 : 0; + val = max(val, dmc->min_tck->tRC); + reg = &timing_row[4]; + *reg_timing_row |= TIMING_VAL2REG(reg, val); + + val = dmc->timings->tRAS / clk_period_ps; + val += dmc->timings->tRAS % clk_period_ps ? 1 : 0; + val = max(val, dmc->min_tck->tRAS); + reg = &timing_row[5]; + *reg_timing_row |= TIMING_VAL2REG(reg, val); + + /* data related timings */ + val = dmc->timings->tWTR / clk_period_ps; + val += dmc->timings->tWTR % clk_period_ps ? 1 : 0; + val = max(val, dmc->min_tck->tWTR); + reg = &timing_data[0]; + *reg_timing_data |= TIMING_VAL2REG(reg, val); + + val = dmc->timings->tWR / clk_period_ps; + val += dmc->timings->tWR % clk_period_ps ? 1 : 0; + val = max(val, dmc->min_tck->tWR); + reg = &timing_data[1]; + *reg_timing_data |= TIMING_VAL2REG(reg, val); + + val = dmc->timings->tRTP / clk_period_ps; + val += dmc->timings->tRTP % clk_period_ps ? 1 : 0; + val = max(val, dmc->min_tck->tRTP); + reg = &timing_data[2]; + *reg_timing_data |= TIMING_VAL2REG(reg, val); + + val = dmc->timings->tW2W_C2C / clk_period_ps; + val += dmc->timings->tW2W_C2C % clk_period_ps ? 1 : 0; + val = max(val, dmc->min_tck->tW2W_C2C); + reg = &timing_data[3]; + *reg_timing_data |= TIMING_VAL2REG(reg, val); + + val = dmc->timings->tR2R_C2C / clk_period_ps; + val += dmc->timings->tR2R_C2C % clk_period_ps ? 1 : 0; + val = max(val, dmc->min_tck->tR2R_C2C); + reg = &timing_data[4]; + *reg_timing_data |= TIMING_VAL2REG(reg, val); + + val = dmc->timings->tWL / clk_period_ps; + val += dmc->timings->tWL % clk_period_ps ? 1 : 0; + val = max(val, dmc->min_tck->tWL); + reg = &timing_data[5]; + *reg_timing_data |= TIMING_VAL2REG(reg, val); + + val = dmc->timings->tDQSCK / clk_period_ps; + val += dmc->timings->tDQSCK % clk_period_ps ? 1 : 0; + val = max(val, dmc->min_tck->tDQSCK); + reg = &timing_data[6]; + *reg_timing_data |= TIMING_VAL2REG(reg, val); + + val = dmc->timings->tRL / clk_period_ps; + val += dmc->timings->tRL % clk_period_ps ? 1 : 0; + val = max(val, dmc->min_tck->tRL); + reg = &timing_data[7]; + *reg_timing_data |= TIMING_VAL2REG(reg, val); + + /* power related timings */ + val = dmc->timings->tFAW / clk_period_ps; + val += dmc->timings->tFAW % clk_period_ps ? 1 : 0; + val = max(val, dmc->min_tck->tXP); + reg = &timing_power[0]; + *reg_timing_power |= TIMING_VAL2REG(reg, val); + + val = dmc->timings->tXSR / clk_period_ps; + val += dmc->timings->tXSR % clk_period_ps ? 1 : 0; + val = max(val, dmc->min_tck->tXSR); + reg = &timing_power[1]; + *reg_timing_power |= TIMING_VAL2REG(reg, val); + + val = dmc->timings->tXP / clk_period_ps; + val += dmc->timings->tXP % clk_period_ps ? 1 : 0; + val = max(val, dmc->min_tck->tXP); + reg = &timing_power[2]; + *reg_timing_power |= TIMING_VAL2REG(reg, val); + + val = dmc->timings->tCKE / clk_period_ps; + val += dmc->timings->tCKE % clk_period_ps ? 1 : 0; + val = max(val, dmc->min_tck->tCKE); + reg = &timing_power[3]; + *reg_timing_power |= TIMING_VAL2REG(reg, val); + + val = dmc->timings->tMRD / clk_period_ps; + val += dmc->timings->tMRD % clk_period_ps ? 1 : 0; + val = max(val, dmc->min_tck->tMRD); + reg = &timing_power[4]; + *reg_timing_power |= TIMING_VAL2REG(reg, val); + + return 0; +} + +/** + * of_get_dram_timings() - helper function for parsing DT settings for DRAM + * @dmc: device for which the frequency is going to be set + * + * The function parses DT entries with DRAM information. + */ +static int of_get_dram_timings(struct exynos5_dmc *dmc) +{ + int ret = 0; + struct device_node *np; + int idx; + struct device_node *np_ddr; + u32 freq_mhz, clk_period_ps; + + np_ddr = of_parse_phandle(dmc->dev->of_node, "device-handle", 0); + if (!np_ddr) { + dev_warn(dmc->dev, "could not find 'device-handle' in DT\n"); + return -EINVAL; + } + + dmc->timing_row = devm_kmalloc_array(dmc->dev, TIMING_COUNT, + sizeof(u32), GFP_KERNEL); + if (!dmc->timing_row) + return -ENOMEM; + + dmc->timing_data = devm_kmalloc_array(dmc->dev, TIMING_COUNT, + sizeof(u32), GFP_KERNEL); + if (!dmc->timing_data) + return -ENOMEM; + + dmc->timing_power = devm_kmalloc_array(dmc->dev, TIMING_COUNT, + sizeof(u32), GFP_KERNEL); + if (!dmc->timing_power) + return -ENOMEM; + + dmc->timings = of_lpddr3_get_ddr_timings(np_ddr, dmc->dev, + DDR_TYPE_LPDDR3, + &dmc->timings_arr_size); + if (!dmc->timings) { + of_node_put(np_ddr); + dev_warn(dmc->dev, "could not get timings from DT\n"); + return -EINVAL; + } + + dmc->min_tck = of_lpddr3_get_min_tck(np_ddr, dmc->dev); + if (!dmc->min_tck) { + of_node_put(np_ddr); + dev_warn(dmc->dev, "could not get tck from DT\n"); + return -EINVAL; + } + + /* Sorted array of OPPs with frequency ascending */ + for (idx = 0; idx < dmc->opp_count; idx++) { + freq_mhz = dmc->opp[idx].freq_hz / 1000000; + clk_period_ps = 1000000 / freq_mhz; + + ret = create_timings_aligned(dmc, &dmc->timing_row[idx], + &dmc->timing_data[idx], + &dmc->timing_power[idx], + clk_period_ps); + } + + of_node_put(np); + + /* Take the highest frequency's timings as 'bypass' */ + dmc->bypass_timing_row = dmc->timing_row[idx - 1]; + dmc->bypass_timing_data = dmc->timing_data[idx - 1]; + dmc->bypass_timing_power = dmc->timing_power[idx - 1]; + + return ret; +} + +/** + * exynos5_dmc_init_clks() - Initialize clocks needed for DMC operation. + * @dev: device for which the clocks are setup + * @dmc: DMC structure containing needed fields + * + * Get the needed clocks defined in DT device, enable and set the right parents. + * Read current frequency and initialize the initial rate for governor. + */ +static int exynos5_dmc_init_clks(struct device *dev, struct exynos5_dmc *dmc) +{ + int ret; + unsigned long target_volt = 0; + unsigned long target_rate = 0; + + dmc->fout_spll = devm_clk_get(dev, "fout_spll"); + if (IS_ERR(dmc->fout_spll)) + return PTR_ERR(dmc->fout_spll); + + dmc->fout_bpll = devm_clk_get(dev, "fout_bpll"); + if (IS_ERR(dmc->fout_bpll)) + return PTR_ERR(dmc->fout_bpll); + + dmc->mout_mclk_cdrex = devm_clk_get(dev, "mout_mclk_cdrex"); + if (IS_ERR(dmc->mout_mclk_cdrex)) + return PTR_ERR(dmc->mout_mclk_cdrex); + + dmc->mout_bpll = devm_clk_get(dev, "mout_bpll"); + if (IS_ERR(dmc->mout_bpll)) + return PTR_ERR(dmc->mout_bpll); + + dmc->mout_mx_mspll_ccore = devm_clk_get(dev, "mout_mx_mspll_ccore"); + if (IS_ERR(dmc->mout_mx_mspll_ccore)) + return PTR_ERR(dmc->mout_mx_mspll_ccore); + + dmc->dout_clk2x_phy0 = devm_clk_get(dev, "dout_clk2x_phy0"); + if (IS_ERR(dmc->dout_clk2x_phy0)) + return PTR_ERR(dmc->dout_clk2x_phy0); + + dmc->mout_spll = devm_clk_get(dev, "ff_dout_spll2"); + if (IS_ERR(dmc->mout_spll)) { + dmc->mout_spll = devm_clk_get(dev, "mout_sclk_spll"); + if (IS_ERR(dmc->mout_spll)) + return PTR_ERR(dmc->mout_spll); + } + + /* + * Convert frequency to KHz values and set it for the governor. + */ + dmc->curr_rate = clk_get_rate(dmc->mout_mclk_cdrex); + dmc->curr_rate = exynos5_dmc_align_init_freq(dmc, dmc->curr_rate); + exynos5_dmc_df_profile.initial_freq = dmc->curr_rate; + + ret = exynos5_dmc_get_volt_freq(dev, &dmc->curr_rate, &target_rate, + &target_volt, 0); + if (ret) + return ret; + + dmc->curr_volt = target_volt; + + clk_prepare_enable(dmc->mout_spll); + clk_set_parent(dmc->mout_mx_mspll_ccore, dmc->mout_spll); + clk_prepare_enable(dmc->mout_mx_mspll_ccore); + + dmc->bypass_rate = clk_get_rate(dmc->mout_mx_mspll_ccore); + + clk_prepare_enable(dmc->fout_bpll); + clk_prepare_enable(dmc->mout_bpll); + + return 0; +} + +/** + * exynos5_performance_counters_init() - Initializes performance DMC's counters + * @dmc: DMC for which it does the setup + * + * Initialization of performance counters in DMC for estimating usage. + * The counter's values are used for calculation of a memory bandwidth and based + * on that the governor changes the frequency. + * The counters are not used when the governor is GOVERNOR_USERSPACE. + */ +static int exynos5_performance_counters_init(struct exynos5_dmc *dmc) +{ + int counters_size; + int ret, i; + + dmc->num_counters = devfreq_event_get_edev_count(dmc->dev); + if (dmc->num_counters < 0) { + dev_err(dmc->dev, "could not get devfreq-event counters\n"); + return dmc->num_counters; + } + + counters_size = sizeof(struct devfreq_event_dev) * dmc->num_counters; + dmc->counter = devm_kzalloc(dmc->dev, counters_size, GFP_KERNEL); + if (!dmc->counter) + return -ENOMEM; + + for (i = 0; i < dmc->num_counters; i++) { + dmc->counter[i] = + devfreq_event_get_edev_by_phandle(dmc->dev, i); + if (IS_ERR_OR_NULL(dmc->counter[i])) + return -EPROBE_DEFER; + } + + ret = exynos5_counters_enable_edev(dmc); + if (ret < 0) { + dev_err(dmc->dev, "could not enable event counter\n"); + return ret; + } + + ret = exynos5_counters_set_event(dmc); + if (ret < 0) { + dev_err(dmc->dev, "counld not set event counter\n"); + return ret; + } + + mutex_lock(&dmc->lock); + dmc->counters_enabled = true; + mutex_unlock(&dmc->lock); + + return 0; +} + +static struct regmap_config exynos5_clk_regmap_cfg = { + .reg_bits = 32, + .val_bits = 32, + .reg_stride = 4, +}; + +static int exynos5_dmc_init_clk_regmap(struct platform_device *pdev, + struct exynos5_dmc *dmc) +{ + struct resource *res; + void __iomem *base; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 3); + base = devm_ioremap_resource(dmc->dev, res); + if (IS_ERR(base)) + return PTR_ERR(base); + + exynos5_clk_regmap_cfg.max_register = resource_size(res) - 4; + dmc->clk_regmap = devm_regmap_init_mmio(dmc->dev, base, + &exynos5_clk_regmap_cfg); + if (IS_ERR(dmc->clk_regmap)) + return PTR_ERR(dmc->clk_regmap); + + return 0; +} + +#ifdef CONFIG_DEBUG_FS + +static int dmc_dbg_show_timings(struct seq_file *seq, void *na) +{ + struct exynos5_dmc *dmc = seq->private; + int i, j; + u32 val; + struct timing_reg *reg; + + seq_printf(seq, "timings for each frequency\n"); + for (j = dmc->opp_count - 1; j >= 0; j--) { + seq_printf(seq, "frequency = %uMHz\n", + dmc->opp[j].freq_hz / 1000000); + seq_printf(seq, "timing_row, timing_data, timing_power\n"); + seq_printf(seq, "0x%08X, 0x%08X, 0x%08X\n", dmc->timing_row[j], + dmc->timing_data[j], dmc->timing_power[j]); + } + + for (j = dmc->opp_count - 1; j >= 0; j--) { + seq_printf(seq, "frequency [MHz] = %u\n", + dmc->opp[j].freq_hz / 1000000); + + for (i = 0; i < ARRAY_SIZE(timing_row); i++) { + reg = &timing_row[i]; + val = TIMING_REG2VAL(dmc->timing_row[j], reg); + seq_printf(seq, "%s = %u\n", reg->name, val); + } + + for (i = 0; i < ARRAY_SIZE(timing_data); i++) { + reg = &timing_data[i]; + val = TIMING_REG2VAL(dmc->timing_data[j], reg); + seq_printf(seq, "%s = %u\n", reg->name, val); + } + + for (i = 0; i < ARRAY_SIZE(timing_power); i++) { + reg = &timing_power[i]; + val = TIMING_REG2VAL(dmc->timing_power[j], reg); + seq_printf(seq, "%s = %u\n", reg->name, val); + } + } + + return 0; +} + +static int dmc_dbg_open_timings(struct inode *inode, struct file *f) +{ + return single_open(f, dmc_dbg_show_timings, inode->i_private); +} + +static const char *event_get_name(const char *evt) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(event_name); i += 2) { + if (!strcmp(event_name[i], evt)) + return event_name[i + 1]; + } + + return "Unknown"; +} + +static int dmc_dbg_show_cnt(struct seq_file *seq, void *na) +{ + struct exynos5_dmc *dmc = seq->private; + int i; + struct devfreq_event_data event; + struct devfreq_event_dev *edev; + int ret; + const char *evt_name; + u64 ts_new, delta; + static u64 ts; + + seq_printf(seq, "Performance based on PMU counters\n"); + seq_printf(seq, "The counters could overflow every ~9.2 sec\n"); + + ts_new = ktime_get_ns(); + delta = ts_new - ts; + + for (i = 0; i < dmc->num_counters; i++) { + edev = dmc->counter[i]; + if (!edev) + continue; + + evt_name = event_get_name(edev->desc->name); + + ret = devfreq_event_get_event(edev, &event); + if (ret < 0) + return ret; + + seq_printf(seq, "%s = %lu / %lu\n", evt_name, event.load_count, + event.total_count); + } + + seq_printf(seq, "For last %llu ms\n", + div64_u64(delta, 1000000UL)); + + ts = ktime_get_ns(); + ret = exynos5_counters_set_event(dmc); + if (ret < 0) { + dev_err(dmc->dev, "could not set event counter\n"); + return ret; + } + + return 0; +} + +static int dmc_dbg_open_cnt(struct inode *inode, struct file *f) +{ + return single_open(f, dmc_dbg_show_cnt, inode->i_private); +} + +struct counter { + u64 load; + u64 total; +}; + +static int dmc_dbg_show_cnt_100ms(struct seq_file *seq, void *na) +{ + struct exynos5_dmc *dmc = seq->private; + int i; + u64 bandwidth = 0; + struct devfreq_event_data event; + struct devfreq_event_dev *edev; + int ret; + const char *evt_name; + u64 ts_new, delta; + static u64 ts; + struct counter *cnt; + u64 total[3] = {0, 0, 0 }; /* read, write, read+write data*/ + const char *type[3] = {"read", "write", "read+write"}; + u64 bus_cyc_count = 0; + int offset = 0; + char *s; + + s = kzalloc(PAGE_SIZE * sizeof(char), GFP_KERNEL); + if (!s) + return -ENOMEM; + + cnt = kcalloc(dmc->num_counters, sizeof(struct counter), GFP_KERNEL); + if (!cnt) + return -ENOMEM; + + ret = exynos5_counters_set_event(dmc); + if (ret < 0) { + dev_err(dmc->dev, "could not set event counter\n"); + return ret; + } + + ts = ktime_get_ns(); + msleep(100); + + /* Seprate data acquisition from presentation due to some + overheads. */ + for (i = 0; i < dmc->num_counters; i++) { + edev = dmc->counter[i]; + if (!edev) + continue; + + ret = devfreq_event_get_event(edev, &event); + if (ret < 0) + return ret; + + total[i % 3] += event.load_count; + cnt[i].load = event.load_count; + cnt[i].total = event.total_count; + + if (bus_cyc_count < event.total_count) + bus_cyc_count = event.total_count; + } + + ts_new = ktime_get_ns(); + delta = ts_new - ts; + if (delta == 0) + delta = 1; + + for (i = 0; i < dmc->num_counters; i++) { + edev = dmc->counter[i]; + if (!edev) + continue; + + evt_name = event_get_name(edev->desc->name); + + bandwidth = (u64)cnt[i].load * AXI_BUS_WIDTH_BYTES * 1000; + bandwidth = div64_u64(bandwidth, delta); + + offset += sprintf(s + offset, "%s\t\t%llu MB/s\n", + evt_name, bandwidth); + } + + for (i = 0; i < 3; i++) { + bandwidth = (u64)total[i] * AXI_BUS_WIDTH_BYTES * 1000; + bandwidth = div64_u64(bandwidth, delta); + + offset += sprintf(s + offset, "total\t%s\t\t%llu MB/s\n", + type[i], bandwidth); + } + + /* AXI speed is presented in MHz*/ + bus_cyc_count *= 1000; + + seq_printf(seq, "Performance based on PMU counters\n"); + seq_printf(seq, "The counters will overflow every ~9.2 sec\n"); + seq_printf(seq, "%s", s); + seq_printf(seq, "AXI bus frequency %llu MHz, width %u B, SDR mode\n", + div64_u64(bus_cyc_count, delta), AXI_BUS_WIDTH_BYTES); + seq_printf(seq, "For last %llu ms\n", + div64_u64(delta, 1000000UL)); + + kfree(cnt); + kfree(s); + + return 0; +} + +static int dmc_dbg_show_cnt_100ms_raw(struct seq_file *seq, void *na) +{ + struct exynos5_dmc *dmc = seq->private; + int i; + struct devfreq_event_data event; + struct devfreq_event_dev *edev; + int ret; + const char *evt_name; + u64 ts_new, delta; + static u64 ts; + struct counter *cnt; + const char *type[3] = {"read", "write", "read+write"}; + int offset = 0; + char *s; + + s = kzalloc(PAGE_SIZE * sizeof(char), GFP_KERNEL); + if (!s) + return -ENOMEM; + + cnt = kcalloc(dmc->num_counters, sizeof(struct counter), GFP_KERNEL); + if (!cnt) + return -ENOMEM; + + ret = exynos5_counters_set_event(dmc); + if (ret < 0) { + dev_err(dmc->dev, "could not set event counter\n"); + return ret; + } + + ts = ktime_get_ns(); + msleep(100); + + /* Seprate data acquisition from presentation due to some + overheads. */ + for (i = 0; i < dmc->num_counters; i++) { + edev = dmc->counter[i]; + if (!edev) + continue; + + ret = devfreq_event_get_event(edev, &event); + if (ret < 0) + return ret; + + cnt[i].load = event.load_count; + cnt[i].total = event.total_count; + } + + ts_new = ktime_get_ns(); + delta = ts_new - ts; + if (delta == 0) + delta = 1; + + for (i = 0; i < dmc->num_counters; i++) { + edev = dmc->counter[i]; + if (!edev) + continue; + + evt_name = event_get_name(edev->desc->name); + + offset += sprintf(s + offset, "%s (%s)\t\t%llu / %llu\n", + evt_name, type[i % 3], cnt[i].load, + cnt[i].total); + } + + seq_printf(seq, "Performance based on PMU counters ('load'/'total')\n"); + seq_printf(seq, "The counters will overflow every ~9.2 sec\n"); + seq_printf(seq, "%s", s); + seq_printf(seq, "For last %llu ms\n", + div64_u64(delta, 1000000UL)); + + kfree(cnt); + kfree(s); + + return 0; +} + +static int dmc_dbg_open_cnt_100ms(struct inode *inode, struct file *f) +{ + return single_open(f, dmc_dbg_show_cnt_100ms, inode->i_private); +} + +static int dmc_dbg_open_cnt_100ms_raw(struct inode *inode, struct file *f) +{ + return single_open(f, dmc_dbg_show_cnt_100ms_raw, inode->i_private); +} + +static const struct file_operations dmc_debugfs_ops_timings = { + .open = dmc_dbg_open_timings, + .read = seq_read, + .release = single_release, +}; + +static const struct file_operations dmc_debugfs_ops_cnt = { + .open = dmc_dbg_open_cnt, + .read = seq_read, + .release = single_release, +}; + +static const struct file_operations dmc_debugfs_ops_cnt_100ms = { + .open = dmc_dbg_open_cnt_100ms, + .read = seq_read, + .release = single_release, +}; + +static const struct file_operations dmc_debugfs_ops_cnt_100ms_raw = { + .open = dmc_dbg_open_cnt_100ms_raw, + .read = seq_read, + .release = single_release, +}; + +static void exynos5_dmc_debugfs_init(struct exynos5_dmc *dmc) +{ + struct dentry *dentry; + + dmc->dbg_root = debugfs_create_dir(dev_name(dmc->dev), NULL); + if (!dmc->dbg_root) + return; + + dentry = debugfs_create_file("timings", 0444, dmc->dbg_root, dmc, + &dmc_debugfs_ops_timings); + if (!dentry) + goto clean_debugfs; + + dentry = debugfs_create_file("counters", 0444, dmc->dbg_root, dmc, + &dmc_debugfs_ops_cnt); + if (!dentry) + goto clean_debugfs; + + dentry = debugfs_create_file("100ms_counters", 0444, dmc->dbg_root, dmc, + &dmc_debugfs_ops_cnt_100ms); + if (!dentry) + goto clean_debugfs; + + dentry = debugfs_create_file("100ms_raw_counters", 0444, dmc->dbg_root, + dmc, &dmc_debugfs_ops_cnt_100ms_raw); + if (!dentry) + goto clean_debugfs; + + return; + +clean_debugfs: + debugfs_remove_recursive(dmc->dbg_root); +} +#else +static void exynos5_dmc_debugfs_init(struct exynos5_dmc *dmc) +{} +#endif + +/** + * exynos5_dmc_set_pause_on_switching() - Controls a pause feature in DMC + * @dmc: device which is used for changing this feature + * @set: a boolean state passing enable/disable request + * + * There is a need of pausing DREX DMC when divider or MUX in clock tree + * changes its configuration. In such situation access to the memory is blocked + * in DMC automatically. This feature is used when clock frequency change + * request appears and touches clock tree. + */ +static inline int exynos5_dmc_set_pause_on_switching(struct exynos5_dmc *dmc) +{ + unsigned int val; + int ret; + + ret = regmap_read(dmc->clk_regmap, CDREX_PAUSE, &val); + if (ret) + return ret; + + val |= 1UL; + regmap_write(dmc->clk_regmap, CDREX_PAUSE, val); + + return 0; +} + +/** + * exynos5_dmc_probe() - Probe function for the DMC driver + * @pdev: platform device for which the driver is going to be initialized + * + * Initialize basic components: clocks, regulators, performance counters, etc. + * Read out product version and based on the information setup + * internal structures for the controller (frequency and voltage) and for DRAM + * memory parameters: timings for each operating frequency. + * Register new devfreq device for controlling DVFS of the DMC. + */ +static int exynos5_dmc_probe(struct platform_device *pdev) +{ + int ret = 0; + struct exynos5_dmc *dmc; + struct device *dev = &pdev->dev; + struct resource *res; + + dmc = devm_kzalloc(dev, sizeof(*dmc), GFP_KERNEL); + if (!dmc) + return -ENOMEM; + + mutex_init(&dmc->lock); + + dmc->dev = dev; + platform_set_drvdata(pdev, dmc); + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + dmc->base_drexi0 = devm_ioremap_resource(dev, res); + if (IS_ERR(dmc->base_drexi0)) + return PTR_ERR(dmc->base_drexi0); + + res = platform_get_resource(pdev, IORESOURCE_MEM, 1); + dmc->base_drexi1 = devm_ioremap_resource(dev, res); + if (IS_ERR(dmc->base_drexi1)) + return PTR_ERR(dmc->base_drexi1); + + res = platform_get_resource(pdev, IORESOURCE_MEM, 2); + dmc->chip_id = devm_ioremap_resource(dev, res); + if (IS_ERR(dmc->chip_id)) + return PTR_ERR(dmc->chip_id); + + ret = exynos5_dmc_chip_revision_settings(dmc); + if (ret) + return ret; + + ret = exynos5_init_freq_table(dev, dmc, &exynos5_dmc_df_profile); + if (ret) { + dev_warn(dev, "couldn't initialize frequency settings\n"); + return ret; + } + + dmc->vdd_mif = devm_regulator_get(dev, "vdd"); + if (IS_ERR(dmc->vdd_mif)) { + ret = PTR_ERR(dmc->vdd_mif); + dev_warn(dev, "couldn't get regulator\n"); + return ret; + } + + ret = exynos5_dmc_init_clks(dev, dmc); + if (ret) { + dev_warn(dev, "couldn't initialize clocks\n"); + return ret; + } + + ret = exynos5_dmc_init_clk_regmap(pdev, dmc); + if (ret) { + dev_warn(dev, "couldn't initialize clock regmap\n"); + return ret; + } + + ret = of_get_dram_timings(dmc); + if (ret) { + dev_warn(dev, "couldn't initialize timings settings\n"); + return ret; + } + + ret = exynos5_performance_counters_init(dmc); + if (ret) { + dev_warn(dev, "couldn't probe performance counters\n"); + goto remove_clocks; + } + + ret = exynos5_dmc_set_pause_on_switching(dmc); + if (ret) { + dev_warn(dev, "couldn't get access to PAUSE register\n"); + goto remove_clocks; + } + + + /* + * Setup default thresholds for the devfreq governor. + * The values are chosen based on experiments. + */ + dmc->gov_data.upthreshold = 30; + dmc->gov_data.downdifferential = 5; + + dmc->df = devm_devfreq_add_device(dev, &exynos5_dmc_df_profile, + DEVFREQ_GOV_USERSPACE, + &dmc->gov_data); + + if (IS_ERR(dmc->df)) { + ret = PTR_ERR(dmc->df); + goto err_devfreq_add; + } + + exynos5_dmc_debugfs_init(dmc); + + dev_info(&pdev->dev, "DMC init for prod_id=0x%08x pkg_id=0x%08x\n", + dmc->prod_rev, dmc->pkg_rev); + + return 0; + +err_devfreq_add: + exynos5_counters_disable_edev(dmc); +remove_clocks: + clk_disable_unprepare(dmc->mout_mx_mspll_ccore); + clk_disable_unprepare(dmc->mout_spll); + + return ret; +} + +/** + * exynos5_dmc_remove() - Remove function for the platform device + * @pdev: platform device which is going to be removed + * + * The function relies on 'devm' framework function which automatically + * clean the device's resources. It just calls explicitly disable function for + * the performance counters. + */ +static int exynos5_dmc_remove(struct platform_device *pdev) +{ + struct exynos5_dmc *dmc = dev_get_drvdata(&pdev->dev); + + exynos5_counters_disable_edev(dmc); + + clk_disable_unprepare(dmc->mout_mx_mspll_ccore); + clk_disable_unprepare(dmc->mout_spll); + + dev_pm_opp_remove_table(&pdev->dev); + + dev_info(&pdev->dev, "DMC removed\n"); + + return 0; +} + +static const struct of_device_id exynos5_dmc_of_match[] = { + { .compatible = "samsung,exynos5422-dmc", }, + { }, +}; +MODULE_DEVICE_TABLE(of, exynos5_dmc_of_match); + +static struct platform_driver exynos5_dmc_platdrv = { + .probe = exynos5_dmc_probe, + .remove = exynos5_dmc_remove, + .driver = { + .name = "exynos5-dmc", + .of_match_table = exynos5_dmc_of_match, + }, +}; +module_platform_driver(exynos5_dmc_platdrv); +MODULE_DESCRIPTION("Driver for Exynos5422 Dynamic Memory Controller dynamic frequency and voltage change" +); +MODULE_LICENSE("GPL v2"); +MODULE_AUTHOR("Samsung"); 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Fri, 19 Apr 2019 14:19:49 +0000 (GMT) From: Lukasz Luba To: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-samsung-soc@vger.kernel.org Cc: b.zolnierkie@samsung.com, krzk@kernel.org, kgene@kernel.org, cw00.choi@samsung.com, kyungmin.park@samsung.com, m.szyprowski@samsung.com, s.nawrocki@samsung.com, myungjoo.ham@samsung.com, keescook@chromium.org, tony@atomide.com, jroedel@suse.de, treding@nvidia.com, digetx@gmail.com, willy.mh.wolff.ml@gmail.com, Lukasz Luba Subject: [PATCH v6 08/10] drivers: devfreq: events: add Exynos PPMU new events Date: Fri, 19 Apr 2019 16:19:26 +0200 Message-Id: <1555683568-20882-9-git-send-email-l.luba@partner.samsung.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1555683568-20882-1-git-send-email-l.luba@partner.samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA0WSWUwTURSGvZ3pzLSxZCxGbhDR1GhcIkvCw3UJkcSHSX3xwQejJFhhAmhb oQMq4kMRXBAqShNBRRDrggVBoGmg0VpLYw20ZRNZq0aUGmQJVAhoMFKm6tt///Od85+cXAqT OoThVLo6i9WoFUoZIcbNbxY9u8jB1sQYW3UYaixvEKL+Hz4hqnJ4hKh2ZhQgffs9AXIVqVDJ 6HcMdXY+J5H74gSJhrQRqNdSQSC/zgFQeadVgJ45vCQazqshUNvEFSF69U6Ohn+FoPm3n8H+ UGZ+rhRn7mq7cab1jpdkmoyFBKPLnyKY11MvBMx1kxEwzR25jL8p8pDoqHhfCqtMP8NqouOP i9OsPXlExhRxzmA3EVowLbwGRBSk46Cr2QWuATElpWsArMjvwfnHDwBnLJVYgJLSfgAnC7C/ HZ5LL4Q89ATAK4992L+Oae3X5QpFEXQUbDFmBhrW0rlwpP/VCoPREwLo/rmABwqh9CHof/Ac D/A4vQVa6zYHbAkth+O6WQEfFgkHPYUrwSL6ILQ8NRGBOZD+QMKBh06Shw5AY21DUIfCcacp qCNgh74Y5zUHtbpqwOsLcLTkXpDZC9uc3Ss7Y/R22GCJ5u0EaC4qEwRsSIfAgck1ARtblqXm Moy3JfDqZSlPb4Om4q7gxuvgk7pbweEMnGx3k/x1KgF8POQmb4CNd/6H3QfACMLYbE6VynKx avZsFKdQcdnq1Kjk06omsPy3On47Z1vAXM8JO6ApIFstsZW2JkqFijNcjsoOIIXJ1koSUkyJ UkmKIuc8qzmdpMlWspwdrKdwWZgkd9WnY1I6VZHFnmLZDFbztyqgROFaoEdd6xa2RhY0biL3 fNz31R51t8U21nZk9vjNNNugr09V71lTZnBl7K+PK2qsuf6oPXNJ/rQ8Iu6Wz1uFVcsOvO+b 9p5Mvn3ZOqL3jhmSwhdiMd0ICHnZa0rYXvjWkeekNsybdxt2fov3xXwBi4YZbClrTut1yCsO U2yF0vVJhnNpitgdmIZT/AEBClIKVwMAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrOIsWRmVeSWpSXmKPExsVy+t/xe7psN3fGGEw4L2WxccZ6VovrX56z Wsw/co7VYvXHx4wWk0/NZbI4051r0f/4NbPF+fMb2C3ONr1ht7jVIGNxedccNovPvUcYLWac 38dksfbIXXaL240r2CwOv2lntdh/xcvi9m8+i28nHjE6CHt8+zqJxWN2w0UWj52z7rJ7bFrV yebR2/yOzePguz1MHn1bVjF6bD5d7fF5k1wAZ5SeTVF+aUmqQkZ+cYmtUrShhZGeoaWFnpGJ pZ6hsXmslZGpkr6dTUpqTmZZapG+XYJexr5LjWwF79gqFh/awtbA+J61i5GTQ0LAROJc6x4g m4tDSGApo8SUFcuZIBJiEpP2bWeHsIUl/lzrYoMo+sQoMeH/UpYuRg4ONgE9iR2rCkFqRATq JfrfXAKrYRZoYJZYs/0q2AZhAT+JJWfusYHUswioSuxbowwS5hXwknjV+wlql5zEzXOdzCA2 p4C3xK6VW9hAbCGgmg3X9jJNYORbwMiwilEktbQ4Nz232FCvODG3uDQvXS85P3cTIzCSth37 uXkH46WNwYcYBTgYlXh4D0zaGSPEmlhWXJl7iFGCg1lJhNcxZUuMEG9KYmVValF+fFFpTmrx IUZToJsmMkuJJucDozyvJN7Q1NDcwtLQ3Njc2MxCSZz3vEFllJBAemJJanZqakFqEUwfEwen VAMji+G+qeu/TLovXRiwetl3ptmdrMaFf5ne9no7q9/ca/0gRDjvTnH1jvPF+8wtQpys+DY/ Tgp1kMlfZ5fwsXviol9P2fyXWJ/kyk/Q5umeEVHTxiItMi/s2Jy38m3li3ISrfnmB7DtNS7m KGg49bw6J+i7aWHov9T/z9V9dvudXlZ29/Vlth9KLMUZiYZazEXFiQBlbPxFugIAAA== X-CMS-MailID: 20190419141950eucas1p2e810215d1ceaf75fc9e807bbaa78e003 X-Msg-Generator: CA X-RootMTR: 20190419141950eucas1p2e810215d1ceaf75fc9e807bbaa78e003 X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20190419141950eucas1p2e810215d1ceaf75fc9e807bbaa78e003 References: <1555683568-20882-1-git-send-email-l.luba@partner.samsung.com> Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Define new performance events supported by Exynos5422 SoC counters. The counters are built-in in Dynamic Memory Controller and provide information regarding memory utilization. Signed-off-by: Lukasz Luba --- drivers/devfreq/event/exynos-ppmu.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/devfreq/event/exynos-ppmu.c b/drivers/devfreq/event/exynos-ppmu.c index 073bf2c..dca97ca 100644 --- a/drivers/devfreq/event/exynos-ppmu.c +++ b/drivers/devfreq/event/exynos-ppmu.c @@ -89,6 +89,12 @@ static struct __exynos_ppmu_events { PPMU_EVENT(d1-cpu), PPMU_EVENT(d1-general), PPMU_EVENT(d1-rt), + + /* For Exynos5422 SoC */ + PPMU_EVENT(dmc0_0), + PPMU_EVENT(dmc0_1), + PPMU_EVENT(dmc1_0), + PPMU_EVENT(dmc1_1), }; static int exynos_ppmu_find_ppmu_id(struct devfreq_event_dev *edev) From patchwork Fri Apr 19 14:19:27 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lukasz Luba X-Patchwork-Id: 10909567 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id E66A714DB for ; Fri, 19 Apr 2019 19:07:53 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id D9F2B28DFA for ; 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Fri, 19 Apr 2019 14:19:52 +0000 (GMT) Received: from eusmgms1.samsung.com (unknown [182.198.249.179]) by eusmtrp1.samsung.com (KnoxPortal) with ESMTP id 20190419141951eusmtrp182221d5655f3c759af35b5b986a98c4f~W5fwHU8zB1902919029eusmtrp1B; Fri, 19 Apr 2019 14:19:51 +0000 (GMT) X-AuditID: cbfec7f4-113ff70000001119-30-5cb9d908fb65 Received: from eusmtip2.samsung.com ( [203.254.199.222]) by eusmgms1.samsung.com (EUCPMTA) with SMTP id 31.12.04146.709D9BC5; Fri, 19 Apr 2019 15:19:51 +0100 (BST) Received: from AMDC3778.DIGITAL.local (unknown [106.120.51.20]) by eusmtip2.samsung.com (KnoxPortal) with ESMTPA id 20190419141951eusmtip205da8a4bb5849df5fae85fc6dddd8ccb~W5fvVd0qR3043530435eusmtip2A; Fri, 19 Apr 2019 14:19:51 +0000 (GMT) From: Lukasz Luba To: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-samsung-soc@vger.kernel.org Cc: b.zolnierkie@samsung.com, krzk@kernel.org, kgene@kernel.org, cw00.choi@samsung.com, kyungmin.park@samsung.com, m.szyprowski@samsung.com, s.nawrocki@samsung.com, myungjoo.ham@samsung.com, keescook@chromium.org, tony@atomide.com, jroedel@suse.de, treding@nvidia.com, digetx@gmail.com, willy.mh.wolff.ml@gmail.com, Lukasz Luba Subject: [PATCH v6 09/10] ARM: dts: exynos: add DMC device for exynos5422 Date: Fri, 19 Apr 2019 16:19:27 +0200 Message-Id: <1555683568-20882-10-git-send-email-l.luba@partner.samsung.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1555683568-20882-1-git-send-email-l.luba@partner.samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA0WSa0hTYRjHe89tZ6PJaYa+pBgNorLysvrwQhJKRSeDrA/1QYWaepjVtmrH S2bE8ta0bKFd1DIdJNpSKlsy12W1Ta10WmTMTLtJCjWDcHbRtJxH8dvvufyf//O8vDQuc5HL 6IPaDE6nVarllIRoaf/Ts55+25oc1Ve9Dt2tuE0ij2+ERDWubhLd+jEEUPmLagx1ndUg49A3 HPX03BEhd55XhPr1oei17RqFxkpdAFX0PMZQk2tQhN6dbqCQ03uGRPbeePRuMgD9fPYZxAay P8fLCPaq/hXBtlYNithmczHFluZ/p9in3x9i7HmLGbD3OnPZseaw3eJESUwapz6YxekiNx+Q pJumKoijt2KPT7VOk3pwMboEiGnIbIT9tWNUCZDQMqYBQGv+c0wIfABOmKpJIRgD8EGeG8xL Gnt7caFQD6C30r0gsRY9mpHQNMVEQKv5mF+wlMmFAx77rABnvBh0T/wm/IVAZgd0ON6QfiaY lbDI6xH5WcrshMZOEyW4hcG33cW4n8UzedtNy+yykHkvgp+6RzG/GWS2wr7yVKE/EH7tsIgE DoWd5ecIgXmoLzXNXXASDhmr53o2QWfHq9mdcWYNvG2LFCbGwa6CEAEDYN/oEn8zPoNlLVdw IS2FhiKZMGM1tJx7iQkcBOsbL8/NZmGb5xIQHuc6gI6+YeoCWF614FULgBkEc5m8RsXxCi2X HcErNXymVhWRekTTDGb+Vud0h88KbH9THIChgXyx9ElZa7KMVGbxORoHgDQuXyqNS7Mky6Rp ypwTnO7Ifl2mmuMdIIQm5MHS3EUfk2SMSpnBHea4o5xuvorR4mV6ULDd2dRoTMg+1OBM6jJ8 MRjFzrrCJXVRx9V7U/s3kHn3V61IdtZ8+Frp9hkwGG5f+yCephT/Vp1qqPuIi9OzCkxBwJkS XKzY2N4mGrbfVWgLvZuObdl2kf10I3Ggfdf1eHEMp+InK/eNTyWUvnx0ITrmqnpPjjKgYsTX kvrrkpzg05XR4biOV/4HihENI1cDAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrBIsWRmVeSWpSXmKPExsVy+t/xe7rsN3fGGBy5YmyxccZ6VovrX56z Wsw/co7VYvXHx4wWk0/NZbI4051r0f/4NbPF+fMb2C3ONr1ht7jVIGNxedccNovPvUcYLWac 38dksfbIXXaL240r2CwOv2lntdh/xcvi9m8+i28nHjE6CHt8+zqJxWN2w0UWj52z7rJ7bFrV yebR2/yOzePguz1MHn1bVjF6bD5d7fF5k1wAZ5SeTVF+aUmqQkZ+cYmtUrShhZGeoaWFnpGJ pZ6hsXmslZGpkr6dTUpqTmZZapG+XYJexsK/M1gKVjtU/N35j7WBcYphFyMnh4SAicSaK1eY uxi5OIQEljJK9M59wwiREJOYtG87O4QtLPHnWhcbRNEnRonHzfNYuxg5ONgE9CR2rCoEqRER qJfof3MJrIZZoIFZYs32q6wgCWEBT4lDhyBsFgFVibY318GG8gp4S/SfXsgGsUBO4ua5TmYQ mxMovmvlFrC4kICXxIZre5kmMPItYGRYxSiSWlqcm55bbKhXnJhbXJqXrpecn7uJERhL2479 3LyD8dLG4EOMAhyMSjy8BybtjBFiTSwrrsw9xCjBwawkwuuYsiVGiDclsbIqtSg/vqg0J7X4 EKMp0FETmaVEk/OBcZ5XEm9oamhuYWlobmxubGahJM573qAySkggPbEkNTs1tSC1CKaPiYNT qoGxq2rPxq9HzeZNVOeYdfJv7KuPjenbvMqE5v92EuKrLeI5dUl1lddi5xPRu+zKejZoX5n4 9uPr75p/wg5MEX2a9L/uh9vCRW9ZGOTWfP4WcV6fo+vkK8W+xxWsV7Uvi11OUwutv56V6dJ8 4TbrGe9Tty3K7f2O776hv0hJsuY5h/+UVPVNNa7flViKMxINtZiLihMBnm0LF7sCAAA= X-CMS-MailID: 20190419141952eucas1p11dc36f30c873a947122e0f7e8d55a3bb X-Msg-Generator: CA X-RootMTR: 20190419141952eucas1p11dc36f30c873a947122e0f7e8d55a3bb X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20190419141952eucas1p11dc36f30c873a947122e0f7e8d55a3bb References: <1555683568-20882-1-git-send-email-l.luba@partner.samsung.com> Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add description of Dynamic Memory Controller and PPMU counters. They are used by exynos5422-dmc driver. There is a definition of the memory chip, hwich is then used during calculation of timings for each OPP. The algorithm in the driver needs these two sets to bound the timings. Signed-off-by: Lukasz Luba --- arch/arm/boot/dts/exynos5420.dtsi | 120 ++++++++++++++++++++++++++ arch/arm/boot/dts/exynos5422-odroid-core.dtsi | 120 ++++++++++++++++++++++++++ 2 files changed, 240 insertions(+) diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi index aaff158..b687cd7 100644 --- a/arch/arm/boot/dts/exynos5420.dtsi +++ b/arch/arm/boot/dts/exynos5420.dtsi @@ -14,6 +14,7 @@ #include #include #include +#include / { compatible = "samsung,exynos5420", "samsung,exynos5"; @@ -235,6 +236,37 @@ status = "disabled"; }; + dmc: memory-controller@10c20000 { + compatible = "samsung,exynos5422-dmc"; + reg = <0x10c20000 0x10000>, <0x10c30000 0x10000>, + <0x10000000 0x1000>, <0x10030000 0x1000>; + clocks = <&clock CLK_FOUT_SPLL>, + <&clock CLK_MOUT_SCLK_SPLL>, + <&clock CLK_FF_DOUT_SPLL2>, + <&clock CLK_FOUT_BPLL>, + <&clock CLK_MOUT_BPLL>, + <&clock CLK_SCLK_BPLL>, + <&clock CLK_MOUT_MX_MSPLL_CCORE>, + <&clock CLK_MOUT_MX_MSPLL_CCORE_PHY>, + <&clock CLK_MOUT_MCLK_CDREX>, + <&clock CLK_DOUT_CLK2X_PHY0>, + <&clock CLK_CLKM_PHY0>, + <&clock CLK_CLKM_PHY1>; + clock-names = "fout_spll", + "mout_sclk_spll", + "ff_dout_spll2", + "fout_bpll", + "mout_bpll", + "sclk_bpll", + "mout_mx_mspll_ccore", + "mout_mx_mspll_ccore_phy", + "mout_mclk_cdrex", + "dout_clk2x_phy0", + "clkm_phy0", + "clkm_phy1"; + status = "disabled"; + }; + nocp_mem0_0: nocp@10ca1000 { compatible = "samsung,exynos5420-nocp"; reg = <0x10CA1000 0x200>; @@ -271,6 +303,94 @@ status = "disabled"; }; + ppmu_dmc0_0: ppmu@10d00000 { + compatible = "samsung,exynos-ppmu"; + reg = <0x10d00000 0x2000>; + clocks = <&clock CLK_PCLK_PPMU_DREX0_0>; + clock-names = "ppmu"; + events { + ppmu_event0_dmc0_0: ppmu-event0-dmc0_0 { + event-name = "ppmu-event0-dmc0_0"; + event-data-type = ; + }; + ppmu_event1_dmc0_0: ppmu-event1-dmc0_0 { + event-name = "ppmu-event1-dmc0_0"; + event-data-type = ; + }; + ppmu_event3_dmc0_0: ppmu-event3-dmc0_0 { + event-name = "ppmu-event3-dmc0_0"; + event-data-type = <(PPMU_RO_DATA_CNT | + PPMU_WO_DATA_CNT)>; + }; + }; + }; + + ppmu_dmc0_1: ppmu@10d10000 { + compatible = "samsung,exynos-ppmu"; + reg = <0x10d10000 0x2000>; + clocks = <&clock CLK_PCLK_PPMU_DREX0_1>; + clock-names = "ppmu"; + events { + ppmu_event0_dmc0_1: ppmu-event0-dmc0_1 { + event-name = "ppmu-event0-dmc0_1"; + event-data-type = ; + }; + ppmu_event1_dmc0_1: ppmu-event1-dmc0_1 { + event-name = "ppmu-event1-dmc0_1"; + event-data-type = ; + }; + ppmu_event3_dmc0_1: ppmu-event3-dmc0_1 { + event-name = "ppmu-event3-dmc0_1"; + event-data-type = <(PPMU_RO_DATA_CNT | + PPMU_WO_DATA_CNT)>; + }; + }; + }; + + ppmu_dmc1_0: ppmu@10d60000 { + compatible = "samsung,exynos-ppmu"; + reg = <0x10d60000 0x2000>; + clocks = <&clock CLK_PCLK_PPMU_DREX1_0>; + clock-names = "ppmu"; + events { + ppmu_event0_dmc1_0: ppmu-event0-dmc1_0 { + event-name = "ppmu-event0-dmc1_0"; + event-data-type = ; + }; + ppmu_event1_dmc1_0: ppmu-event1-dmc1_0 { + event-name = "ppmu-event1-dmc1_0"; + event-data-type = ; + }; + ppmu_event3_dmc1_0: ppmu-event3-dmc1_0 { + event-name = "ppmu-event3-dmc1_0"; + event-data-type = <(PPMU_RO_DATA_CNT | + PPMU_WO_DATA_CNT)>; + }; + }; + }; + + ppmu_dmc1_1: ppmu@10d70000 { + compatible = "samsung,exynos-ppmu"; + reg = <0x10d70000 0x2000>; + clocks = <&clock CLK_PCLK_PPMU_DREX1_1>; + clock-names = "ppmu"; + events { + ppmu_event0_dmc1_1: ppmu-event0-dmc1_1 { + event-name = "ppmu-event0-dmc1_1"; + event-data-type = ; + }; + ppmu_event1_dmc1_1: ppmu-event1-dmc1_1 { + event-name = "ppmu-event1-dmc1_1"; + event-data-type = ; + }; + ppmu_event3_dmc1_1: ppmu-event3-dmc1_1 { + event-name = "ppmu-event3-dmc1_1"; + event-data-type = <(PPMU_RO_DATA_CNT | + PPMU_WO_DATA_CNT)>; + }; + }; + }; + gsc_pd: power-domain@10044000 { compatible = "samsung,exynos4210-pd"; reg = <0x10044000 0x20>; diff --git a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi index 25d95de1..76bf0dbf 100644 --- a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi +++ b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi @@ -34,6 +34,95 @@ clock-frequency = <24000000>; }; }; + + dmc_opp_table: opp_table2 { + compatible = "operating-points-v2"; + + opp00 { + opp-hz = /bits/ 64 <165000000>; + opp-microvolt = <875000>; + }; + opp01 { + opp-hz = /bits/ 64 <206000000>; + opp-microvolt = <875000>; + }; + opp02 { + opp-hz = /bits/ 64 <275000000>; + opp-microvolt = <875000>; + }; + opp03 { + opp-hz = /bits/ 64 <413000000>; + opp-microvolt = <887500>; + }; + opp04 { + opp-hz = /bits/ 64 <543000000>; + opp-microvolt = <937500>; + }; + opp05 { + opp-hz = /bits/ 64 <633000000>; + opp-microvolt = <1012500>; + }; + opp06 { + opp-hz = /bits/ 64 <728000000>; + opp-microvolt = <1037500>; + }; + opp07 { + opp-hz = /bits/ 64 <825000000>; + opp-microvolt = <1050000>; + }; + }; + + samsung_K3QF2F20DB: lpddr3 { + compatible = "Samsung,K3QF2F20DB","jedec,lpddr3"; + density = <16384>; + io-width = <32>; + + tRFC-min-tck = <17>; + tRRD-min-tck = <2>; + tRPab-min-tck = <2>; + tRPpb-min-tck = <2>; + tRCD-min-tck = <3>; + tRC-min-tck = <6>; + tRAS-min-tck = <5>; + tWTR-min-tck = <2>; + tWR-min-tck = <7>; + tRTP-min-tck = <2>; + tW2W-C2C-min-tck = <0>; + tR2R-C2C-min-tck = <0>; + tWL-min-tck = <8>; + tDQSCK-min-tck = <5>; + tRL-min-tck = <14>; + tFAW-min-tck = <5>; + tXSR-min-tck = <12>; + tXP-min-tck = <2>; + tCKE-min-tck = <2>; + tCKESR-min-tck = <2>; + tMRD-min-tck = <5>; + + timings_samsung_K3QF2F20DB_800mhz: lpddr3-timings@0 { + compatible = "jedec,lpddr3-timings"; + min-freq = <100000000>; + max-freq = <800000000>; + tRFC = <65000>; + tRRD = <6000>; + tRPab = <12000>; + tRPpb = <12000>; + tRCD = <10000>; + tRC = <33750>; + tRAS = <23000>; + tWTR = <3750>; + tWR = <7500>; + tRTP = <3750>; + tW2W-C2C = <0>; + tR2R-C2C = <0>; + tFAW = <25000>; + tXSR = <70000>; + tXP = <3750>; + tCKE = <3750>; + tCKESR = <3750>; + tMRD = <7000>; + }; + }; }; &adc { @@ -132,6 +221,21 @@ cpu-supply = <&buck2_reg>; }; +&dmc { + devfreq-events = <&ppmu_event0_dmc0_0>, <&ppmu_event1_dmc0_0>, + <&ppmu_event3_dmc0_0>, + <&ppmu_event0_dmc0_1>,<&ppmu_event1_dmc0_1>, + <&ppmu_event3_dmc0_1>, + <&ppmu_event0_dmc1_0>, <&ppmu_event1_dmc1_0>, + <&ppmu_event3_dmc1_0>, + <&ppmu_event0_dmc1_1>,<&ppmu_event1_dmc1_1>, + <&ppmu_event3_dmc1_1>; + device-handle = <&samsung_K3QF2F20DB>; + operating-points-v2 = <&dmc_opp_table>; + vdd-supply = <&buck1_reg>; + status = "okay"; +}; + &hsi2c_4 { status = "okay"; @@ -540,6 +644,22 @@ }; }; +&ppmu_dmc0_0 { + status = "okay"; +}; + +&ppmu_dmc0_1 { + status = "okay"; +}; + +&ppmu_dmc1_0 { + status = "okay"; +}; + +&ppmu_dmc1_1 { + status = "okay"; +}; + &tmu_cpu0 { vtmu-supply = <&ldo7_reg>; }; From patchwork Fri Apr 19 14:19:28 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lukasz Luba X-Patchwork-Id: 10909591 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 9D10618FD for ; Fri, 19 Apr 2019 19:10:01 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 8EDA128A3A for ; Fri, 19 Apr 2019 19:10:01 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 8282728B21; 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Fri, 19 Apr 2019 14:19:53 +0000 (GMT) Received: from eusmgms1.samsung.com (unknown [182.198.249.179]) by eusmtrp1.samsung.com (KnoxPortal) with ESMTP id 20190419141953eusmtrp11e0e0cdd551996e6aa8258d8f3b685fb~W5fxa1w2G1759317593eusmtrp1k; Fri, 19 Apr 2019 14:19:53 +0000 (GMT) X-AuditID: cbfec7f2-f2dff700000010ca-31-5cb9d90a748c Received: from eusmtip2.samsung.com ( [203.254.199.222]) by eusmgms1.samsung.com (EUCPMTA) with SMTP id 72.12.04146.909D9BC5; Fri, 19 Apr 2019 15:19:53 +0100 (BST) Received: from AMDC3778.DIGITAL.local (unknown [106.120.51.20]) by eusmtip2.samsung.com (KnoxPortal) with ESMTPA id 20190419141952eusmtip265c67a3930848a783e7feb5fdee309e5~W5fwkwQDv3242832428eusmtip2X; Fri, 19 Apr 2019 14:19:52 +0000 (GMT) From: Lukasz Luba To: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-samsung-soc@vger.kernel.org Cc: b.zolnierkie@samsung.com, krzk@kernel.org, kgene@kernel.org, cw00.choi@samsung.com, kyungmin.park@samsung.com, m.szyprowski@samsung.com, s.nawrocki@samsung.com, myungjoo.ham@samsung.com, keescook@chromium.org, tony@atomide.com, jroedel@suse.de, treding@nvidia.com, digetx@gmail.com, willy.mh.wolff.ml@gmail.com, Lukasz Luba Subject: [PATCH v6 10/10] ARM: exynos_defconfig: enable DMC driver Date: Fri, 19 Apr 2019 16:19:28 +0200 Message-Id: <1555683568-20882-11-git-send-email-l.luba@partner.samsung.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1555683568-20882-1-git-send-email-l.luba@partner.samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA0WSe0hTURzHO/ex3Y0Wtyl5MLFYBBalCSsOFFFRcE2CwkpIQ2de1HJqu2kt K6aBz5mllK98IaVNzUfLplm+lqamZkq+0kqtIM3wrQnRrnfVf5/v9/f9/c7vHA6Fy5tIeyoo 5BKrCVEFK0RSoqp5uWundKDae1fLMoYq0stI1Df3jUS55k4SFU+PAZTalo2hN4lqlDw2gaOu rnIx6oieFKNBnQPqqbkvQrNJZoDSu15iqNQ8LEZDUUUi1DQZS6K63qNoaGUdWng9Cg7YMAvz KQSTpesmmOrMYTFTaYgXMUk3p0RMw1QtxtwyGgDzpD2Sma10PC45I93nzwYHRbAal/2+0sA2 vUfYF/KKcSmO0IFEMgFIKEgrYUriKwtLKTldBGDG03FMEHMA6kfSxYKYBXByOMEiqNWWOr0b 3y2nCwFMLT3/r6E2P5ngMyLaGZoMF/mMLR0JP/TV4XwGpycx2PFrieALNvQhWLzYgfNM0Fth SXmamGcZ7Q4NpmlcWM8RDnTGr7LE4tc8Mor4QZAeEcMi84A1dBh+HRkVCWwDv7cYxQI7wPZU PSEwB3VJ+UDga3AsOdua2QubWrpJfmmc3gbLalwE+yBcaC2w3ncd7P+xnrdxC6ZUpeGCLYNx MXIh7QSN+reYwBtgYck963AGxrcZrU+YA+DMSjN2G2zK/H9YHgAGYMeGc+oAlnMNYS87cyo1 Fx4S4HwuVF0JLF+r/XfLjAnMv/NrBDQFFGtl9SnV3nJSFcFp1Y0AUrjCVnbQ3+gtl/mrtFdZ TaiPJjyY5RrBRopQ2Mki13zyktMBqkvsBZYNYzV/qxglsdeBPTkySYPni8F4z1kPZc6xPYv9 rbedzmbaxuCPNz/XeT/IOqVse+sjzSvM6svz8Tc/S1BEmB7ujd7hq7Xvre/8GPtl+vqtAm1s 6s/3iye3+uVW9BOjJ05luPklgewF9wavO8qez2T15rwjHm7zN07PxOVMDEWdMPQoHMe1W7rL Tu++qyC4QJXrdlzDqf4ApRZqBVYDAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrKIsWRmVeSWpSXmKPExsVy+t/xe7qcN3fGGOxbxmuxccZ6VovrX56z Wsw/co7VYvXHx4wWk0/NZbI4051r0f/4NbPF+fMb2C3ONr1ht7jVIGNxedccNovPvUcYLWac 38dksfbIXXaL240r2CwOv2lntdh/xcvi9m8+i28nHjE6CHt8+zqJxWN2w0UWj52z7rJ7bFrV yebR2/yOzePguz1MHn1bVjF6bD5d7fF5k1wAZ5SeTVF+aUmqQkZ+cYmtUrShhZGeoaWFnpGJ pZ6hsXmslZGpkr6dTUpqTmZZapG+XYJexqme4IKnrBVbfnSwNDB2s3YxcnBICJhI7O/x7GLk 5BASWMoo8XAhG4gtISAmMWnfdnYIW1jiz7UuoDgXUM0nRolHW7eC9bIJ6EnsWFUIUiMiUC/R /+YSWA2zQAOzxJrtV1lBEsICThKrv59lBrFZBFQl1myYDjaUV8BbYtWOj8wQC+Qkbp7rBLM5 geK7Vm5hgzjIS2LDtb1MExj5FjAyrGIUSS0tzk3PLTbUK07MLS7NS9dLzs/dxAiMom3Hfm7e wXhpY/AhRgEORiUe3gOTdsYIsSaWFVfmHmKU4GBWEuF1TNkSI8SbklhZlVqUH19UmpNafIjR FOioicxSosn5wAjPK4k3NDU0t7A0NDc2NzazUBLnPW9QGSUkkJ5YkpqdmlqQWgTTx8TBKdXA WLhevurO8cVevs/SdHbs/vXjZej3KW+uiLTpL96yVqbV8W/8rO4sc55LcrVXr/gsmP5wz7MF L9n/XpgQab7p6t+5VsmyDDZSJad3/+QrWXWIX7Bo5rsjqzb69nV/+7B+6qGNPzq//YvomnDp ut205pIzGfp+OrqaidsaKzt6uy4ztR7q74hcMU2JpTgj0VCLuag4EQCMSGGruAIAAA== X-CMS-MailID: 20190419141953eucas1p1b403be15353fa31de3e226599b675f67 X-Msg-Generator: CA X-RootMTR: 20190419141953eucas1p1b403be15353fa31de3e226599b675f67 X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20190419141953eucas1p1b403be15353fa31de3e226599b675f67 References: <1555683568-20882-1-git-send-email-l.luba@partner.samsung.com> Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Enable driver for Exynos5422 Dynamic Memory Controller supporting dynamic frequency and voltage scaling in Exynos5422 SoCs. Signed-off-by: Lukasz Luba --- arch/arm/configs/exynos_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/configs/exynos_defconfig b/arch/arm/configs/exynos_defconfig index d635edf..04c076e 100644 --- a/arch/arm/configs/exynos_defconfig +++ b/arch/arm/configs/exynos_defconfig @@ -291,6 +291,7 @@ CONFIG_DEVFREQ_GOV_PERFORMANCE=y CONFIG_DEVFREQ_GOV_POWERSAVE=y CONFIG_DEVFREQ_GOV_USERSPACE=y CONFIG_ARM_EXYNOS_BUS_DEVFREQ=y +CONFIG_ARM_EXYNOS5422_DMC=y CONFIG_DEVFREQ_EVENT_EXYNOS_NOCP=y CONFIG_EXYNOS_IOMMU=y CONFIG_EXTCON=y