From patchwork Tue Apr 23 08:51:24 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neil Armstrong X-Patchwork-Id: 10912331 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 37D2F1575 for ; Tue, 23 Apr 2019 08:51:59 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 2B8592870B for ; Tue, 23 Apr 2019 08:51:59 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 2979F28882; Tue, 23 Apr 2019 08:51:59 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id C4811287C3 for ; Tue, 23 Apr 2019 08:51:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726966AbfDWIve (ORCPT ); Tue, 23 Apr 2019 04:51:34 -0400 Received: from mail-wm1-f65.google.com ([209.85.128.65]:37656 "EHLO mail-wm1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726645AbfDWIvd (ORCPT ); Tue, 23 Apr 2019 04:51:33 -0400 Received: by mail-wm1-f65.google.com with SMTP id v14so17742040wmf.2 for ; Tue, 23 Apr 2019 01:51:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=1H3HhuutqaciX5XVa5YZyQWcZq+QYJmYc29n+3rNfQQ=; b=zDLfJXO39CUmp95Ai/ksmyDI9XHay6nQzRnKtjQ2i8UHKXeEP28qNnthrBCPqTV4Uy y/G1NORz8CVzk9Cu3mTyeTzg+7R+PwWGjtLX7L34SmMDghYjE0BfEhd50CGEGTVFUp7S kGYdeldsWFA2dm0/bxlQLIJyBDFu6GkNkK89t5k2Hj09sr3L4tKuxOksYZLq3oYwRFTK JOohS6Hr9Fb64gzVB/Q8ULzq1kA0pAlMW0LU5zLT00kp+DLcHCd49p/MBc7zEHAZ+xUG RtbGZ2Cra3TB2hNpZ8vP+oMnBPGopX6EZsWb/5ox5neyRCCg5q5pfydTs7OIkJuyh4PE PjaA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=1H3HhuutqaciX5XVa5YZyQWcZq+QYJmYc29n+3rNfQQ=; b=r/E5y/Q0yarqWwgeuFjC7XtkqjxEAJfp4ROuzO+S3BtWjMIX90zIcPcOVFzJLG0roa 1rV3rU9//DxRHzPyggOwWLpieWODsQzqcdUDQwdNzHaccgWDqDNJXIE/YAwITOk4109K +h8//MXuB05qnTXOmIiJtlHA3STujIN85/aHcEArgqTeoACEKhUAaIsvpIyMCKcIYW9W BQhvLGB8qyXcLGLIStH4deOwyM6QfWn2UTRihVjQ575RHahlcc04EUKFMtLFpwD58TYj GVGqfW/vN1P8iEKGN1Qveews532LlPcUmStMJb/W+uYyJWy+lfXQ4zVDxYDQ83AmJV5b xzww== X-Gm-Message-State: APjAAAXIyNJ/wiXXNDojQlw+6RIt4Zqs6vwt2ft6ix3IG885+fqDbXHZ wBZs7O0i4av/CC+wGlCMfitV9Q== X-Google-Smtp-Source: APXvYqz7WYQn3ddhxQGgEV0tPmUF4XhHH+DjXXbgvObw/DvJbVNAIQR7c5flZU8nKuvJ6DfIpMCjlg== X-Received: by 2002:a7b:c3c9:: with SMTP id t9mr1315184wmj.131.1556009491848; Tue, 23 Apr 2019 01:51:31 -0700 (PDT) Received: from bender.baylibre.local (lmontsouris-657-1-212-31.w90-63.abo.wanadoo.fr. [90.63.244.31]) by smtp.gmail.com with ESMTPSA id b8sm12515566wrr.64.2019.04.23.01.51.30 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 23 Apr 2019 01:51:31 -0700 (PDT) From: Neil Armstrong To: gregkh@linuxfoundation.org, hminas@synopsys.com, balbi@kernel.org, kishon@ti.com, devicetree@vger.kernel.org, chunfeng.yun@mediatek.com Cc: Neil Armstrong , linux-amlogic@lists.infradead.org, linux-usb@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Martin Blumenstingl , Rob Herring Subject: [PATCH v6 1/4] dt-bindings: usb: dwc2: Add Amlogic G12A DWC2 Compatible Date: Tue, 23 Apr 2019 10:51:24 +0200 Message-Id: <20190423085127.3863-2-narmstrong@baylibre.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190423085127.3863-1-narmstrong@baylibre.com> References: <20190423085127.3863-1-narmstrong@baylibre.com> MIME-Version: 1.0 Sender: linux-usb-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Adds the specific compatible string for the DWC2 IP found in the Amlogic G12A SoC Family. Signed-off-by: Neil Armstrong Reviewed-by: Martin Blumenstingl Reviewed-by: Rob Herring --- Documentation/devicetree/bindings/usb/dwc2.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/usb/dwc2.txt b/Documentation/devicetree/bindings/usb/dwc2.txt index 6dc3c4a34483..e150b7b227c9 100644 --- a/Documentation/devicetree/bindings/usb/dwc2.txt +++ b/Documentation/devicetree/bindings/usb/dwc2.txt @@ -14,6 +14,7 @@ Required properties: - "amlogic,meson8-usb": The DWC2 USB controller instance in Amlogic Meson8 SoCs; - "amlogic,meson8b-usb": The DWC2 USB controller instance in Amlogic Meson8b SoCs; - "amlogic,meson-gxbb-usb": The DWC2 USB controller instance in Amlogic S905 SoCs; + - "amlogic,meson-g12a-usb": The DWC2 USB controller instance in Amlogic G12A SoCs; - "amcc,dwc-otg": The DWC2 USB controller instance in AMCC Canyonlands 460EX SoCs; - snps,dwc2: A generic DWC2 USB controller with default parameters. - "st,stm32f4x9-fsotg": The DWC2 USB FS/HS controller instance in STM32F4x9 SoCs From patchwork Tue Apr 23 08:51:25 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neil Armstrong X-Patchwork-Id: 10912317 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 7A2E1112C for ; Tue, 23 Apr 2019 08:51:38 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 6E02528849 for ; Tue, 23 Apr 2019 08:51:38 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 6C44028866; Tue, 23 Apr 2019 08:51:38 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 48C6928862 for ; Tue, 23 Apr 2019 08:51:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727010AbfDWIvg (ORCPT ); Tue, 23 Apr 2019 04:51:36 -0400 Received: from mail-wr1-f68.google.com ([209.85.221.68]:34269 "EHLO mail-wr1-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726502AbfDWIvf (ORCPT ); Tue, 23 Apr 2019 04:51:35 -0400 Received: by mail-wr1-f68.google.com with SMTP id c6so13410962wrm.1 for ; Tue, 23 Apr 2019 01:51:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=2eRvrsWl11jM2CeP6qjHv6pCX8ts9ZzW3hyQekHEmZg=; b=NFxNZ2q15C/vPadP8pQ/wqkRWfwbF8oj5aMRWlrjab/n/RYtvEokoBJPhzat+nnly3 TZJFVAItm8wG6AvwCp3hRgFfaKafRR1Tf8chFM6wxjUdSRGeE4hQjxAJdsCezVpiUNeU BLYJ4dCLa3XY8p0zXytJtVowyJrL5HLCrXPnViF2FW/0BseGumfot5QI/jxWgEO2f4nu xBnoLtxdSH8Mk0VFFNBNxPEP0aEukt3LR2MSmHj9ukZjo4QE85awN30KhYMjWtpZH5Z2 fqkddNkmJ0ZNfW3Q0RCaKLjnZ3s5/o06I41s9XdomxLI0GyUhBq5c5kob1xjGJ+ZM2Kj Q5WA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=2eRvrsWl11jM2CeP6qjHv6pCX8ts9ZzW3hyQekHEmZg=; b=O22t8DK6Fr5Fc7/qZmSJLwBjxgldO6FnKgw5pRdCUxPKRKu0rCbKW1mfUu5L8KILAM hh1NRbQ6qpWPPMlMafhS1ciDAPz9nlf+/+zamZT3VkdBe0dsjBsJxNRmU4+Uf85aA1Hq Nif/GgyilSJ4duM7GBwN7zIGmIVAEX4HCZPxP8/Ki0viByeYyKn1VQUuVRyvRhRcHTSX bXNlSvOLOxm9/8LKt3ygDI9VEh7/ZXp9eBQQAfsZ3mznb2KP8EvBKJKzSqHORokX55e6 sdS9GmSgsl2wMHcj3fJDh5dixBfetWjZkWN2nv/RTFy+HKhoew4+TGMP2Jwqw1Yhu0s7 rL9g== X-Gm-Message-State: APjAAAUJjvjVuz5xToibMbSWecjeixS2bHQunNUaVLYZfA5R6AaCWDsr eriQVq7cNGKpfZgSYYLHCTntUQ== X-Google-Smtp-Source: APXvYqxxzoajGmQ1hMWGbD+YMXI75HgSK2kM6eXk2ENdEpvOEUn3dUDT26PABekTmPBqCQjkTRcKOg== X-Received: by 2002:adf:9051:: with SMTP id h75mr1539366wrh.115.1556009493067; Tue, 23 Apr 2019 01:51:33 -0700 (PDT) Received: from bender.baylibre.local (lmontsouris-657-1-212-31.w90-63.abo.wanadoo.fr. [90.63.244.31]) by smtp.gmail.com with ESMTPSA id b8sm12515566wrr.64.2019.04.23.01.51.31 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 23 Apr 2019 01:51:32 -0700 (PDT) From: Neil Armstrong To: gregkh@linuxfoundation.org, hminas@synopsys.com, balbi@kernel.org, kishon@ti.com, devicetree@vger.kernel.org, chunfeng.yun@mediatek.com Cc: Neil Armstrong , linux-amlogic@lists.infradead.org, linux-usb@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Martin Blumenstingl , Rob Herring Subject: [PATCH v6 2/4] dt-bindings: usb: dwc3: Add Amlogic G12A DWC3 Glue Bindings Date: Tue, 23 Apr 2019 10:51:25 +0200 Message-Id: <20190423085127.3863-3-narmstrong@baylibre.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190423085127.3863-1-narmstrong@baylibre.com> References: <20190423085127.3863-1-narmstrong@baylibre.com> MIME-Version: 1.0 Sender: linux-usb-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Adds the bindings for the Amlogic G12A USB Glue HW. The Amlogic G12A SoC Family embeds 2 USB Controllers : - a DWC3 IP configured as Host for USB2 and USB3 - a DWC2 IP configured as Peripheral USB2 Only A glue connects these both controllers to 2 USB2 PHYs, and optionnally to an USB3+PCIE Combo PHY shared with the PCIE controller. The Glue configures the UTMI 8bit interfaces for the USB2 PHYs, including routing of the OTG PHY between the DWC3 and DWC2 controllers, and setups the on-chip OTG mode selection for this PHY. The PHYs phandles are passed to the Glue node since the Glue controls the interface with the PHY, not the DWC3 controller. Signed-off-by: Neil Armstrong Reviewed-by: Martin Blumenstingl Reviewed-by: Rob Herring --- .../devicetree/bindings/usb/amlogic,dwc3.txt | 88 +++++++++++++++++++ 1 file changed, 88 insertions(+) diff --git a/Documentation/devicetree/bindings/usb/amlogic,dwc3.txt b/Documentation/devicetree/bindings/usb/amlogic,dwc3.txt index 9a8b631904fd..b9f04e617eb7 100644 --- a/Documentation/devicetree/bindings/usb/amlogic,dwc3.txt +++ b/Documentation/devicetree/bindings/usb/amlogic,dwc3.txt @@ -40,3 +40,91 @@ Example device nodes: phy-names = "usb2-phy", "usb3-phy"; }; }; + +Amlogic Meson G12A DWC3 USB SoC Controller Glue + +The Amlogic G12A embeds a DWC3 USB IP Core configured for USB2 and USB3 +in host-only mode, and a DWC2 IP Core configured for USB2 peripheral mode +only. + +A glue connects the DWC3 core to USB2 PHYs and optionnaly to an USB3 PHY. + +One of the USB2 PHY can be re-routed in peripheral mode to a DWC2 USB IP. + +The DWC3 Glue controls the PHY routing and power, an interrupt line is +connected to the Glue to serve as OTG ID change detection. + +Required properties: +- compatible: Should be "amlogic,meson-g12a-usb-ctrl" +- clocks: a handle for the "USB" clock +- resets: a handle for the shared "USB" reset line +- reg: The base address and length of the registers +- interrupts: the interrupt specifier for the OTG detection +- phys: handle to used PHYs on the system + - a <0> phandle can be used if a PHY is not used +- phy-names: names of the used PHYs on the system : + - "usb2-phy0" for USB2 PHY0 if USBHOST_A port is used + - "usb2-phy1" for USB2 PHY1 if USBOTG_B port is used + - "usb3-phy0" for USB3 PHY if USB3_0 is used +- dr_mode: should be "host", "peripheral", or "otg" depending on + the usage and configuration of the OTG Capable port. + - "host" and "peripheral" means a fixed Host or Device only connection + - "otg" means the port can be used as both Host or Device and + be switched automatically using the OTG ID pin. + +Optional properties: +- vbus-supply: should be a phandle to the regulator controlling the VBUS + power supply when used in OTG switchable mode + +Required child nodes: + +A child node must exist to represent the core DWC3 IP block. The name of +the node is not important. The content of the node is defined in dwc3.txt. + +A child node must exist to represent the core DWC2 IP block. The name of +the node is not important. The content of the node is defined in dwc2.txt. + +PHY documentation is provided in the following places: +- Documentation/devicetree/bindings/phy/meson-g12a-usb2-phy.txt +- Documentation/devicetree/bindings/phy/meson-g12a-usb3-pcie-phy.txt + +Example device nodes: + usb: usb@ffe09000 { + compatible = "amlogic,meson-g12a-usb-ctrl"; + reg = <0x0 0xffe09000 0x0 0xa0>; + interrupts = ; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + clocks = <&clkc CLKID_USB>; + resets = <&reset RESET_USB>; + + dr_mode = "otg"; + + phys = <&usb2_phy0>, <&usb2_phy1>, + <&usb3_pcie_phy PHY_TYPE_USB3>; + phy-names = "usb2-phy0", "usb2-phy1", "usb3-phy0"; + + dwc2: usb@ff400000 { + compatible = "amlogic,meson-g12a-usb", "snps,dwc2"; + reg = <0x0 0xff400000 0x0 0x40000>; + interrupts = ; + clocks = <&clkc CLKID_USB1_DDR_BRIDGE>; + clock-names = "ddr"; + phys = <&usb2_phy1>; + dr_mode = "peripheral"; + g-rx-fifo-size = <192>; + g-np-tx-fifo-size = <128>; + g-tx-fifo-size = <128 128 16 16 16>; + }; + + dwc3: usb@ff500000 { + compatible = "snps,dwc3"; + reg = <0x0 0xff500000 0x0 0x100000>; + interrupts = ; + dr_mode = "host"; + snps,dis_u2_susphy_quirk; + snps,quirk-frame-length-adjustment; + }; + }; From patchwork Tue Apr 23 08:51:26 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neil Armstrong X-Patchwork-Id: 10912329 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 164F3112C for ; Tue, 23 Apr 2019 08:51:58 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 0A13128789 for ; Tue, 23 Apr 2019 08:51:58 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 08118287B3; Tue, 23 Apr 2019 08:51:58 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id E3DA32888A for ; Tue, 23 Apr 2019 08:51:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727094AbfDWIvv (ORCPT ); Tue, 23 Apr 2019 04:51:51 -0400 Received: from mail-wr1-f67.google.com ([209.85.221.67]:38795 "EHLO mail-wr1-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726991AbfDWIvg (ORCPT ); Tue, 23 Apr 2019 04:51:36 -0400 Received: by mail-wr1-f67.google.com with SMTP id f14so18525660wrj.5 for ; Tue, 23 Apr 2019 01:51:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=coKjxKEGXPOOgyUNg/X4oYYa6DNUzfkR3oMZh6thI8k=; b=ihj+o2ZmtmjS3IXh+DTe7xY3Q/wvndiKyf4IBEXxM3dQd4o8dwgq+d7GAfShEyu+Nz 4pL6CcLuTMiwugg8guG56xbbYfpzBnbkxmv3+P9ILJXDf8fTJsNVSi/iAbJq5+PM5N1w Czj8BYpaIRv4O8+ATXw4kpI5ZUo5LfINnbscU2vZPI8WR3a33JmktoTZ6rXbAaGP1AeX cyynp7snEhs9mvji0QMwPFC3uq9ynKKaI5zXJnI6NH7HlnB9bEeugWkpP5bW1EsbEbIz XDyy2nqQZRgGCqjpCAEfty51r+0zICh5QjSIP2KyIrTzL6a2yzdZKJOXjiG2rbIdFaDO VQTg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=coKjxKEGXPOOgyUNg/X4oYYa6DNUzfkR3oMZh6thI8k=; b=cNOCC4cWCCVgHN7tyW/vbjhHklLjD9RNojRV7sl0KumcXe1G+Kd3Qjon6yQbQaB8Qi x1XzTst05dtMc1MHVsXxoIp8dO+m4LEcjfPYX6aQ3DNCviz86t9UhK6suuddOrW+6SIx TvnZY5ZFw5nu4UZ1XbbK/WR26qXMYRWLIutBqwFYfIe9Mo0GFcccDqqQfQEYFEVfYyvQ X1k5mvEBz9QbbQxNuOkxCZ1Hh8OP8uA3mYIvxVoBxyGBRgQqUA17g5EXmd+UGk/jMwsY 7vHKjNb/rCgYGZoO/i4CfIgAMaBgRzd4A5ZbEvFKQrDqjxojMAUcFwhW94bjAEc2WRsD mFzg== X-Gm-Message-State: APjAAAWVqdFkft0jBHhtNCMgpCrPL/7PnmkFM9pfXP9vl6eoPcZjPaeU Ptm0nyA4P3HZZKI9XN5C2jHgSg== X-Google-Smtp-Source: APXvYqyW/gIU7AhNE1eDBER3np45Wvdh3xrRnMDM4D6q4COqDjzzUTJIN8//q+XpGVfl8Whe2SDRzQ== X-Received: by 2002:a5d:62cf:: with SMTP id o15mr9862063wrv.45.1556009494215; Tue, 23 Apr 2019 01:51:34 -0700 (PDT) Received: from bender.baylibre.local (lmontsouris-657-1-212-31.w90-63.abo.wanadoo.fr. [90.63.244.31]) by smtp.gmail.com with ESMTPSA id b8sm12515566wrr.64.2019.04.23.01.51.33 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 23 Apr 2019 01:51:33 -0700 (PDT) From: Neil Armstrong To: gregkh@linuxfoundation.org, hminas@synopsys.com, balbi@kernel.org, kishon@ti.com, chunfeng.yun@mediatek.com Cc: Neil Armstrong , linux-amlogic@lists.infradead.org, linux-usb@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v6 3/4] usb: dwc2: Add Amlogic G12A DWC2 Params Date: Tue, 23 Apr 2019 10:51:26 +0200 Message-Id: <20190423085127.3863-4-narmstrong@baylibre.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190423085127.3863-1-narmstrong@baylibre.com> References: <20190423085127.3863-1-narmstrong@baylibre.com> MIME-Version: 1.0 Sender: linux-usb-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patchs sets the params for the DWC2 Controller found in the Amlogic G12A SoC family. It mainly sets the settings reported incorrect by the driver, leaving the remaining detected automatically by the driver and provided by the DT node. Signed-off-by: Neil Armstrong Acked-by: Minas Harutyunyan --- drivers/usb/dwc2/params.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/usb/dwc2/params.c b/drivers/usb/dwc2/params.c index 24ff5f21cb25..442113246cba 100644 --- a/drivers/usb/dwc2/params.c +++ b/drivers/usb/dwc2/params.c @@ -121,6 +121,16 @@ static void dwc2_set_amlogic_params(struct dwc2_hsotg *hsotg) p->power_down = DWC2_POWER_DOWN_PARAM_NONE; } +static void dwc2_set_amlogic_g12a_params(struct dwc2_hsotg *hsotg) +{ + struct dwc2_core_params *p = &hsotg->params; + + p->lpm = false; + p->lpm_clock_gating = false; + p->besl = false; + p->hird_threshold_en = false; +} + static void dwc2_set_amcc_params(struct dwc2_hsotg *hsotg) { struct dwc2_core_params *p = &hsotg->params; @@ -167,6 +177,8 @@ const struct of_device_id dwc2_of_match_table[] = { .data = dwc2_set_amlogic_params }, { .compatible = "amlogic,meson-gxbb-usb", .data = dwc2_set_amlogic_params }, + { .compatible = "amlogic,meson-g12a-usb", + .data = dwc2_set_amlogic_g12a_params }, { .compatible = "amcc,dwc-otg", .data = dwc2_set_amcc_params }, { .compatible = "st,stm32f4x9-fsotg", .data = dwc2_set_stm32f4x9_fsotg_params }, From patchwork Tue Apr 23 08:51:27 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neil Armstrong X-Patchwork-Id: 10912325 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 7D2971575 for ; Tue, 23 Apr 2019 08:51:51 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 6EE5A287FE for ; Tue, 23 Apr 2019 08:51:51 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 6CBFD287C3; Tue, 23 Apr 2019 08:51:51 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 2B90128892 for ; Tue, 23 Apr 2019 08:51:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727068AbfDWIvo (ORCPT ); Tue, 23 Apr 2019 04:51:44 -0400 Received: from mail-wm1-f68.google.com ([209.85.128.68]:54975 "EHLO mail-wm1-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727014AbfDWIvh (ORCPT ); Tue, 23 Apr 2019 04:51:37 -0400 Received: by mail-wm1-f68.google.com with SMTP id c1so17575971wml.4 for ; Tue, 23 Apr 2019 01:51:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=dNQId/lIoLaeASu9LURTpjplB7RM/acz/QEseA3Bzw0=; b=wNwbHM+dPBYbTvbj6S96lLoR+fA56F5c5QeYF5FiD5uvmoelO7DkvYBkXgRTCRp+Cc AwnEkC4Jx0bYdNyFRHiWTZB8KPnTAZnH7wJvjucX9/BgS6qKj7I3S9fNVNCiR28XCtiC 4CkQSDq8I4iIqdMgG+p2uxWqCULcpOIf0My7DwITbhmDtgorCanGeBRcVGxen8SsnO4S xYrVZ04iXXa0Vy326mOlyfGeacGnwjTXX1sydjFnpBBuRq1oY4TLOKKh0Yp7MfW4sfRb A++gYnjPVYzifFZ9QREwzkR6vfWt9cl6Sk0lyTleltomBiQPeI+9mB1D3/x2UbjHb32J 7Urw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=dNQId/lIoLaeASu9LURTpjplB7RM/acz/QEseA3Bzw0=; b=pTdj/c9nUeDHbfANr4yLheA5NS3LU1OXSve/fJgp28jAIboz+FsB+UYA+Rxk54RgKp nMMjhYJ4x1+25z/Tr3NoFHfqTsBUn8ZMGBGNYL4aANXpg3V4m5iGnmo8BzCTVZiQnnco JbBNPd+rtmR1fJWfofNKCojQvkezFI9Hrzb6oLhg/GNv8+lM1xvFFN9yDcPOSir8YWxb /4b3KPzFQs1uCSdX+/twh3UrXKvk/AOutgCCH67TnRDAny40AqSIgGRYFnabjzD2SdGV zditEB88hdf/2HRGqc79Gzi18IxL9z9uMElIvBQayVvTrZP4IIuT0LLfwisfenqUgZsp NCIA== X-Gm-Message-State: APjAAAV+XyTAuz0d8gaoXuJCgvHl9ib6B7MwZSIAXs+wlUTQFLs5EVbm ENJa7PRuN5I16zcCMw357zuBKA== X-Google-Smtp-Source: APXvYqytrK8zNaMr68FTBm7awfbMxPJjBj5ZYU0dDtjdDhjcK50UI9pXPQQXIZ6DkTKRS8RczvPLGA== X-Received: by 2002:a1c:6783:: with SMTP id b125mr1340549wmc.79.1556009495366; Tue, 23 Apr 2019 01:51:35 -0700 (PDT) Received: from bender.baylibre.local (lmontsouris-657-1-212-31.w90-63.abo.wanadoo.fr. [90.63.244.31]) by smtp.gmail.com with ESMTPSA id b8sm12515566wrr.64.2019.04.23.01.51.34 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 23 Apr 2019 01:51:34 -0700 (PDT) From: Neil Armstrong To: gregkh@linuxfoundation.org, hminas@synopsys.com, balbi@kernel.org, kishon@ti.com, chunfeng.yun@mediatek.com Cc: Neil Armstrong , linux-amlogic@lists.infradead.org, linux-usb@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Martin Blumenstingl Subject: [PATCH v6 4/4] usb: dwc3: Add Amlogic G12A DWC3 glue Date: Tue, 23 Apr 2019 10:51:27 +0200 Message-Id: <20190423085127.3863-5-narmstrong@baylibre.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190423085127.3863-1-narmstrong@baylibre.com> References: <20190423085127.3863-1-narmstrong@baylibre.com> MIME-Version: 1.0 Sender: linux-usb-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Adds support for Amlogic G12A USB Control Glue HW. The Amlogic G12A SoC Family embeds 2 USB Controllers : - a DWC3 IP configured as Host for USB2 and USB3 - a DWC2 IP configured as Peripheral USB2 Only A glue connects these both controllers to 2 USB2 PHYs, and optionnally to an USB3+PCIE Combo PHY shared with the PCIE controller. The Glue configures the UTMI 8bit interfaces for the USB2 PHYs, including routing of the OTG PHY between the DWC3 and DWC2 controllers, and setups the on-chip OTG mode selection for this PHY. This drivers supports the on-probe setup of the OTG mode, and manually via a debugfs interface. The IRQ mode change detect is yet to be added in a future patchset, mainly due to lack of hardware to validate on. Signed-off-by: Neil Armstrong Reviewed-by: Martin Blumenstingl --- drivers/usb/dwc3/Kconfig | 10 + drivers/usb/dwc3/Makefile | 1 + drivers/usb/dwc3/dwc3-meson-g12a.c | 604 +++++++++++++++++++++++++++++ 3 files changed, 615 insertions(+) create mode 100644 drivers/usb/dwc3/dwc3-meson-g12a.c diff --git a/drivers/usb/dwc3/Kconfig b/drivers/usb/dwc3/Kconfig index 2b1494460d0c..d2ea9670563c 100644 --- a/drivers/usb/dwc3/Kconfig +++ b/drivers/usb/dwc3/Kconfig @@ -95,6 +95,16 @@ config USB_DWC3_KEYSTONE Support of USB2/3 functionality in TI Keystone2 and AM654 platforms. Say 'Y' or 'M' here if you have one such device +config USB_DWC3_MESON_G12A + tristate "Amlogic Meson G12A Platforms" + depends on OF && COMMON_CLK + depends on ARCH_MESON || COMPILE_TEST + default USB_DWC3 + select USB_ROLE_SWITCH + help + Support USB2/3 functionality in Amlogic G12A platforms. + Say 'Y' or 'M' if you have one such device. + config USB_DWC3_OF_SIMPLE tristate "Generic OF Simple Glue Layer" depends on OF && COMMON_CLK diff --git a/drivers/usb/dwc3/Makefile b/drivers/usb/dwc3/Makefile index 6e3ef6144e5d..ae86da0dc5bd 100644 --- a/drivers/usb/dwc3/Makefile +++ b/drivers/usb/dwc3/Makefile @@ -47,6 +47,7 @@ obj-$(CONFIG_USB_DWC3_EXYNOS) += dwc3-exynos.o obj-$(CONFIG_USB_DWC3_PCI) += dwc3-pci.o obj-$(CONFIG_USB_DWC3_HAPS) += dwc3-haps.o obj-$(CONFIG_USB_DWC3_KEYSTONE) += dwc3-keystone.o +obj-$(CONFIG_USB_DWC3_MESON_G12A) += dwc3-meson-g12a.o obj-$(CONFIG_USB_DWC3_OF_SIMPLE) += dwc3-of-simple.o obj-$(CONFIG_USB_DWC3_ST) += dwc3-st.o obj-$(CONFIG_USB_DWC3_QCOM) += dwc3-qcom.o diff --git a/drivers/usb/dwc3/dwc3-meson-g12a.c b/drivers/usb/dwc3/dwc3-meson-g12a.c new file mode 100644 index 000000000000..2aec31a2eacb --- /dev/null +++ b/drivers/usb/dwc3/dwc3-meson-g12a.c @@ -0,0 +1,604 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * USB Glue for Amlogic G12A SoCs + * + * Copyright (c) 2019 BayLibre, SAS + * Author: Neil Armstrong + */ + +/* + * The USB is organized with a glue around the DWC3 Controller IP as : + * - Control registers for each USB2 Ports + * - Control registers for the USB PHY layer + * - SuperSpeed PHY can be enabled only if port is used + * + * TOFIX: + * - Add dynamic OTG switching with ID change interrupt + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* USB2 Ports Control Registers */ + +#define U2P_REG_SIZE 0x20 + +#define U2P_R0 0x0 + #define U2P_R0_HOST_DEVICE BIT(0) + #define U2P_R0_POWER_OK BIT(1) + #define U2P_R0_HAST_MODE BIT(2) + #define U2P_R0_POWER_ON_RESET BIT(3) + #define U2P_R0_ID_PULLUP BIT(4) + #define U2P_R0_DRV_VBUS BIT(5) + +#define U2P_R1 0x4 + #define U2P_R1_PHY_READY BIT(0) + #define U2P_R1_ID_DIG BIT(1) + #define U2P_R1_OTG_SESSION_VALID BIT(2) + #define U2P_R1_VBUS_VALID BIT(3) + +/* USB Glue Control Registers */ + +#define USB_R0 0x80 + #define USB_R0_P30_LANE0_TX2RX_LOOPBACK BIT(17) + #define USB_R0_P30_LANE0_EXT_PCLK_REQ BIT(18) + #define USB_R0_P30_PCS_RX_LOS_MASK_VAL_MASK GENMASK(28, 19) + #define USB_R0_U2D_SS_SCALEDOWN_MODE_MASK GENMASK(30, 29) + #define USB_R0_U2D_ACT BIT(31) + +#define USB_R1 0x84 + #define USB_R1_U3H_BIGENDIAN_GS BIT(0) + #define USB_R1_U3H_PME_ENABLE BIT(1) + #define USB_R1_U3H_HUB_PORT_OVERCURRENT_MASK GENMASK(4, 2) + #define USB_R1_U3H_HUB_PORT_PERM_ATTACH_MASK GENMASK(9, 7) + #define USB_R1_U3H_HOST_U2_PORT_DISABLE_MASK GENMASK(13, 12) + #define USB_R1_U3H_HOST_U3_PORT_DISABLE BIT(16) + #define USB_R1_U3H_HOST_PORT_POWER_CONTROL_PRESENT BIT(17) + #define USB_R1_U3H_HOST_MSI_ENABLE BIT(18) + #define USB_R1_U3H_FLADJ_30MHZ_REG_MASK GENMASK(24, 19) + #define USB_R1_P30_PCS_TX_SWING_FULL_MASK GENMASK(31, 25) + +#define USB_R2 0x88 + #define USB_R2_P30_PCS_TX_DEEMPH_3P5DB_MASK GENMASK(25, 20) + #define USB_R2_P30_PCS_TX_DEEMPH_6DB_MASK GENMASK(31, 26) + +#define USB_R3 0x8c + #define USB_R3_P30_SSC_ENABLE BIT(0) + #define USB_R3_P30_SSC_RANGE_MASK GENMASK(3, 1) + #define USB_R3_P30_SSC_REF_CLK_SEL_MASK GENMASK(12, 4) + #define USB_R3_P30_REF_SSP_EN BIT(13) + +#define USB_R4 0x90 + #define USB_R4_P21_PORT_RESET_0 BIT(0) + #define USB_R4_P21_SLEEP_M0 BIT(1) + #define USB_R4_MEM_PD_MASK GENMASK(3, 2) + #define USB_R4_P21_ONLY BIT(4) + +#define USB_R5 0x94 + #define USB_R5_ID_DIG_SYNC BIT(0) + #define USB_R5_ID_DIG_REG BIT(1) + #define USB_R5_ID_DIG_CFG_MASK GENMASK(3, 2) + #define USB_R5_ID_DIG_EN_0 BIT(4) + #define USB_R5_ID_DIG_EN_1 BIT(5) + #define USB_R5_ID_DIG_CURR BIT(6) + #define USB_R5_ID_DIG_IRQ BIT(7) + #define USB_R5_ID_DIG_TH_MASK GENMASK(15, 8) + #define USB_R5_ID_DIG_CNT_MASK GENMASK(23, 16) + +enum { + USB2_HOST_PHY = 0, + USB2_OTG_PHY, + USB3_HOST_PHY, + PHY_COUNT, +}; + +static const char *phy_names[PHY_COUNT] = { + "usb2-phy0", "usb2-phy1", "usb3-phy0", +}; + +struct dwc3_meson_g12a { + struct device *dev; + struct regmap *regmap; + struct clk *clk; + struct reset_control *reset; + struct phy *phys[PHY_COUNT]; + enum usb_dr_mode otg_mode; + enum phy_mode otg_phy_mode; + unsigned int usb2_ports; + unsigned int usb3_ports; + struct regulator *vbus; + struct usb_role_switch_desc switch_desc; + struct usb_role_switch *role_switch; +}; + +static void dwc3_meson_g12a_usb2_set_mode(struct dwc3_meson_g12a *priv, + int i, enum phy_mode mode) +{ + if (mode == PHY_MODE_USB_HOST) + regmap_update_bits(priv->regmap, U2P_R0 + (U2P_REG_SIZE * i), + U2P_R0_HOST_DEVICE, + U2P_R0_HOST_DEVICE); + else + regmap_update_bits(priv->regmap, U2P_R0 + (U2P_REG_SIZE * i), + U2P_R0_HOST_DEVICE, 0); +} + +static int dwc3_meson_g12a_usb2_init(struct dwc3_meson_g12a *priv) +{ + int i; + + if (priv->otg_mode == USB_DR_MODE_PERIPHERAL) + priv->otg_phy_mode = PHY_MODE_USB_DEVICE; + else + priv->otg_phy_mode = PHY_MODE_USB_HOST; + + for (i = 0 ; i < USB3_HOST_PHY ; ++i) { + if (!priv->phys[i]) + continue; + + regmap_update_bits(priv->regmap, U2P_R0 + (U2P_REG_SIZE * i), + U2P_R0_POWER_ON_RESET, + U2P_R0_POWER_ON_RESET); + + if (i == USB2_OTG_PHY) { + regmap_update_bits(priv->regmap, + U2P_R0 + (U2P_REG_SIZE * i), + U2P_R0_ID_PULLUP | U2P_R0_DRV_VBUS, + U2P_R0_ID_PULLUP | U2P_R0_DRV_VBUS); + + dwc3_meson_g12a_usb2_set_mode(priv, i, + priv->otg_phy_mode); + } else + dwc3_meson_g12a_usb2_set_mode(priv, i, + PHY_MODE_USB_HOST); + + regmap_update_bits(priv->regmap, U2P_R0 + (U2P_REG_SIZE * i), + U2P_R0_POWER_ON_RESET, 0); + } + + return 0; +} + +static void dwc3_meson_g12a_usb3_init(struct dwc3_meson_g12a *priv) +{ + regmap_update_bits(priv->regmap, USB_R3, + USB_R3_P30_SSC_RANGE_MASK | + USB_R3_P30_REF_SSP_EN, + USB_R3_P30_SSC_ENABLE | + FIELD_PREP(USB_R3_P30_SSC_RANGE_MASK, 2) | + USB_R3_P30_REF_SSP_EN); + udelay(2); + + regmap_update_bits(priv->regmap, USB_R2, + USB_R2_P30_PCS_TX_DEEMPH_3P5DB_MASK, + FIELD_PREP(USB_R2_P30_PCS_TX_DEEMPH_3P5DB_MASK, 0x15)); + + regmap_update_bits(priv->regmap, USB_R2, + USB_R2_P30_PCS_TX_DEEMPH_6DB_MASK, + FIELD_PREP(USB_R2_P30_PCS_TX_DEEMPH_6DB_MASK, 0x20)); + + udelay(2); + + regmap_update_bits(priv->regmap, USB_R1, + USB_R1_U3H_HOST_PORT_POWER_CONTROL_PRESENT, + USB_R1_U3H_HOST_PORT_POWER_CONTROL_PRESENT); + + regmap_update_bits(priv->regmap, USB_R1, + USB_R1_P30_PCS_TX_SWING_FULL_MASK, + FIELD_PREP(USB_R1_P30_PCS_TX_SWING_FULL_MASK, 127)); +} + +static void dwc3_meson_g12a_usb_otg_apply_mode(struct dwc3_meson_g12a *priv) +{ + if (priv->otg_phy_mode == PHY_MODE_USB_DEVICE) { + regmap_update_bits(priv->regmap, USB_R0, + USB_R0_U2D_ACT, USB_R0_U2D_ACT); + regmap_update_bits(priv->regmap, USB_R0, + USB_R0_U2D_SS_SCALEDOWN_MODE_MASK, 0); + regmap_update_bits(priv->regmap, USB_R4, + USB_R4_P21_SLEEP_M0, USB_R4_P21_SLEEP_M0); + } else { + regmap_update_bits(priv->regmap, USB_R0, + USB_R0_U2D_ACT, 0); + regmap_update_bits(priv->regmap, USB_R4, + USB_R4_P21_SLEEP_M0, 0); + } +} + +static int dwc3_meson_g12a_usb_init(struct dwc3_meson_g12a *priv) +{ + int ret; + + ret = dwc3_meson_g12a_usb2_init(priv); + if (ret) + return ret; + + regmap_update_bits(priv->regmap, USB_R1, + USB_R1_U3H_FLADJ_30MHZ_REG_MASK, + FIELD_PREP(USB_R1_U3H_FLADJ_30MHZ_REG_MASK, 0x20)); + + regmap_update_bits(priv->regmap, USB_R5, + USB_R5_ID_DIG_EN_0, + USB_R5_ID_DIG_EN_0); + regmap_update_bits(priv->regmap, USB_R5, + USB_R5_ID_DIG_EN_1, + USB_R5_ID_DIG_EN_1); + regmap_update_bits(priv->regmap, USB_R5, + USB_R5_ID_DIG_TH_MASK, + FIELD_PREP(USB_R5_ID_DIG_TH_MASK, 0xff)); + + /* If we have an actual SuperSpeed port, initialize it */ + if (priv->usb3_ports) + dwc3_meson_g12a_usb3_init(priv); + + dwc3_meson_g12a_usb_otg_apply_mode(priv); + + return 0; +} + +static const struct regmap_config phy_meson_g12a_usb3_regmap_conf = { + .reg_bits = 8, + .val_bits = 32, + .reg_stride = 4, + .max_register = USB_R5, +}; + +static int dwc3_meson_g12a_get_phys(struct dwc3_meson_g12a *priv) +{ + int i; + + for (i = 0 ; i < PHY_COUNT ; ++i) { + priv->phys[i] = devm_phy_optional_get(priv->dev, phy_names[i]); + if (!priv->phys[i]) + continue; + + if (IS_ERR(priv->phys[i])) + return PTR_ERR(priv->phys[i]); + + if (i == USB3_HOST_PHY) + priv->usb3_ports++; + else + priv->usb2_ports++; + } + + dev_info(priv->dev, "USB2 ports: %d\n", priv->usb2_ports); + dev_info(priv->dev, "USB3 ports: %d\n", priv->usb3_ports); + + return 0; +} + +static enum phy_mode dwc3_meson_g12a_get_id(struct dwc3_meson_g12a *priv) +{ + u32 reg; + + regmap_read(priv->regmap, USB_R5, ®); + + if (reg & (USB_R5_ID_DIG_SYNC | USB_R5_ID_DIG_REG)) + return PHY_MODE_USB_DEVICE; + + return PHY_MODE_USB_HOST; +} + +static int dwc3_meson_g12a_otg_mode_set(struct dwc3_meson_g12a *priv, + enum phy_mode mode) +{ + int ret; + + if (!priv->phys[USB2_OTG_PHY]) + return -EINVAL; + + if (mode == PHY_MODE_USB_HOST) + dev_info(priv->dev, "switching to Host Mode\n"); + else + dev_info(priv->dev, "switching to Device Mode\n"); + + if (priv->vbus) { + if (mode == PHY_MODE_USB_DEVICE) + ret = regulator_disable(priv->vbus); + else + ret = regulator_enable(priv->vbus); + if (ret) + return ret; + } + + priv->otg_phy_mode = mode; + + dwc3_meson_g12a_usb2_set_mode(priv, USB2_OTG_PHY, mode); + + dwc3_meson_g12a_usb_otg_apply_mode(priv); + + return 0; +} + +static int dwc3_meson_g12a_role_set(struct device *dev, enum usb_role role) +{ + struct dwc3_meson_g12a *priv = dev_get_drvdata(dev); + enum phy_mode mode; + + if (role == USB_ROLE_NONE) + return 0; + + mode = (role == USB_ROLE_HOST) ? PHY_MODE_USB_HOST + : PHY_MODE_USB_DEVICE; + + if (mode == priv->otg_phy_mode) + return 0; + + return dwc3_meson_g12a_otg_mode_set(priv, mode); +} + +static enum usb_role dwc3_meson_g12a_role_get(struct device *dev) +{ + struct dwc3_meson_g12a *priv = dev_get_drvdata(dev); + + return priv->otg_phy_mode == PHY_MODE_USB_HOST ? + USB_ROLE_HOST : USB_ROLE_DEVICE; +} + +static struct device *dwc3_meson_g12_find_child(struct device *dev, + const char *compatible) +{ + struct platform_device *pdev; + struct device_node *np; + + np = of_get_compatible_child(dev->of_node, compatible); + if (!np) + return NULL; + + pdev = of_find_device_by_node(np); + of_node_put(np); + if (!pdev) + return NULL; + + return &pdev->dev; +} + +static int dwc3_meson_g12a_probe(struct platform_device *pdev) +{ + struct dwc3_meson_g12a *priv; + struct device *dev = &pdev->dev; + struct device_node *np = dev->of_node; + void __iomem *base; + struct resource *res; + enum phy_mode otg_id; + int ret, i; + + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + base = devm_ioremap_resource(dev, res); + if (IS_ERR(base)) + return PTR_ERR(base); + + priv->regmap = devm_regmap_init_mmio(dev, base, + &phy_meson_g12a_usb3_regmap_conf); + if (IS_ERR(priv->regmap)) + return PTR_ERR(priv->regmap); + + priv->vbus = devm_regulator_get_optional(dev, "vbus"); + if (IS_ERR(priv->vbus)) { + if (PTR_ERR(priv->vbus) == -EPROBE_DEFER) + return PTR_ERR(priv->vbus); + priv->vbus = NULL; + } + + priv->clk = devm_clk_get(dev, NULL); + if (IS_ERR(priv->clk)) + return PTR_ERR(priv->clk); + + ret = clk_prepare_enable(priv->clk); + if (ret) + return ret; + + devm_add_action_or_reset(dev, + (void(*)(void *))clk_disable_unprepare, + priv->clk); + + platform_set_drvdata(pdev, priv); + priv->dev = dev; + + priv->reset = devm_reset_control_get(dev, NULL); + if (IS_ERR(priv->reset)) { + ret = PTR_ERR(priv->reset); + dev_err(dev, "failed to get device reset, err=%d\n", ret); + return ret; + } + + ret = reset_control_reset(priv->reset); + if (ret) + return ret; + + ret = dwc3_meson_g12a_get_phys(priv); + if (ret) + return ret; + + if (priv->vbus) { + ret = regulator_enable(priv->vbus); + if (ret) + return ret; + } + + /* Get dr_mode */ + priv->otg_mode = usb_get_dr_mode(dev); + + dwc3_meson_g12a_usb_init(priv); + + /* Init PHYs */ + for (i = 0 ; i < PHY_COUNT ; ++i) { + ret = phy_init(priv->phys[i]); + if (ret) + return ret; + } + + /* Set PHY Power */ + for (i = 0 ; i < PHY_COUNT ; ++i) { + ret = phy_power_on(priv->phys[i]); + if (ret) + goto err_phys_exit; + } + + ret = of_platform_populate(np, NULL, NULL, dev); + if (ret) { + clk_disable_unprepare(priv->clk); + goto err_phys_power; + } + + /* Setup OTG mode corresponding to the ID pin */ + if (priv->otg_mode == USB_DR_MODE_OTG) { + /* TOFIX Handle ID mode toggling via IRQ */ + otg_id = dwc3_meson_g12a_get_id(priv); + if (otg_id != priv->otg_phy_mode) { + if (dwc3_meson_g12a_otg_mode_set(priv, otg_id)) + dev_warn(dev, "Failed to switch OTG mode\n"); + } + } + + /* Setup role switcher */ + priv->switch_desc.usb2_port = dwc3_meson_g12_find_child(dev, + "snps,dwc3"); + priv->switch_desc.udc = dwc3_meson_g12_find_child(dev, "snps,dwc2"); + priv->switch_desc.allow_userspace_control = true; + priv->switch_desc.set = dwc3_meson_g12a_role_set; + priv->switch_desc.get = dwc3_meson_g12a_role_get; + + priv->role_switch = usb_role_switch_register(dev, &priv->switch_desc); + if (IS_ERR(priv->role_switch)) + dev_warn(dev, "Unable to register Role Switch\n"); + + pm_runtime_set_active(dev); + pm_runtime_enable(dev); + pm_runtime_get_sync(dev); + + return 0; + +err_phys_power: + for (i = 0 ; i < PHY_COUNT ; ++i) + phy_power_off(priv->phys[i]); + +err_phys_exit: + for (i = 0 ; i < PHY_COUNT ; ++i) + phy_exit(priv->phys[i]); + + return ret; +} + +static int dwc3_meson_g12a_remove(struct platform_device *pdev) +{ + struct dwc3_meson_g12a *priv = platform_get_drvdata(pdev); + struct device *dev = &pdev->dev; + int i; + + usb_role_switch_unregister(priv->role_switch); + + of_platform_depopulate(dev); + + for (i = 0 ; i < PHY_COUNT ; ++i) { + phy_power_off(priv->phys[i]); + phy_exit(priv->phys[i]); + } + + pm_runtime_disable(dev); + pm_runtime_put_noidle(dev); + pm_runtime_set_suspended(dev); + + return 0; +} + +static int __maybe_unused dwc3_meson_g12a_runtime_suspend(struct device *dev) +{ + struct dwc3_meson_g12a *priv = dev_get_drvdata(dev); + + clk_disable(priv->clk); + + return 0; +} + +static int __maybe_unused dwc3_meson_g12a_runtime_resume(struct device *dev) +{ + struct dwc3_meson_g12a *priv = dev_get_drvdata(dev); + + return clk_enable(priv->clk); +} + +static int __maybe_unused dwc3_meson_g12a_suspend(struct device *dev) +{ + struct dwc3_meson_g12a *priv = dev_get_drvdata(dev); + int i; + + for (i = 0 ; i < PHY_COUNT ; ++i) { + phy_power_off(priv->phys[i]); + phy_exit(priv->phys[i]); + } + + reset_control_assert(priv->reset); + + return 0; +} + +static int __maybe_unused dwc3_meson_g12a_resume(struct device *dev) +{ + struct dwc3_meson_g12a *priv = dev_get_drvdata(dev); + int i, ret; + + reset_control_deassert(priv->reset); + + dwc3_meson_g12a_usb_init(priv); + + /* Init PHYs */ + for (i = 0 ; i < PHY_COUNT ; ++i) { + ret = phy_init(priv->phys[i]); + if (ret) + return ret; + } + + /* Set PHY Power */ + for (i = 0 ; i < PHY_COUNT ; ++i) { + ret = phy_power_on(priv->phys[i]); + if (ret) + return ret; + } + + return 0; +} + +static const struct dev_pm_ops dwc3_meson_g12a_dev_pm_ops = { + SET_SYSTEM_SLEEP_PM_OPS(dwc3_meson_g12a_suspend, dwc3_meson_g12a_resume) + SET_RUNTIME_PM_OPS(dwc3_meson_g12a_runtime_suspend, + dwc3_meson_g12a_runtime_resume, NULL) +}; + +static const struct of_device_id dwc3_meson_g12a_match[] = { + { .compatible = "amlogic,meson-g12a-usb-ctrl" }, + { /* Sentinel */ } +}; +MODULE_DEVICE_TABLE(of, dwc3_meson_g12a_match); + +static struct platform_driver dwc3_meson_g12a_driver = { + .probe = dwc3_meson_g12a_probe, + .remove = dwc3_meson_g12a_remove, + .driver = { + .name = "dwc3-meson-g12a", + .of_match_table = dwc3_meson_g12a_match, + .pm = &dwc3_meson_g12a_dev_pm_ops, + }, +}; + +module_platform_driver(dwc3_meson_g12a_driver); +MODULE_LICENSE("GPL v2"); +MODULE_DESCRIPTION("Amlogic Meson G12A USB Glue Layer"); +MODULE_AUTHOR("Neil Armstrong ");