From patchwork Tue Apr 23 09:02:29 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jerome Brunet X-Patchwork-Id: 10912359 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id B9A5F112C for ; Tue, 23 Apr 2019 09:02:51 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id AA83E28843 for ; Tue, 23 Apr 2019 09:02:51 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 9ED6328856; Tue, 23 Apr 2019 09:02:51 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 3AD5928843 for ; Tue, 23 Apr 2019 09:02:51 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=YM6DMOCAgbzRX1f2Cnd6sPoiz6OsfIuJjGVlRY0hxSM=; b=V/fPA/gjMz6dfi +LOVthGgC1YbT41gIanPa+XXUISYRf0iEvVBq5FUyyAkag5vLB441/QLG3Vk9YJMR8dkC1cBpg/8G bIdUuiZhTTv979evf+k2FXLD36qxSHfjYpf3KxoM55td4Qwg+qsdOH3qsR8Ksvw7G+k3InntepQZ7 045YPa02DSkA7M8gAyV95vnwH2h7VNRxcbo85/EQFOjLbodujsfXAMZwpeeVsJV0caekd/DQuTevD 8e4VEe+jDS+qOxro6MjwJLK9FM15wGhww3Ub8UcOiYzbEG9BsjfjiTN5A5c5UTESqcXtoLHN5jaWb JoPrXthdiH3zYXX9QzWw==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1hIrKE-0005e0-LZ; Tue, 23 Apr 2019 09:02:50 +0000 Received: from mail-wr1-x441.google.com ([2a00:1450:4864:20::441]) by bombadil.infradead.org with esmtps (Exim 4.90_1 #2 (Red Hat Linux)) id 1hIrKB-0005bo-CA for linux-amlogic@lists.infradead.org; Tue, 23 Apr 2019 09:02:48 +0000 Received: by mail-wr1-x441.google.com with SMTP id t17so7424018wrr.4 for ; Tue, 23 Apr 2019 02:02:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=VS6sWtIBcpW++wv0mYIjcVLqIR7LghrNYUg8/Ta7WWE=; b=xbMqCO6zj/632iEPHiWSPhZGMBKBsDiZrQeirlU04yPkWiApOm24k7zLVyG5N1k4ZS fRf30jGYSKoSdVluBAAxFRnrxdV1uMkUIBU9ZIlhwO2NPoKtjJOBE3/L2tp34JpdjWTu uCQaT5k/IM10+QaOAd/NEVTX+lTW9dI8CMNXUPv6AecORRQres0ZqV6wz7G4tdiU8N8X M+FxI87l3FQXlJdI8UvEkd3dSwBOCoPsKBLbbqZmobuUT8Qqn2SHZEjYsV9HXy49HzGq 1i4rmkfEokMShkmMUvIf4jkscOg9xyIImE3i+kurOVotZf3Qwu5sPLb907IzKSLd5JDt RBMQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=VS6sWtIBcpW++wv0mYIjcVLqIR7LghrNYUg8/Ta7WWE=; b=ETLW3kCWHd3gwsq26YlXXg0NxTrwC5KsxpQt3Q2/S+X67pty3MAg2HYuy/lyYz6Grr eab0PtAp1He6I2xa2Q0yysN0rfLIHhd9vWOAjlrtfrmeSE0KxxKbTEo6UH/EaqNZW7zb 6kkDPYIANClrmNXqoekxVbdZ0FWh0jx6VRYPufNlRZa8zC9L337NM0Swtw8cRhgZ4Umm bcf83GBb5fs5WHnKVPKmVy+uu2H+0bX6Juw8Xdhzkn2Hh5OVDgaA90cpEI5Uw4Uo5f/U lPkApiXwa4Oki4nAivmR6eQGVw5Bl1VtlBRvbiPXEDJKDh2xxFz+eIWWOerTx9M2X9AW /Q7w== X-Gm-Message-State: APjAAAXsdjNE6BkCEBjkP9S8yjJhk3jmhGfZ1XPpUwiVC6s9B/mOlEBP nS73biCKMC789VU7hafdz8WKcw== X-Google-Smtp-Source: APXvYqx291aocUxzzWbLRxtrvn///4nfCCUgX6RRRyBi0FRPwZ0/0Vn+i4JlIb15XtkLkI2qr76qUw== X-Received: by 2002:a5d:6604:: with SMTP id n4mr13301965wru.42.1556010165874; Tue, 23 Apr 2019 02:02:45 -0700 (PDT) Received: from boomer.local (lmontsouris-657-1-212-31.w90-63.abo.wanadoo.fr. [90.63.244.31]) by smtp.googlemail.com with ESMTPSA id z23sm12361894wma.0.2019.04.23.02.02.44 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 23 Apr 2019 02:02:45 -0700 (PDT) From: Jerome Brunet To: Ulf Hansson , Kevin Hilman Subject: [PATCH v2 1/7] mmc: meson-gx: remove open coded read with timeout Date: Tue, 23 Apr 2019 11:02:29 +0200 Message-Id: <20190423090235.17244-2-jbrunet@baylibre.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190423090235.17244-1-jbrunet@baylibre.com> References: <20190423090235.17244-1-jbrunet@baylibre.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190423_020247_410542_5F6E6203 X-CRM114-Status: GOOD ( 12.82 ) X-BeenThere: linux-amlogic@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Martin Blumenstingl , linux-amlogic@lists.infradead.org, linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, Jerome Brunet Sender: "linux-amlogic" Errors-To: linux-amlogic-bounces+patchwork-linux-amlogic=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP There is already a function available to poll a register until a condition is met. Let's use it instead of open coding it. Reviewed-by: Martin Blumenstingl Signed-off-by: Jerome Brunet --- drivers/mmc/host/meson-gx-mmc.c | 18 ++++-------------- 1 file changed, 4 insertions(+), 14 deletions(-) diff --git a/drivers/mmc/host/meson-gx-mmc.c b/drivers/mmc/host/meson-gx-mmc.c index 2eba507790e4..2deeacc051b1 100644 --- a/drivers/mmc/host/meson-gx-mmc.c +++ b/drivers/mmc/host/meson-gx-mmc.c @@ -23,6 +23,7 @@ #include #include #include +#include #include #include #include @@ -1100,7 +1101,6 @@ static irqreturn_t meson_mmc_irq(int irq, void *dev_id) static int meson_mmc_wait_desc_stop(struct meson_host *host) { - int loop; u32 status; /* @@ -1110,20 +1110,10 @@ static int meson_mmc_wait_desc_stop(struct meson_host *host) * If we don't confirm the descriptor is stopped, it might raise new * IRQs after we have called mmc_request_done() which is bad. */ - for (loop = 50; loop; loop--) { - status = readl(host->regs + SD_EMMC_STATUS); - if (status & (STATUS_BUSY | STATUS_DESC_BUSY)) - udelay(100); - else - break; - } - if (status & (STATUS_BUSY | STATUS_DESC_BUSY)) { - dev_err(host->dev, "Timed out waiting for host to stop\n"); - return -ETIMEDOUT; - } - - return 0; + return readl_poll_timeout(host->regs + SD_EMMC_STATUS, status, + !(status & (STATUS_BUSY | STATUS_DESC_BUSY)), + 100, 5000); } static irqreturn_t meson_mmc_irq_thread(int irq, void *dev_id) From patchwork Tue Apr 23 09:02:30 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jerome Brunet X-Patchwork-Id: 10912363 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 930F61515 for ; Tue, 23 Apr 2019 09:02:54 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 855F92882C for ; Tue, 23 Apr 2019 09:02:54 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 796682884B; Tue, 23 Apr 2019 09:02:54 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 2C89F28832 for ; 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[90.63.244.31]) by smtp.googlemail.com with ESMTPSA id z23sm12361894wma.0.2019.04.23.02.02.45 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 23 Apr 2019 02:02:46 -0700 (PDT) From: Jerome Brunet To: Ulf Hansson , Kevin Hilman Subject: [PATCH v2 2/7] mmc: meson-gx: ack only raised irq Date: Tue, 23 Apr 2019 11:02:30 +0200 Message-Id: <20190423090235.17244-3-jbrunet@baylibre.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190423090235.17244-1-jbrunet@baylibre.com> References: <20190423090235.17244-1-jbrunet@baylibre.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190423_020248_515312_95B1BECD X-CRM114-Status: GOOD ( 12.26 ) X-BeenThere: linux-amlogic@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-amlogic@lists.infradead.org, linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, Jerome Brunet Sender: "linux-amlogic" Errors-To: linux-amlogic-bounces+patchwork-linux-amlogic=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP This is merely a clean up. It makes sense to only ack raised irqs instead of acking everything all the time. Signed-off-by: Jerome Brunet Acked-by: Martin Blumenstingl --- drivers/mmc/host/meson-gx-mmc.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/mmc/host/meson-gx-mmc.c b/drivers/mmc/host/meson-gx-mmc.c index 2deeacc051b1..8b690ecde4c5 100644 --- a/drivers/mmc/host/meson-gx-mmc.c +++ b/drivers/mmc/host/meson-gx-mmc.c @@ -1082,9 +1082,6 @@ static irqreturn_t meson_mmc_irq(int irq, void *dev_id) } out: - /* ack all enabled interrupts */ - writel(irq_en, host->regs + SD_EMMC_STATUS); - if (cmd->error) { /* Stop desc in case of errors */ u32 start = readl(host->regs + SD_EMMC_START); @@ -1096,6 +1093,9 @@ static irqreturn_t meson_mmc_irq(int irq, void *dev_id) if (ret == IRQ_HANDLED) meson_mmc_request_done(host->mmc, cmd->mrq); + /* ack all raised interrupts */ + writel(status, host->regs + SD_EMMC_STATUS); + return ret; } From patchwork Tue Apr 23 09:02:31 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jerome Brunet X-Patchwork-Id: 10912367 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 0FE821515 for ; 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[90.63.244.31]) by smtp.googlemail.com with ESMTPSA id z23sm12361894wma.0.2019.04.23.02.02.47 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 23 Apr 2019 02:02:47 -0700 (PDT) From: Jerome Brunet To: Ulf Hansson , Kevin Hilman Subject: [PATCH v2 3/7] mmc: meson-gx: correct irq flag Date: Tue, 23 Apr 2019 11:02:31 +0200 Message-Id: <20190423090235.17244-4-jbrunet@baylibre.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190423090235.17244-1-jbrunet@baylibre.com> References: <20190423090235.17244-1-jbrunet@baylibre.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190423_020249_678532_57B6AAE9 X-CRM114-Status: GOOD ( 12.45 ) X-BeenThere: linux-amlogic@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-amlogic@lists.infradead.org, linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, Jerome Brunet Sender: "linux-amlogic" Errors-To: linux-amlogic-bounces+patchwork-linux-amlogic=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP There is no reason for another device to request the MMC irq. It should only be used the MMC device, so remove IRQ_SHARED and replace by IRQ_ONESHOT as we don't the irq to fire again until the irq thread is done Signed-off-by: Jerome Brunet Reviewed-by: Martin Blumenstingl --- drivers/mmc/host/meson-gx-mmc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/mmc/host/meson-gx-mmc.c b/drivers/mmc/host/meson-gx-mmc.c index 8b690ecde4c5..3df50b53f834 100644 --- a/drivers/mmc/host/meson-gx-mmc.c +++ b/drivers/mmc/host/meson-gx-mmc.c @@ -1328,7 +1328,7 @@ static int meson_mmc_probe(struct platform_device *pdev) host->regs + SD_EMMC_IRQ_EN); ret = request_threaded_irq(host->irq, meson_mmc_irq, - meson_mmc_irq_thread, IRQF_SHARED, + meson_mmc_irq_thread, IRQF_ONESHOT, dev_name(&pdev->dev), host); if (ret) goto err_init_clk; From patchwork Tue Apr 23 09:02:32 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jerome Brunet X-Patchwork-Id: 10912369 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id C71F91515 for ; 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[90.63.244.31]) by smtp.googlemail.com with ESMTPSA id z23sm12361894wma.0.2019.04.23.02.02.48 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 23 Apr 2019 02:02:48 -0700 (PDT) From: Jerome Brunet To: Ulf Hansson , Kevin Hilman Subject: [PATCH v2 4/7] mmc: meson-gx: disable HS400 Date: Tue, 23 Apr 2019 11:02:32 +0200 Message-Id: <20190423090235.17244-5-jbrunet@baylibre.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190423090235.17244-1-jbrunet@baylibre.com> References: <20190423090235.17244-1-jbrunet@baylibre.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190423_020252_642309_4A042104 X-CRM114-Status: GOOD ( 12.81 ) X-BeenThere: linux-amlogic@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-amlogic@lists.infradead.org, linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, Jerome Brunet Sender: "linux-amlogic" Errors-To: linux-amlogic-bounces+patchwork-linux-amlogic=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP At the moment, all our attempts to enable HS400 on Amlogic chipsets have been unsuccessful or unreliable. Until we can figure out how to enable this mode safely and reliably, let's force it off. Signed-off-by: Jerome Brunet Acked-by: Martin Blumenstingl Acked-by: Martin Blumenstingl --- drivers/mmc/host/meson-gx-mmc.c | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/drivers/mmc/host/meson-gx-mmc.c b/drivers/mmc/host/meson-gx-mmc.c index 3df50b53f834..118f09da8dfb 100644 --- a/drivers/mmc/host/meson-gx-mmc.c +++ b/drivers/mmc/host/meson-gx-mmc.c @@ -823,10 +823,6 @@ static void meson_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) if (meson_mmc_timing_is_ddr(ios)) val |= CFG_DDR; - val &= ~CFG_CHK_DS; - if (ios->timing == MMC_TIMING_MMC_HS400) - val |= CFG_CHK_DS; - err = meson_mmc_clk_set(host, ios); if (err) dev_err(host->dev, "Failed to set clock: %d\n,", err); @@ -1339,6 +1335,13 @@ static int meson_mmc_probe(struct platform_device *pdev) mmc->max_segs = SD_EMMC_DESC_BUF_LEN / sizeof(struct sd_emmc_desc); mmc->max_seg_size = mmc->max_req_size; + /* + * At the moment, we don't know how to reliably enable HS400. + * From the different datasheets, it is not even clear if this mode + * is officially supported by any of the SoCs + */ + mmc->caps2 &= ~MMC_CAP2_HS400; + /* data bounce buffer */ host->bounce_buf_size = mmc->max_req_size; host->bounce_buf = From patchwork Tue Apr 23 09:02:33 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jerome Brunet X-Patchwork-Id: 10912373 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id E3AD7112C for ; Tue, 23 Apr 2019 09:03:04 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id D5FE2287E2 for ; Tue, 23 Apr 2019 09:03:04 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id D422F28862; Tue, 23 Apr 2019 09:03:04 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 50D862882C for ; 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[90.63.244.31]) by smtp.googlemail.com with ESMTPSA id z23sm12361894wma.0.2019.04.23.02.02.50 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 23 Apr 2019 02:02:50 -0700 (PDT) From: Jerome Brunet To: Ulf Hansson , Kevin Hilman Subject: [PATCH v2 5/7] mmc: meson-gx: avoid clock glitch when switching to DDR modes Date: Tue, 23 Apr 2019 11:02:33 +0200 Message-Id: <20190423090235.17244-6-jbrunet@baylibre.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190423090235.17244-1-jbrunet@baylibre.com> References: <20190423090235.17244-1-jbrunet@baylibre.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190423_020253_806603_35DA27AF X-CRM114-Status: GOOD ( 16.87 ) X-BeenThere: linux-amlogic@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-amlogic@lists.infradead.org, linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, Jerome Brunet Sender: "linux-amlogic" Errors-To: linux-amlogic-bounces+patchwork-linux-amlogic=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Activating DDR in the Amlogic mmc controller, among other things, will divide the output clock by 2. So by activating it with clock on, we are creating a glitch on the output. Instead, let's deal with DDR when the clock output is off, when setting the clock. Signed-off-by: Jerome Brunet Tested-by: Martin Blumenstingl --- drivers/mmc/host/meson-gx-mmc.c | 73 +++++++++++++++++++-------------- 1 file changed, 43 insertions(+), 30 deletions(-) diff --git a/drivers/mmc/host/meson-gx-mmc.c b/drivers/mmc/host/meson-gx-mmc.c index 118f09da8dfb..0454021c9ff5 100644 --- a/drivers/mmc/host/meson-gx-mmc.c +++ b/drivers/mmc/host/meson-gx-mmc.c @@ -169,6 +169,7 @@ struct meson_host { struct clk *rx_clk; struct clk *tx_clk; unsigned long req_rate; + bool ddr; struct pinctrl *pinctrl; struct pinctrl_state *pins_default; @@ -384,16 +385,6 @@ static void meson_mmc_post_req(struct mmc_host *mmc, struct mmc_request *mrq, mmc_get_dma_dir(data)); } -static bool meson_mmc_timing_is_ddr(struct mmc_ios *ios) -{ - if (ios->timing == MMC_TIMING_MMC_DDR52 || - ios->timing == MMC_TIMING_UHS_DDR50 || - ios->timing == MMC_TIMING_MMC_HS400) - return true; - - return false; -} - /* * Gating the clock on this controller is tricky. It seems the mmc clock * is also used by the controller. It may crash during some operation if the @@ -430,36 +421,41 @@ static void meson_mmc_clk_ungate(struct meson_host *host) writel(cfg, host->regs + SD_EMMC_CFG); } -static int meson_mmc_clk_set(struct meson_host *host, struct mmc_ios *ios) +static int meson_mmc_clk_set(struct meson_host *host, unsigned long rate, + bool ddr) { struct mmc_host *mmc = host->mmc; - unsigned long rate = ios->clock; int ret; u32 cfg; - /* DDR modes require higher module clock */ - if (meson_mmc_timing_is_ddr(ios)) - rate <<= 1; - /* Same request - bail-out */ - if (host->req_rate == rate) + if (host->ddr == ddr && host->req_rate == rate) return 0; /* stop clock */ meson_mmc_clk_gate(host); host->req_rate = 0; + mmc->actual_clock = 0; - if (!rate) { - mmc->actual_clock = 0; - /* return with clock being stopped */ + /* return with clock being stopped */ + if (!rate) return 0; - } /* Stop the clock during rate change to avoid glitches */ cfg = readl(host->regs + SD_EMMC_CFG); cfg |= CFG_STOP_CLOCK; writel(cfg, host->regs + SD_EMMC_CFG); + if (ddr) { + /* DDR modes require higher module clock */ + rate <<= 1; + cfg |= CFG_DDR; + } else { + cfg &= ~CFG_DDR; + } + writel(cfg, host->regs + SD_EMMC_CFG); + host->ddr = ddr; + ret = clk_set_rate(host->mmc_clk, rate); if (ret) { dev_err(host->dev, "Unable to set cfg_div_clk to %lu. ret=%d\n", @@ -471,12 +467,14 @@ static int meson_mmc_clk_set(struct meson_host *host, struct mmc_ios *ios) mmc->actual_clock = clk_get_rate(host->mmc_clk); /* We should report the real output frequency of the controller */ - if (meson_mmc_timing_is_ddr(ios)) + if (ddr) { + host->req_rate >>= 1; mmc->actual_clock >>= 1; + } dev_dbg(host->dev, "clk rate: %u Hz\n", mmc->actual_clock); - if (ios->clock != mmc->actual_clock) - dev_dbg(host->dev, "requested rate was %u\n", ios->clock); + if (rate != mmc->actual_clock) + dev_dbg(host->dev, "requested rate was %lu\n", rate); /* (re)start clock */ meson_mmc_clk_ungate(host); @@ -750,6 +748,25 @@ static int meson_mmc_execute_tuning(struct mmc_host *mmc, u32 opcode) return meson_mmc_clk_phase_tuning(mmc, opcode, host->rx_clk); } +static int meson_mmc_prepare_ios_clock(struct meson_host *host, + struct mmc_ios *ios) +{ + bool ddr; + + switch (ios->timing) { + case MMC_TIMING_MMC_DDR52: + case MMC_TIMING_UHS_DDR50: + ddr = true; + break; + + default: + ddr = false; + break; + } + + return meson_mmc_clk_set(host, ios->clock, ddr); +} + static void meson_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) { struct meson_host *host = mmc_priv(mmc); @@ -818,16 +835,12 @@ static void meson_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) val = readl(host->regs + SD_EMMC_CFG); val &= ~CFG_BUS_WIDTH_MASK; val |= FIELD_PREP(CFG_BUS_WIDTH_MASK, bus_width); + writel(val, host->regs + SD_EMMC_CFG); - val &= ~CFG_DDR; - if (meson_mmc_timing_is_ddr(ios)) - val |= CFG_DDR; - - err = meson_mmc_clk_set(host, ios); + err = meson_mmc_prepare_ios_clock(host, ios); if (err) dev_err(host->dev, "Failed to set clock: %d\n,", err); - writel(val, host->regs + SD_EMMC_CFG); dev_dbg(host->dev, "SD_EMMC_CFG: 0x%08x\n", val); } From patchwork Tue Apr 23 09:02:34 2019 Content-Type: text/plain; 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[90.63.244.31]) by smtp.googlemail.com with ESMTPSA id z23sm12361894wma.0.2019.04.23.02.02.52 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 23 Apr 2019 02:02:52 -0700 (PDT) From: Jerome Brunet To: Ulf Hansson , Kevin Hilman Subject: [PATCH v2 6/7] mmc: meson-gx: remove Rx phase tuning Date: Tue, 23 Apr 2019 11:02:34 +0200 Message-Id: <20190423090235.17244-7-jbrunet@baylibre.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190423090235.17244-1-jbrunet@baylibre.com> References: <20190423090235.17244-1-jbrunet@baylibre.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190423_020255_966955_E6873CBC X-CRM114-Status: GOOD ( 21.36 ) X-BeenThere: linux-amlogic@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-amlogic@lists.infradead.org, linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, Jerome Brunet Sender: "linux-amlogic" Errors-To: linux-amlogic-bounces+patchwork-linux-amlogic=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP This remove all the code related to phase settings. Using the Rx phase for tuning has not been reliable. We had several issues over the past months, on both v2 and v3 mmc chips After discussing the issue matter with Amlogic, They suggested to set a phase shift of 180 between Core and Tx and use signal resampling for the tuning. Since we won't be playing with the phase anymore, let's remove all the clock code related to it and set the appropriate value on init. Signed-off-by: Jerome Brunet Tested-by: Martin Blumenstingl --- drivers/mmc/host/meson-gx-mmc.c | 290 ++------------------------------ 1 file changed, 13 insertions(+), 277 deletions(-) diff --git a/drivers/mmc/host/meson-gx-mmc.c b/drivers/mmc/host/meson-gx-mmc.c index 0454021c9ff5..acdc5520d02c 100644 --- a/drivers/mmc/host/meson-gx-mmc.c +++ b/drivers/mmc/host/meson-gx-mmc.c @@ -49,6 +49,8 @@ #define CLK_CORE_PHASE_MASK GENMASK(9, 8) #define CLK_TX_PHASE_MASK GENMASK(11, 10) #define CLK_RX_PHASE_MASK GENMASK(13, 12) +#define CLK_PHASE_0 0 +#define CLK_PHASE_180 2 #define CLK_V2_TX_DELAY_MASK GENMASK(19, 16) #define CLK_V2_RX_DELAY_MASK GENMASK(23, 20) #define CLK_V2_ALWAYS_ON BIT(24) @@ -57,10 +59,6 @@ #define CLK_V3_RX_DELAY_MASK GENMASK(27, 22) #define CLK_V3_ALWAYS_ON BIT(28) -#define CLK_DELAY_STEP_PS 200 -#define CLK_PHASE_STEP 30 -#define CLK_PHASE_POINT_NUM (360 / CLK_PHASE_STEP) - #define CLK_TX_DELAY_MASK(h) (h->data->tx_delay_mask) #define CLK_RX_DELAY_MASK(h) (h->data->rx_delay_mask) #define CLK_ALWAYS_ON(h) (h->data->always_on) @@ -165,9 +163,8 @@ struct meson_host { void __iomem *regs; struct clk *core_clk; + struct clk *mux_clk; struct clk *mmc_clk; - struct clk *rx_clk; - struct clk *tx_clk; unsigned long req_rate; bool ddr; @@ -209,90 +206,6 @@ struct meson_host { #define CMD_RESP_MASK GENMASK(31, 1) #define CMD_RESP_SRAM BIT(0) -struct meson_mmc_phase { - struct clk_hw hw; - void __iomem *reg; - unsigned long phase_mask; - unsigned long delay_mask; - unsigned int delay_step_ps; -}; - -#define to_meson_mmc_phase(_hw) container_of(_hw, struct meson_mmc_phase, hw) - -static int meson_mmc_clk_get_phase(struct clk_hw *hw) -{ - struct meson_mmc_phase *mmc = to_meson_mmc_phase(hw); - unsigned int phase_num = 1 << hweight_long(mmc->phase_mask); - unsigned long period_ps, p, d; - int degrees; - u32 val; - - val = readl(mmc->reg); - p = (val & mmc->phase_mask) >> __ffs(mmc->phase_mask); - degrees = p * 360 / phase_num; - - if (mmc->delay_mask) { - period_ps = DIV_ROUND_UP((unsigned long)NSEC_PER_SEC * 1000, - clk_get_rate(hw->clk)); - d = (val & mmc->delay_mask) >> __ffs(mmc->delay_mask); - degrees += d * mmc->delay_step_ps * 360 / period_ps; - degrees %= 360; - } - - return degrees; -} - -static void meson_mmc_apply_phase_delay(struct meson_mmc_phase *mmc, - unsigned int phase, - unsigned int delay) -{ - u32 val; - - val = readl(mmc->reg); - val &= ~mmc->phase_mask; - val |= phase << __ffs(mmc->phase_mask); - - if (mmc->delay_mask) { - val &= ~mmc->delay_mask; - val |= delay << __ffs(mmc->delay_mask); - } - - writel(val, mmc->reg); -} - -static int meson_mmc_clk_set_phase(struct clk_hw *hw, int degrees) -{ - struct meson_mmc_phase *mmc = to_meson_mmc_phase(hw); - unsigned int phase_num = 1 << hweight_long(mmc->phase_mask); - unsigned long period_ps, d = 0, r; - uint64_t p; - - p = degrees % 360; - - if (!mmc->delay_mask) { - p = DIV_ROUND_CLOSEST_ULL(p, 360 / phase_num); - } else { - period_ps = DIV_ROUND_UP((unsigned long)NSEC_PER_SEC * 1000, - clk_get_rate(hw->clk)); - - /* First compute the phase index (p), the remainder (r) is the - * part we'll try to acheive using the delays (d). - */ - r = do_div(p, 360 / phase_num); - d = DIV_ROUND_CLOSEST(r * period_ps, - 360 * mmc->delay_step_ps); - d = min(d, mmc->delay_mask >> __ffs(mmc->delay_mask)); - } - - meson_mmc_apply_phase_delay(mmc, p, d); - return 0; -} - -static const struct clk_ops meson_mmc_clk_phase_ops = { - .get_phase = meson_mmc_clk_get_phase, - .set_phase = meson_mmc_clk_set_phase, -}; - static unsigned int meson_mmc_get_timeout_msecs(struct mmc_data *data) { unsigned int timeout = data->timeout_ns / NSEC_PER_MSEC; @@ -492,8 +405,6 @@ static int meson_mmc_clk_init(struct meson_host *host) struct clk_init_data init; struct clk_mux *mux; struct clk_divider *div; - struct meson_mmc_phase *core, *tx, *rx; - struct clk *clk; char clk_name[32]; int i, ret = 0; const char *mux_parent_names[MUX_CLK_NUM_PARENTS]; @@ -501,9 +412,11 @@ static int meson_mmc_clk_init(struct meson_host *host) u32 clk_reg; /* init SD_EMMC_CLOCK to sane defaults w/min clock rate */ - clk_reg = 0; - clk_reg |= CLK_ALWAYS_ON(host); + clk_reg = CLK_ALWAYS_ON(host); clk_reg |= CLK_DIV_MASK; + clk_reg |= FIELD_PREP(CLK_CORE_PHASE_MASK, CLK_PHASE_180); + clk_reg |= FIELD_PREP(CLK_TX_PHASE_MASK, CLK_PHASE_0); + clk_reg |= FIELD_PREP(CLK_RX_PHASE_MASK, CLK_PHASE_0); writel(clk_reg, host->regs + SD_EMMC_CLOCK); /* get the mux parents */ @@ -539,9 +452,9 @@ static int meson_mmc_clk_init(struct meson_host *host) mux->mask = CLK_SRC_MASK >> mux->shift; mux->hw.init = &init; - clk = devm_clk_register(host->dev, &mux->hw); - if (WARN_ON(IS_ERR(clk))) - return PTR_ERR(clk); + host->mux_clk = devm_clk_register(host->dev, &mux->hw); + if (WARN_ON(IS_ERR(host->mux_clk))) + return PTR_ERR(host->mux_clk); /* create the divider */ div = devm_kzalloc(host->dev, sizeof(*div), GFP_KERNEL); @@ -552,7 +465,7 @@ static int meson_mmc_clk_init(struct meson_host *host) init.name = clk_name; init.ops = &clk_divider_ops; init.flags = CLK_SET_RATE_PARENT; - clk_parent[0] = __clk_get_name(clk); + clk_parent[0] = __clk_get_name(host->mux_clk); init.parent_names = clk_parent; init.num_parents = 1; @@ -562,192 +475,19 @@ static int meson_mmc_clk_init(struct meson_host *host) div->hw.init = &init; div->flags = CLK_DIVIDER_ONE_BASED; - clk = devm_clk_register(host->dev, &div->hw); - if (WARN_ON(IS_ERR(clk))) - return PTR_ERR(clk); - - /* create the mmc core clock */ - core = devm_kzalloc(host->dev, sizeof(*core), GFP_KERNEL); - if (!core) - return -ENOMEM; - - snprintf(clk_name, sizeof(clk_name), "%s#core", dev_name(host->dev)); - init.name = clk_name; - init.ops = &meson_mmc_clk_phase_ops; - init.flags = CLK_SET_RATE_PARENT; - clk_parent[0] = __clk_get_name(clk); - init.parent_names = clk_parent; - init.num_parents = 1; - - core->reg = host->regs + SD_EMMC_CLOCK; - core->phase_mask = CLK_CORE_PHASE_MASK; - core->hw.init = &init; - - host->mmc_clk = devm_clk_register(host->dev, &core->hw); - if (WARN_ON(PTR_ERR_OR_ZERO(host->mmc_clk))) + host->mmc_clk = devm_clk_register(host->dev, &div->hw); + if (WARN_ON(IS_ERR(host->mmc_clk))) return PTR_ERR(host->mmc_clk); - /* create the mmc tx clock */ - tx = devm_kzalloc(host->dev, sizeof(*tx), GFP_KERNEL); - if (!tx) - return -ENOMEM; - - snprintf(clk_name, sizeof(clk_name), "%s#tx", dev_name(host->dev)); - init.name = clk_name; - init.ops = &meson_mmc_clk_phase_ops; - init.flags = 0; - clk_parent[0] = __clk_get_name(host->mmc_clk); - init.parent_names = clk_parent; - init.num_parents = 1; - - tx->reg = host->regs + SD_EMMC_CLOCK; - tx->phase_mask = CLK_TX_PHASE_MASK; - tx->delay_mask = CLK_TX_DELAY_MASK(host); - tx->delay_step_ps = CLK_DELAY_STEP_PS; - tx->hw.init = &init; - - host->tx_clk = devm_clk_register(host->dev, &tx->hw); - if (WARN_ON(PTR_ERR_OR_ZERO(host->tx_clk))) - return PTR_ERR(host->tx_clk); - - /* create the mmc rx clock */ - rx = devm_kzalloc(host->dev, sizeof(*rx), GFP_KERNEL); - if (!rx) - return -ENOMEM; - - snprintf(clk_name, sizeof(clk_name), "%s#rx", dev_name(host->dev)); - init.name = clk_name; - init.ops = &meson_mmc_clk_phase_ops; - init.flags = 0; - clk_parent[0] = __clk_get_name(host->mmc_clk); - init.parent_names = clk_parent; - init.num_parents = 1; - - rx->reg = host->regs + SD_EMMC_CLOCK; - rx->phase_mask = CLK_RX_PHASE_MASK; - rx->delay_mask = CLK_RX_DELAY_MASK(host); - rx->delay_step_ps = CLK_DELAY_STEP_PS; - rx->hw.init = &init; - - host->rx_clk = devm_clk_register(host->dev, &rx->hw); - if (WARN_ON(PTR_ERR_OR_ZERO(host->rx_clk))) - return PTR_ERR(host->rx_clk); - /* init SD_EMMC_CLOCK to sane defaults w/min clock rate */ host->mmc->f_min = clk_round_rate(host->mmc_clk, 400000); ret = clk_set_rate(host->mmc_clk, host->mmc->f_min); if (ret) return ret; - clk_set_phase(host->mmc_clk, 180); - clk_set_phase(host->tx_clk, 0); - clk_set_phase(host->rx_clk, 0); - return clk_prepare_enable(host->mmc_clk); } -static void meson_mmc_shift_map(unsigned long *map, unsigned long shift) -{ - DECLARE_BITMAP(left, CLK_PHASE_POINT_NUM); - DECLARE_BITMAP(right, CLK_PHASE_POINT_NUM); - - /* - * shift the bitmap right and reintroduce the dropped bits on the left - * of the bitmap - */ - bitmap_shift_right(right, map, shift, CLK_PHASE_POINT_NUM); - bitmap_shift_left(left, map, CLK_PHASE_POINT_NUM - shift, - CLK_PHASE_POINT_NUM); - bitmap_or(map, left, right, CLK_PHASE_POINT_NUM); -} - -static void meson_mmc_find_next_region(unsigned long *map, - unsigned long *start, - unsigned long *stop) -{ - *start = find_next_bit(map, CLK_PHASE_POINT_NUM, *start); - *stop = find_next_zero_bit(map, CLK_PHASE_POINT_NUM, *start); -} - -static int meson_mmc_find_tuning_point(unsigned long *test) -{ - unsigned long shift, stop, offset = 0, start = 0, size = 0; - - /* Get the all good/all bad situation out the way */ - if (bitmap_full(test, CLK_PHASE_POINT_NUM)) - return 0; /* All points are good so point 0 will do */ - else if (bitmap_empty(test, CLK_PHASE_POINT_NUM)) - return -EIO; /* No successful tuning point */ - - /* - * Now we know there is a least one region find. Make sure it does - * not wrap by the shifting the bitmap if necessary - */ - shift = find_first_zero_bit(test, CLK_PHASE_POINT_NUM); - if (shift != 0) - meson_mmc_shift_map(test, shift); - - while (start < CLK_PHASE_POINT_NUM) { - meson_mmc_find_next_region(test, &start, &stop); - - if ((stop - start) > size) { - offset = start; - size = stop - start; - } - - start = stop; - } - - /* Get the center point of the region */ - offset += (size / 2); - - /* Shift the result back */ - offset = (offset + shift) % CLK_PHASE_POINT_NUM; - - return offset; -} - -static int meson_mmc_clk_phase_tuning(struct mmc_host *mmc, u32 opcode, - struct clk *clk) -{ - int point, ret; - DECLARE_BITMAP(test, CLK_PHASE_POINT_NUM); - - dev_dbg(mmc_dev(mmc), "%s phase/delay tunning...\n", - __clk_get_name(clk)); - bitmap_zero(test, CLK_PHASE_POINT_NUM); - - /* Explore tuning points */ - for (point = 0; point < CLK_PHASE_POINT_NUM; point++) { - clk_set_phase(clk, point * CLK_PHASE_STEP); - ret = mmc_send_tuning(mmc, opcode, NULL); - if (!ret) - set_bit(point, test); - } - - /* Find the optimal tuning point and apply it */ - point = meson_mmc_find_tuning_point(test); - if (point < 0) - return point; /* tuning failed */ - - clk_set_phase(clk, point * CLK_PHASE_STEP); - dev_dbg(mmc_dev(mmc), "success with phase: %d\n", - clk_get_phase(clk)); - return 0; -} - -static int meson_mmc_execute_tuning(struct mmc_host *mmc, u32 opcode) -{ - struct meson_host *host = mmc_priv(mmc); - int adj = 0; - - /* enable signal resampling w/o delay */ - adj = ADJUST_ADJ_EN; - writel(adj, host->regs + host->data->adjust); - - return meson_mmc_clk_phase_tuning(mmc, opcode, host->rx_clk); -} - static int meson_mmc_prepare_ios_clock(struct meson_host *host, struct mmc_ios *ios) { @@ -796,9 +536,6 @@ static void meson_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) /* disable signal resampling */ writel(0, host->regs + host->data->adjust); - /* Reset rx phase */ - clk_set_phase(host->rx_clk, 0); - break; case MMC_POWER_ON: @@ -1226,7 +963,6 @@ static const struct mmc_host_ops meson_mmc_ops = { .get_cd = meson_mmc_get_cd, .pre_req = meson_mmc_pre_req, .post_req = meson_mmc_post_req, - .execute_tuning = meson_mmc_execute_tuning, .card_busy = meson_mmc_card_busy, .start_signal_voltage_switch = meson_mmc_voltage_switch, }; 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[90.63.244.31]) by smtp.googlemail.com with ESMTPSA id z23sm12361894wma.0.2019.04.23.02.02.53 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 23 Apr 2019 02:02:53 -0700 (PDT) From: Jerome Brunet To: Ulf Hansson , Kevin Hilman Subject: [PATCH v2 7/7] mmc: meson-gx: add signal resampling tuning Date: Tue, 23 Apr 2019 11:02:35 +0200 Message-Id: <20190423090235.17244-8-jbrunet@baylibre.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190423090235.17244-1-jbrunet@baylibre.com> References: <20190423090235.17244-1-jbrunet@baylibre.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190423_020256_288413_4D8A45B1 X-CRM114-Status: GOOD ( 14.12 ) X-BeenThere: linux-amlogic@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-amlogic@lists.infradead.org, linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, Jerome Brunet Sender: "linux-amlogic" Errors-To: linux-amlogic-bounces+patchwork-linux-amlogic=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Use signal resampling tuning for the UHS and HS200 modes. Instead of trying to get the *best* resampling setting with complex window calculation, we just stop on the first working setting. If the tuning setting later proves unstable, we will just continue the tuning where we left it. Signed-off-by: Jerome Brunet Tested-by: Martin Blumenstingl --- drivers/mmc/host/meson-gx-mmc.c | 73 +++++++++++++++++++++++++++++++-- 1 file changed, 70 insertions(+), 3 deletions(-) diff --git a/drivers/mmc/host/meson-gx-mmc.c b/drivers/mmc/host/meson-gx-mmc.c index acdc5520d02c..c5a8af4ca76b 100644 --- a/drivers/mmc/host/meson-gx-mmc.c +++ b/drivers/mmc/host/meson-gx-mmc.c @@ -488,6 +488,61 @@ static int meson_mmc_clk_init(struct meson_host *host) return clk_prepare_enable(host->mmc_clk); } +static void meson_mmc_disable_resampling(struct meson_host *host) +{ + unsigned int val = readl(host->regs + host->data->adjust); + + val &= ~ADJUST_ADJ_EN; + writel(val, host->regs + host->data->adjust); +} + +static void meson_mmc_reset_resampling(struct meson_host *host) +{ + unsigned int val; + + meson_mmc_disable_resampling(host); + + val = readl(host->regs + host->data->adjust); + val &= ~ADJUST_ADJ_DELAY_MASK; + writel(val, host->regs + host->data->adjust); +} + +static int meson_mmc_resampling_tuning(struct mmc_host *mmc, u32 opcode) +{ + struct meson_host *host = mmc_priv(mmc); + unsigned int val, dly, max_dly, i; + int ret; + + /* Resampling is done using the source clock */ + max_dly = DIV_ROUND_UP(clk_get_rate(host->mux_clk), + clk_get_rate(host->mmc_clk)); + + val = readl(host->regs + host->data->adjust); + val |= ADJUST_ADJ_EN; + writel(val, host->regs + host->data->adjust); + + if (mmc->doing_retune) + dly = FIELD_GET(ADJUST_ADJ_DELAY_MASK, val) + 1; + else + dly = 0; + + for (i = 0; i < max_dly; i++) { + val &= ~ADJUST_ADJ_DELAY_MASK; + val |= FIELD_PREP(ADJUST_ADJ_DELAY_MASK, (dly + i) % max_dly); + writel(val, host->regs + host->data->adjust); + + ret = mmc_send_tuning(mmc, opcode, NULL); + if (!ret) { + dev_dbg(mmc_dev(mmc), "resampling delay: %u\n", + (dly + i) % max_dly); + return 0; + } + } + + meson_mmc_reset_resampling(host); + return -EIO; +} + static int meson_mmc_prepare_ios_clock(struct meson_host *host, struct mmc_ios *ios) { @@ -507,6 +562,19 @@ static int meson_mmc_prepare_ios_clock(struct meson_host *host, return meson_mmc_clk_set(host, ios->clock, ddr); } +static void meson_mmc_check_resampling(struct meson_host *host, + struct mmc_ios *ios) +{ + switch (ios->timing) { + case MMC_TIMING_LEGACY: + case MMC_TIMING_MMC_HS: + case MMC_TIMING_SD_HS: + case MMC_TIMING_MMC_DDR52: + meson_mmc_disable_resampling(host); + break; + } +} + static void meson_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) { struct meson_host *host = mmc_priv(mmc); @@ -533,9 +601,6 @@ static void meson_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) if (!IS_ERR(mmc->supply.vmmc)) mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, ios->vdd); - /* disable signal resampling */ - writel(0, host->regs + host->data->adjust); - break; case MMC_POWER_ON: @@ -574,6 +639,7 @@ static void meson_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) val |= FIELD_PREP(CFG_BUS_WIDTH_MASK, bus_width); writel(val, host->regs + SD_EMMC_CFG); + meson_mmc_check_resampling(host, ios); err = meson_mmc_prepare_ios_clock(host, ios); if (err) dev_err(host->dev, "Failed to set clock: %d\n,", err); @@ -963,6 +1029,7 @@ static const struct mmc_host_ops meson_mmc_ops = { .get_cd = meson_mmc_get_cd, .pre_req = meson_mmc_pre_req, .post_req = meson_mmc_post_req, + .execute_tuning = meson_mmc_resampling_tuning, .card_busy = meson_mmc_card_busy, .start_signal_voltage_switch = meson_mmc_voltage_switch, };