From patchwork Wed Apr 24 19:32:48 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fenghua Yu X-Patchwork-Id: 10915653 X-Patchwork-Delegate: johannes@sipsolutions.net Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id B067B922 for ; Wed, 24 Apr 2019 19:44:21 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 9F6BB28B8A for ; Wed, 24 Apr 2019 19:44:21 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 924E728B91; Wed, 24 Apr 2019 19:44:21 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 25C6328B8A for ; Wed, 24 Apr 2019 19:44:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728554AbfDXToO (ORCPT ); Wed, 24 Apr 2019 15:44:14 -0400 Received: from mga09.intel.com ([134.134.136.24]:15194 "EHLO mga09.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728269AbfDXTll (ORCPT ); Wed, 24 Apr 2019 15:41:41 -0400 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga102.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 24 Apr 2019 12:41:39 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.60,390,1549958400"; d="scan'208";a="340454867" Received: from romley-ivt3.sc.intel.com ([172.25.110.60]) by fmsmga005.fm.intel.com with ESMTP; 24 Apr 2019 12:41:39 -0700 From: Fenghua Yu To: "Thomas Gleixner" , "Ingo Molnar" , "Borislav Petkov" , "H Peter Anvin" , "Paolo Bonzini" , "Dave Hansen" , "Ashok Raj" , "Peter Zijlstra" , "Ravi V Shankar" , "Xiaoyao Li " , "Christopherson Sean J" , "Kalle Valo" , "Michael Chan" Cc: "linux-kernel" , "x86" , kvm@vger.kernel.org, netdev@vger.kernel.org, linux-wireless@vger.kernel.org, Fenghua Yu Subject: [PATCH v8 01/15] x86/common: Align cpu_caps_cleared and cpu_caps_set to unsigned long Date: Wed, 24 Apr 2019 12:32:48 -0700 Message-Id: <1556134382-58814-2-git-send-email-fenghua.yu@intel.com> X-Mailer: git-send-email 2.5.0 In-Reply-To: <1556134382-58814-1-git-send-email-fenghua.yu@intel.com> References: <1556134382-58814-1-git-send-email-fenghua.yu@intel.com> Sender: linux-wireless-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-wireless@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP cpu_caps_cleared[] and cpu_caps_set[] may not be aligned to unsigned long. Atomic operations (i.e. set_bit() and clear_bit()) on the bitmaps may access two cache lines (a.k.a. split lock) and cause the CPU to do a bus lock to block all memory accesses from other processors to ensure atomicity. To avoid the overall performance degradation from the bus locking, align the two variables to unsigned long. Defining the variables as unsigned long may also fix the issue because they will be naturally aligned to unsigned long. But that needs additional code changes. Adding __aligned(unsigned long) is a simpler fix. Signed-off-by: Fenghua Yu Reviewed-by: Borislav Petkov --- arch/x86/kernel/cpu/common.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c index cb28e98a0659..3716e2bb028b 100644 --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -488,8 +488,9 @@ static const char *table_lookup_model(struct cpuinfo_x86 *c) return NULL; /* Not found */ } -__u32 cpu_caps_cleared[NCAPINTS + NBUGINTS]; -__u32 cpu_caps_set[NCAPINTS + NBUGINTS]; +/* Aligned to unsigned long to avoid split lock in atomic bitmap ops */ +__u32 cpu_caps_cleared[NCAPINTS + NBUGINTS] __aligned(sizeof(unsigned long)); +__u32 cpu_caps_set[NCAPINTS + NBUGINTS] __aligned(sizeof(unsigned long)); void load_percpu_segment(int cpu) { From patchwork Wed Apr 24 19:32:49 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fenghua Yu X-Patchwork-Id: 10915657 X-Patchwork-Delegate: johannes@sipsolutions.net Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 939C8922 for ; Wed, 24 Apr 2019 19:44:28 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 8261728B8A for ; Wed, 24 Apr 2019 19:44:28 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 75B2F28B90; Wed, 24 Apr 2019 19:44:28 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id EF14228B8A for ; Wed, 24 Apr 2019 19:44:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728592AbfDXTlk (ORCPT ); Wed, 24 Apr 2019 15:41:40 -0400 Received: from mga09.intel.com ([134.134.136.24]:15194 "EHLO mga09.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728001AbfDXTlk (ORCPT ); Wed, 24 Apr 2019 15:41:40 -0400 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga102.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 24 Apr 2019 12:41:39 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.60,390,1549958400"; d="scan'208";a="340454870" Received: from romley-ivt3.sc.intel.com ([172.25.110.60]) by fmsmga005.fm.intel.com with ESMTP; 24 Apr 2019 12:41:39 -0700 From: Fenghua Yu To: "Thomas Gleixner" , "Ingo Molnar" , "Borislav Petkov" , "H Peter Anvin" , "Paolo Bonzini" , "Dave Hansen" , "Ashok Raj" , "Peter Zijlstra" , "Ravi V Shankar" , "Xiaoyao Li " , "Christopherson Sean J" , "Kalle Valo" , "Michael Chan" Cc: "linux-kernel" , "x86" , kvm@vger.kernel.org, netdev@vger.kernel.org, linux-wireless@vger.kernel.org, Fenghua Yu Subject: [PATCH v8 02/15] drivers/net/b44: Align pwol_mask to unsigned long for better performance Date: Wed, 24 Apr 2019 12:32:49 -0700 Message-Id: <1556134382-58814-3-git-send-email-fenghua.yu@intel.com> X-Mailer: git-send-email 2.5.0 In-Reply-To: <1556134382-58814-1-git-send-email-fenghua.yu@intel.com> References: <1556134382-58814-1-git-send-email-fenghua.yu@intel.com> Sender: linux-wireless-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-wireless@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Peter Zijlstra A bit in pwol_mask is set in b44_magic_pattern() by atomic set_bit(). But since pwol_mask is local and never exposed to concurrency, there is no need to set bit in pwol_mask atomically. set_bit() sets the bit in a single unsigned long location. Because pwol_mask may not be aligned to unsigned long, the location may cross two cache lines. On x86, accessing two cache lines in locked instruction in set_bit() is called split locked access and can cause overall performance degradation. So use non atomic __set_bit() to set pwol_mask bits. __set_bit() won't hit split lock issue on x86. Signed-off-by: Peter Zijlstra Signed-off-by: Fenghua Yu --- drivers/net/ethernet/broadcom/b44.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/net/ethernet/broadcom/b44.c b/drivers/net/ethernet/broadcom/b44.c index 97ab0dd25552..5738ab963dfb 100644 --- a/drivers/net/ethernet/broadcom/b44.c +++ b/drivers/net/ethernet/broadcom/b44.c @@ -1520,7 +1520,7 @@ static int b44_magic_pattern(u8 *macaddr, u8 *ppattern, u8 *pmask, int offset) memset(ppattern + offset, 0xff, magicsync); for (j = 0; j < magicsync; j++) - set_bit(len++, (unsigned long *) pmask); + __set_bit(len++, (unsigned long *)pmask); for (j = 0; j < B44_MAX_PATTERNS; j++) { if ((B44_PATTERN_SIZE - len) >= ETH_ALEN) @@ -1532,7 +1532,7 @@ static int b44_magic_pattern(u8 *macaddr, u8 *ppattern, u8 *pmask, int offset) for (k = 0; k< ethaddr_bytes; k++) { ppattern[offset + magicsync + (j * ETH_ALEN) + k] = macaddr[k]; - set_bit(len++, (unsigned long *) pmask); + __set_bit(len++, (unsigned long *)pmask); } } return len - 1; From patchwork Wed Apr 24 19:32:50 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fenghua Yu X-Patchwork-Id: 10915635 X-Patchwork-Delegate: kvalo@adurom.com Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 4E7FF1390 for ; Wed, 24 Apr 2019 19:43:47 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 3EC4828B24 for ; Wed, 24 Apr 2019 19:43:47 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 322FE28B8E; Wed, 24 Apr 2019 19:43:47 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id C00DE28B24 for ; Wed, 24 Apr 2019 19:43:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729652AbfDXTlm (ORCPT ); Wed, 24 Apr 2019 15:41:42 -0400 Received: from mga09.intel.com ([134.134.136.24]:15196 "EHLO mga09.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728001AbfDXTll (ORCPT ); Wed, 24 Apr 2019 15:41:41 -0400 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga102.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 24 Apr 2019 12:41:39 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.60,390,1549958400"; d="scan'208";a="340454873" Received: from romley-ivt3.sc.intel.com ([172.25.110.60]) by fmsmga005.fm.intel.com with ESMTP; 24 Apr 2019 12:41:39 -0700 From: Fenghua Yu To: "Thomas Gleixner" , "Ingo Molnar" , "Borislav Petkov" , "H Peter Anvin" , "Paolo Bonzini" , "Dave Hansen" , "Ashok Raj" , "Peter Zijlstra" , "Ravi V Shankar" , "Xiaoyao Li " , "Christopherson Sean J" , "Kalle Valo" , "Michael Chan" Cc: "linux-kernel" , "x86" , kvm@vger.kernel.org, netdev@vger.kernel.org, linux-wireless@vger.kernel.org, Fenghua Yu Subject: [PATCH v8 03/15] wlcore: simplify/fix/optimize reg_ch_conf_pending operations Date: Wed, 24 Apr 2019 12:32:50 -0700 Message-Id: <1556134382-58814-4-git-send-email-fenghua.yu@intel.com> X-Mailer: git-send-email 2.5.0 In-Reply-To: <1556134382-58814-1-git-send-email-fenghua.yu@intel.com> References: <1556134382-58814-1-git-send-email-fenghua.yu@intel.com> Sender: linux-wireless-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-wireless@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Paolo Bonzini Bitmaps are defined on unsigned longs, so the usage of u32[2] in the wlcore driver is incorrect. As noted by Peter Zijlstra, casting arrays to a bitmap is incorrect for big-endian architectures. When looking at it I observed that: - operations on reg_ch_conf_pending is always under the wl_lock mutex, so set_bit is overkill - the only case where reg_ch_conf_pending is accessed a u32 at a time is unnecessary too. This patch cleans up everything in this area, and changes tmp_ch_bitmap to have the proper alignment. Signed-off-by: Paolo Bonzini Signed-off-by: Fenghua Yu --- drivers/net/wireless/ti/wlcore/cmd.c | 15 ++++++--------- drivers/net/wireless/ti/wlcore/wlcore.h | 4 ++-- 2 files changed, 8 insertions(+), 11 deletions(-) diff --git a/drivers/net/wireless/ti/wlcore/cmd.c b/drivers/net/wireless/ti/wlcore/cmd.c index 348be0aed97e..0415a064f6e2 100644 --- a/drivers/net/wireless/ti/wlcore/cmd.c +++ b/drivers/net/wireless/ti/wlcore/cmd.c @@ -1700,14 +1700,14 @@ void wlcore_set_pending_regdomain_ch(struct wl1271 *wl, u16 channel, ch_bit_idx = wlcore_get_reg_conf_ch_idx(band, channel); if (ch_bit_idx >= 0 && ch_bit_idx <= WL1271_MAX_CHANNELS) - set_bit(ch_bit_idx, (long *)wl->reg_ch_conf_pending); + __set_bit_le(ch_bit_idx, (long *)wl->reg_ch_conf_pending); } int wlcore_cmd_regdomain_config_locked(struct wl1271 *wl) { struct wl12xx_cmd_regdomain_dfs_config *cmd = NULL; int ret = 0, i, b, ch_bit_idx; - u32 tmp_ch_bitmap[2]; + __le32 tmp_ch_bitmap[2] __aligned(sizeof(unsigned long)); struct wiphy *wiphy = wl->hw->wiphy; struct ieee80211_supported_band *band; bool timeout = false; @@ -1717,7 +1717,7 @@ int wlcore_cmd_regdomain_config_locked(struct wl1271 *wl) wl1271_debug(DEBUG_CMD, "cmd reg domain config"); - memset(tmp_ch_bitmap, 0, sizeof(tmp_ch_bitmap)); + memcpy(tmp_ch_bitmap, wl->reg_ch_conf_pending, sizeof(tmp_ch_bitmap)); for (b = NL80211_BAND_2GHZ; b <= NL80211_BAND_5GHZ; b++) { band = wiphy->bands[b]; @@ -1738,13 +1738,10 @@ int wlcore_cmd_regdomain_config_locked(struct wl1271 *wl) if (ch_bit_idx < 0) continue; - set_bit(ch_bit_idx, (long *)tmp_ch_bitmap); + __set_bit_le(ch_bit_idx, (long *)tmp_ch_bitmap); } } - tmp_ch_bitmap[0] |= wl->reg_ch_conf_pending[0]; - tmp_ch_bitmap[1] |= wl->reg_ch_conf_pending[1]; - if (!memcmp(tmp_ch_bitmap, wl->reg_ch_conf_last, sizeof(tmp_ch_bitmap))) goto out; @@ -1754,8 +1751,8 @@ int wlcore_cmd_regdomain_config_locked(struct wl1271 *wl) goto out; } - cmd->ch_bit_map1 = cpu_to_le32(tmp_ch_bitmap[0]); - cmd->ch_bit_map2 = cpu_to_le32(tmp_ch_bitmap[1]); + cmd->ch_bit_map1 = tmp_ch_bitmap[0]; + cmd->ch_bit_map2 = tmp_ch_bitmap[1]; cmd->dfs_region = wl->dfs_region; wl1271_debug(DEBUG_CMD, diff --git a/drivers/net/wireless/ti/wlcore/wlcore.h b/drivers/net/wireless/ti/wlcore/wlcore.h index dd14850b0603..870eea3e7a27 100644 --- a/drivers/net/wireless/ti/wlcore/wlcore.h +++ b/drivers/net/wireless/ti/wlcore/wlcore.h @@ -320,9 +320,9 @@ struct wl1271 { bool watchdog_recovery; /* Reg domain last configuration */ - u32 reg_ch_conf_last[2] __aligned(8); + DECLARE_BITMAP(reg_ch_conf_last, 64); /* Reg domain pending configuration */ - u32 reg_ch_conf_pending[2]; + DECLARE_BITMAP(reg_ch_conf_pending, 64); /* Pointer that holds DMA-friendly block for the mailbox */ void *mbox; From patchwork Wed Apr 24 19:32:51 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fenghua Yu X-Patchwork-Id: 10915647 X-Patchwork-Delegate: johannes@sipsolutions.net Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 92B431708 for ; Wed, 24 Apr 2019 19:43:56 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 848EC28B24 for ; Wed, 24 Apr 2019 19:43:56 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 77EAA28B8E; Wed, 24 Apr 2019 19:43:56 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 2D65228B24 for ; Wed, 24 Apr 2019 19:43:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727532AbfDXTns (ORCPT ); Wed, 24 Apr 2019 15:43:48 -0400 Received: from mga09.intel.com ([134.134.136.24]:15196 "EHLO mga09.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729346AbfDXTlm (ORCPT ); Wed, 24 Apr 2019 15:41:42 -0400 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga102.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 24 Apr 2019 12:41:40 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.60,390,1549958400"; d="scan'208";a="340454876" Received: from romley-ivt3.sc.intel.com ([172.25.110.60]) by fmsmga005.fm.intel.com with ESMTP; 24 Apr 2019 12:41:39 -0700 From: Fenghua Yu To: "Thomas Gleixner" , "Ingo Molnar" , "Borislav Petkov" , "H Peter Anvin" , "Paolo Bonzini" , "Dave Hansen" , "Ashok Raj" , "Peter Zijlstra" , "Ravi V Shankar" , "Xiaoyao Li " , "Christopherson Sean J" , "Kalle Valo" , "Michael Chan" Cc: "linux-kernel" , "x86" , kvm@vger.kernel.org, netdev@vger.kernel.org, linux-wireless@vger.kernel.org, Fenghua Yu Subject: [PATCH v8 04/15] x86/split_lock: Align x86_capability to unsigned long to avoid split locked access Date: Wed, 24 Apr 2019 12:32:51 -0700 Message-Id: <1556134382-58814-5-git-send-email-fenghua.yu@intel.com> X-Mailer: git-send-email 2.5.0 In-Reply-To: <1556134382-58814-1-git-send-email-fenghua.yu@intel.com> References: <1556134382-58814-1-git-send-email-fenghua.yu@intel.com> Sender: linux-wireless-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-wireless@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP set_cpu_cap() calls locked BTS and clear_cpu_cap() calls locked BTR to operate on bitmap defined in x86_capability. Locked BTS/BTR accesses a single unsigned long location. In 64-bit mode, the location is at: base address of x86_capability + (bit offset in x86_capability / 64) * 8 Since base address of x86_capability may not be aligned to unsigned long, the single unsigned long location may cross two cache lines and accessing the location by locked BTS/BTR introductions will cause split lock. To fix the split lock issue, align x86_capability to size of unsigned long so that the location will be always within one cache line. Changing x86_capability's type to unsigned long may also fix the issue because x86_capability will be naturally aligned to size of unsigned long. But this needs additional code changes. So choose the simpler solution by setting the array's alignment to size of unsigned long. Signed-off-by: Fenghua Yu --- arch/x86/include/asm/processor.h | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/processor.h index 2bb3a648fc12..7c62b9ad6e5a 100644 --- a/arch/x86/include/asm/processor.h +++ b/arch/x86/include/asm/processor.h @@ -93,7 +93,9 @@ struct cpuinfo_x86 { __u32 extended_cpuid_level; /* Maximum supported CPUID level, -1=no CPUID: */ int cpuid_level; - __u32 x86_capability[NCAPINTS + NBUGINTS]; + /* Aligned to size of unsigned long to avoid split lock in atomic ops */ + __u32 x86_capability[NCAPINTS + NBUGINTS] + __aligned(sizeof(unsigned long)); char x86_vendor_id[16]; char x86_model_id[64]; /* in KB - valid for CPUS which support this call: */ From patchwork Wed Apr 24 19:32:52 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fenghua Yu X-Patchwork-Id: 10915631 X-Patchwork-Delegate: johannes@sipsolutions.net Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 602F8922 for ; Wed, 24 Apr 2019 19:43:42 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 4EA2028B24 for ; Wed, 24 Apr 2019 19:43:42 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 4246D28B8E; Wed, 24 Apr 2019 19:43:42 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id E816A28B24 for ; Wed, 24 Apr 2019 19:43:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726904AbfDXTnd (ORCPT ); Wed, 24 Apr 2019 15:43:33 -0400 Received: from mga09.intel.com ([134.134.136.24]:15194 "EHLO mga09.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729527AbfDXTlm (ORCPT ); Wed, 24 Apr 2019 15:41:42 -0400 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga102.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 24 Apr 2019 12:41:40 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.60,390,1549958400"; d="scan'208";a="340454879" Received: from romley-ivt3.sc.intel.com ([172.25.110.60]) by fmsmga005.fm.intel.com with ESMTP; 24 Apr 2019 12:41:40 -0700 From: Fenghua Yu To: "Thomas Gleixner" , "Ingo Molnar" , "Borislav Petkov" , "H Peter Anvin" , "Paolo Bonzini" , "Dave Hansen" , "Ashok Raj" , "Peter Zijlstra" , "Ravi V Shankar" , "Xiaoyao Li " , "Christopherson Sean J" , "Kalle Valo" , "Michael Chan" Cc: "linux-kernel" , "x86" , kvm@vger.kernel.org, netdev@vger.kernel.org, linux-wireless@vger.kernel.org, Fenghua Yu Subject: [PATCH v8 05/15] x86/msr-index: Define MSR_IA32_CORE_CAPABILITY and split lock detection bit Date: Wed, 24 Apr 2019 12:32:52 -0700 Message-Id: <1556134382-58814-6-git-send-email-fenghua.yu@intel.com> X-Mailer: git-send-email 2.5.0 In-Reply-To: <1556134382-58814-1-git-send-email-fenghua.yu@intel.com> References: <1556134382-58814-1-git-send-email-fenghua.yu@intel.com> Sender: linux-wireless-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-wireless@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP A new MSR_IA32_CORE_CAPABILITY (0xcf) is defined. Each bit in the MSR enumerates a model specific feature. Currently bit 5 enumerates split lock detection. When bit 5 is 1, split lock detection is supported. When the bit is 0, split lock detection is not supported. Please check the latest Intel 64 and IA-32 Architectures Software Developer's Manual for more detailed information on the MSR and the split lock detection bit. Signed-off-by: Fenghua Yu --- arch/x86/include/asm/msr-index.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index ca5bc0eacb95..f65ef6f783d2 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -59,6 +59,9 @@ #define MSR_PLATFORM_INFO_CPUID_FAULT_BIT 31 #define MSR_PLATFORM_INFO_CPUID_FAULT BIT_ULL(MSR_PLATFORM_INFO_CPUID_FAULT_BIT) +#define MSR_IA32_CORE_CAPABILITY 0x000000cf +#define CORE_CAP_SPLIT_LOCK_DETECT BIT(5) /* Detect split lock */ + #define MSR_PKG_CST_CONFIG_CONTROL 0x000000e2 #define NHM_C3_AUTO_DEMOTE (1UL << 25) #define NHM_C1_AUTO_DEMOTE (1UL << 26) From patchwork Wed Apr 24 19:32:53 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fenghua Yu X-Patchwork-Id: 10915621 X-Patchwork-Delegate: johannes@sipsolutions.net Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 50E211390 for ; Wed, 24 Apr 2019 19:43:18 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 413C328B27 for ; Wed, 24 Apr 2019 19:43:18 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 348E128B24; Wed, 24 Apr 2019 19:43:18 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id D2BD928B24 for ; Wed, 24 Apr 2019 19:43:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2390159AbfDXTm6 (ORCPT ); Wed, 24 Apr 2019 15:42:58 -0400 Received: from mga09.intel.com ([134.134.136.24]:15202 "EHLO mga09.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729695AbfDXTlm (ORCPT ); Wed, 24 Apr 2019 15:41:42 -0400 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga102.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 24 Apr 2019 12:41:40 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.60,390,1549958400"; d="scan'208";a="340454883" Received: from romley-ivt3.sc.intel.com ([172.25.110.60]) by fmsmga005.fm.intel.com with ESMTP; 24 Apr 2019 12:41:40 -0700 From: Fenghua Yu To: "Thomas Gleixner" , "Ingo Molnar" , "Borislav Petkov" , "H Peter Anvin" , "Paolo Bonzini" , "Dave Hansen" , "Ashok Raj" , "Peter Zijlstra" , "Ravi V Shankar" , "Xiaoyao Li " , "Christopherson Sean J" , "Kalle Valo" , "Michael Chan" Cc: "linux-kernel" , "x86" , kvm@vger.kernel.org, netdev@vger.kernel.org, linux-wireless@vger.kernel.org, Fenghua Yu Subject: [PATCH v8 06/15] x86/cpufeatures: Enumerate MSR_IA32_CORE_CAPABILITY Date: Wed, 24 Apr 2019 12:32:53 -0700 Message-Id: <1556134382-58814-7-git-send-email-fenghua.yu@intel.com> X-Mailer: git-send-email 2.5.0 In-Reply-To: <1556134382-58814-1-git-send-email-fenghua.yu@intel.com> References: <1556134382-58814-1-git-send-email-fenghua.yu@intel.com> Sender: linux-wireless-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-wireless@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP MSR_IA32_CORE_CAPABILITY (0xcf) contains bits that enumerate some model specific features. The MSR 0xcf itself is enumerated by CPUID.(EAX=0x7,ECX=0):EDX[30]. When this CPUID bit is 1, the MSR 0xcf exists. Detailed information on the CPUID bit and the MSR can be found in the latest Intel 64 and IA-32 Architectures Software Developer's Manual. Signed-off-by: Fenghua Yu --- arch/x86/include/asm/cpufeatures.h | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h index 981ff9479648..eff25e2015a5 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -350,6 +350,7 @@ #define X86_FEATURE_INTEL_STIBP (18*32+27) /* "" Single Thread Indirect Branch Predictors */ #define X86_FEATURE_FLUSH_L1D (18*32+28) /* Flush L1D cache */ #define X86_FEATURE_ARCH_CAPABILITIES (18*32+29) /* IA32_ARCH_CAPABILITIES MSR (Intel) */ +#define X86_FEATURE_CORE_CAPABILITY (18*32+30) /* "" IA32_CORE_CAPABILITY MSR */ #define X86_FEATURE_SPEC_CTRL_SSBD (18*32+31) /* "" Speculative Store Bypass Disable */ /* From patchwork Wed Apr 24 19:32:54 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fenghua Yu X-Patchwork-Id: 10915595 X-Patchwork-Delegate: johannes@sipsolutions.net Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 4E9A61708 for ; Wed, 24 Apr 2019 19:42:10 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 3E16828C04 for ; Wed, 24 Apr 2019 19:42:10 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 3BDA028C46; Wed, 24 Apr 2019 19:42:10 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 8E67A28B8A for ; Wed, 24 Apr 2019 19:42:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2389645AbfDXTlo (ORCPT ); Wed, 24 Apr 2019 15:41:44 -0400 Received: from mga09.intel.com ([134.134.136.24]:15196 "EHLO mga09.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729724AbfDXTln (ORCPT ); Wed, 24 Apr 2019 15:41:43 -0400 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga102.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 24 Apr 2019 12:41:40 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.60,390,1549958400"; d="scan'208";a="340454886" Received: from romley-ivt3.sc.intel.com ([172.25.110.60]) by fmsmga005.fm.intel.com with ESMTP; 24 Apr 2019 12:41:40 -0700 From: Fenghua Yu To: "Thomas Gleixner" , "Ingo Molnar" , "Borislav Petkov" , "H Peter Anvin" , "Paolo Bonzini" , "Dave Hansen" , "Ashok Raj" , "Peter Zijlstra" , "Ravi V Shankar" , "Xiaoyao Li " , "Christopherson Sean J" , "Kalle Valo" , "Michael Chan" Cc: "linux-kernel" , "x86" , kvm@vger.kernel.org, netdev@vger.kernel.org, linux-wireless@vger.kernel.org, Fenghua Yu Subject: [PATCH v8 07/15] x86/split_lock: Enumerate split lock detection by MSR_IA32_CORE_CAPABILITY Date: Wed, 24 Apr 2019 12:32:54 -0700 Message-Id: <1556134382-58814-8-git-send-email-fenghua.yu@intel.com> X-Mailer: git-send-email 2.5.0 In-Reply-To: <1556134382-58814-1-git-send-email-fenghua.yu@intel.com> References: <1556134382-58814-1-git-send-email-fenghua.yu@intel.com> Sender: linux-wireless-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-wireless@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Bits in MSR_IA32_CORE_CAPABILITY enumerate a few features that are not enumerated through CPUID. Currently bit 5 is defined to enumerate feature of split lock detection. All other bits are reserved now. When bit 5 is 1, the feature is supported and feature bit X86_FEATURE_SPLIT_LOCK_DETECT is set. Otherwise, the feature is not available. The MSR_IA32_CORE_CAPABILITY itself is enumerated by CPUID.(EAX=0x7,ECX=0):EDX[30]. Signed-off-by: Fenghua Yu --- arch/x86/include/asm/cpu.h | 5 ++ arch/x86/include/asm/cpufeatures.h | 1 + arch/x86/kernel/cpu/common.c | 2 + arch/x86/kernel/cpu/cpuid-deps.c | 79 +++++++++++++++--------------- arch/x86/kernel/cpu/intel.c | 21 ++++++++ 5 files changed, 69 insertions(+), 39 deletions(-) diff --git a/arch/x86/include/asm/cpu.h b/arch/x86/include/asm/cpu.h index adc6cc86b062..4e03f53fc079 100644 --- a/arch/x86/include/asm/cpu.h +++ b/arch/x86/include/asm/cpu.h @@ -40,4 +40,9 @@ int mwait_usable(const struct cpuinfo_x86 *); unsigned int x86_family(unsigned int sig); unsigned int x86_model(unsigned int sig); unsigned int x86_stepping(unsigned int sig); +#ifdef CONFIG_CPU_SUP_INTEL +void __init cpu_set_core_cap_bits(struct cpuinfo_x86 *c); +#else +static inline void __init cpu_set_core_cap_bits(struct cpuinfo_x86 *c) {} +#endif #endif /* _ASM_X86_CPU_H */ diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h index eff25e2015a5..db0c1826d7ad 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -221,6 +221,7 @@ #define X86_FEATURE_ZEN ( 7*32+28) /* "" CPU is AMD family 0x17 (Zen) */ #define X86_FEATURE_L1TF_PTEINV ( 7*32+29) /* "" L1TF workaround PTE inversion */ #define X86_FEATURE_IBRS_ENHANCED ( 7*32+30) /* Enhanced IBRS */ +#define X86_FEATURE_SPLIT_LOCK_DETECT ( 7*32+31) /* #AC for split lock */ /* Virtualization flags: Linux defined, word 8 */ #define X86_FEATURE_TPR_SHADOW ( 8*32+ 0) /* Intel TPR Shadow */ diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c index 3716e2bb028b..bbdd69dd4f5f 100644 --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -1105,6 +1105,8 @@ static void __init early_identify_cpu(struct cpuinfo_x86 *c) cpu_set_bug_bits(c); + cpu_set_core_cap_bits(c); + fpu__init_system(c); #ifdef CONFIG_X86_32 diff --git a/arch/x86/kernel/cpu/cpuid-deps.c b/arch/x86/kernel/cpu/cpuid-deps.c index 2c0bd38a44ab..3d633f67fbd7 100644 --- a/arch/x86/kernel/cpu/cpuid-deps.c +++ b/arch/x86/kernel/cpu/cpuid-deps.c @@ -20,45 +20,46 @@ struct cpuid_dep { * but it's difficult to tell that to the init reference checker. */ static const struct cpuid_dep cpuid_deps[] = { - { X86_FEATURE_XSAVEOPT, X86_FEATURE_XSAVE }, - { X86_FEATURE_XSAVEC, X86_FEATURE_XSAVE }, - { X86_FEATURE_XSAVES, X86_FEATURE_XSAVE }, - { X86_FEATURE_AVX, X86_FEATURE_XSAVE }, - { X86_FEATURE_PKU, X86_FEATURE_XSAVE }, - { X86_FEATURE_MPX, X86_FEATURE_XSAVE }, - { X86_FEATURE_XGETBV1, X86_FEATURE_XSAVE }, - { X86_FEATURE_FXSR_OPT, X86_FEATURE_FXSR }, - { X86_FEATURE_XMM, X86_FEATURE_FXSR }, - { X86_FEATURE_XMM2, X86_FEATURE_XMM }, - { X86_FEATURE_XMM3, X86_FEATURE_XMM2 }, - { X86_FEATURE_XMM4_1, X86_FEATURE_XMM2 }, - { X86_FEATURE_XMM4_2, X86_FEATURE_XMM2 }, - { X86_FEATURE_XMM3, X86_FEATURE_XMM2 }, - { X86_FEATURE_PCLMULQDQ, X86_FEATURE_XMM2 }, - { X86_FEATURE_SSSE3, X86_FEATURE_XMM2, }, - { X86_FEATURE_F16C, X86_FEATURE_XMM2, }, - { X86_FEATURE_AES, X86_FEATURE_XMM2 }, - { X86_FEATURE_SHA_NI, X86_FEATURE_XMM2 }, - { X86_FEATURE_FMA, X86_FEATURE_AVX }, - { X86_FEATURE_AVX2, X86_FEATURE_AVX, }, - { X86_FEATURE_AVX512F, X86_FEATURE_AVX, }, - { X86_FEATURE_AVX512IFMA, X86_FEATURE_AVX512F }, - { X86_FEATURE_AVX512PF, X86_FEATURE_AVX512F }, - { X86_FEATURE_AVX512ER, X86_FEATURE_AVX512F }, - { X86_FEATURE_AVX512CD, X86_FEATURE_AVX512F }, - { X86_FEATURE_AVX512DQ, X86_FEATURE_AVX512F }, - { X86_FEATURE_AVX512BW, X86_FEATURE_AVX512F }, - { X86_FEATURE_AVX512VL, X86_FEATURE_AVX512F }, - { X86_FEATURE_AVX512VBMI, X86_FEATURE_AVX512F }, - { X86_FEATURE_AVX512_VBMI2, X86_FEATURE_AVX512VL }, - { X86_FEATURE_GFNI, X86_FEATURE_AVX512VL }, - { X86_FEATURE_VAES, X86_FEATURE_AVX512VL }, - { X86_FEATURE_VPCLMULQDQ, X86_FEATURE_AVX512VL }, - { X86_FEATURE_AVX512_VNNI, X86_FEATURE_AVX512VL }, - { X86_FEATURE_AVX512_BITALG, X86_FEATURE_AVX512VL }, - { X86_FEATURE_AVX512_4VNNIW, X86_FEATURE_AVX512F }, - { X86_FEATURE_AVX512_4FMAPS, X86_FEATURE_AVX512F }, - { X86_FEATURE_AVX512_VPOPCNTDQ, X86_FEATURE_AVX512F }, + { X86_FEATURE_XSAVEOPT, X86_FEATURE_XSAVE }, + { X86_FEATURE_XSAVEC, X86_FEATURE_XSAVE }, + { X86_FEATURE_XSAVES, X86_FEATURE_XSAVE }, + { X86_FEATURE_AVX, X86_FEATURE_XSAVE }, + { X86_FEATURE_PKU, X86_FEATURE_XSAVE }, + { X86_FEATURE_MPX, X86_FEATURE_XSAVE }, + { X86_FEATURE_XGETBV1, X86_FEATURE_XSAVE }, + { X86_FEATURE_FXSR_OPT, X86_FEATURE_FXSR }, + { X86_FEATURE_XMM, X86_FEATURE_FXSR }, + { X86_FEATURE_XMM2, X86_FEATURE_XMM }, + { X86_FEATURE_XMM3, X86_FEATURE_XMM2 }, + { X86_FEATURE_XMM4_1, X86_FEATURE_XMM2 }, + { X86_FEATURE_XMM4_2, X86_FEATURE_XMM2 }, + { X86_FEATURE_XMM3, X86_FEATURE_XMM2 }, + { X86_FEATURE_PCLMULQDQ, X86_FEATURE_XMM2 }, + { X86_FEATURE_SSSE3, X86_FEATURE_XMM2, }, + { X86_FEATURE_F16C, X86_FEATURE_XMM2, }, + { X86_FEATURE_AES, X86_FEATURE_XMM2 }, + { X86_FEATURE_SHA_NI, X86_FEATURE_XMM2 }, + { X86_FEATURE_FMA, X86_FEATURE_AVX }, + { X86_FEATURE_AVX2, X86_FEATURE_AVX, }, + { X86_FEATURE_AVX512F, X86_FEATURE_AVX, }, + { X86_FEATURE_AVX512IFMA, X86_FEATURE_AVX512F }, + { X86_FEATURE_AVX512PF, X86_FEATURE_AVX512F }, + { X86_FEATURE_AVX512ER, X86_FEATURE_AVX512F }, + { X86_FEATURE_AVX512CD, X86_FEATURE_AVX512F }, + { X86_FEATURE_AVX512DQ, X86_FEATURE_AVX512F }, + { X86_FEATURE_AVX512BW, X86_FEATURE_AVX512F }, + { X86_FEATURE_AVX512VL, X86_FEATURE_AVX512F }, + { X86_FEATURE_AVX512VBMI, X86_FEATURE_AVX512F }, + { X86_FEATURE_AVX512_VBMI2, X86_FEATURE_AVX512VL }, + { X86_FEATURE_GFNI, X86_FEATURE_AVX512VL }, + { X86_FEATURE_VAES, X86_FEATURE_AVX512VL }, + { X86_FEATURE_VPCLMULQDQ, X86_FEATURE_AVX512VL }, + { X86_FEATURE_AVX512_VNNI, X86_FEATURE_AVX512VL }, + { X86_FEATURE_AVX512_BITALG, X86_FEATURE_AVX512VL }, + { X86_FEATURE_AVX512_4VNNIW, X86_FEATURE_AVX512F }, + { X86_FEATURE_AVX512_4FMAPS, X86_FEATURE_AVX512F }, + { X86_FEATURE_AVX512_VPOPCNTDQ, X86_FEATURE_AVX512F }, + { X86_FEATURE_SPLIT_LOCK_DETECT, X86_FEATURE_CORE_CAPABILITY}, {} }; diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c index 3142fd7a9b32..86a3a646e0ce 100644 --- a/arch/x86/kernel/cpu/intel.c +++ b/arch/x86/kernel/cpu/intel.c @@ -1029,3 +1029,24 @@ static const struct cpu_dev intel_cpu_dev = { cpu_dev_register(intel_cpu_dev); +static void __init set_split_lock_detect(void) +{ + setup_force_cpu_cap(X86_FEATURE_SPLIT_LOCK_DETECT); +} + +void __init cpu_set_core_cap_bits(struct cpuinfo_x86 *c) +{ + u64 ia32_core_cap = 0; + + if (!cpu_has(c, X86_FEATURE_CORE_CAPABILITY)) + return; + + /* + * If MSR_IA32_CORE_CAPABILITY exists, enumerate features that are + * reported in the MSR. + */ + rdmsrl(MSR_IA32_CORE_CAPABILITY, ia32_core_cap); + + if (ia32_core_cap & CORE_CAP_SPLIT_LOCK_DETECT) + set_split_lock_detect(); +} From patchwork Wed Apr 24 19:32:55 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fenghua Yu X-Patchwork-Id: 10915615 X-Patchwork-Delegate: johannes@sipsolutions.net Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id E3B861708 for ; Wed, 24 Apr 2019 19:42:50 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id D254C28A71 for ; Wed, 24 Apr 2019 19:42:50 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id C5FA928B24; Wed, 24 Apr 2019 19:42:50 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 748E328A71 for ; Wed, 24 Apr 2019 19:42:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730344AbfDXTmm (ORCPT ); Wed, 24 Apr 2019 15:42:42 -0400 Received: from mga09.intel.com ([134.134.136.24]:15202 "EHLO mga09.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729841AbfDXTlo (ORCPT ); Wed, 24 Apr 2019 15:41:44 -0400 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga102.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 24 Apr 2019 12:41:40 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.60,390,1549958400"; d="scan'208";a="340454889" Received: from romley-ivt3.sc.intel.com ([172.25.110.60]) by fmsmga005.fm.intel.com with ESMTP; 24 Apr 2019 12:41:40 -0700 From: Fenghua Yu To: "Thomas Gleixner" , "Ingo Molnar" , "Borislav Petkov" , "H Peter Anvin" , "Paolo Bonzini" , "Dave Hansen" , "Ashok Raj" , "Peter Zijlstra" , "Ravi V Shankar" , "Xiaoyao Li " , "Christopherson Sean J" , "Kalle Valo" , "Michael Chan" Cc: "linux-kernel" , "x86" , kvm@vger.kernel.org, netdev@vger.kernel.org, linux-wireless@vger.kernel.org, Fenghua Yu Subject: [PATCH v8 08/15] x86/split_lock: Enumerate split lock detection on Icelake mobile processor Date: Wed, 24 Apr 2019 12:32:55 -0700 Message-Id: <1556134382-58814-9-git-send-email-fenghua.yu@intel.com> X-Mailer: git-send-email 2.5.0 In-Reply-To: <1556134382-58814-1-git-send-email-fenghua.yu@intel.com> References: <1556134382-58814-1-git-send-email-fenghua.yu@intel.com> Sender: linux-wireless-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-wireless@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Icelake mobile processor can detect split lock operations although the processor doesn't have MSR IA32_CORE_CAPABILITY and split lock detection bit in the MSR. Set split lock detection feature bit X86_FEATURE_SPLIT_LOCK_DETECT on the processor based on its family/model/stepping. In the future, a few other processors may also have the split lock detection feature but don't have MSR IA32_CORE_CAPABILITY. The feature will be enumerated on those processors once their family/model/stepping information is released. Signed-off-by: Fenghua Yu --- arch/x86/kernel/cpu/intel.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c index 86a3a646e0ce..d7e676c2aebf 100644 --- a/arch/x86/kernel/cpu/intel.c +++ b/arch/x86/kernel/cpu/intel.c @@ -1038,8 +1038,18 @@ void __init cpu_set_core_cap_bits(struct cpuinfo_x86 *c) { u64 ia32_core_cap = 0; - if (!cpu_has(c, X86_FEATURE_CORE_CAPABILITY)) + if (!cpu_has(c, X86_FEATURE_CORE_CAPABILITY)) { + /* + * The following processors have split lock detection feature. + * But since they don't have MSR IA32_CORE_CAPABILITY, the + * feature cannot be enumerated by the MSR. So enumerate the + * feature by family/model/stepping. + */ + if (c->x86 == 6 && c->x86_model == INTEL_FAM6_ICELAKE_MOBILE) + set_split_lock_detect(); + return; + } /* * If MSR_IA32_CORE_CAPABILITY exists, enumerate features that are From patchwork Wed Apr 24 19:32:56 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fenghua Yu X-Patchwork-Id: 10915629 X-Patchwork-Delegate: johannes@sipsolutions.net Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 9C3101708 for ; Wed, 24 Apr 2019 19:43:28 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 8E19628B24 for ; Wed, 24 Apr 2019 19:43:28 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 8251D28B8A; Wed, 24 Apr 2019 19:43:28 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 3CFD328B8E for ; Wed, 24 Apr 2019 19:43:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2388791AbfDXTm5 (ORCPT ); Wed, 24 Apr 2019 15:42:57 -0400 Received: from mga09.intel.com ([134.134.136.24]:15194 "EHLO mga09.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729810AbfDXTln (ORCPT ); Wed, 24 Apr 2019 15:41:43 -0400 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga102.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 24 Apr 2019 12:41:40 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.60,390,1549958400"; d="scan'208";a="340454892" Received: from romley-ivt3.sc.intel.com ([172.25.110.60]) by fmsmga005.fm.intel.com with ESMTP; 24 Apr 2019 12:41:40 -0700 From: Fenghua Yu To: "Thomas Gleixner" , "Ingo Molnar" , "Borislav Petkov" , "H Peter Anvin" , "Paolo Bonzini" , "Dave Hansen" , "Ashok Raj" , "Peter Zijlstra" , "Ravi V Shankar" , "Xiaoyao Li " , "Christopherson Sean J" , "Kalle Valo" , "Michael Chan" Cc: "linux-kernel" , "x86" , kvm@vger.kernel.org, netdev@vger.kernel.org, linux-wireless@vger.kernel.org, Fenghua Yu Subject: [PATCH v8 09/15] x86/split_lock: Define MSR TEST_CTL register Date: Wed, 24 Apr 2019 12:32:56 -0700 Message-Id: <1556134382-58814-10-git-send-email-fenghua.yu@intel.com> X-Mailer: git-send-email 2.5.0 In-Reply-To: <1556134382-58814-1-git-send-email-fenghua.yu@intel.com> References: <1556134382-58814-1-git-send-email-fenghua.yu@intel.com> Sender: linux-wireless-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-wireless@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Setting bit 29 in MSR TEST_CTL (0x33) enables split lock detection and clearing the bit disables split lock detection. Define the MSR and the bit. The definitions will be used in enabling or disabling split lock detection. Signed-off-by: Fenghua Yu --- arch/x86/include/asm/msr-index.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index f65ef6f783d2..296eeb761ab6 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -39,6 +39,10 @@ /* Intel MSRs. Some also available on other CPUs */ +#define MSR_TEST_CTL 0x00000033 +#define TEST_CTL_SPLIT_LOCK_DETECT_SHIFT 29 +#define TEST_CTL_SPLIT_LOCK_DETECT BIT(29) + #define MSR_IA32_SPEC_CTRL 0x00000048 /* Speculation Control */ #define SPEC_CTRL_IBRS (1 << 0) /* Indirect Branch Restricted Speculation */ #define SPEC_CTRL_STIBP_SHIFT 1 /* Single Thread Indirect Branch Predictor (STIBP) bit */ From patchwork Wed Apr 24 19:32:57 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fenghua Yu X-Patchwork-Id: 10915625 X-Patchwork-Delegate: johannes@sipsolutions.net Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 8A8F0922 for ; Wed, 24 Apr 2019 19:43:22 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 7995F28B24 for ; Wed, 24 Apr 2019 19:43:22 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 6B61228B8E; Wed, 24 Apr 2019 19:43:22 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id DD43C28B24 for ; Wed, 24 Apr 2019 19:43:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2390101AbfDXTm5 (ORCPT ); Wed, 24 Apr 2019 15:42:57 -0400 Received: from mga09.intel.com ([134.134.136.24]:15196 "EHLO mga09.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729833AbfDXTln (ORCPT ); Wed, 24 Apr 2019 15:41:43 -0400 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga102.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 24 Apr 2019 12:41:40 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.60,390,1549958400"; d="scan'208";a="340454895" Received: from romley-ivt3.sc.intel.com ([172.25.110.60]) by fmsmga005.fm.intel.com with ESMTP; 24 Apr 2019 12:41:40 -0700 From: Fenghua Yu To: "Thomas Gleixner" , "Ingo Molnar" , "Borislav Petkov" , "H Peter Anvin" , "Paolo Bonzini" , "Dave Hansen" , "Ashok Raj" , "Peter Zijlstra" , "Ravi V Shankar" , "Xiaoyao Li " , "Christopherson Sean J" , "Kalle Valo" , "Michael Chan" Cc: "linux-kernel" , "x86" , kvm@vger.kernel.org, netdev@vger.kernel.org, linux-wireless@vger.kernel.org, Fenghua Yu Subject: [PATCH v8 10/15] x86/split_lock: Handle #AC exception for split lock Date: Wed, 24 Apr 2019 12:32:57 -0700 Message-Id: <1556134382-58814-11-git-send-email-fenghua.yu@intel.com> X-Mailer: git-send-email 2.5.0 In-Reply-To: <1556134382-58814-1-git-send-email-fenghua.yu@intel.com> References: <1556134382-58814-1-git-send-email-fenghua.yu@intel.com> Sender: linux-wireless-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-wireless@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP There may be different considerations on how to handle #AC for split lock, e.g. how to handle system hang caused by split lock issue in firmware, how to emulate faulting instruction, etc. We use a simple method to handle user and kernel split lock and may extend the method in the future. When #AC exception for split lock is triggered from user process, the process is killed by SIGBUS. To execute the process properly, a user application developer needs to fix the split lock issue. When #AC exception for split lock is triggered from a kernel instruction, disable split lock detection on local CPU and warn the split lock issue. After the exception, the faulting instruction will be executed and kernel execution continues. Split lock detection is only disabled on the local CPU, not globally. It will be re-enabled if the CPU is offline and then online or through sysfs interface. A kernel/driver developer should check the warning, which contains helpful faulting address, context, and callstack info, and fix the split lock issues. Then further split lock issues may be captured and fixed. After bit 29 in MSR_TEST_CTL is set to 1 in kernel, firmware inherits the setting when firmware is executed in S4, S5, run time services, SMI, etc. If there is a split lock operation in firmware, it will triggers #AC and may hang the system depending on how firmware handles the #AC. It's up to a firmware developer to fix split lock issues in firmware. MSR TEST_CTL value is cached in per CPU msr_test_ctl_cache which will be used in virtualization to avoid costly MSR read. Signed-off-by: Fenghua Yu --- arch/x86/include/asm/cpu.h | 3 +++ arch/x86/kernel/cpu/intel.c | 24 ++++++++++++++++++++++++ arch/x86/kernel/traps.c | 31 ++++++++++++++++++++++++++++++- 3 files changed, 57 insertions(+), 1 deletion(-) diff --git a/arch/x86/include/asm/cpu.h b/arch/x86/include/asm/cpu.h index 4e03f53fc079..5706461eb60f 100644 --- a/arch/x86/include/asm/cpu.h +++ b/arch/x86/include/asm/cpu.h @@ -42,7 +42,10 @@ unsigned int x86_model(unsigned int sig); unsigned int x86_stepping(unsigned int sig); #ifdef CONFIG_CPU_SUP_INTEL void __init cpu_set_core_cap_bits(struct cpuinfo_x86 *c); +DECLARE_PER_CPU(u64, msr_test_ctl_cache); +void handle_split_lock_kernel_mode(void); #else static inline void __init cpu_set_core_cap_bits(struct cpuinfo_x86 *c) {} +static inline void handle_split_lock_kernel_mode(void) {} #endif #endif /* _ASM_X86_CPU_H */ diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c index d7e676c2aebf..2cc69217ca7c 100644 --- a/arch/x86/kernel/cpu/intel.c +++ b/arch/x86/kernel/cpu/intel.c @@ -31,6 +31,9 @@ #include #endif +DEFINE_PER_CPU(u64, msr_test_ctl_cache); +EXPORT_PER_CPU_SYMBOL_GPL(msr_test_ctl_cache); + /* * Just in case our CPU detection goes bad, or you have a weird system, * allow a way to override the automatic disabling of MPX. @@ -654,6 +657,17 @@ static void init_intel_misc_features(struct cpuinfo_x86 *c) wrmsrl(MSR_MISC_FEATURES_ENABLES, msr); } +static void init_split_lock_detect(struct cpuinfo_x86 *c) +{ + if (cpu_has(c, X86_FEATURE_SPLIT_LOCK_DETECT)) { + u64 test_ctl_val; + + /* Cache MSR TEST_CTL */ + rdmsrl(MSR_TEST_CTL, test_ctl_val); + this_cpu_write(msr_test_ctl_cache, test_ctl_val); + } +} + static void init_intel(struct cpuinfo_x86 *c) { early_init_intel(c); @@ -766,6 +780,8 @@ static void init_intel(struct cpuinfo_x86 *c) init_intel_energy_perf(c); init_intel_misc_features(c); + + init_split_lock_detect(c); } #ifdef CONFIG_X86_32 @@ -1060,3 +1076,11 @@ void __init cpu_set_core_cap_bits(struct cpuinfo_x86 *c) if (ia32_core_cap & CORE_CAP_SPLIT_LOCK_DETECT) set_split_lock_detect(); } + +void handle_split_lock_kernel_mode(void) +{ + /* Warn and disable split lock detection on this CPU */ + msr_clear_bit(MSR_TEST_CTL, TEST_CTL_SPLIT_LOCK_DETECT_SHIFT); + this_cpu_and(msr_test_ctl_cache, ~TEST_CTL_SPLIT_LOCK_DETECT); + WARN_ONCE(1, "split lock operation detected\n"); +} diff --git a/arch/x86/kernel/traps.c b/arch/x86/kernel/traps.c index d26f9e9c3d83..db6b18311dbc 100644 --- a/arch/x86/kernel/traps.c +++ b/arch/x86/kernel/traps.c @@ -61,6 +61,7 @@ #include #include #include +#include #ifdef CONFIG_X86_64 #include @@ -293,9 +294,37 @@ DO_ERROR(X86_TRAP_OLD_MF, SIGFPE, 0, NULL, "coprocessor segment overru DO_ERROR(X86_TRAP_TS, SIGSEGV, 0, NULL, "invalid TSS", invalid_TSS) DO_ERROR(X86_TRAP_NP, SIGBUS, 0, NULL, "segment not present", segment_not_present) DO_ERROR(X86_TRAP_SS, SIGBUS, 0, NULL, "stack segment", stack_segment) -DO_ERROR(X86_TRAP_AC, SIGBUS, BUS_ADRALN, NULL, "alignment check", alignment_check) #undef IP +dotraplinkage void do_alignment_check(struct pt_regs *regs, long error_code) +{ + unsigned int trapnr = X86_TRAP_AC; + char str[] = "alignment check"; + int signr = SIGBUS; + + RCU_LOCKDEP_WARN(!rcu_is_watching(), "entry code didn't wake RCU"); + + if (notify_die(DIE_TRAP, str, regs, error_code, trapnr, signr) == + NOTIFY_STOP) + return; + + cond_local_irq_enable(regs); + if (!user_mode(regs) && + static_cpu_has(X86_FEATURE_SPLIT_LOCK_DETECT)) { + /* + * Only split lock can generate #AC from kernel at this point. + * Warn and disable split lock detection on this CPU. The + * faulting instruction will be executed without generating + * another #AC fault. + */ + return handle_split_lock_kernel_mode(); + } + + /* Handle #AC generated in any other cases. */ + do_trap(X86_TRAP_AC, SIGBUS, "alignment check", regs, + error_code, BUS_ADRALN, NULL); +} + #ifdef CONFIG_VMAP_STACK __visible void __noreturn handle_stack_overflow(const char *message, struct pt_regs *regs, From patchwork Wed Apr 24 19:32:58 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fenghua Yu X-Patchwork-Id: 10915601 X-Patchwork-Delegate: johannes@sipsolutions.net Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 302B21390 for ; Wed, 24 Apr 2019 19:42:33 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 1BA322022C for ; Wed, 24 Apr 2019 19:42:33 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 0FE4F28A71; Wed, 24 Apr 2019 19:42:33 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 89AE12899D for ; Wed, 24 Apr 2019 19:42:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2389969AbfDXTmW (ORCPT ); Wed, 24 Apr 2019 15:42:22 -0400 Received: from mga09.intel.com ([134.134.136.24]:15194 "EHLO mga09.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730042AbfDXTlo (ORCPT ); Wed, 24 Apr 2019 15:41:44 -0400 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga102.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 24 Apr 2019 12:41:41 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.60,390,1549958400"; d="scan'208";a="340454898" Received: from romley-ivt3.sc.intel.com ([172.25.110.60]) by fmsmga005.fm.intel.com with ESMTP; 24 Apr 2019 12:41:40 -0700 From: Fenghua Yu To: "Thomas Gleixner" , "Ingo Molnar" , "Borislav Petkov" , "H Peter Anvin" , "Paolo Bonzini" , "Dave Hansen" , "Ashok Raj" , "Peter Zijlstra" , "Ravi V Shankar" , "Xiaoyao Li " , "Christopherson Sean J" , "Kalle Valo" , "Michael Chan" Cc: "linux-kernel" , "x86" , kvm@vger.kernel.org, netdev@vger.kernel.org, linux-wireless@vger.kernel.org, Xiaoyao Li , Fenghua Yu Subject: [PATCH v8 11/15] kvm/x86: Emulate MSR IA32_CORE_CAPABILITY Date: Wed, 24 Apr 2019 12:32:58 -0700 Message-Id: <1556134382-58814-12-git-send-email-fenghua.yu@intel.com> X-Mailer: git-send-email 2.5.0 In-Reply-To: <1556134382-58814-1-git-send-email-fenghua.yu@intel.com> References: <1556134382-58814-1-git-send-email-fenghua.yu@intel.com> Sender: linux-wireless-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-wireless@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Xiaoyao Li MSR IA32_CORE_CAPABILITY is a feature-enumerating MSR, bit 5 of which reports the capability of enabling detection of split locks (will be supported on future processors based on Tremont microarchitecture and later). CPUID.(EAX=7H,ECX=0):EDX[30] enumerates the presence of the IA32_CORE_CAPABILITY MSR. Please check the latest Intel 64 and IA-32 Architectures Software Developer's Manual for more detailed information on the MSR and the split lock bit. Since MSR_IA32_CORE_CAPABILITY is a feature-enumerating MSR that plays the similar role as CPUID, it can be emulated in software regardless of host's capability. What we need to do is to set the right value of it to report the capability of guest. In this patch, just set the guest's core_capability as 0, because we haven't added support of the features it indicates to guest. It's for bisectability. Signed-off-by: Xiaoyao Li Signed-off-by: Fenghua Yu --- Changes in v7: - make kvm_get_core_capability() static since it's only used in this file. arch/x86/include/asm/kvm_host.h | 1 + arch/x86/kvm/cpuid.c | 6 ++++++ arch/x86/kvm/x86.c | 22 ++++++++++++++++++++++ 3 files changed, 29 insertions(+) diff --git a/arch/x86/include/asm/kvm_host.h b/arch/x86/include/asm/kvm_host.h index a9d03af34030..d4f9b13fcdd6 100644 --- a/arch/x86/include/asm/kvm_host.h +++ b/arch/x86/include/asm/kvm_host.h @@ -570,6 +570,7 @@ struct kvm_vcpu_arch { u64 ia32_xss; u64 microcode_version; u64 arch_capabilities; + u64 core_capability; /* * Paging state of the vcpu diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c index fd3951638ae4..4a2f7892ea31 100644 --- a/arch/x86/kvm/cpuid.c +++ b/arch/x86/kvm/cpuid.c @@ -505,6 +505,12 @@ static inline int __do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function, * if the host doesn't support it. */ entry->edx |= F(ARCH_CAPABILITIES); + /* + * Since we emulate MSR IA32_CORE_CAPABILITY in + * software, we can always enable it for guest + * regardless of host's capability. + */ + entry->edx |= F(CORE_CAPABILITY); } else { entry->ebx = 0; entry->ecx = 0; diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index a0d1fc80ac5a..e88be97d47b9 100644 --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -1161,6 +1161,7 @@ static u32 emulated_msrs[] = { MSR_IA32_TSC_ADJUST, MSR_IA32_TSCDEADLINE, MSR_IA32_ARCH_CAPABILITIES, + MSR_IA32_CORE_CAPABILITY, MSR_IA32_MISC_ENABLE, MSR_IA32_MCG_STATUS, MSR_IA32_MCG_CTL, @@ -1200,6 +1201,7 @@ static u32 msr_based_features[] = { MSR_F10H_DECFG, MSR_IA32_UCODE_REV, + MSR_IA32_CORE_CAPABILITY, MSR_IA32_ARCH_CAPABILITIES, }; @@ -1227,9 +1229,17 @@ u64 kvm_get_arch_capabilities(void) } EXPORT_SYMBOL_GPL(kvm_get_arch_capabilities); +static u64 kvm_get_core_capability(void) +{ + return 0; +} + static int kvm_get_msr_feature(struct kvm_msr_entry *msr) { switch (msr->index) { + case MSR_IA32_CORE_CAPABILITY: + msr->data = kvm_get_core_capability(); + break; case MSR_IA32_ARCH_CAPABILITIES: msr->data = kvm_get_arch_capabilities(); break; @@ -2453,6 +2463,11 @@ int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info) break; case MSR_EFER: return set_efer(vcpu, data); + case MSR_IA32_CORE_CAPABILITY: + if (!msr_info->host_initiated) + return 1; + vcpu->arch.core_capability = data; + break; case MSR_K7_HWCR: data &= ~(u64)0x40; /* ignore flush filter disable */ data &= ~(u64)0x100; /* ignore ignne emulation enable */ @@ -2764,6 +2779,12 @@ int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info) case MSR_IA32_TSC: msr_info->data = kvm_scale_tsc(vcpu, rdtsc()) + vcpu->arch.tsc_offset; break; + case MSR_IA32_CORE_CAPABILITY: + if (!msr_info->host_initiated && + !guest_cpuid_has(vcpu, X86_FEATURE_CORE_CAPABILITY)) + return 1; + msr_info->data = vcpu->arch.core_capability; + break; case MSR_MTRRcap: case 0x200 ... 0x2ff: return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data); @@ -8760,6 +8781,7 @@ struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm, int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu) { vcpu->arch.arch_capabilities = kvm_get_arch_capabilities(); + vcpu->arch.core_capability = kvm_get_core_capability(); vcpu->arch.msr_platform_info = MSR_PLATFORM_INFO_CPUID_FAULT; kvm_vcpu_mtrr_init(vcpu); vcpu_load(vcpu); From patchwork Wed Apr 24 19:32:59 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fenghua Yu X-Patchwork-Id: 10915607 X-Patchwork-Delegate: johannes@sipsolutions.net Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 332F5922 for ; Wed, 24 Apr 2019 19:42:38 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 20F672022C for ; Wed, 24 Apr 2019 19:42:38 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 1324128A29; Wed, 24 Apr 2019 19:42:38 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 95AD22022C for ; Wed, 24 Apr 2019 19:42:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2389931AbfDXTmW (ORCPT ); Wed, 24 Apr 2019 15:42:22 -0400 Received: from mga09.intel.com ([134.134.136.24]:15196 "EHLO mga09.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730021AbfDXTlo (ORCPT ); Wed, 24 Apr 2019 15:41:44 -0400 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga102.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 24 Apr 2019 12:41:41 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.60,390,1549958400"; d="scan'208";a="340454902" Received: from romley-ivt3.sc.intel.com ([172.25.110.60]) by fmsmga005.fm.intel.com with ESMTP; 24 Apr 2019 12:41:41 -0700 From: Fenghua Yu To: "Thomas Gleixner" , "Ingo Molnar" , "Borislav Petkov" , "H Peter Anvin" , "Paolo Bonzini" , "Dave Hansen" , "Ashok Raj" , "Peter Zijlstra" , "Ravi V Shankar" , "Xiaoyao Li " , "Christopherson Sean J" , "Kalle Valo" , "Michael Chan" Cc: "linux-kernel" , "x86" , kvm@vger.kernel.org, netdev@vger.kernel.org, linux-wireless@vger.kernel.org, Xiaoyao Li , Fenghua Yu Subject: [PATCH v8 12/15] kvm/vmx: Emulate MSR TEST_CTL Date: Wed, 24 Apr 2019 12:32:59 -0700 Message-Id: <1556134382-58814-13-git-send-email-fenghua.yu@intel.com> X-Mailer: git-send-email 2.5.0 In-Reply-To: <1556134382-58814-1-git-send-email-fenghua.yu@intel.com> References: <1556134382-58814-1-git-send-email-fenghua.yu@intel.com> Sender: linux-wireless-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-wireless@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Xiaoyao Li A control bit (bit 29) in TEST_CTL MSR 0x33 will be introduced in future x86 processors. When bit 29 is set, the processor causes #AC exception for split locked accesses at all CPL. Please check the latest Intel 64 and IA-32 Architectures Software Developer's Manual for more detailed information on the MSR and the split lock bit. This patch emulates MSR_TEST_CTL with vmx->msr_test_ctl and does the following: 1. As MSR TEST_CTL of guest is emulated, enable the related bit in CORE_CAPABILITY to correctly report this feature to guest. 2. Differentiate MSR_TEST_CTL between host and guest. To avoid costly RDMSR of TEST_CTL when switching between host and guest during vmentry, read per CPU variable msr_test_ctl_cache which caches the MSR value. Signed-off-by: Xiaoyao Li Signed-off-by: Fenghua Yu --- Changes in v7: - Add vmx->msr_test_ctl_mask to indicate the valid bits of guest's MSR_TEST_CTL. - Add X86_FEATURE_SPLIT_LOCK_DETECT check to determine if it needs switch MSR_TEST_CTL. - Use msr_test_ctl_cache to replace costly RDMSR. - minimal adjustment in kvm_get_core_capability(), making it more clear. arch/x86/kvm/vmx/vmx.c | 42 ++++++++++++++++++++++++++++++++++++++++++ arch/x86/kvm/vmx/vmx.h | 2 ++ arch/x86/kvm/x86.c | 19 ++++++++++++++++++- 3 files changed, 62 insertions(+), 1 deletion(-) diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c index b4e7d645275a..bbb9859350b5 100644 --- a/arch/x86/kvm/vmx/vmx.c +++ b/arch/x86/kvm/vmx/vmx.c @@ -1663,6 +1663,11 @@ static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info) u32 index; switch (msr_info->index) { + case MSR_TEST_CTL: + if (!vmx->msr_test_ctl_mask) + return 1; + msr_info->data = vmx->msr_test_ctl; + break; #ifdef CONFIG_X86_64 case MSR_FS_BASE: msr_info->data = vmcs_readl(GUEST_FS_BASE); @@ -1797,6 +1802,12 @@ static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info) u32 index; switch (msr_index) { + case MSR_TEST_CTL: + if (!vmx->msr_test_ctl_mask || + (data & vmx->msr_test_ctl_mask) != data) + return 1; + vmx->msr_test_ctl = data; + break; case MSR_EFER: ret = kvm_set_msr_common(vcpu, msr_info); break; @@ -4106,6 +4117,16 @@ static void vmx_vcpu_setup(struct vcpu_vmx *vmx) } } +static u64 vmx_get_msr_test_ctl_mask(struct kvm_vcpu *vcpu) +{ + u64 mask = 0; + + if (vcpu->arch.core_capability & CORE_CAP_SPLIT_LOCK_DETECT) + mask |= TEST_CTL_SPLIT_LOCK_DETECT; + + return mask; +} + static void vmx_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event) { struct vcpu_vmx *vmx = to_vmx(vcpu); @@ -4114,6 +4135,8 @@ static void vmx_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event) vmx->rmode.vm86_active = 0; vmx->spec_ctrl = 0; + vmx->msr_test_ctl = 0; + vmx->msr_test_ctl_mask = vmx_get_msr_test_ctl_mask(vcpu); vcpu->arch.microcode_version = 0x100000000ULL; vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val(); @@ -6313,6 +6336,23 @@ static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx) msrs[i].host, false); } +static void atomic_switch_msr_test_ctl(struct vcpu_vmx *vmx) +{ + u64 host_msr_test_ctl; + + if (!boot_cpu_has(X86_FEATURE_SPLIT_LOCK_DETECT)) + return; + + host_msr_test_ctl = this_cpu_read(msr_test_ctl_cache); + + if (host_msr_test_ctl == vmx->msr_test_ctl) { + clear_atomic_switch_msr(vmx, MSR_TEST_CTL); + } else { + add_atomic_switch_msr(vmx, MSR_TEST_CTL, vmx->msr_test_ctl, + host_msr_test_ctl, false); + } +} + static void vmx_arm_hv_timer(struct vcpu_vmx *vmx, u32 val) { vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, val); @@ -6421,6 +6461,8 @@ static void vmx_vcpu_run(struct kvm_vcpu *vcpu) atomic_switch_perf_msrs(vmx); + atomic_switch_msr_test_ctl(vmx); + vmx_update_hv_timer(vcpu); /* diff --git a/arch/x86/kvm/vmx/vmx.h b/arch/x86/kvm/vmx/vmx.h index f879529906b4..8690a1295548 100644 --- a/arch/x86/kvm/vmx/vmx.h +++ b/arch/x86/kvm/vmx/vmx.h @@ -190,6 +190,8 @@ struct vcpu_vmx { u64 msr_guest_kernel_gs_base; #endif + u64 msr_test_ctl; + u64 msr_test_ctl_mask; u64 spec_ctrl; u32 vm_entry_controls_shadow; diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index e88be97d47b9..60aaf75d0fe5 100644 --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -1231,7 +1231,24 @@ EXPORT_SYMBOL_GPL(kvm_get_arch_capabilities); static u64 kvm_get_core_capability(void) { - return 0; + u64 data = 0; + + if (boot_cpu_has(X86_FEATURE_CORE_CAPABILITY)) { + rdmsrl(MSR_IA32_CORE_CAPABILITY, data); + + /* mask non-virtualizable functions */ + data &= CORE_CAP_SPLIT_LOCK_DETECT; + } else if (boot_cpu_has(X86_FEATURE_SPLIT_LOCK_DETECT)) { + /* + * There will be a list of FMS values that have split lock + * detection but lack the CORE CAPABILITY MSR. In this case, + * set CORE_CAP_SPLIT_LOCK_DETECT since we emulate + * MSR CORE_CAPABILITY. + */ + data |= CORE_CAP_SPLIT_LOCK_DETECT; + } + + return data; } static int kvm_get_msr_feature(struct kvm_msr_entry *msr) From patchwork Wed Apr 24 19:33:00 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fenghua Yu X-Patchwork-Id: 10915599 X-Patchwork-Delegate: johannes@sipsolutions.net Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 0F6881708 for ; Wed, 24 Apr 2019 19:42:19 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 00FE22022C for ; Wed, 24 Apr 2019 19:42:19 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id E8EC528A72; Wed, 24 Apr 2019 19:42:18 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 955E828980 for ; Wed, 24 Apr 2019 19:42:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2389880AbfDXTmL (ORCPT ); Wed, 24 Apr 2019 15:42:11 -0400 Received: from mga09.intel.com ([134.134.136.24]:15202 "EHLO mga09.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2389390AbfDXTlo (ORCPT ); Wed, 24 Apr 2019 15:41:44 -0400 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga102.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 24 Apr 2019 12:41:41 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.60,390,1549958400"; d="scan'208";a="340454905" Received: from romley-ivt3.sc.intel.com ([172.25.110.60]) by fmsmga005.fm.intel.com with ESMTP; 24 Apr 2019 12:41:41 -0700 From: Fenghua Yu To: "Thomas Gleixner" , "Ingo Molnar" , "Borislav Petkov" , "H Peter Anvin" , "Paolo Bonzini" , "Dave Hansen" , "Ashok Raj" , "Peter Zijlstra" , "Ravi V Shankar" , "Xiaoyao Li " , "Christopherson Sean J" , "Kalle Valo" , "Michael Chan" Cc: "linux-kernel" , "x86" , kvm@vger.kernel.org, netdev@vger.kernel.org, linux-wireless@vger.kernel.org, Fenghua Yu Subject: [PATCH v8 13/15] x86/split_lock: Enable split lock detection by default Date: Wed, 24 Apr 2019 12:33:00 -0700 Message-Id: <1556134382-58814-14-git-send-email-fenghua.yu@intel.com> X-Mailer: git-send-email 2.5.0 In-Reply-To: <1556134382-58814-1-git-send-email-fenghua.yu@intel.com> References: <1556134382-58814-1-git-send-email-fenghua.yu@intel.com> Sender: linux-wireless-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-wireless@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP A split locked access locks bus and degrades overall memory access performance. When split lock detection feature is enumerated, enable the feature by default by writing 1 to bit 29 in MSR TEST_CTL to find any split lock issue. Signed-off-by: Fenghua Yu --- arch/x86/kernel/cpu/intel.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c index 2cc69217ca7c..28cc6891ba48 100644 --- a/arch/x86/kernel/cpu/intel.c +++ b/arch/x86/kernel/cpu/intel.c @@ -657,6 +657,13 @@ static void init_intel_misc_features(struct cpuinfo_x86 *c) wrmsrl(MSR_MISC_FEATURES_ENABLES, msr); } +static void split_lock_update_msr(void) +{ + /* Enable split lock detection */ + msr_set_bit(MSR_TEST_CTL, TEST_CTL_SPLIT_LOCK_DETECT_SHIFT); + this_cpu_or(msr_test_ctl_cache, TEST_CTL_SPLIT_LOCK_DETECT); +} + static void init_split_lock_detect(struct cpuinfo_x86 *c) { if (cpu_has(c, X86_FEATURE_SPLIT_LOCK_DETECT)) { @@ -665,6 +672,8 @@ static void init_split_lock_detect(struct cpuinfo_x86 *c) /* Cache MSR TEST_CTL */ rdmsrl(MSR_TEST_CTL, test_ctl_val); this_cpu_write(msr_test_ctl_cache, test_ctl_val); + + split_lock_update_msr(); } } @@ -1045,9 +1054,13 @@ static const struct cpu_dev intel_cpu_dev = { cpu_dev_register(intel_cpu_dev); +#undef pr_fmt +#define pr_fmt(fmt) "x86/split lock detection: " fmt + static void __init set_split_lock_detect(void) { setup_force_cpu_cap(X86_FEATURE_SPLIT_LOCK_DETECT); + pr_info("enabled\n"); } void __init cpu_set_core_cap_bits(struct cpuinfo_x86 *c) From patchwork Wed Apr 24 19:33:01 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fenghua Yu X-Patchwork-Id: 10915611 X-Patchwork-Delegate: johannes@sipsolutions.net Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 36B741708 for ; Wed, 24 Apr 2019 19:42:42 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 280C728A29 for ; Wed, 24 Apr 2019 19:42:42 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 1B46228A71; Wed, 24 Apr 2019 19:42:42 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id B7EF728A72 for ; Wed, 24 Apr 2019 19:42:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730041AbfDXTlo (ORCPT ); Wed, 24 Apr 2019 15:41:44 -0400 Received: from mga18.intel.com ([134.134.136.126]:44995 "EHLO mga18.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729378AbfDXTln (ORCPT ); Wed, 24 Apr 2019 15:41:43 -0400 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga106.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 24 Apr 2019 12:41:41 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.60,390,1549958400"; d="scan'208";a="340454908" Received: from romley-ivt3.sc.intel.com ([172.25.110.60]) by fmsmga005.fm.intel.com with ESMTP; 24 Apr 2019 12:41:41 -0700 From: Fenghua Yu To: "Thomas Gleixner" , "Ingo Molnar" , "Borislav Petkov" , "H Peter Anvin" , "Paolo Bonzini" , "Dave Hansen" , "Ashok Raj" , "Peter Zijlstra" , "Ravi V Shankar" , "Xiaoyao Li " , "Christopherson Sean J" , "Kalle Valo" , "Michael Chan" Cc: "linux-kernel" , "x86" , kvm@vger.kernel.org, netdev@vger.kernel.org, linux-wireless@vger.kernel.org, Fenghua Yu Subject: [PATCH v8 14/15] x86/split_lock: Disable split lock detection by kernel parameter "nosplit_lock_detect" Date: Wed, 24 Apr 2019 12:33:01 -0700 Message-Id: <1556134382-58814-15-git-send-email-fenghua.yu@intel.com> X-Mailer: git-send-email 2.5.0 In-Reply-To: <1556134382-58814-1-git-send-email-fenghua.yu@intel.com> References: <1556134382-58814-1-git-send-email-fenghua.yu@intel.com> Sender: linux-wireless-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-wireless@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP To work around or debug split lock issues, the kernel parameter "nosplit_lock_detect" is introduced to disable the feature during boot time. Signed-off-by: Fenghua Yu --- .../admin-guide/kernel-parameters.txt | 2 ++ arch/x86/kernel/cpu/intel.c | 25 ++++++++++++++++--- 2 files changed, 23 insertions(+), 4 deletions(-) diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt index 2b8ee90bb644..623a5f223ff1 100644 --- a/Documentation/admin-guide/kernel-parameters.txt +++ b/Documentation/admin-guide/kernel-parameters.txt @@ -3019,6 +3019,8 @@ nosoftlockup [KNL] Disable the soft-lockup detector. + nosplit_lock_detect [X86] Disable split lock detection + nosync [HW,M68K] Disables sync negotiation for all devices. nowatchdog [KNL] Disable both lockup detectors, i.e. diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c index 28cc6891ba48..959ebf25beda 100644 --- a/arch/x86/kernel/cpu/intel.c +++ b/arch/x86/kernel/cpu/intel.c @@ -19,6 +19,7 @@ #include #include #include +#include #ifdef CONFIG_X86_64 #include @@ -34,6 +35,8 @@ DEFINE_PER_CPU(u64, msr_test_ctl_cache); EXPORT_PER_CPU_SYMBOL_GPL(msr_test_ctl_cache); +static bool split_lock_detect_enable; + /* * Just in case our CPU detection goes bad, or you have a weird system, * allow a way to override the automatic disabling of MPX. @@ -659,9 +662,15 @@ static void init_intel_misc_features(struct cpuinfo_x86 *c) static void split_lock_update_msr(void) { - /* Enable split lock detection */ - msr_set_bit(MSR_TEST_CTL, TEST_CTL_SPLIT_LOCK_DETECT_SHIFT); - this_cpu_or(msr_test_ctl_cache, TEST_CTL_SPLIT_LOCK_DETECT); + if (split_lock_detect_enable) { + /* Enable split lock detection */ + msr_set_bit(MSR_TEST_CTL, TEST_CTL_SPLIT_LOCK_DETECT_SHIFT); + this_cpu_or(msr_test_ctl_cache, TEST_CTL_SPLIT_LOCK_DETECT); + } else { + /* Disable split lock detection */ + msr_clear_bit(MSR_TEST_CTL, TEST_CTL_SPLIT_LOCK_DETECT_SHIFT); + this_cpu_and(msr_test_ctl_cache, ~TEST_CTL_SPLIT_LOCK_DETECT); + } } static void init_split_lock_detect(struct cpuinfo_x86 *c) @@ -1060,7 +1069,15 @@ cpu_dev_register(intel_cpu_dev); static void __init set_split_lock_detect(void) { setup_force_cpu_cap(X86_FEATURE_SPLIT_LOCK_DETECT); - pr_info("enabled\n"); + + if (cmdline_find_option_bool(boot_command_line, + "nosplit_lock_detect")) { + split_lock_detect_enable = false; + pr_info("disabled\n"); + } else { + split_lock_detect_enable = true; + pr_info("enabled\n"); + } } void __init cpu_set_core_cap_bits(struct cpuinfo_x86 *c) From patchwork Wed Apr 24 19:33:02 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fenghua Yu X-Patchwork-Id: 10915589 X-Patchwork-Delegate: johannes@sipsolutions.net Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 6487C922 for ; Wed, 24 Apr 2019 19:42:02 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 53AEE28C47 for ; Wed, 24 Apr 2019 19:42:02 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 476C828C4D; Wed, 24 Apr 2019 19:42:02 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id A53F728B94 for ; Wed, 24 Apr 2019 19:42:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2389734AbfDXTlp (ORCPT ); Wed, 24 Apr 2019 15:41:45 -0400 Received: from mga18.intel.com ([134.134.136.126]:44995 "EHLO mga18.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729820AbfDXTln (ORCPT ); Wed, 24 Apr 2019 15:41:43 -0400 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga106.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 24 Apr 2019 12:41:41 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.60,390,1549958400"; d="scan'208";a="340454911" Received: from romley-ivt3.sc.intel.com ([172.25.110.60]) by fmsmga005.fm.intel.com with ESMTP; 24 Apr 2019 12:41:41 -0700 From: Fenghua Yu To: "Thomas Gleixner" , "Ingo Molnar" , "Borislav Petkov" , "H Peter Anvin" , "Paolo Bonzini" , "Dave Hansen" , "Ashok Raj" , "Peter Zijlstra" , "Ravi V Shankar" , "Xiaoyao Li " , "Christopherson Sean J" , "Kalle Valo" , "Michael Chan" Cc: "linux-kernel" , "x86" , kvm@vger.kernel.org, netdev@vger.kernel.org, linux-wireless@vger.kernel.org, Fenghua Yu Subject: [PATCH v8 15/15] x86/split_lock: Add a sysfs interface to enable/disable split lock detection during run time Date: Wed, 24 Apr 2019 12:33:02 -0700 Message-Id: <1556134382-58814-16-git-send-email-fenghua.yu@intel.com> X-Mailer: git-send-email 2.5.0 In-Reply-To: <1556134382-58814-1-git-send-email-fenghua.yu@intel.com> References: <1556134382-58814-1-git-send-email-fenghua.yu@intel.com> Sender: linux-wireless-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-wireless@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP To workaround or debug a split lock issue, the administrator may need to disable or enable split lock detection during run time without rebooting the system. The interface /sys/device/system/cpu/split_lock_detect is added to allow the administrator to disable or enable split lock detection and show current split lock detection setting. Writing [yY1] or [oO][nN] to the file enables split lock detection and writing [nN0] or [oO][fF] disables split lock detection. Split lock detection is enabled or disabled on all CPUs. Reading the file returns current global split lock detection setting: 0: disabled 1: enabled Add an ABI document entry for /sys/devices/system/cpu/split_lock_detect. Signed-off-by: Fenghua Yu --- Not sure if the justification for the sysfs knob is valid. If not, this patch could be removed from this patch set. .../ABI/testing/sysfs-devices-system-cpu | 22 ++++++++ arch/x86/kernel/cpu/intel.c | 52 ++++++++++++++++++- 2 files changed, 72 insertions(+), 2 deletions(-) diff --git a/Documentation/ABI/testing/sysfs-devices-system-cpu b/Documentation/ABI/testing/sysfs-devices-system-cpu index 9605dbd4b5b5..aad7b1698065 100644 --- a/Documentation/ABI/testing/sysfs-devices-system-cpu +++ b/Documentation/ABI/testing/sysfs-devices-system-cpu @@ -67,6 +67,28 @@ Description: Discover NUMA node a CPU belongs to /sys/devices/system/cpu/cpu42/node2 -> ../../node/node2 +What: /sys/devices/system/cpu/split_lock_detect +Date: March 2019 +Contact: Linux kernel mailing list +Description: (RW) Control split lock detection on Intel Tremont and + future CPUs + + Reads return split lock detection status: + 0: disabled + 1: enabled + + Writes enable or disable split lock detection: + The first character is one of 'Nn0' or [oO][fF] for off + disables the feature. + The first character is one of 'Yy1' or [oO][nN] for on + enables the feature. + + Please note the interface only shows or controls global setting. + During run time, split lock detection on one CPU may be + disabled if split lock operation in kernel code happens on + the CPU. The interface doesn't show or control split lock + detection on individual CPU. + What: /sys/devices/system/cpu/cpu#/topology/core_id /sys/devices/system/cpu/cpu#/topology/core_siblings /sys/devices/system/cpu/cpu#/topology/core_siblings_list diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c index 959ebf25beda..f257d1e92706 100644 --- a/arch/x86/kernel/cpu/intel.c +++ b/arch/x86/kernel/cpu/intel.c @@ -35,6 +35,7 @@ DEFINE_PER_CPU(u64, msr_test_ctl_cache); EXPORT_PER_CPU_SYMBOL_GPL(msr_test_ctl_cache); +static DEFINE_MUTEX(split_lock_detect_mutex); static bool split_lock_detect_enable; /* @@ -660,7 +661,7 @@ static void init_intel_misc_features(struct cpuinfo_x86 *c) wrmsrl(MSR_MISC_FEATURES_ENABLES, msr); } -static void split_lock_update_msr(void) +static void split_lock_update_msr(void *__unused) { if (split_lock_detect_enable) { /* Enable split lock detection */ @@ -682,7 +683,7 @@ static void init_split_lock_detect(struct cpuinfo_x86 *c) rdmsrl(MSR_TEST_CTL, test_ctl_val); this_cpu_write(msr_test_ctl_cache, test_ctl_val); - split_lock_update_msr(); + split_lock_update_msr(NULL); } } @@ -1114,3 +1115,50 @@ void handle_split_lock_kernel_mode(void) this_cpu_and(msr_test_ctl_cache, ~TEST_CTL_SPLIT_LOCK_DETECT); WARN_ONCE(1, "split lock operation detected\n"); } + +static ssize_t +split_lock_detect_show(struct device *dev, struct device_attribute *attr, + char *buf) +{ + return sprintf(buf, "%u\n", split_lock_detect_enable); +} + +static ssize_t +split_lock_detect_store(struct device *dev, struct device_attribute *attr, + const char *buf, size_t count) +{ + bool val; + int ret; + + ret = strtobool(buf, &val); + if (ret) + return ret; + + mutex_lock(&split_lock_detect_mutex); + + split_lock_detect_enable = val; + + /* Update the split lock detection setting in MSR on all online CPUs. */ + on_each_cpu(split_lock_update_msr, NULL, 1); + + if (split_lock_detect_enable) + pr_info("enabled\n"); + else + pr_info("disabled\n"); + + mutex_unlock(&split_lock_detect_mutex); + + return count; +} + +static DEVICE_ATTR_RW(split_lock_detect); + +static int __init split_lock_init(void) +{ + if (!boot_cpu_has(X86_FEATURE_SPLIT_LOCK_DETECT)) + return -ENODEV; + + return device_create_file(cpu_subsys.dev_root, + &dev_attr_split_lock_detect); +} +subsys_initcall(split_lock_init);