From patchwork Fri Aug 24 07:36:03 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hanjie Lin X-Patchwork-Id: 10575369 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id E5D921579 for ; Fri, 24 Aug 2018 14:38:07 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id D1B172B67F for ; Fri, 24 Aug 2018 14:38:07 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id C1FDD2B686; Fri, 24 Aug 2018 14:38:07 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.9 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_NONE autolearn=unavailable version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id C90E42B67F for ; Fri, 24 Aug 2018 14:38:06 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=jdOksuOZNKt6KsXyXvjsBU0Ohf+lQd2pt2kzkAf89Ak=; b=LJigM6mUCxQZug EefmR+EuUtBgAT72U2G7nMnDNg/L+o0554ZXCO1xSlNQ2uS+Gk3oZCDLTdVk247iBDQdxTKXtIy6D iYnBeOULOdD52V82i2Goc4MCm+txuGIPlZbwdkKvvs/KLeh2ZTA0ciJ4qX0Nn+0TzgrsPZ084WkTG rDQYAnpqSbe0Y54EI8XBJ0V1W+tg5GzTmFXH16cUb54yP7k26t/cM3Z4EtT8uGWDedd6IPaEI3HJI jYRmuLTcj1RDz0PnNCzgXYsoUOvLbHhAC0zQbhJFEqfFxhg7MM9wQIESvdyf54CbnVJHAPHQ94zge zGmfJ+3AAKcwGn9eZyfw==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1ftDDy-0000XW-0l; Fri, 24 Aug 2018 14:38:06 +0000 Received: from mail-sh2.amlogic.com ([58.32.228.45]) by bombadil.infradead.org with esmtps (Exim 4.90_1 #2 (Red Hat Linux)) id 1ft7Ao-0002qG-Ty; Fri, 24 Aug 2018 08:13:04 +0000 Received: from droid10.amlogic.com (10.18.11.213) by mail-sh2.amlogic.com (10.18.11.6) with Microsoft SMTP Server id 15.0.1320.4; Fri, 24 Aug 2018 15:35:39 +0800 From: Hanjie Lin To: Bjorn Helgaas Subject: [PATCH v2 1/2] dt-bindings: PCI: meson: add DT bindings for Amlogic Meson PCIe controller Date: Fri, 24 Aug 2018 15:36:03 +0800 Message-ID: <1535096165-45827-2-git-send-email-hanjie.lin@amlogic.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1535096165-45827-1-git-send-email-hanjie.lin@amlogic.com> References: <1535096165-45827-1-git-send-email-hanjie.lin@amlogic.com> MIME-Version: 1.0 X-Originating-IP: [10.18.11.213] X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Rob Herring , Hanjie Lin , Jianxin Pan , devicetree@vger.kernel.org, Kevin Hilman , Yixun Lan , linux-kernel@vger.kernel.org, Yue Wang , Liang Yang , Jian Hu , linux-pci@vger.kernel.org, Qiufang Dai , linux-amlogic@lists.infradead.org, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP From: Yue Wang The Amlogic Meson PCIe host controller is based on the Synopsys DesignWare PCI core. This patch adds documentation for the DT bindings in Meson PCIe controller. Signed-off-by: Yue Wang Signed-off-by: Hanjie Lin --- .../devicetree/bindings/pci/amlogic,meson-pcie.txt | 63 ++++++++++++++++++++++ 1 file changed, 63 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt diff --git a/Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt b/Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt new file mode 100644 index 0000000..8a831d1 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt @@ -0,0 +1,63 @@ +Amlogic Meson AXG DWC PCIE SoC controller + +Amlogic Meson PCIe host controller is based on the Synopsys DesignWare PCI core. +It shares common functions with the PCIe DesignWare core driver and +inherits common properties defined in +Documentation/devicetree/bindings/pci/designware-pci.txt. + +Additional properties are described here: + +Required properties: +- compatible: + should contain "amlogic,axg-pcie" to identify the core. +- reg: + Should contain the configuration address space. +- reg-names: Must be + - "elbi" External local bus interface registers + - "cfg" Meson specific registers + - "config" PCIe configuration space +- reset-gpios: The GPIO to generate PCIe PERST# assert and deassert signal. +- clocks: Must contain an entry for each entry in clock-names. +- clock-names: Must include the following entries: + - "pclk" PCIe GEN 100M PLL clock + - "port" PCIe_x(A or B) RC clock gate + - "general" PCIe Phy clock + - "mipi" PCIe_x(A or B) 100M ref clock gate +- resets: phandle to the reset lines. +- reset-names: must contain "phy" and "peripheral" + - "port" Port A or B reset + - "apb" APB reset + +Example configuration: + + pcie: pcie@f9800000 { + compatible = "amlogic,axg-pcie", "snps,dw-pcie"; + reg = <0x0 0xf9800000 0x0 0x400000 + 0x0 0xff646000 0x0 0x2000 + 0x0 0xf9f00000 0x0 0x100000>; + reg-names = "elbi", "cfg", "config"; + reset-gpios = <&gpio GPIOX_19 GPIO_ACTIVE_HIGH>; + interrupts = ; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 179 IRQ_TYPE_EDGE_RISING>; + bus-range = <0x0 0xff>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + phys = <&pcie_phy>; + ranges = <0x82000000 0 0 0x0 0xf9c00000 0 0x00300000>; + + clocks = <&clkc CLKID_USB + &clkc CLKID_MIPI_ENABLE + &clkc CLKID_PCIE_A + &clkc CLKID_PCIE_CML_EN0>; + clock-names = "general", + "mipi", + "pclk", + "port"; + resets = <&reset RESET_PCIE_A>, + <&reset RESET_PCIE_APB>; + reset-names = "port", + "apb"; + }; From patchwork Fri Aug 24 07:33:26 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hanjie Lin X-Patchwork-Id: 10575373 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id B53BD1579 for ; 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bh=o6f76JygZdkAcPnkVk+Y76xRDTxql9DrGWATmSfQzNk=; b=Vy3O2+KUhtcXDMK5IYtOrOfUS n1/S9a0JXOlEW9tYLqzAgKDE42spKykA4cBmbE5auW+iu8+YGjVFyme1vAfQn82pZjn6/ck9FH5ec jJu9O9Huh15JWCJd1u2RBF1E2y4PhVOGScn1XhweIZbc5l84AR3elDHjgA2YQUXnQx46gCC9aAeca rjbZX+wok0J/Me8e1vyteBWgQiFqAJq2Eg9nIUCJB85ExRuH1/1jLflk/K56yDfI+Po6m1cVNbGV7 Mduq0Lw3a2RtIw7dAMX+DtU3aCc/w86oahniCDUTdEsdr63tphccCbfl6Np6/ZPB8Q141raGwP1Hq FJicxxXQA==; Received: from mail-sh2.amlogic.com ([58.32.228.45]) by casper.infradead.org with esmtps (Exim 4.90_1 #2 (Red Hat Linux)) id 1ft6pW-00030e-87; Fri, 24 Aug 2018 07:48:27 +0000 Received: from droid10.amlogic.com (10.18.11.213) by mail-sh2.amlogic.com (10.18.11.6) with Microsoft SMTP Server id 15.0.1320.4; Fri, 24 Aug 2018 15:33:01 +0800 From: Hanjie Lin To: Kishon Vijay Abraham I Subject: [PATCH v2 2/2] PCI: meson: add the Amlogic Meson PCIe phy driver Date: Fri, 24 Aug 2018 15:33:26 +0800 Message-ID: <1535096006-152091-3-git-send-email-hanjie.lin@amlogic.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1535096006-152091-1-git-send-email-hanjie.lin@amlogic.com> References: <1535096006-152091-1-git-send-email-hanjie.lin@amlogic.com> MIME-Version: 1.0 X-Originating-IP: [10.18.11.213] X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20180824_084826_282520_18DF9CD0 X-CRM114-Status: GOOD ( 18.87 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Rob Herring , Hanjie Lin , Jianxin Pan , linux-pci@vger.kernel.org, Yixun Lan , Yue Wang , Qiufang Dai , Liang Yang , Jian Hu , Kevin Hilman , Carlo Caione , linux-amlogic@lists.infradead.org, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP From: Yue Wang The Meson-PCIE-PHY controller supports the 5-Gbps data rate of the PCI Express Gen 2 specification and is backwardcompatible with the 2.5-Gbps Gen 1.1 specification with only inferred idle detection supported on AMLOGIC SoCs. Signed-off-by: Yue Wang Signed-off-by: Hanjie Lin --- drivers/phy/amlogic/Kconfig | 8 ++ drivers/phy/amlogic/Makefile | 1 + drivers/phy/amlogic/phy-meson-axg-pcie.c | 124 +++++++++++++++++++++++++++++++ 3 files changed, 133 insertions(+) create mode 100644 drivers/phy/amlogic/phy-meson-axg-pcie.c diff --git a/drivers/phy/amlogic/Kconfig b/drivers/phy/amlogic/Kconfig index 23fe1cd..3ab07f9 100644 --- a/drivers/phy/amlogic/Kconfig +++ b/drivers/phy/amlogic/Kconfig @@ -36,3 +36,11 @@ config PHY_MESON_GXL_USB3 Enable this to support the Meson USB3 PHY and OTG detection IP block found in Meson GXL and GXM SoCs. If unsure, say N. + +config PHY_MESON_AXG_PCIE + bool "Meson AXG PCIe PHY driver" + depends on OF && (ARCH_MESON || COMPILE_TEST) + select GENERIC_PHY + help + Enable PCIe PHY support for Meson AXG SoC series. + This driver provides PHY interface for Meson PCIe controller. \ No newline at end of file diff --git a/drivers/phy/amlogic/Makefile b/drivers/phy/amlogic/Makefile index 4fd8848..5ab8578 100644 --- a/drivers/phy/amlogic/Makefile +++ b/drivers/phy/amlogic/Makefile @@ -1,3 +1,4 @@ obj-$(CONFIG_PHY_MESON8B_USB2) += phy-meson8b-usb2.o obj-$(CONFIG_PHY_MESON_GXL_USB2) += phy-meson-gxl-usb2.o obj-$(CONFIG_PHY_MESON_GXL_USB3) += phy-meson-gxl-usb3.o +obj-$(CONFIG_PHY_MESON_AXG_PCIE) += phy-meson-axg-pcie.o diff --git a/drivers/phy/amlogic/phy-meson-axg-pcie.c b/drivers/phy/amlogic/phy-meson-axg-pcie.c new file mode 100644 index 0000000..b517f9e --- /dev/null +++ b/drivers/phy/amlogic/phy-meson-axg-pcie.c @@ -0,0 +1,124 @@ +// SPDX-License-Identifier: (GPL-2.0+ or MIT) +/* + * Amlogic MESON SoC series PCIe PHY driver + * + * Phy provider for PCIe controller on MESON SoC series + * + * Copyright (c) 2018 Amlogic, inc. + * Yue Wang + */ + +#include +#include +#include +#include +#include +#include +#include + +struct meson_pcie_phy_data { + const struct phy_ops *ops; +}; + +struct meson_pcie_reset { + struct reset_control *phy; +}; + +struct meson_pcie_phy { + const struct meson_pcie_phy_data *data; + struct meson_pcie_reset reset; + void __iomem *phy_base; +}; + +#define MESON_PCIE_PHY_POWERUP 0x1c + +static int meson_pcie_phy_init(struct phy *phy) +{ + struct meson_pcie_phy *mphy = phy_get_drvdata(phy); + struct meson_pcie_reset *mrst = &mphy->reset; + + writel(MESON_PCIE_PHY_POWERUP, mphy->phy_base); + reset_control_assert(mrst->phy); + udelay(400); + reset_control_deassert(mrst->phy); + udelay(500); + + return 0; +} + +static const struct phy_ops meson_phy_ops = { + .init = meson_pcie_phy_init, + .owner = THIS_MODULE, +}; + +static const struct meson_pcie_phy_data meson_pcie_phy_data = { + .ops = &meson_phy_ops, +}; + +static const struct of_device_id meson_pcie_phy_match[] = { + { + .compatible = "amlogic,axg-pcie-phy", + .data = &meson_pcie_phy_data, + }, + {}, +}; + +static int meson_pcie_phy_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct meson_pcie_phy *mphy; + struct meson_pcie_reset *mrst; + struct phy *generic_phy; + struct phy_provider *phy_provider; + struct resource *res; + const struct meson_pcie_phy_data *data; + + data = of_device_get_match_data(dev); + if (!data) + return -ENODEV; + + mphy = devm_kzalloc(dev, sizeof(*mphy), GFP_KERNEL); + if (!mphy) + return -ENOMEM; + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + mphy->phy_base = devm_ioremap_resource(dev, res); + if (IS_ERR(mphy->phy_base)) + return PTR_ERR(mphy->phy_base); + + mrst = &mphy->reset; + + mrst->phy = devm_reset_control_get_shared(dev, "phy"); + if (IS_ERR(mrst->phy)) { + if (PTR_ERR(mrst->phy) != -EPROBE_DEFER) + dev_err(dev, "couldn't get phy reset\n"); + + return PTR_ERR(mrst->phy); + } + + reset_control_deassert(mrst->phy); + + mphy->data = data; + + generic_phy = devm_phy_create(dev, dev->of_node, mphy->data->ops); + if (IS_ERR(generic_phy)) { + if (PTR_ERR(generic_phy) != -EPROBE_DEFER) + dev_err(dev, "failed to create PHY\n"); + + return PTR_ERR(generic_phy); + } + + phy_set_drvdata(generic_phy, mphy); + phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); + + return PTR_ERR_OR_ZERO(phy_provider); +} + +static struct platform_driver meson_pcie_phy_driver = { + .probe = meson_pcie_phy_probe, + .driver = { + .of_match_table = meson_pcie_phy_match, + .name = "meson-pcie-phy", + } +}; + +builtin_platform_driver(meson_pcie_phy_driver);