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Thu, 25 Apr 2019 03:20:23 -0700 (PDT) From: Ard Biesheuvel To: linux-arm-kernel@lists.infradead.org Subject: [RFC PATCH 1/3] irqchip/exiu: preparatory refactor for ACPI support Date: Thu, 25 Apr 2019 12:20:18 +0200 Message-Id: <20190425102020.21533-2-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190425102020.21533-1-ard.biesheuvel@linaro.org> References: <20190425102020.21533-1-ard.biesheuvel@linaro.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190425_032026_272925_54D08DF3 X-CRM114-Status: GOOD ( 14.78 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Graeme Gregory , Ard Biesheuvel , Marc Zyngier , Linus Walleij , linux-gpio@vger.kernel.org, Masahisa Kojima Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP In preparation of exposing the EXIU controller as the irqchip part of the GPIO controller, split the DT init function in a DT specific and a generic part, where the latter will be reused for ACPI support later. Signed-off-by: Ard Biesheuvel --- drivers/irqchip/irq-sni-exiu.c | 77 ++++++++++++-------- 1 file changed, 48 insertions(+), 29 deletions(-) diff --git a/drivers/irqchip/irq-sni-exiu.c b/drivers/irqchip/irq-sni-exiu.c index 1927b2f36ff6..52ce662334d4 100644 --- a/drivers/irqchip/irq-sni-exiu.c +++ b/drivers/irqchip/irq-sni-exiu.c @@ -1,7 +1,7 @@ /* * Driver for Socionext External Interrupt Unit (EXIU) * - * Copyright (c) 2017 Linaro, Ltd. + * Copyright (c) 2017-2019 Linaro, Ltd. * * Based on irq-tegra.c: * Copyright (C) 2011 Google, Inc. @@ -167,35 +167,25 @@ static const struct irq_domain_ops exiu_domain_ops = { .free = irq_domain_free_irqs_common, }; -static int __init exiu_init(struct device_node *node, - struct device_node *parent) +static struct irq_domain *exiu_init(struct irq_domain *parent_domain, + struct fwnode_handle *fwnode, + struct resource *res) { - struct irq_domain *parent_domain, *domain; + struct irq_domain *domain; struct exiu_irq_data *data; int err; - if (!parent) { - pr_err("%pOF: no parent, giving up\n", node); - return -ENODEV; - } - - parent_domain = irq_find_host(parent); - if (!parent_domain) { - pr_err("%pOF: unable to obtain parent domain\n", node); - return -ENXIO; - } - data = kzalloc(sizeof(*data), GFP_KERNEL); if (!data) - return -ENOMEM; + return ERR_PTR(-ENOMEM); - if (of_property_read_u32(node, "socionext,spi-base", &data->spi_base)) { - pr_err("%pOF: failed to parse 'spi-base' property\n", node); + if (fwnode_property_read_u32_array(fwnode, "socionext,spi-base", + &data->spi_base, 1)) { err = -ENODEV; goto out_free; } - data->base = of_iomap(node, 0); + data->base = ioremap(res->start, resource_size(res)); if (!data->base) { err = -ENODEV; goto out_free; @@ -205,23 +195,52 @@ static int __init exiu_init(struct device_node *node, writel_relaxed(0xFFFFFFFF, data->base + EIREQCLR); writel_relaxed(0xFFFFFFFF, data->base + EIMASK); - domain = irq_domain_add_hierarchy(parent_domain, 0, NUM_IRQS, node, - &exiu_domain_ops, data); + domain = irq_domain_create_hierarchy(parent_domain, 0, NUM_IRQS, + fwnode, &exiu_domain_ops, data); if (!domain) { - pr_err("%pOF: failed to allocate domain\n", node); err = -ENOMEM; goto out_unmap; } + return domain; +out_unmap: + iounmap(data->base); +out_free: + kfree(data); + return ERR_PTR(err); +} + +static int __init exiu_dt_init(struct device_node *node, + struct device_node *parent) +{ + struct irq_domain *parent_domain, *domain; + struct resource res; + + if (!parent) { + pr_err("%pOF: no parent, giving up\n", node); + return -ENODEV; + } + + parent_domain = irq_find_host(parent); + if (!parent_domain) { + pr_err("%pOF: unable to obtain parent domain\n", node); + return -ENXIO; + } + + if (of_address_to_resource(node, 0, &res)) { + pr_err("%pOF: failed to parse memory resource\n", node); + return -ENXIO; + } + + domain = exiu_init(parent_domain, of_node_to_fwnode(node), &res); + if (IS_ERR(domain)) { + pr_err("%pOF: failed to create IRQ domain (%ld)\n", node, + PTR_ERR(domain)); + return PTR_ERR(domain); + } pr_info("%pOF: %d interrupts forwarded to %pOF\n", node, NUM_IRQS, parent); return 0; - -out_unmap: - iounmap(data->base); -out_free: - kfree(data); - return err; } -IRQCHIP_DECLARE(exiu, "socionext,synquacer-exiu", exiu_init); +IRQCHIP_DECLARE(exiu, "socionext,synquacer-exiu", exiu_dt_init); From patchwork Thu Apr 25 10:20:19 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ard Biesheuvel X-Patchwork-Id: 10916763 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 191F01575 for ; Thu, 25 Apr 2019 10:20:55 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 0890F28AFB for ; Thu, 25 Apr 2019 10:20:55 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id F0C1228C3F; Thu, 25 Apr 2019 10:20:54 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 8590C28AFB for ; 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Thu, 25 Apr 2019 03:20:24 -0700 (PDT) From: Ard Biesheuvel To: linux-arm-kernel@lists.infradead.org Subject: [RFC PATCH 2/3] irqchip/exiu: implement ACPI gpiolib/irqchip support Date: Thu, 25 Apr 2019 12:20:19 +0200 Message-Id: <20190425102020.21533-3-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190425102020.21533-1-ard.biesheuvel@linaro.org> References: <20190425102020.21533-1-ard.biesheuvel@linaro.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190425_032028_441095_C1A0B2B8 X-CRM114-Status: GOOD ( 15.87 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Graeme Gregory , Ard Biesheuvel , Marc Zyngier , Linus Walleij , linux-gpio@vger.kernel.org, Masahisa Kojima Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Expose the existing EXIU hierarchical irqchip domain code to permit the interrupt controller to be used as the irqchip component of a GPIO controller on ACPI systems. Signed-off-by: Ard Biesheuvel --- drivers/irqchip/irq-sni-exiu.c | 82 +++++++++++++++++--- 1 file changed, 73 insertions(+), 9 deletions(-) diff --git a/drivers/irqchip/irq-sni-exiu.c b/drivers/irqchip/irq-sni-exiu.c index 52ce662334d4..99351cf997d9 100644 --- a/drivers/irqchip/irq-sni-exiu.c +++ b/drivers/irqchip/irq-sni-exiu.c @@ -12,6 +12,7 @@ * published by the Free Software Foundation. */ +#include #include #include #include @@ -20,6 +21,7 @@ #include #include #include +#include #include @@ -134,9 +136,13 @@ static int exiu_domain_translate(struct irq_domain *domain, *hwirq = fwspec->param[1] - info->spi_base; *type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK; - return 0; + } else { + if (fwspec->param_count != 2) + return -EINVAL; + *hwirq = fwspec->param[0]; + *type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK; } - return -EINVAL; + return 0; } static int exiu_domain_alloc(struct irq_domain *dom, unsigned int virq, @@ -147,16 +153,23 @@ static int exiu_domain_alloc(struct irq_domain *dom, unsigned int virq, struct exiu_irq_data *info = dom->host_data; irq_hw_number_t hwirq; - if (fwspec->param_count != 3) - return -EINVAL; /* Not GIC compliant */ - if (fwspec->param[0] != GIC_SPI) - return -EINVAL; /* No PPI should point to this domain */ - + parent_fwspec = *fwspec; + if (is_of_node(dom->parent->fwnode)) { + if (fwspec->param_count != 3) + return -EINVAL; /* Not GIC compliant */ + if (fwspec->param[0] != GIC_SPI) + return -EINVAL; /* No PPI should point to this domain */ + + hwirq = fwspec->param[1] - info->spi_base; + } else if (is_fwnode_irqchip(dom->parent->fwnode)) { + hwirq = fwspec->param[0]; + parent_fwspec.param[0] = hwirq + info->spi_base + 32; + } else { + return -EINVAL; + } WARN_ON(nr_irqs != 1); - hwirq = fwspec->param[1] - info->spi_base; irq_domain_set_hwirq_and_chip(dom, virq, hwirq, &exiu_irq_chip, info); - parent_fwspec = *fwspec; parent_fwspec.fwnode = dom->parent->fwnode; return irq_domain_alloc_irqs_parent(dom, virq, nr_irqs, &parent_fwspec); } @@ -244,3 +257,54 @@ static int __init exiu_dt_init(struct device_node *node, return 0; } IRQCHIP_DECLARE(exiu, "socionext,synquacer-exiu", exiu_dt_init); + +#ifdef CONFIG_ACPI +static int exiu_acpi_gpio_to_irq(struct gpio_chip *gc, u32 gpio) +{ + struct irq_fwspec fwspec; + + fwspec.fwnode = gc->parent->fwnode; + fwspec.param_count = 2; + fwspec.param[0] = gpio; + fwspec.param[1] = IRQ_TYPE_LEVEL_HIGH; + + return irq_create_fwspec_mapping(&fwspec); +} + +int exiu_acpi_init(struct platform_device *pdev, struct gpio_chip *gc) +{ + struct irq_domain *parent_domain = NULL, *domain; + struct resource *res; + int irq; + + irq = platform_get_irq(pdev, 0); + if (irq > 0) + parent_domain = irq_get_irq_data(irq)->domain; + + if (!parent_domain) { + dev_err(&pdev->dev, "unable to obtain parent domain\n"); + return -ENODEV; + } + + res = platform_get_resource(pdev, IORESOURCE_MEM, 1); + if (!res) { + dev_err(&pdev->dev, "failed to parse memory resource\n"); + return -ENXIO; + } + + domain = exiu_init(parent_domain, dev_fwnode(&pdev->dev), res); + if (IS_ERR(domain)) { + dev_err(&pdev->dev, "failed to create IRQ domain (%ld)\n", + PTR_ERR(domain)); + return PTR_ERR(domain); + } + + gc->irq.domain = domain; + gc->to_irq = exiu_acpi_gpio_to_irq; + + dev_info(&pdev->dev, "%d interrupts forwarded\n", NUM_IRQS); + + return 0; +} +EXPORT_SYMBOL(exiu_acpi_init); +#endif From patchwork Thu Apr 25 10:20:20 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ard Biesheuvel X-Patchwork-Id: 10916765 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 65ADA1575 for ; Thu, 25 Apr 2019 10:21:09 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 5583D28AFB for ; Thu, 25 Apr 2019 10:21:09 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 46E6C28C3F; Thu, 25 Apr 2019 10:21:09 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id BB2A228AFB for ; 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Thu, 25 Apr 2019 03:20:26 -0700 (PDT) From: Ard Biesheuvel To: linux-arm-kernel@lists.infradead.org Subject: [RFC PATCH 3/3] gpio: mb86s70: enable ACPI and irqchip support Date: Thu, 25 Apr 2019 12:20:20 +0200 Message-Id: <20190425102020.21533-4-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190425102020.21533-1-ard.biesheuvel@linaro.org> References: <20190425102020.21533-1-ard.biesheuvel@linaro.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190425_032029_886592_739D1343 X-CRM114-Status: GOOD ( 18.14 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Graeme Gregory , Ard Biesheuvel , Marc Zyngier , Linus Walleij , linux-gpio@vger.kernel.org, Masahisa Kojima Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP In order to support this GPIO block in combination with an EXIU interrupt controller on ACPI systems such as Socionext SynQuacer, add the enumeration boilerplate, and add the EXIU irqchip handling to the probe path. Also, make the clock handling conditonal on non-ACPI enumeration, since ACPI handles this internally. Signed-off-by: Ard Biesheuvel --- drivers/gpio/Kconfig | 4 ++ drivers/gpio/gpio-mb86s7x.c | 58 +++++++++++++++++--- 2 files changed, 53 insertions(+), 9 deletions(-) diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index 3f50526a771f..2c2773ea9627 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -315,6 +315,10 @@ config GPIO_MB86S7X help Say yes here to support the GPIO controller in Fujitsu MB86S70 SoCs. +config GPIO_MB86S7X_ACPI + def_bool y + depends on ACPI && ARCH_SYNQUACER + config GPIO_MENZ127 tristate "MEN 16Z127 GPIO support" depends on MCB diff --git a/drivers/gpio/gpio-mb86s7x.c b/drivers/gpio/gpio-mb86s7x.c index 3134c0d2bfe4..d254783f7e71 100644 --- a/drivers/gpio/gpio-mb86s7x.c +++ b/drivers/gpio/gpio-mb86s7x.c @@ -14,6 +14,7 @@ * GNU General Public License for more details. */ +#include #include #include #include @@ -27,6 +28,8 @@ #include #include +#include "gpiolib.h" + /* * Only first 8bits of a register correspond to each pin, * so there are 4 registers for 32 pins. @@ -44,6 +47,8 @@ struct mb86s70_gpio_chip { spinlock_t lock; }; +int exiu_acpi_init(struct platform_device *pdev, struct gpio_chip *gc); + static int mb86s70_gpio_request(struct gpio_chip *gc, unsigned gpio) { struct mb86s70_gpio_chip *gchip = gpiochip_get_data(gc); @@ -143,6 +148,12 @@ static void mb86s70_gpio_set(struct gpio_chip *gc, unsigned gpio, int value) spin_unlock_irqrestore(&gchip->lock, flags); } +static bool mb86s70_gpio_have_acpi(struct platform_device *pdev) +{ + return IS_ENABLED(CONFIG_GPIO_MB86S7X_ACPI) && + ACPI_COMPANION(&pdev->dev); +} + static int mb86s70_gpio_probe(struct platform_device *pdev) { struct mb86s70_gpio_chip *gchip; @@ -160,13 +171,15 @@ static int mb86s70_gpio_probe(struct platform_device *pdev) if (IS_ERR(gchip->base)) return PTR_ERR(gchip->base); - gchip->clk = devm_clk_get(&pdev->dev, NULL); - if (IS_ERR(gchip->clk)) - return PTR_ERR(gchip->clk); + if (!mb86s70_gpio_have_acpi(pdev)) { + gchip->clk = devm_clk_get(&pdev->dev, NULL); + if (IS_ERR(gchip->clk)) + return PTR_ERR(gchip->clk); - ret = clk_prepare_enable(gchip->clk); - if (ret) - return ret; + ret = clk_prepare_enable(gchip->clk); + if (ret) + return ret; + } spin_lock_init(&gchip->lock); @@ -182,21 +195,39 @@ static int mb86s70_gpio_probe(struct platform_device *pdev) gchip->gc.parent = &pdev->dev; gchip->gc.base = -1; + if (mb86s70_gpio_have_acpi(pdev)) { + ret = exiu_acpi_init(pdev, &gchip->gc); + if (ret) { + dev_err(&pdev->dev, "couldn't register gpio irqchip\n"); + return ret; + } + } + ret = gpiochip_add_data(&gchip->gc, gchip); if (ret) { dev_err(&pdev->dev, "couldn't register gpio driver\n"); - clk_disable_unprepare(gchip->clk); + if (gchip->clk) + clk_disable_unprepare(gchip->clk); + return ret; } - return ret; + if (mb86s70_gpio_have_acpi(pdev)) + acpi_gpiochip_request_interrupts(&gchip->gc); + + return 0; } static int mb86s70_gpio_remove(struct platform_device *pdev) { struct mb86s70_gpio_chip *gchip = platform_get_drvdata(pdev); + if (gchip->gc.irq.domain) { + acpi_gpiochip_free_interrupts(&gchip->gc); + irq_domain_remove(gchip->gc.irq.domain); + } gpiochip_remove(&gchip->gc); - clk_disable_unprepare(gchip->clk); + if (gchip->clk) + clk_disable_unprepare(gchip->clk); return 0; } @@ -207,10 +238,19 @@ static const struct of_device_id mb86s70_gpio_dt_ids[] = { }; MODULE_DEVICE_TABLE(of, mb86s70_gpio_dt_ids); +#ifdef CONFIG_ACPI +static const struct acpi_device_id mb86s70_gpio_acpi_ids[] = { + { "SCX0007" }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(acpi, mb86s70_gpio_acpi_ids); +#endif + static struct platform_driver mb86s70_gpio_driver = { .driver = { .name = "mb86s70-gpio", .of_match_table = mb86s70_gpio_dt_ids, + .acpi_match_table = ACPI_PTR(mb86s70_gpio_acpi_ids), }, .probe = mb86s70_gpio_probe, .remove = mb86s70_gpio_remove,