From patchwork Fri Apr 26 10:22:45 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Andrew Cooper X-Patchwork-Id: 10918991 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 0741F14C0 for ; Fri, 26 Apr 2019 10:24:29 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id EA15928DBA for ; Fri, 26 Apr 2019 10:24:28 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id DE3C928DC0; Fri, 26 Apr 2019 10:24:28 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 7537728DBA for ; Fri, 26 Apr 2019 10:24:28 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1hJy0L-0001CH-OD; Fri, 26 Apr 2019 10:22:53 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57] helo=us1-amaz-eas2.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1hJy0J-0001CC-W4 for xen-devel@lists.xenproject.org; Fri, 26 Apr 2019 10:22:52 +0000 X-Inumbo-ID: 3cf6191c-680d-11e9-8e78-6f51b3b727ef Received: from SMTP03.CITRIX.COM (unknown [162.221.156.55]) by us1-amaz-eas2.inumbo.com (Halon) with ESMTPS id 3cf6191c-680d-11e9-8e78-6f51b3b727ef; Fri, 26 Apr 2019 10:22:48 +0000 (UTC) X-IronPort-AV: E=Sophos;i="5.60,397,1549929600"; d="scan'208";a="84487959" From: Andrew Cooper To: Xen-devel Date: Fri, 26 Apr 2019 11:22:45 +0100 Message-ID: <1556274165-31022-1-git-send-email-andrew.cooper3@citrix.com> X-Mailer: git-send-email 2.1.4 MIME-Version: 1.0 Subject: [Xen-devel] [PATCH] x86/cpu: Use cpu_has_sep for configuring the SYSENTER MSRs X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Andrew Cooper , FionaLi-oc , Wei Liu , Jan Beulich , =?utf-8?q?Roger_Pau_Monn=C3=A9?= Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" X-Virus-Scanned: ClamAV using ClamSMTP Currently, configuration of the SYSENTER MSRs are behind a vendor check for Intel and Centaur, but this misses Zhaoxin. Use the feature bit, rather than a vendor check. cpu_has_sep is cleared early for AMD processors, which can't use SYSENTER/SYSEXIT when operating in long mode. Suggested-by: Jan Beulich Signed-off-by: Andrew Cooper Reviewed-by: Jan Beulich --- CC: Jan Beulich CC: Wei Liu CC: Roger Pau Monné CC: FionaLi-oc Please double check that this works for Zhaoxin. I've tried Intel and AMD. --- xen/arch/x86/acpi/suspend.c | 6 ++++-- xen/arch/x86/x86_64/traps.c | 2 +- 2 files changed, 5 insertions(+), 3 deletions(-) diff --git a/xen/arch/x86/acpi/suspend.c b/xen/arch/x86/acpi/suspend.c index 9e69bf2..ba9d2e1 100644 --- a/xen/arch/x86/acpi/suspend.c +++ b/xen/arch/x86/acpi/suspend.c @@ -27,11 +27,13 @@ void save_rest_processor_state(void) rdmsrl(MSR_SHADOW_GS_BASE, saved_kernel_gs_base); rdmsrl(MSR_CSTAR, saved_cstar); rdmsrl(MSR_LSTAR, saved_lstar); - if ( boot_cpu_data.x86_vendor & (X86_VENDOR_INTEL | X86_VENDOR_CENTAUR) ) + + if ( cpu_has_sep ) { rdmsrl(MSR_IA32_SYSENTER_ESP, saved_sysenter_esp); rdmsrl(MSR_IA32_SYSENTER_EIP, saved_sysenter_eip); } + if ( cpu_has_xsave ) saved_xcr0 = get_xcr0(); } @@ -51,7 +53,7 @@ void restore_rest_processor_state(void) wrgsbase(saved_gs_base); wrmsrl(MSR_SHADOW_GS_BASE, saved_kernel_gs_base); - if ( boot_cpu_data.x86_vendor & (X86_VENDOR_INTEL | X86_VENDOR_CENTAUR) ) + if ( cpu_has_sep ) { /* Recover sysenter MSRs */ wrmsrl(MSR_IA32_SYSENTER_ESP, saved_sysenter_esp); diff --git a/xen/arch/x86/x86_64/traps.c b/xen/arch/x86/x86_64/traps.c index 44af765..cb4bf0a 100644 --- a/xen/arch/x86/x86_64/traps.c +++ b/xen/arch/x86/x86_64/traps.c @@ -334,7 +334,7 @@ void subarch_percpu_traps_init(void) (unsigned long)lstar_enter); stub_va += offset; - if ( boot_cpu_data.x86_vendor & (X86_VENDOR_INTEL | X86_VENDOR_CENTAUR) ) + if ( cpu_has_sep ) { /* SYSENTER entry. */ wrmsrl(MSR_IA32_SYSENTER_ESP, stack_bottom);