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Mon, 29 Apr 2019 03:18:43 +0000 Received: from DB3PR0402MB3916.eurprd04.prod.outlook.com ([fe80::e8ca:4f6b:e43:c170]) by DB3PR0402MB3916.eurprd04.prod.outlook.com ([fe80::e8ca:4f6b:e43:c170%3]) with mapi id 15.20.1835.018; Mon, 29 Apr 2019 03:18:43 +0000 From: Anson Huang To: "mturquette@baylibre.com" , "sboyd@kernel.org" , "shawnguo@kernel.org" , "s.hauer@pengutronix.de" , "kernel@pengutronix.de" , "festevam@gmail.com" , Aisheng Dong , "linux-clk@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "linux-kernel@vger.kernel.org" CC: dl-linux-imx Subject: [PATCH] clk: imx: add fractional-N pll support to pllv4 Thread-Topic: [PATCH] clk: imx: add fractional-N pll support to pllv4 Thread-Index: AQHU/jo/D2ZwDi5WREOeVbOKgmEXYQ== Date: Mon, 29 Apr 2019 03:18:43 +0000 Message-ID: <1556507637-22847-1-git-send-email-Anson.Huang@nxp.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-mailer: git-send-email 2.7.4 x-clientproxiedby: HK2PR03CA0059.apcprd03.prod.outlook.com (2603:1096:202:17::29) To DB3PR0402MB3916.eurprd04.prod.outlook.com (2603:10a6:8:10::18) authentication-results: spf=none (sender IP is ) smtp.mailfrom=anson.huang@nxp.com; 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received-spf: None (protection.outlook.com: nxp.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: YDnUAWd0UZ2nqTuFYIMpg4zROUGw4Zo7/K/+YZI4ZNDnYAoob7OY6LYAurgSltu/69oSUCDD4BH4I4Xcz1QmsGsxJPVTjyZygDO7in5EBVvSt4bZyVS+Us0pSil3JZu7i8Zl86ow23/vqCwf9sq2leWix/WFvQaFHn8HteMR4DU3Lddl1VB/sYDc3e8eT6fXkC+lsTg3Fa8CiaNO+C6KSqGWiWibX5MmGS+mwYOchqmJuPvAku8uzqw06SgyPvSmnidwh5gDYhX03g2fUvY1IzxSkUuzbEKX2zefe9NcK3fvaECwBVYQ9XzR+3x9wHpM7X7aGPyztYY6uDzqLY+oM0JNIGHvO4p7YrhmV7IpD053wzOQ+SV7JoAh3UdL1TbNxQ70DuRCAbPdo8tp71BbiOBjh6fe1XkLcicL3/4qoMA= MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 1621dcd0-9aa4-4613-ac6c-08d6cc5161f9 X-MS-Exchange-CrossTenant-originalarrivaltime: 29 Apr 2019 03:18:43.1046 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB3PR0402MB3724 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The pllv4 supports fractional-N function, the formula is: PLL output freq = input * (mult + num/denom), This patch adds fractional-N function support, including clock round rate, calculate rate and set rate, with this patch, the clock rate of APLL in clock tree is more accurate than before: Without fraction: apll_pre_sel 1 1 1 24000000 0 0 50000 apll_pre_div 1 1 2 24000000 0 0 50000 apll 1 1 2 528000000 0 0 50000 apll_pfd3 0 0 0 792000000 0 0 50000 apll_pfd2 0 0 0 339428571 0 0 50000 apll_pfd1 0 0 0 352000000 0 0 50000 usdhc0 0 0 0 352000000 0 0 50000 apll_pfd0 1 1 1 352000000 0 0 50000 With fraction: apll_pre_sel 1 1 1 24000000 0 0 50000 apll_pre_div 1 1 2 24000000 0 0 50000 apll 1 1 2 529200000 0 0 50000 apll_pfd3 0 0 0 793800000 0 0 50000 apll_pfd2 0 0 0 340200000 0 0 50000 apll_pfd1 0 0 0 352800000 0 0 50000 usdhc0 0 0 0 352800000 0 0 50000 apll_pfd0 1 1 1 352800000 0 0 50000 Signed-off-by: Anson Huang Reviewed-by: Dong Aisheng --- drivers/clk/imx/clk-pllv4.c | 68 +++++++++++++++++++++++++++++++++++++++------ 1 file changed, 60 insertions(+), 8 deletions(-) diff --git a/drivers/clk/imx/clk-pllv4.c b/drivers/clk/imx/clk-pllv4.c index d38bc9f..4ced5ca 100644 --- a/drivers/clk/imx/clk-pllv4.c +++ b/drivers/clk/imx/clk-pllv4.c @@ -64,13 +64,18 @@ static unsigned long clk_pllv4_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { struct clk_pllv4 *pll = to_clk_pllv4(hw); - u32 div; + u32 mult = readl_relaxed(pll->base + PLL_CFG_OFFSET); + u32 mfn = readl_relaxed(pll->base + PLL_NUM_OFFSET); + u32 mfd = readl_relaxed(pll->base + PLL_DENOM_OFFSET); + u64 temp64 = parent_rate; - div = readl_relaxed(pll->base + PLL_CFG_OFFSET); - div &= BM_PLL_MULT; - div >>= BP_PLL_MULT; + mult &= BM_PLL_MULT; + mult >>= BP_PLL_MULT; - return parent_rate * div; + temp64 *= mfn; + do_div(temp64, mfd); + + return (parent_rate * mult) + (u32)temp64; } static long clk_pllv4_round_rate(struct clk_hw *hw, unsigned long rate, @@ -78,14 +83,47 @@ static long clk_pllv4_round_rate(struct clk_hw *hw, unsigned long rate, { unsigned long parent_rate = *prate; unsigned long round_rate, i; + bool found = false; + u32 mfn, mfd = 1000000; + u32 max_mfd = 0x3FFFFFFF; + u64 temp64; for (i = 0; i < ARRAY_SIZE(pllv4_mult_table); i++) { round_rate = parent_rate * pllv4_mult_table[i]; - if (rate >= round_rate) - return round_rate; + if (rate >= round_rate) { + found = true; + break; + } + } + + if (!found) { + pr_warn("%s: unable to round rate %lu, parent rate %lu\n", + clk_hw_get_name(hw), rate, parent_rate); + return 0; } - return round_rate; + if (parent_rate <= max_mfd) + mfd = parent_rate; + + temp64 = (u64)(rate - round_rate); + temp64 *= mfd; + do_div(temp64, parent_rate); + mfn = temp64; + + /* + * NOTE: The value of numerator must always be configured to be + * less than the value of the denominator. If we can't get a proper + * pair of mfn/mfd, we simply return the round_rate without using + * the frac part. + */ + if (mfn >= mfd) + return round_rate; + + temp64 = (u64)parent_rate; + temp64 *= mfn; + do_div(temp64, mfd); + + return round_rate + (u32)temp64; } static bool clk_pllv4_is_valid_mult(unsigned int mult) @@ -106,17 +144,31 @@ static int clk_pllv4_set_rate(struct clk_hw *hw, unsigned long rate, { struct clk_pllv4 *pll = to_clk_pllv4(hw); u32 val, mult; + u32 mfn, mfd = 1000000; + u32 max_mfd = 0x3FFFFFFF; + u64 temp64; mult = rate / parent_rate; if (!clk_pllv4_is_valid_mult(mult)) return -EINVAL; + if (parent_rate <= max_mfd) + mfd = parent_rate; + + temp64 = (u64)(rate - mult * parent_rate); + temp64 *= mfd; + do_div(temp64, parent_rate); + mfn = temp64; + val = readl_relaxed(pll->base + PLL_CFG_OFFSET); val &= ~BM_PLL_MULT; val |= mult << BP_PLL_MULT; writel_relaxed(val, pll->base + PLL_CFG_OFFSET); + writel_relaxed(mfn, pll->base + PLL_NUM_OFFSET); + writel_relaxed(mfd, pll->base + PLL_DENOM_OFFSET); + return 0; }