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[68.232.141.245]) by mx.google.com with ESMTPS id c3si34040478plo.243.2019.04.29.12.58.28 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 29 Apr 2019 12:58:28 -0700 (PDT) Received-SPF: pass (google.com: domain of prvs=0155011cf=atish.patra@wdc.com designates 68.232.141.245 as permitted sender) client-ip=68.232.141.245; Authentication-Results: mx.google.com; dkim=pass header.i=@wdc.com header.s=dkim.wdc.com header.b=m9WkW3Cy; spf=pass (google.com: domain of prvs=0155011cf=atish.patra@wdc.com designates 68.232.141.245 as permitted sender) smtp.mailfrom="prvs=0155011cf=atish.patra@wdc.com"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=wdc.com DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1556567908; x=1588103908; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=GQpKXJ6rfJbjxybm+qOYB3z1XmPhKagdgdILF7N0WwA=; b=m9WkW3CyoJ0xdoGw9nilS1jXk0EC9w4+iAIX7YTyk4IhawUfNuJ0LfyI 5zCtbtU5dbdzPru1A2aB8mQZqVdci11Of4IWgDHOxzdmEg6ztt1xuwIM6 Z0ZIzM6k1YKwIkA1bSaJybLWSevNJ7lQn6mqHEiPkwqhi4h3e3cHTwSmM S+2Yllc/lQ7uXgWkUT4WoT8+IBak10DSdyWJij00LvPvskHrCShZvAOqg lzjcWVynBkMUmgelbiBwWznoVG23fX76L8rTZjUMGBBb537+8aCCPOafQ c5nvjj0Au/hKkeZNlInsmvtAEAo8mMFCneTmbUDh7/lq6bJk5Gs2dznpS Q==; X-IronPort-AV: E=Sophos;i="5.60,410,1549900800"; d="scan'208";a="212999870" Received: from h199-255-45-14.hgst.com (HELO uls-op-cesaep01.wdc.com) ([199.255.45.14]) by ob1.hgst.iphmx.com with ESMTP; 30 Apr 2019 03:58:11 +0800 IronPort-SDR: jBjPovgmsobnZmrrksjuxix2kl6D7esOMHIhvxag0FPlRNBWDsDbkROf2CBhIFmUJS6eLu7V30 2ZZ4feR9PB/wS6t5iiiXZK1w1UOtWFRMudD5G91akZJxKivfA3RCPY+x+3eSzPpmYPPgeU4sHC mOM03NruN55doZhvRRMvJ9qKwpP+Bj2RnYxe4KGofEC8BGJXbGdN45DZnsnl1xiX2T/6x+kzBb y0+bi6hkj62E8LjT5MJuGuHz0IOtteDJZnLs3ksnM/20xU9xBH66KiPmvEUWwyrjHMp3k++fdj NDc+IbXr1hpa/9/e1vcvGXG1 Received: from uls-op-cesaip01.wdc.com ([10.248.3.36]) by uls-op-cesaep01.wdc.com with ESMTP; 29 Apr 2019 12:34:34 -0700 IronPort-SDR: wz9YGcayYviARxURW0XYZuUzYVCZFmYVx0XdGd5JZHZiNh02M12LMvPMG8IMYcAtZPZcy1EeDb h3W9jYm/1FQlZZHxDvV7Prowbsd3Hyz1a/RTdWFHN0r5GMxoiiiDXhfxhLeiwqugDGnA05Ljq4 moiPxBN2X9YhDPIWKJYtQve9/hgsixthYTDEgtOkb23Yld3IOO/JdsyvvCGFG92A8VPkK75xXs A9KKcfbWLwIjssH3PDU+LBp77MSbbrSFkbhUoC8pi5FigiTn+C/eTzzxNX9qF9uVZ00cmOxTce epM= Received: from jedi-01.sdcorp.global.sandisk.com (HELO jedi-01.int.fusionio.com) ([10.11.143.218]) by uls-op-cesaip01.wdc.com with ESMTP; 29 Apr 2019 12:58:11 -0700 From: Atish Patra To: linux-kernel@vger.kernel.org Cc: Atish Patra , Albert Ou , Andrew Morton , Anup Patel , Borislav Petkov , Changbin Du , Gary Guo , "H. Peter Anvin" , Ingo Molnar , Kees Cook , linux-mm@kvack.org, linux-riscv@lists.infradead.org, Luc Van Oostenryck , Palmer Dabbelt , Thomas Gleixner , Vlastimil Babka , x86@kernel.org (maintainer:X86 ARCHITECTURE (32-BIT AND 64-BIT)), Christoph Hellwig Subject: [PATCH v2 1/3] x86: Move DEBUG_TLBFLUSH option. Date: Mon, 29 Apr 2019 12:57:57 -0700 Message-Id: <20190429195759.18330-2-atish.patra@wdc.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190429195759.18330-1-atish.patra@wdc.com> References: <20190429195759.18330-1-atish.patra@wdc.com> MIME-Version: 1.0 X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: X-Virus-Scanned: ClamAV using ClamSMTP CONFIG_DEBUG_TLBFLUSH was added in 'commit 3df3212f9722 ("x86/tlb: add tlb_flushall_shift knob into debugfs")' to support tlb_flushall_shift knob. The knob was removed in 'commit e9f4e0a9fe27 ("x86/mm: Rip out complicated, out-of-date, buggy TLB flushing")'. However, the debug option was never removed from Kconfig. It was reused in commit '9824cf9753ec ("mm: vmstats: tlb flush counters")' but the commit text was never updated accordingly. Update the Kconfig option description as per its current usage. Take this opprtunity to make this kconfig option a common option as it touches the common vmstat code. Introduce another arch specific config HAVE_ARCH_DEBUG_TLBFLUSH that can be selected to enable this config. Signed-off-by: Atish Patra --- arch/x86/Kconfig | 1 + arch/x86/Kconfig.debug | 19 ------------------- mm/Kconfig.debug | 13 +++++++++++++ 3 files changed, 14 insertions(+), 19 deletions(-) diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 62fc3fda1a05..4c59f59e9491 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -132,6 +132,7 @@ config X86 select HAVE_ARCH_TRANSPARENT_HUGEPAGE_PUD if X86_64 select HAVE_ARCH_VMAP_STACK if X86_64 select HAVE_ARCH_WITHIN_STACK_FRAMES + select HAVE_ARCH_DEBUG_TLBFLUSH if DEBUG_KERNEL select HAVE_CMPXCHG_DOUBLE select HAVE_CMPXCHG_LOCAL select HAVE_CONTEXT_TRACKING if X86_64 diff --git a/arch/x86/Kconfig.debug b/arch/x86/Kconfig.debug index 15d0fbe27872..0c8f9931e901 100644 --- a/arch/x86/Kconfig.debug +++ b/arch/x86/Kconfig.debug @@ -124,25 +124,6 @@ config DOUBLEFAULT option saves about 4k and might cause you much additional grey hair. -config DEBUG_TLBFLUSH - bool "Set upper limit of TLB entries to flush one-by-one" - depends on DEBUG_KERNEL - ---help--- - - X86-only for now. - - This option allows the user to tune the amount of TLB entries the - kernel flushes one-by-one instead of doing a full TLB flush. In - certain situations, the former is cheaper. This is controlled by the - tlb_flushall_shift knob under /sys/kernel/debug/x86. If you set it - to -1, the code flushes the whole TLB unconditionally. Otherwise, - for positive values of it, the kernel will use single TLB entry - invalidating instructions according to the following formula: - - flush_entries <= active_tlb_entries / 2^tlb_flushall_shift - - If in doubt, say "N". - config IOMMU_DEBUG bool "Enable IOMMU debugging" depends on GART_IOMMU && DEBUG_KERNEL diff --git a/mm/Kconfig.debug b/mm/Kconfig.debug index e3df921208c0..760c3fda8b57 100644 --- a/mm/Kconfig.debug +++ b/mm/Kconfig.debug @@ -111,3 +111,16 @@ config DEBUG_RODATA_TEST depends on STRICT_KERNEL_RWX ---help--- This option enables a testcase for the setting rodata read-only. + +config HAVE_ARCH_DEBUG_TLBFLUSH + bool + depends on DEBUG_KERNEL + +config DEBUG_TLBFLUSH + bool "Save tlb flush statstics to vmstat" + depends on HAVE_ARCH_DEBUG_TLBFLUSH + help + + Add tlbflush statstics to vmstat. It is really helpful understand tlbflush + performance and behavior. It should be enabled only for debugging purpose + by individual architectures explicitly by selecting HAVE_ARCH_DEBUG_TLBFLUSH. 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[68.232.141.245]) by mx.google.com with ESMTPS id c3si34040478plo.243.2019.04.29.12.58.28 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 29 Apr 2019 12:58:28 -0700 (PDT) Received-SPF: pass (google.com: domain of prvs=0155011cf=atish.patra@wdc.com designates 68.232.141.245 as permitted sender) client-ip=68.232.141.245; Authentication-Results: mx.google.com; dkim=pass header.i=@wdc.com header.s=dkim.wdc.com header.b=Oujy3vVT; spf=pass (google.com: domain of prvs=0155011cf=atish.patra@wdc.com designates 68.232.141.245 as permitted sender) smtp.mailfrom="prvs=0155011cf=atish.patra@wdc.com"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=wdc.com DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1556567908; x=1588103908; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=674EX0iIftC/tP47ciQ2WAq8p0Blf4MJzfJ6YEpD/54=; b=Oujy3vVTrTYWAj/seY8BIy620epPPCi27Y81ZFx7zhOATMEbRe8Z/lFC oxprWO7nSt6o0n5pcbLH0xIq0Ve8a/gOj7r6Mq/o2RNQiA7iqxWykTYko iHuMrMdCQbSURqtLV6viI6/pzdW5mM/l606ect5F4XlPPE65sD/vY+xWL GrF2WxsyMy92m4n/YxMeVeBb+gbQnhr4pyuP5wSe682/4U5xdAsbhQgfO RRwTJclLb0MLrHZI/Ea8n5u62gQdEoco/LQ6jtuEs5l5fOAGI+AkjuWKS VSfnKc9XAqlImViAorgYHo30XsLG+T7+rPHLJ36Mjr+r5uARZGs9DQZMV A==; X-IronPort-AV: E=Sophos;i="5.60,410,1549900800"; d="scan'208";a="212999881" Received: from h199-255-45-14.hgst.com (HELO uls-op-cesaep01.wdc.com) ([199.255.45.14]) by ob1.hgst.iphmx.com with ESMTP; 30 Apr 2019 03:58:12 +0800 IronPort-SDR: KuWhFv47et2z13s4ogsFydIuOHEUFbDE1H5YHCXxj4NfDq+KZzHYEVEcJQMz8xQKW9eH9uPC8A z50hSxMrHZud/+caVvYrkOs4WRFbqPfjdP8E5fiUv3LR80IKCHZ8SYZaqEbKIpoqY2AP6PEBcl cRKd9qF/baH9E304gOpH2aQ4FKzoAmmLKDwcBhY3GWBx0CJHd7JQkkEU4X0rEdRx8ZaURLE0Li odbp1pAhWh7W6nO/ewOr5Uywt+3wrsZ86wR0lhuqaI0qRA0NdPOBxWmnkXvmocrIiMOx6eTWFr pCKDGT6RqUPItX+jWyHzkvWj Received: from uls-op-cesaip01.wdc.com ([10.248.3.36]) by uls-op-cesaep01.wdc.com with ESMTP; 29 Apr 2019 12:34:35 -0700 IronPort-SDR: Bt0jcdD1gm6d1cRvYD8xLZ7OUU/7ALDxMP8bBhd/gEWwUm0ZOsyuoXKhnV/Htgbmrf1RFmzG5a KdmEWUvthppVLvTA/Wn2Wuh9DNVRFYVw78A+JrkdrPf+GhM2TyGnTWr7XZAa/3XETeB0z6VmGW Nr8nyyN1U1289sezewNwGRjArVhMrC560i55lAnYqYS4xUqANmVFYO1xUWVEonuy8UVyPN4UZY SpvkvHtvLuG2nrfaNqKYpDrYj+YxmwOv76nBf9H3mxnpjf3yRS75QhSJzUH0vhLsZUtfAEVqHj T54= Received: from jedi-01.sdcorp.global.sandisk.com (HELO jedi-01.int.fusionio.com) ([10.11.143.218]) by uls-op-cesaip01.wdc.com with ESMTP; 29 Apr 2019 12:58:11 -0700 From: Atish Patra To: linux-kernel@vger.kernel.org Cc: Atish Patra , Albert Ou , Andrew Morton , Anup Patel , Borislav Petkov , Changbin Du , Gary Guo , "H. Peter Anvin" , Ingo Molnar , Kees Cook , linux-mm@kvack.org, linux-riscv@lists.infradead.org, Luc Van Oostenryck , Palmer Dabbelt , Thomas Gleixner , Vlastimil Babka , x86@kernel.org (maintainer:X86 ARCHITECTURE (32-BIT AND 64-BIT)), Christoph Hellwig Subject: [PATCH v2 2/3] RISC-V: Enable TLBFLUSH counters for debug kernel. Date: Mon, 29 Apr 2019 12:57:58 -0700 Message-Id: <20190429195759.18330-3-atish.patra@wdc.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190429195759.18330-1-atish.patra@wdc.com> References: <20190429195759.18330-1-atish.patra@wdc.com> MIME-Version: 1.0 X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: X-Virus-Scanned: ClamAV using ClamSMTP The TLB flush counters under vmstat seems to be very helpful while debugging TLB flush performance in RISC-V. Add the Kconfig option only for debug kernels. Signed-off-by: Atish Patra --- arch/riscv/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index eb56c82d8aa1..c1ee876d1e7f 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -49,6 +49,7 @@ config RISCV select GENERIC_IRQ_MULTI_HANDLER select ARCH_HAS_PTE_SPECIAL select HAVE_EBPF_JIT if 64BIT + select HAVE_ARCH_DEBUG_TLBFLUSH if DEBUG_KERNEL config MMU def_bool y From patchwork Mon Apr 29 19:57:59 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Atish Patra X-Patchwork-Id: 10922453 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 5CAC914C0 for ; Mon, 29 Apr 2019 19:58:38 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 4D5B6288BA for ; Mon, 29 Apr 2019 19:58:38 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 4089528931; 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[68.232.141.245]) by mx.google.com with ESMTPS id c3si34040478plo.243.2019.04.29.12.58.31 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 29 Apr 2019 12:58:31 -0700 (PDT) Received-SPF: pass (google.com: domain of prvs=0155011cf=atish.patra@wdc.com designates 68.232.141.245 as permitted sender) client-ip=68.232.141.245; Authentication-Results: mx.google.com; dkim=pass header.i=@wdc.com header.s=dkim.wdc.com header.b=O7DKFuWY; spf=pass (google.com: domain of prvs=0155011cf=atish.patra@wdc.com designates 68.232.141.245 as permitted sender) smtp.mailfrom="prvs=0155011cf=atish.patra@wdc.com"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=wdc.com DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1556567911; x=1588103911; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=6yEgNpC7nkfK5Gt64tHVR1TWf8LgYKpoRswHlGybH9k=; b=O7DKFuWYml8vJpoTRORYQORsbSEYjSfwPFA+LajwawmCgWRz+2W9fcKo dOdbALnSU1azuu1Mjv8cMAkffDIispMdaOdPqfoSdXbv1JJon8eyTCCx6 1Cl0u7o+535YRkoeLolsj0bw1Hmv6sN3384Og1l6W4/2JfMm0AG/ubNne wqKS8TkznyN2lGJWHHMocgdeAMWnI0JVuD0zzi6loarbCvk0U5vT7e0Jj GCt/YRAZ1WQPOvt7ukLFJY0Z6Ds+D5B0yDb1y0zYdSFbwuz2r18XTmi2P a8JG3+D2Aa/Wymm0u8MDMxE8t3CUtug8Jd8ULICwzfLT7zisgZufRQw/3 w==; X-IronPort-AV: E=Sophos;i="5.60,410,1549900800"; d="scan'208";a="212999887" Received: from h199-255-45-14.hgst.com (HELO uls-op-cesaep01.wdc.com) ([199.255.45.14]) by ob1.hgst.iphmx.com with ESMTP; 30 Apr 2019 03:58:12 +0800 IronPort-SDR: 9R/3UsBlEX8q3Lm/gyzN3lfy9sq9BJ3QxRrhYSNxfkthtv/S2z0bqegVlyOgb2qoZbDwwWg4MI 6d98nyVrNTqGzlrLSihxxPfHkzDex9K+1acs1bVxD9YHBQg7/rwGu/75t4N85h+SxZLO6D7ych ThjZsKLMCgMQsxr2Nza0FG1ODnayjaUI+V18OYuEt4miSJI90qCkBpyyhdxNIBxPpAWLVgdynA GT1ZCgKuq2UfhkzsRb+pqAi6QrQ+wrVkIO2iz2TbPckhSoDxWpD1zGLlAX2hSQTt2I6NOBH0GS K/t+PJZXaBCtlYkLxmWx2wCU Received: from uls-op-cesaip01.wdc.com ([10.248.3.36]) by uls-op-cesaep01.wdc.com with ESMTP; 29 Apr 2019 12:34:35 -0700 IronPort-SDR: UFWPaNgFKiyS+kM5SJyaKOUbUteycQhA9GHu35ZdcqxcIAwpMq8jMx6cNKm2y61EvnKQIFA4g6 adyt71wuZeOe/j/KIJZpFB2cH7aaoEu+AewDQCjkARDNK6tKK3Ss/l+or3zUgnpe45r8pEQkIk Y4X8GvyOZtE6EMtIew7DWbZqn+xPD9yVsW1Tg3JnbklQSamvfjNHbVdnBrVnlis/LKUG2/sMoI J22J0Ee7szjf8iEwrssNPsTdXyQfMfR6jgh0cXur2FRS7yIgCImTKqhsa+TrLQ0cRGszY6tVQd xPQ= Received: from jedi-01.sdcorp.global.sandisk.com (HELO jedi-01.int.fusionio.com) ([10.11.143.218]) by uls-op-cesaip01.wdc.com with ESMTP; 29 Apr 2019 12:58:12 -0700 From: Atish Patra To: linux-kernel@vger.kernel.org Cc: Atish Patra , Albert Ou , Andrew Morton , Anup Patel , Borislav Petkov , Changbin Du , Gary Guo , "H. Peter Anvin" , Ingo Molnar , Kees Cook , linux-mm@kvack.org, linux-riscv@lists.infradead.org, Luc Van Oostenryck , Palmer Dabbelt , Thomas Gleixner , Vlastimil Babka , x86@kernel.org (maintainer:X86 ARCHITECTURE (32-BIT AND 64-BIT)), Christoph Hellwig Subject: [PATCH v2 3/3] RISC-V: Update tlb flush counters Date: Mon, 29 Apr 2019 12:57:59 -0700 Message-Id: <20190429195759.18330-4-atish.patra@wdc.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190429195759.18330-1-atish.patra@wdc.com> References: <20190429195759.18330-1-atish.patra@wdc.com> MIME-Version: 1.0 X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: X-Virus-Scanned: ClamAV using ClamSMTP The TLB flush counters under vmstat seems to be very helpful while debugging TLB flush performance in RISC-V. Update the counters in every TLB flush methods respectively. Signed-off-by: Atish Patra --- arch/riscv/include/asm/tlbflush.h | 5 +++++ arch/riscv/mm/tlbflush.c | 12 ++++++++++++ 2 files changed, 17 insertions(+) diff --git a/arch/riscv/include/asm/tlbflush.h b/arch/riscv/include/asm/tlbflush.h index 29a780ca232a..19779a083f52 100644 --- a/arch/riscv/include/asm/tlbflush.h +++ b/arch/riscv/include/asm/tlbflush.h @@ -9,6 +9,7 @@ #define _ASM_RISCV_TLBFLUSH_H #include +#include /* * Flush entire local TLB. 'sfence.vma' implicitly fences with the instruction @@ -16,11 +17,13 @@ */ static inline void local_flush_tlb_all(void) { + count_vm_tlb_event(NR_TLB_LOCAL_FLUSH_ALL); __asm__ __volatile__ ("sfence.vma" : : : "memory"); } static inline void local_flush_tlb_mm(struct mm_struct *mm) { + count_vm_tlb_event(NR_TLB_LOCAL_FLUSH_ALL); /* Flush ASID 0 so that global mappings are not affected */ __asm__ __volatile__ ("sfence.vma x0, %0" : : "r" (0) : "memory"); } @@ -28,6 +31,7 @@ static inline void local_flush_tlb_mm(struct mm_struct *mm) static inline void local_flush_tlb_page(struct vm_area_struct *vma, unsigned long addr) { + count_vm_tlb_event(NR_TLB_LOCAL_FLUSH_ONE); __asm__ __volatile__ ("sfence.vma %0, %1" : : "r" (addr), "r" (0) : "memory"); @@ -35,6 +39,7 @@ static inline void local_flush_tlb_page(struct vm_area_struct *vma, static inline void local_flush_tlb_kernel_page(unsigned long addr) { + count_vm_tlb_event(NR_TLB_LOCAL_FLUSH_ONE); __asm__ __volatile__ ("sfence.vma %0" : : "r" (addr) : "memory"); } diff --git a/arch/riscv/mm/tlbflush.c b/arch/riscv/mm/tlbflush.c index ceee76f14a0a..8072d7da32bb 100644 --- a/arch/riscv/mm/tlbflush.c +++ b/arch/riscv/mm/tlbflush.c @@ -4,6 +4,8 @@ */ #include +#include +#include #include #define SFENCE_VMA_FLUSH_ALL ((unsigned long) -1) @@ -110,6 +112,7 @@ static void ipi_remote_sfence_vma(void *info) unsigned long size = data->size; unsigned long i; + count_vm_tlb_event(NR_TLB_REMOTE_FLUSH_RECEIVED); if (size == SFENCE_VMA_FLUSH_ALL) { local_flush_tlb_all(); } @@ -129,6 +132,8 @@ static void ipi_remote_sfence_vma_asid(void *info) unsigned long size = data->size; unsigned long i; + count_vm_tlb_event(NR_TLB_REMOTE_FLUSH_RECEIVED); + /* Flush entire MM context */ if (size == SFENCE_VMA_FLUSH_ALL) { __asm__ __volatile__ ("sfence.vma x0, %0" : : "r" (asid) @@ -158,6 +163,13 @@ static void remote_sfence_vma(unsigned long start, unsigned long size) static void remote_sfence_vma_asid(cpumask_t *mask, unsigned long start, unsigned long size, unsigned long asid) { + int cpuid = smp_processor_id(); + + if (cpumask_equal(mask, cpumask_of(cpuid))) + count_vm_tlb_event(NR_TLB_LOCAL_FLUSH_ALL); + else + count_vm_tlb_event(NR_TLB_REMOTE_FLUSH); + if (tlbi_ipi) { struct tlbi info = { .start = start,