From patchwork Mon Apr 29 21:27:48 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Atish Patra X-Patchwork-Id: 10922515 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 032CE933 for ; Mon, 29 Apr 2019 21:28:07 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id E5BF8284F9 for ; Mon, 29 Apr 2019 21:28:06 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id D95E128998; Mon, 29 Apr 2019 21:28:06 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED autolearn=unavailable version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 7EB8D2862A for ; Mon, 29 Apr 2019 21:28:06 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=e6m+z4ZzbhaDnaG2XTUm9HkwTIMgzx45h2DFb1TY+UY=; b=tfJimpTVLDCjel L2Vm+8KNbb0SU8CkxMP5Jm6dBWqvpEBtj2fSyW/oH2sK2gzNDD1jwdP16J1pvlRrQJbb+BU3GDFlB dpcyeUnU9TWtI5CGAIGOX3iq8DUqypQE0FdfVAYTZK5AJAlYrFa81UTPKr7i5cbdRdo4TjpG13UnL IXCwjb+Yre8KwAtpzCk4iVDER7eeW8eYYX5ghUHcmzj8QwkoVXtt6zV6molfOh5YbCYC1Zf4/O3lG Zm5fU1UKfzAuooxIqXdFrNs3NZmec58+K8pNYGs6LMdi4owzuwljZHzAKfNxHswtAOeLlrMqkh8AH FndBUNDnd7qQ+Ova7mfA==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1hLDof-0000xI-NK; Mon, 29 Apr 2019 21:28:01 +0000 Received: from esa4.hgst.iphmx.com ([216.71.154.42]) by bombadil.infradead.org with esmtps (Exim 4.90_1 #2 (Red Hat Linux)) id 1hLDoc-0000vm-Fy for linux-riscv@lists.infradead.org; Mon, 29 Apr 2019 21:28:00 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1556573279; x=1588109279; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=tR6tu/boLUZjadiHISW1+7oshhH05ZDXJ3aIDITiz8w=; b=oLhGoXHlQ2EjQWL4hJ1b5lrbOirm5wP6rm8fniu1hMTirGX7bS4oNKE9 ezYJe/dFEVyn37h6QobIHdYIDHmL2m1P3XR0RpaSdg/svBggnYc2GRr3g qpCtsUe18bGtbUKRD9nH0LWVCHVb5kij0WtlHIJEK7Frq6h9l8LUdIIZX /NhBNBljmi/YqQ1kNJNJRUVyvxQDXsQCE4jy+4LgDItBVCQJue1yrLmOl R+4OvKSC5jB6LIy0JVqVLU4kSobS+Ae4ct5LV8mdkBkkCMIiPVjyw8QMi XPBbmTEUWO9zjTZ7ay8Bi6pgCJ06UQ0Aqy/KY3jNiIRkwXKB4B9/Gyvqd Q==; X-IronPort-AV: E=Sophos;i="5.60,411,1549900800"; d="scan'208";a="107107926" Received: from h199-255-45-15.hgst.com (HELO uls-op-cesaep02.wdc.com) ([199.255.45.15]) by ob1.hgst.iphmx.com with ESMTP; 30 Apr 2019 05:27:56 +0800 IronPort-SDR: mSLoDWMfPBCtwjKHzrn6IhLKpF8NdMLqpW63Hqzl+IP+Q6TJiFp8xA98yB3OHPnepgPo50VEpa pFELQB3DggG3bqgYHAVaC1DLStrfvCuGl1U4iFXzqZKdPQGIji6jA/KFuzfO4iS3kXXF4kVCCj 1jX7IxU4Azwa3/AIEm8lq76htWwqCKCWH6aKPLMW1FFtQfTvCR04I5YACoRuBRikpPjoQSgQJI 16hZ6KymsGy95cZQiDq2GHMlW5mcTSU3Bm3CxXSOL4Gv06wd+RK/s1Rsgf+3ygj1CFxJJRfPBh QD+Jhc/5aRkCPqdZId1+QXo6 Received: from uls-op-cesaip02.wdc.com ([10.248.3.37]) by uls-op-cesaep02.wdc.com with ESMTP; 29 Apr 2019 14:06:27 -0700 IronPort-SDR: vbYbPQo4JkJT9Bw0pHc9exinGYDWPnbSJXW9OLyStr6Ikua7imsg7WGL9OFLdpmqGZYjTYx4JR SlQ0ebyX4o3dktLi0pIW6wZ572FFPS4eEpARRdDJ5E6EgXE9NuAFcgQ6LmSZMAeAsKsw3A1pol Z6mvT2BqJX45lL9lr9CS67zyQFTC61d6y2n2mWaugkXK+yxgesD/SEzWnHXi11nISjMimlDbwv J+yaXneSbTiDtMFpy97ZI5749qNhEvodmfVdlmVrU50MSSmw2w40zd0YHjYCC3ZZISmvcb5/Ci WGc= Received: from jedi-01.sdcorp.global.sandisk.com (HELO jedi-01.int.fusionio.com) ([10.11.143.218]) by uls-op-cesaip02.wdc.com with ESMTP; 29 Apr 2019 14:27:56 -0700 From: Atish Patra To: linux-kernel@vger.kernel.org Subject: [PATCH v3 1/3] x86: Move DEBUG_TLBFLUSH option. Date: Mon, 29 Apr 2019 14:27:48 -0700 Message-Id: <20190429212750.26165-2-atish.patra@wdc.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190429212750.26165-1-atish.patra@wdc.com> References: <20190429212750.26165-1-atish.patra@wdc.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190429_142758_600817_C251F87A X-CRM114-Status: GOOD ( 14.73 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Christoph Hellwig , Albert Ou , Thomas Gleixner , Kees Cook , Changbin Du , Anup Patel , Palmer Dabbelt , "maintainer:X86 ARCHITECTURE 32-BIT AND 64-BIT" , linux-mm@kvack.org, Atish Patra , Ingo Molnar , Borislav Petkov , Vlastimil Babka , Gary Guo , "H. Peter Anvin" , Andrew Morton , linux-riscv@lists.infradead.org, Luc Van Oostenryck Sender: "linux-riscv" Errors-To: linux-riscv-bounces+patchwork-linux-riscv=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP CONFIG_DEBUG_TLBFLUSH was added in 'commit 3df3212f9722 ("x86/tlb: add tlb_flushall_shift knob into debugfs")' to support tlb_flushall_shift knob. The knob was removed in 'commit e9f4e0a9fe27 ("x86/mm: Rip out complicated, out-of-date, buggy TLB flushing")'. However, the debug option was never removed from Kconfig. It was reused in commit '9824cf9753ec ("mm: vmstats: tlb flush counters")' but the commit text was never updated accordingly. Update the Kconfig option description as per its current usage. Take this opportunity to make this kconfig option a common option as it touches the common vmstat code. Introduce another arch specific config HAVE_ARCH_DEBUG_TLBFLUSH that can be selected to enable this config. Signed-off-by: Atish Patra --- arch/x86/Kconfig | 1 + arch/x86/Kconfig.debug | 19 ------------------- mm/Kconfig.debug | 13 +++++++++++++ 3 files changed, 14 insertions(+), 19 deletions(-) diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 62fc3fda1a05..4c59f59e9491 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -132,6 +132,7 @@ config X86 select HAVE_ARCH_TRANSPARENT_HUGEPAGE_PUD if X86_64 select HAVE_ARCH_VMAP_STACK if X86_64 select HAVE_ARCH_WITHIN_STACK_FRAMES + select HAVE_ARCH_DEBUG_TLBFLUSH if DEBUG_KERNEL select HAVE_CMPXCHG_DOUBLE select HAVE_CMPXCHG_LOCAL select HAVE_CONTEXT_TRACKING if X86_64 diff --git a/arch/x86/Kconfig.debug b/arch/x86/Kconfig.debug index 15d0fbe27872..0c8f9931e901 100644 --- a/arch/x86/Kconfig.debug +++ b/arch/x86/Kconfig.debug @@ -124,25 +124,6 @@ config DOUBLEFAULT option saves about 4k and might cause you much additional grey hair. -config DEBUG_TLBFLUSH - bool "Set upper limit of TLB entries to flush one-by-one" - depends on DEBUG_KERNEL - ---help--- - - X86-only for now. - - This option allows the user to tune the amount of TLB entries the - kernel flushes one-by-one instead of doing a full TLB flush. In - certain situations, the former is cheaper. This is controlled by the - tlb_flushall_shift knob under /sys/kernel/debug/x86. If you set it - to -1, the code flushes the whole TLB unconditionally. Otherwise, - for positive values of it, the kernel will use single TLB entry - invalidating instructions according to the following formula: - - flush_entries <= active_tlb_entries / 2^tlb_flushall_shift - - If in doubt, say "N". - config IOMMU_DEBUG bool "Enable IOMMU debugging" depends on GART_IOMMU && DEBUG_KERNEL diff --git a/mm/Kconfig.debug b/mm/Kconfig.debug index e3df921208c0..e8622b26f0c2 100644 --- a/mm/Kconfig.debug +++ b/mm/Kconfig.debug @@ -111,3 +111,16 @@ config DEBUG_RODATA_TEST depends on STRICT_KERNEL_RWX ---help--- This option enables a testcase for the setting rodata read-only. + +config HAVE_ARCH_DEBUG_TLBFLUSH + bool + depends on DEBUG_KERNEL + +config DEBUG_TLBFLUSH + bool "Save tlb flush statistics to vmstat" + depends on HAVE_ARCH_DEBUG_TLBFLUSH + help + + Add tlbflush statistics to vmstat. It is really helpful understand tlbflush + performance and behavior. It should be enabled only for debugging purpose + by individual architectures explicitly by selecting HAVE_ARCH_DEBUG_TLBFLUSH. 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Date: Mon, 29 Apr 2019 14:27:49 -0700 Message-Id: <20190429212750.26165-3-atish.patra@wdc.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190429212750.26165-1-atish.patra@wdc.com> References: <20190429212750.26165-1-atish.patra@wdc.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190429_142800_318074_788AFEFC X-CRM114-Status: GOOD ( 10.73 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Christoph Hellwig , Albert Ou , Thomas Gleixner , Kees Cook , Changbin Du , Anup Patel , Palmer Dabbelt , "maintainer:X86 ARCHITECTURE 32-BIT AND 64-BIT" , linux-mm@kvack.org, Atish Patra , Ingo Molnar , Borislav Petkov , Vlastimil Babka , Gary Guo , "H. Peter Anvin" , Andrew Morton , linux-riscv@lists.infradead.org, Luc Van Oostenryck Sender: "linux-riscv" Errors-To: linux-riscv-bounces+patchwork-linux-riscv=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP The TLB flush counters under vmstat seems to be very helpful while debugging TLB flush performance in RISC-V. Add the Kconfig option only for debug kernels. Signed-off-by: Atish Patra --- arch/riscv/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index eb56c82d8aa1..c1ee876d1e7f 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -49,6 +49,7 @@ config RISCV select GENERIC_IRQ_MULTI_HANDLER select ARCH_HAS_PTE_SPECIAL select HAVE_EBPF_JIT if 64BIT + select HAVE_ARCH_DEBUG_TLBFLUSH if DEBUG_KERNEL config MMU def_bool y From patchwork Mon Apr 29 21:27:50 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Atish Patra X-Patchwork-Id: 10922521 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id DA6E814C0 for ; Mon, 29 Apr 2019 21:28:09 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id CC033284F9 for ; Mon, 29 Apr 2019 21:28:09 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id BFD2028998; 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29 Apr 2019 14:06:27 -0700 IronPort-SDR: AeMSfyunL2LsJhLHPw2d6fgcuYcVNj32UjjthqEnf0K3EjrF0GfZMDuDh2OiloNPAlz1aVw0i+ rx3dfrB4ctlfgfcrvEiWMY+xU/qL+lKYERo0bkL1QP8bZFPZXWNmK7AHG7clayjGa0Lj8ENMyx 1wOmvOtnbDL3ngbhjQJ8wQKU3EyfHbxJyNq4JwOyOf6ZFZT8aE5nKv3MOFwnA7Y9OWIXRSIzTU D9skxvS/yaP+Q4I3XwxKDgiOXhch58PXoMJmzb/ezPJ2i0WDiO2HBIWmE1psz19MgvK5WqcNgm V3M= Received: from jedi-01.sdcorp.global.sandisk.com (HELO jedi-01.int.fusionio.com) ([10.11.143.218]) by uls-op-cesaip02.wdc.com with ESMTP; 29 Apr 2019 14:27:57 -0700 From: Atish Patra To: linux-kernel@vger.kernel.org Subject: [PATCH v3 3/3] RISC-V: Update tlb flush counters Date: Mon, 29 Apr 2019 14:27:50 -0700 Message-Id: <20190429212750.26165-4-atish.patra@wdc.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190429212750.26165-1-atish.patra@wdc.com> References: <20190429212750.26165-1-atish.patra@wdc.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190429_142800_465043_B7E620E4 X-CRM114-Status: GOOD ( 12.56 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Christoph Hellwig , Albert Ou , Thomas Gleixner , Kees Cook , Changbin Du , Anup Patel , Palmer Dabbelt , "maintainer:X86 ARCHITECTURE 32-BIT AND 64-BIT" , linux-mm@kvack.org, Atish Patra , Ingo Molnar , Borislav Petkov , Vlastimil Babka , Gary Guo , "H. Peter Anvin" , Andrew Morton , linux-riscv@lists.infradead.org, Luc Van Oostenryck Sender: "linux-riscv" Errors-To: linux-riscv-bounces+patchwork-linux-riscv=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP The TLB flush counters under vmstat seems to be very helpful while debugging TLB flush performance in RISC-V. Update the counters in every TLB flush methods respectively. Signed-off-by: Atish Patra --- arch/riscv/include/asm/tlbflush.h | 5 +++++ arch/riscv/mm/tlbflush.c | 12 ++++++++++++ 2 files changed, 17 insertions(+) diff --git a/arch/riscv/include/asm/tlbflush.h b/arch/riscv/include/asm/tlbflush.h index 29a780ca232a..19779a083f52 100644 --- a/arch/riscv/include/asm/tlbflush.h +++ b/arch/riscv/include/asm/tlbflush.h @@ -9,6 +9,7 @@ #define _ASM_RISCV_TLBFLUSH_H #include +#include /* * Flush entire local TLB. 'sfence.vma' implicitly fences with the instruction @@ -16,11 +17,13 @@ */ static inline void local_flush_tlb_all(void) { + count_vm_tlb_event(NR_TLB_LOCAL_FLUSH_ALL); __asm__ __volatile__ ("sfence.vma" : : : "memory"); } static inline void local_flush_tlb_mm(struct mm_struct *mm) { + count_vm_tlb_event(NR_TLB_LOCAL_FLUSH_ALL); /* Flush ASID 0 so that global mappings are not affected */ __asm__ __volatile__ ("sfence.vma x0, %0" : : "r" (0) : "memory"); } @@ -28,6 +31,7 @@ static inline void local_flush_tlb_mm(struct mm_struct *mm) static inline void local_flush_tlb_page(struct vm_area_struct *vma, unsigned long addr) { + count_vm_tlb_event(NR_TLB_LOCAL_FLUSH_ONE); __asm__ __volatile__ ("sfence.vma %0, %1" : : "r" (addr), "r" (0) : "memory"); @@ -35,6 +39,7 @@ static inline void local_flush_tlb_page(struct vm_area_struct *vma, static inline void local_flush_tlb_kernel_page(unsigned long addr) { + count_vm_tlb_event(NR_TLB_LOCAL_FLUSH_ONE); __asm__ __volatile__ ("sfence.vma %0" : : "r" (addr) : "memory"); } diff --git a/arch/riscv/mm/tlbflush.c b/arch/riscv/mm/tlbflush.c index ceee76f14a0a..8072d7da32bb 100644 --- a/arch/riscv/mm/tlbflush.c +++ b/arch/riscv/mm/tlbflush.c @@ -4,6 +4,8 @@ */ #include +#include +#include #include #define SFENCE_VMA_FLUSH_ALL ((unsigned long) -1) @@ -110,6 +112,7 @@ static void ipi_remote_sfence_vma(void *info) unsigned long size = data->size; unsigned long i; + count_vm_tlb_event(NR_TLB_REMOTE_FLUSH_RECEIVED); if (size == SFENCE_VMA_FLUSH_ALL) { local_flush_tlb_all(); } @@ -129,6 +132,8 @@ static void ipi_remote_sfence_vma_asid(void *info) unsigned long size = data->size; unsigned long i; + count_vm_tlb_event(NR_TLB_REMOTE_FLUSH_RECEIVED); + /* Flush entire MM context */ if (size == SFENCE_VMA_FLUSH_ALL) { __asm__ __volatile__ ("sfence.vma x0, %0" : : "r" (asid) @@ -158,6 +163,13 @@ static void remote_sfence_vma(unsigned long start, unsigned long size) static void remote_sfence_vma_asid(cpumask_t *mask, unsigned long start, unsigned long size, unsigned long asid) { + int cpuid = smp_processor_id(); + + if (cpumask_equal(mask, cpumask_of(cpuid))) + count_vm_tlb_event(NR_TLB_LOCAL_FLUSH_ALL); + else + count_vm_tlb_event(NR_TLB_REMOTE_FLUSH); + if (tlbi_ipi) { struct tlbi info = { .start = start,