From patchwork Tue Apr 30 08:50:55 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Henry Chen X-Patchwork-Id: 10923103 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 1B9D11390 for ; Tue, 30 Apr 2019 09:47:53 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 09F1628A6A for ; Tue, 30 Apr 2019 09:47:53 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id F065628A7A; Tue, 30 Apr 2019 09:47:52 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED,UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id A00DE28A6A for ; Tue, 30 Apr 2019 09:47:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=V8o/fNgOMxmWcQUsipSGpvUmJY5tKadxTyF/693V1uE=; b=qSCrs5LhSO1J3d RB20XJ1uEoKXyKdIL596q/fcrEAzg+B9QAeoH8TgrCPxsSKMHnTISwW6hzF0tRlaqYSvFcqRLGAmD FT4K7qsvgCfNq6LE8/zerraBqXz06oE7eamaJmTv31p80xGzhgWkYFV5s5Zr4Rz0mmkc4mrDbKypn TbAYlckZ5HjU+ePR0aeFMVizmbhK+dsSR2lOF95EQTTpr8yB2E9gjeWYSbyJU1mvPqvIqVUvnLnM+ yv8yuTmdvcbOppMcb42HX8d5V8hMd/FAjGGp078Jr7bwHeIhG3WTcgSSLhop7m5XyjkRTGQ8GK4Lx msRYEZayRCAYotnE1gmg==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1hLPMY-0002U0-2e; Tue, 30 Apr 2019 09:47:46 +0000 Received: from mailgw01.mediatek.com ([216.200.240.184]) by bombadil.infradead.org with esmtps (Exim 4.90_1 #2 (Red Hat Linux)) id 1hLPKg-0000ZQ-Tr; Tue, 30 Apr 2019 09:46:00 +0000 X-UUID: 8213b39f0efe4363be6d6a5951cfa007-20190430 X-UUID: 8213b39f0efe4363be6d6a5951cfa007-20190430 Received: from mtkcas66.mediatek.inc [(172.29.193.44)] by mailgw01.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLS) with ESMTP id 849074116; Tue, 30 Apr 2019 01:45:34 -0800 Received: from MTKMBS02N1.mediatek.inc (172.21.101.77) by MTKMBS62DR.mediatek.inc (172.29.94.18) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Tue, 30 Apr 2019 02:45:32 -0700 Received: from mtkcas09.mediatek.inc (172.21.101.178) by mtkmbs02n1.mediatek.inc (172.21.101.77) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Tue, 30 Apr 2019 17:45:18 +0800 Received: from mtkslt205.mediatek.inc (10.21.15.75) by mtkcas09.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Tue, 30 Apr 2019 17:45:19 +0800 From: Henry Chen To: Georgi Djakov , Rob Herring , Matthias Brugger , Viresh Kumar , Stephen Boyd Subject: [RFC V2 01/11] dt-bindings: soc: Add dvfsrc driver bindings Date: Tue, 30 Apr 2019 16:50:55 +0800 Message-ID: <1556614265-12745-2-git-send-email-henryc.chen@mediatek.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1556614265-12745-1-git-send-email-henryc.chen@mediatek.com> References: <1556614265-12745-1-git-send-email-henryc.chen@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190430_024551_365528_8C8D7DC2 X-CRM114-Status: GOOD ( 12.73 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: James Liao , Weiyi Lu , Nicolas Boichat , linux-kernel@vger.kernel.org, Henry Chen , Fan Chen , devicetree@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Document the binding for enabling dvfsrc on MediaTek SoC. Signed-off-by: Henry Chen Reviewed-by: Rob Herring --- .../devicetree/bindings/soc/mediatek/dvfsrc.txt | 23 ++++++++++++++++++++++ include/dt-bindings/soc/mtk,dvfsrc.h | 14 +++++++++++++ 2 files changed, 37 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/mediatek/dvfsrc.txt create mode 100644 include/dt-bindings/soc/mtk,dvfsrc.h diff --git a/Documentation/devicetree/bindings/soc/mediatek/dvfsrc.txt b/Documentation/devicetree/bindings/soc/mediatek/dvfsrc.txt new file mode 100644 index 0000000..7f43499 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/mediatek/dvfsrc.txt @@ -0,0 +1,23 @@ +MediaTek DVFSRC + +The Dynamic Voltage and Frequency Scaling Resource Collector (DVFSRC) is a +HW module which is used to collect all the requests from both software and +hardware and turn into the decision of minimum operating voltage and minimum +DRAM frequency to fulfill those requests. + +Required Properties: +- compatible: Should be one of the following + - "mediatek,mt8183-dvfsrc": For MT8183 SoC +- reg: Address range of the DVFSRC unit +- clock-names: Must include the following entries: + "dvfsrc": DVFSRC module clock +- clocks: Must contain an entry for each entry in clock-names. + +Example: + + dvfsrc@10012000 { + compatible = "mediatek,mt8183-dvfsrc"; + reg = <0 0x10012000 0 0x1000>; + clocks = <&infracfg CLK_INFRA_DVFSRC>; + clock-names = "dvfsrc"; + }; diff --git a/include/dt-bindings/soc/mtk,dvfsrc.h b/include/dt-bindings/soc/mtk,dvfsrc.h new file mode 100644 index 0000000..a522488 --- /dev/null +++ b/include/dt-bindings/soc/mtk,dvfsrc.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright (c) 2018 MediaTek Inc. + */ + +#ifndef _DT_BINDINGS_POWER_MTK_DVFSRC_H +#define _DT_BINDINGS_POWER_MTK_DVFSRC_H + +#define MT8183_DVFSRC_LEVEL_1 1 +#define MT8183_DVFSRC_LEVEL_2 2 +#define MT8183_DVFSRC_LEVEL_3 3 +#define MT8183_DVFSRC_LEVEL_4 4 + +#endif /* _DT_BINDINGS_POWER_MTK_DVFSRC_H */ From patchwork Tue Apr 30 08:50:56 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Henry Chen X-Patchwork-Id: 10923071 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 96F37933 for ; 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h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=A/ANZfH3EAUpnk/kYhkxFpbVPJeZam98zgD5sOZ5PSM=; b=pFP4DuxBTjzp+0 Aqtkiu87nTjEdQBgDLMfyXmdnKze2pDz15puUxxBBK9YRBT+6CUOl4hxvEG9CD2YstivfjDNmkq5l gvHq9mPCCf+KY9TwHpIuTM3kiarCoNXTJi86BC7xHpir3HhkmlCUTLRMmy/sFSvfNVQzSdG5Kt3t1 kHi25LY4eGYn8SJ+6vbkrUzZ6Zbg77/mtwKiZ0dIQ7RmiR77BnhJqX70NYK6v7n8MaRj801mwN1tO bGjLoErnk/8uOVftO+sk/cM9qrqNqWZy3uvcgePQle7yuVyE7yfY/idvQzt/zoNAaA9Bfg8NteS+Q uSrofJlIB3KHHnbfVtXQ==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1hLPKO-000099-RL; Tue, 30 Apr 2019 09:45:32 +0000 Received: from mailgw01.mediatek.com ([216.200.240.184]) by bombadil.infradead.org with esmtps (Exim 4.90_1 #2 (Red Hat Linux)) id 1hLPKJ-000050-QO; Tue, 30 Apr 2019 09:45:29 +0000 X-UUID: 225b930a55594d29b8f473eef186b34a-20190430 X-UUID: 225b930a55594d29b8f473eef186b34a-20190430 Received: from mtkcas67.mediatek.inc [(172.29.193.45)] by mailgw01.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLS) with ESMTP id 1074161395; Tue, 30 Apr 2019 01:45:23 -0800 Received: from MTKMBS01N2.mediatek.inc (172.21.101.79) by MTKMBS62N2.mediatek.inc (172.29.193.42) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Tue, 30 Apr 2019 02:45:21 -0700 Received: from mtkcas09.mediatek.inc (172.21.101.178) by mtkmbs01n2.mediatek.inc (172.21.101.79) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Tue, 30 Apr 2019 17:45:19 +0800 Received: from mtkslt205.mediatek.inc (10.21.15.75) by mtkcas09.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Tue, 30 Apr 2019 17:45:19 +0800 From: Henry Chen To: Georgi Djakov , Rob Herring , Matthias Brugger , Viresh Kumar , Stephen Boyd Subject: [RFC V2 02/11] dt-bindings: soc: Add opp table on scpsys bindings Date: Tue, 30 Apr 2019 16:50:56 +0800 Message-ID: <1556614265-12745-3-git-send-email-henryc.chen@mediatek.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1556614265-12745-1-git-send-email-henryc.chen@mediatek.com> References: <1556614265-12745-1-git-send-email-henryc.chen@mediatek.com> MIME-Version: 1.0 X-TM-SNTS-SMTP: A0192DEC0B2A71B838B3E54F8F346560A9AFF8FE1F4F8B11C656FF1C2F1997332000:8 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190430_024527_857408_06218472 X-CRM114-Status: UNSURE ( 8.05 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: James Liao , Weiyi Lu , Nicolas Boichat , linux-kernel@vger.kernel.org, Henry Chen , Fan Chen , devicetree@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Add opp table on scpsys dt-bindings for Mediatek SoC. Signed-off-by: Henry Chen Reviewed-by: Rob Herring --- .../devicetree/bindings/soc/mediatek/scpsys.txt | 42 ++++++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt b/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt index b4728ce..33df802 100644 --- a/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt +++ b/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt @@ -63,6 +63,10 @@ Optional properties: - mfg_2d-supply: Power supply for the mfg_2d power domain - mfg-supply: Power supply for the mfg power domain +- operating-points-v2: Phandle to the OPP table for the Power domain. + Refer to Documentation/devicetree/bindings/power/power_domain.txt + and Documentation/devicetree/bindings/opp/opp.txt for more details + Example: scpsys: scpsys@10006000 { @@ -75,6 +79,27 @@ Example: <&topckgen CLK_TOP_VENC_SEL>, <&topckgen CLK_TOP_VENC_LT_SEL>; clock-names = "mfg", "mm", "venc", "venc_lt"; + operating-points-v2 = <&dvfsrc_opp_table>; + + dvfsrc_opp_table: opp-table { + compatible = "operating-points-v2-level"; + + dvfsrc_vol_min: opp1 { + opp,level = ; + }; + + dvfsrc_freq_medium: opp2 { + opp,level = ; + }; + + dvfsrc_freq_max: opp3 { + opp,level = ; + }; + + dvfsrc_vol_max: opp4 { + opp,level = ; + }; + }; }; Example consumer: @@ -82,4 +107,21 @@ Example consumer: afe: mt8173-afe-pcm@11220000 { compatible = "mediatek,mt8173-afe-pcm"; power-domains = <&scpsys MT8173_POWER_DOMAIN_AUDIO>; + operating-points-v2 = <&aud_opp_table>; + }; + + aud_opp_table: aud-opp-table { + compatible = "operating-points-v2"; + opp1 { + opp-hz = /bits/ 64 <793000000>; + required-opps = <&dvfsrc_vol_min>; + }; + opp2 { + opp-hz = /bits/ 64 <910000000>; + required-opps = <&dvfsrc_vol_max>; + }; + opp3 { + opp-hz = /bits/ 64 <1014000000>; + required-opps = <&dvfsrc_vol_max>; + }; }; From patchwork Tue Apr 30 08:50:57 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Henry Chen X-Patchwork-Id: 10923073 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 87166933 for ; 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Tue, 30 Apr 2019 09:45:29 +0000 X-UUID: 05a7876a754f43838c4b4f78faf92ef9-20190430 X-UUID: 05a7876a754f43838c4b4f78faf92ef9-20190430 Received: from mtkcas67.mediatek.inc [(172.29.193.45)] by mailgw01.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLS) with ESMTP id 814310092; Tue, 30 Apr 2019 01:45:23 -0800 Received: from MTKMBS02N2.mediatek.inc (172.21.101.101) by MTKMBS62N2.mediatek.inc (172.29.193.42) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Tue, 30 Apr 2019 02:45:21 -0700 Received: from mtkcas09.mediatek.inc (172.21.101.178) by mtkmbs02n2.mediatek.inc (172.21.101.101) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Tue, 30 Apr 2019 17:45:19 +0800 Received: from mtkslt205.mediatek.inc (10.21.15.75) by mtkcas09.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Tue, 30 Apr 2019 17:45:19 +0800 From: Henry Chen To: Georgi Djakov , Rob Herring , Matthias Brugger , Viresh Kumar , Stephen Boyd Subject: [RFC V2 03/11] soc: mediatek: add support for the performance state Date: Tue, 30 Apr 2019 16:50:57 +0800 Message-ID: <1556614265-12745-4-git-send-email-henryc.chen@mediatek.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1556614265-12745-1-git-send-email-henryc.chen@mediatek.com> References: <1556614265-12745-1-git-send-email-henryc.chen@mediatek.com> MIME-Version: 1.0 X-TM-SNTS-SMTP: 3237D3CA08FF8E8F307433A610F0F2EB87419DAB5EF29E037680A1C513F1CA872000:8 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190430_024527_922338_24C60EE7 X-CRM114-Status: GOOD ( 16.09 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: James Liao , Weiyi Lu , Nicolas Boichat , linux-kernel@vger.kernel.org, Henry Chen , Fan Chen , devicetree@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Support power domain performance state, add header file for scp event. Signed-off-by: Henry Chen --- drivers/soc/mediatek/mtk-scpsys.c | 53 +++++++++++++++++++++++++++++++++++++++ drivers/soc/mediatek/mtk-scpsys.h | 22 ++++++++++++++++ 2 files changed, 75 insertions(+) create mode 100644 drivers/soc/mediatek/mtk-scpsys.h diff --git a/drivers/soc/mediatek/mtk-scpsys.c b/drivers/soc/mediatek/mtk-scpsys.c index f1d82cd..be8c948 100644 --- a/drivers/soc/mediatek/mtk-scpsys.c +++ b/drivers/soc/mediatek/mtk-scpsys.c @@ -10,7 +10,9 @@ #include #include #include +#include #include +#include #include #include @@ -21,6 +23,7 @@ #include #include #include +#include "mtk-scpsys.h" #define MTK_POLL_DELAY_US 10 #define MTK_POLL_TIMEOUT USEC_PER_SEC @@ -188,6 +191,18 @@ struct scp_soc_data { bool bus_prot_reg_update; }; +static BLOCKING_NOTIFIER_HEAD(scpsys_notifier_list); + +int register_scpsys_notifier(struct notifier_block *nb) +{ + return blocking_notifier_chain_register(&scpsys_notifier_list, nb); +} + +int unregister_scpsys_notifier(struct notifier_block *nb) +{ + return blocking_notifier_chain_unregister(&scpsys_notifier_list, nb); +} + static int scpsys_domain_is_on(struct scp_domain *scpd) { struct scp *scp = scpd->scp; @@ -519,6 +534,41 @@ static void init_clks(struct platform_device *pdev, struct clk **clk) clk[i] = devm_clk_get(&pdev->dev, clk_names[i]); } +static int mtk_pd_set_performance(struct generic_pm_domain *genpd, + unsigned int state) +{ + int i; + struct scp_domain *scpd = + container_of(genpd, struct scp_domain, genpd); + struct scp_event_data scpe; + struct scp *scp = scpd->scp; + struct genpd_onecell_data *pd_data = &scp->pd_data; + + for (i = 0; i < pd_data->num_domains; i++) { + if (genpd == pd_data->domains[i]) { + dev_dbg(scp->dev, "%d. %s = %d\n", + i, genpd->name, state); + break; + } + } + + if (i == pd_data->num_domains) + return 0; + + scpe.event_type = MTK_SCPSYS_PSTATE; + scpe.genpd = genpd; + scpe.domain_id = i; + blocking_notifier_call_chain(&scpsys_notifier_list, state, &scpe); + + return 0; +} + +static unsigned int mtk_pd_get_performance(struct generic_pm_domain *genpd, + struct dev_pm_opp *opp) +{ + return dev_pm_opp_get_level(opp); +} + static struct scp *init_scp(struct platform_device *pdev, const struct scp_domain_data *scp_domain_data, int num, const struct scp_ctrl_reg *scp_ctrl_reg, @@ -642,6 +692,9 @@ static struct scp *init_scp(struct platform_device *pdev, genpd->power_on = scpsys_power_on; if (MTK_SCPD_CAPS(scpd, MTK_SCPD_ACTIVE_WAKEUP)) genpd->flags |= GENPD_FLAG_ACTIVE_WAKEUP; + + genpd->set_performance_state = mtk_pd_set_performance; + genpd->opp_to_performance_state = mtk_pd_get_performance; } return scp; diff --git a/drivers/soc/mediatek/mtk-scpsys.h b/drivers/soc/mediatek/mtk-scpsys.h new file mode 100644 index 0000000..c1e8325 --- /dev/null +++ b/drivers/soc/mediatek/mtk-scpsys.h @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright (c) 2018 MediaTek Inc. + */ + +#ifndef __MTK_SCPSYS_H__ +#define __MTK_SCPSYS_H__ + +struct scp_event_data { + int event_type; + int domain_id; + struct generic_pm_domain *genpd; +}; + +enum scp_event_type { + MTK_SCPSYS_PSTATE, +}; + +int register_scpsys_notifier(struct notifier_block *nb); +int unregister_scpsys_notifier(struct notifier_block *nb); + +#endif /* __MTK_SCPSYS_H__ */ From patchwork Tue Apr 30 08:50:58 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Henry Chen X-Patchwork-Id: 10923085 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 93C0A1390 for ; Tue, 30 Apr 2019 09:46:39 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 82FE028A7A for ; Tue, 30 Apr 2019 09:46:39 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 7711A28AAE; Tue, 30 Apr 2019 09:46:39 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED,UNPARSEABLE_RELAY autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 2E56028A15 for ; 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Tue, 30 Apr 2019 17:45:19 +0800 From: Henry Chen To: Georgi Djakov , Rob Herring , Matthias Brugger , Viresh Kumar , Stephen Boyd Subject: [RFC V2 04/11] arm64: dts: mt8183: add performance state support of scpsys Date: Tue, 30 Apr 2019 16:50:58 +0800 Message-ID: <1556614265-12745-5-git-send-email-henryc.chen@mediatek.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1556614265-12745-1-git-send-email-henryc.chen@mediatek.com> References: <1556614265-12745-1-git-send-email-henryc.chen@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190430_024530_850560_145490AA X-CRM114-Status: UNSURE ( 9.20 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: James Liao , Weiyi Lu , Nicolas Boichat , linux-kernel@vger.kernel.org, Henry Chen , Fan Chen , devicetree@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Add support for performance state of scpsys on mt8183 platform. Signed-off-by: Henry Chen --- arch/arm64/boot/dts/mediatek/mt8183.dtsi | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi index 75c4881..665d561 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi @@ -9,6 +9,7 @@ #include #include #include +#include / { compatible = "mediatek,mt8183"; @@ -251,6 +252,26 @@ "vpu-3", "vpu-4", "vpu-5"; infracfg = <&infracfg>; smi_comm = <&smi_common>; + operating-points-v2 = <&dvfsrc_opp_table>; + dvfsrc_opp_table: opp-table { + compatible = "operating-points-v2-level"; + + dvfsrc_vol_min: opp1 { + opp,level = ; + }; + + dvfsrc_freq_medium: opp2 { + opp,level = ; + }; + + dvfsrc_freq_max: opp3 { + opp,level = ; + }; + + dvfsrc_vol_max: opp4 { + opp,level = ; + }; + }; }; apmixedsys: syscon@1000c000 { From patchwork Tue Apr 30 08:50:59 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Henry Chen X-Patchwork-Id: 10923109 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 41001933 for ; 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Tue, 30 Apr 2019 09:46:07 +0000 X-UUID: b37902da790f404bba6102b5dfec74c1-20190430 X-UUID: b37902da790f404bba6102b5dfec74c1-20190430 Received: from mtkcas66.mediatek.inc [(172.29.193.44)] by mailgw02.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLS) with ESMTP id 1069260526; Tue, 30 Apr 2019 01:45:29 -0800 Received: from MTKMBS01N1.mediatek.inc (172.21.101.68) by MTKMBS62N1.mediatek.inc (172.29.193.41) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Tue, 30 Apr 2019 02:45:28 -0700 Received: from mtkcas09.mediatek.inc (172.21.101.178) by mtkmbs01n1.mediatek.inc (172.21.101.68) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Tue, 30 Apr 2019 17:45:19 +0800 Received: from mtkslt205.mediatek.inc (10.21.15.75) by mtkcas09.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Tue, 30 Apr 2019 17:45:19 +0800 From: Henry Chen To: Georgi Djakov , Rob Herring , Matthias Brugger , Viresh Kumar , Stephen Boyd Subject: [RFC V2 05/11] soc: mediatek: add header for mediatek SIP interface Date: Tue, 30 Apr 2019 16:50:59 +0800 Message-ID: <1556614265-12745-6-git-send-email-henryc.chen@mediatek.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1556614265-12745-1-git-send-email-henryc.chen@mediatek.com> References: <1556614265-12745-1-git-send-email-henryc.chen@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190430_024604_505042_5DDD0963 X-CRM114-Status: GOOD ( 11.56 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: James Liao , Weiyi Lu , Nicolas Boichat , linux-kernel@vger.kernel.org, Henry Chen , Fan Chen , devicetree@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Add a header to collect SIPs and add one SIP call to initialize power management hardware for the SIP interface defined to access the SPM handling vcore voltage and ddr rate changes on mt8183 (and most likely later socs). Signed-off-by: Henry Chen --- include/soc/mediatek/mtk_sip.h | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) create mode 100644 include/soc/mediatek/mtk_sip.h diff --git a/include/soc/mediatek/mtk_sip.h b/include/soc/mediatek/mtk_sip.h new file mode 100644 index 0000000..5394ff4 --- /dev/null +++ b/include/soc/mediatek/mtk_sip.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright (c) 2018 MediaTek Inc. + */ +#ifndef __SOC_MTK_SIP_H +#define __SOC_MTK_SIP_H + +#ifdef CONFIG_ARM64 +#define MTK_SIP_SMC_AARCH_BIT 0x40000000 +#else +#define MTK_SIP_SMC_AARCH_BIT 0x00000000 +#endif + +#define MTK_SIP_SPM (0x82000220 | MTK_SIP_SMC_AARCH_BIT) +#define MTK_SIP_SPM_DVFSRC_INIT 0x00 + +#endif From patchwork Tue Apr 30 08:51:00 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Henry Chen X-Patchwork-Id: 10923083 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id DD9B5933 for ; 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Tue, 30 Apr 2019 09:45:31 +0000 X-UUID: 3cd74882d0b04f42a50af1b8c09c990c-20190430 X-UUID: 3cd74882d0b04f42a50af1b8c09c990c-20190430 Received: from mtkcas67.mediatek.inc [(172.29.193.45)] by mailgw01.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLS) with ESMTP id 4890286; Tue, 30 Apr 2019 01:45:23 -0800 Received: from MTKMBS01N2.mediatek.inc (172.21.101.79) by MTKMBS62N2.mediatek.inc (172.29.193.42) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Tue, 30 Apr 2019 02:45:22 -0700 Received: from mtkcas09.mediatek.inc (172.21.101.178) by mtkmbs01n2.mediatek.inc (172.21.101.79) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Tue, 30 Apr 2019 17:45:19 +0800 Received: from mtkslt205.mediatek.inc (10.21.15.75) by mtkcas09.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Tue, 30 Apr 2019 17:45:19 +0800 From: Henry Chen To: Georgi Djakov , Rob Herring , Matthias Brugger , Viresh Kumar , Stephen Boyd Subject: [RFC V2 06/11] soc: mediatek: add MT8183 dvfsrc support Date: Tue, 30 Apr 2019 16:51:00 +0800 Message-ID: <1556614265-12745-7-git-send-email-henryc.chen@mediatek.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1556614265-12745-1-git-send-email-henryc.chen@mediatek.com> References: <1556614265-12745-1-git-send-email-henryc.chen@mediatek.com> MIME-Version: 1.0 X-TM-SNTS-SMTP: BDD94E07BC5F44F49120B03F08715AA8D6CE5FC3BA7FAD63786EFE6B41F660B42000:8 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190430_024529_621105_B5D93FD4 X-CRM114-Status: GOOD ( 21.23 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: James Liao , Weiyi Lu , Nicolas Boichat , linux-kernel@vger.kernel.org, Henry Chen , Fan Chen , devicetree@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Add dvfsrc driver for MT8183 Signed-off-by: Henry Chen --- drivers/soc/mediatek/Kconfig | 15 ++ drivers/soc/mediatek/Makefile | 1 + drivers/soc/mediatek/mtk-dvfsrc.c | 347 ++++++++++++++++++++++++++++++++++++++ include/soc/mediatek/mtk_dvfsrc.h | 22 +++ 4 files changed, 385 insertions(+) create mode 100644 drivers/soc/mediatek/mtk-dvfsrc.c create mode 100644 include/soc/mediatek/mtk_dvfsrc.h diff --git a/drivers/soc/mediatek/Kconfig b/drivers/soc/mediatek/Kconfig index 17bd759..2721fd6 100644 --- a/drivers/soc/mediatek/Kconfig +++ b/drivers/soc/mediatek/Kconfig @@ -24,6 +24,21 @@ config MTK_INFRACFG INFRACFG controller contains various infrastructure registers not directly associated to any device. +config MTK_DVFSRC + bool "MediaTek DVFSRC Support" + depends on ARCH_MEDIATEK + default ARCH_MEDIATEK + select MTK_INFRACFG + select PM_GENERIC_DOMAINS if PM + depends on MTK_SCPSYS + help + Say yes here to add support for the MediaTek DVFSRC (dynamic voltage + and frequency scaling resource collector) found + on different MediaTek SoCs. The DVFSRC is a proprietary + hardware which is used to collect all the requests from + system and turn into the decision of minimum Vcore voltage + and minimum DRAM frequency to fulfill those requests. + config MTK_PMIC_WRAP tristate "MediaTek PMIC Wrapper Support" depends on RESET_CONTROLLER diff --git a/drivers/soc/mediatek/Makefile b/drivers/soc/mediatek/Makefile index b9dbad6..cd9d63f 100644 --- a/drivers/soc/mediatek/Makefile +++ b/drivers/soc/mediatek/Makefile @@ -1,4 +1,5 @@ obj-$(CONFIG_MTK_CMDQ) += mtk-cmdq-helper.o +obj-$(CONFIG_MTK_DVFSRC) += mtk-dvfsrc.o obj-$(CONFIG_MTK_INFRACFG) += mtk-infracfg.o mtk-scpsys-ext.o obj-$(CONFIG_MTK_PMIC_WRAP) += mtk-pmic-wrap.o obj-$(CONFIG_MTK_SCPSYS) += mtk-scpsys.o diff --git a/drivers/soc/mediatek/mtk-dvfsrc.c b/drivers/soc/mediatek/mtk-dvfsrc.c new file mode 100644 index 0000000..e54a654 --- /dev/null +++ b/drivers/soc/mediatek/mtk-dvfsrc.c @@ -0,0 +1,347 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2018 MediaTek Inc. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "mtk-scpsys.h" + +#define DVFSRC_IDLE 0x00 +#define DVFSRC_GET_TARGET_LEVEL(x) (((x) >> 0) & 0x0000ffff) +#define DVFSRC_GET_CURRENT_LEVEL(x) (((x) >> 16) & 0x0000ffff) + +#define MT8183_DVFSRC_OPP_LP4 0 +#define MT8183_DVFSRC_OPP_LP4X 1 +#define MT8183_DVFSRC_OPP_LP3 2 + +struct dvfsrc_opp { + u32 vcore_opp; + u32 dram_opp; +}; + +struct dvfsrc_domain { + u32 id; + u32 state; +}; + +struct mtk_dvfsrc; +struct dvfsrc_soc_data { + const int *regs; + u32 num_opp; + u32 num_domains; + const struct dvfsrc_opp **opps; + struct dvfsrc_domain *domains; + int (*get_target_level)(struct mtk_dvfsrc *dvfsrc); + int (*get_current_level)(struct mtk_dvfsrc *dvfsrc); + void (*set_dram_bw)(struct mtk_dvfsrc *dvfsrc, u64 bw); + void (*set_opp_level)(struct mtk_dvfsrc *dvfsrc, u32 level); +}; + +struct mtk_dvfsrc { + struct device *dev; + struct clk *clk_dvfsrc; + const struct dvfsrc_soc_data *dvd; + int dram_type; + void __iomem *regs; + struct mutex lock; + struct notifier_block scpsys_notifier; +}; + +static u32 dvfsrc_read(struct mtk_dvfsrc *dvfs, u32 offset) +{ + return readl(dvfs->regs + dvfs->dvd->regs[offset]); +} + +static void dvfsrc_write(struct mtk_dvfsrc *dvfs, u32 offset, u32 val) +{ + writel(val, dvfs->regs + dvfs->dvd->regs[offset]); +} + +enum dvfsrc_regs { + DVFSRC_SW_REQ, + DVFSRC_LEVEL, + DVFSRC_SW_BW_0, + DVFSRC_LAST, +}; + +static const int mt8183_regs[] = { + [DVFSRC_SW_REQ] = 0x4, + [DVFSRC_LEVEL] = 0xDC, + [DVFSRC_SW_BW_0] = 0x160, + [DVFSRC_LAST] = 0x308, +}; + +static bool dvfsrc_is_idle(struct mtk_dvfsrc *dvfsrc) +{ + if (!dvfsrc->dvd->get_target_level) + return true; + + return dvfsrc->dvd->get_target_level(dvfsrc) == DVFSRC_IDLE; +} + +static int dvfsrc_wait_for_idle(struct mtk_dvfsrc *dvfsrc) +{ + unsigned long timeout; + + timeout = jiffies + usecs_to_jiffies(1000); + + do { + if (dvfsrc_is_idle(dvfsrc)) + return 0; + } while (!time_after(jiffies, timeout)); + + return -ETIMEDOUT; +} + +static int mt8183_get_target_level(struct mtk_dvfsrc *dvfsrc) +{ + return DVFSRC_GET_TARGET_LEVEL(dvfsrc_read(dvfsrc, DVFSRC_LEVEL)); +} + +static int mt8183_get_current_level(struct mtk_dvfsrc *dvfsrc) +{ + return ffs(DVFSRC_GET_CURRENT_LEVEL(dvfsrc_read(dvfsrc, DVFSRC_LEVEL))); +} + +static void mt8183_set_dram_bw(struct mtk_dvfsrc *dvfsrc, u64 bw) +{ + dvfsrc_write(dvfsrc, DVFSRC_SW_BW_0, bw); +} + +static void mt8183_set_opp_level(struct mtk_dvfsrc *dvfsrc, u32 level) +{ + int vcore_opp, dram_opp; + const struct dvfsrc_opp *opp; + + /* translate pstate to dvfsrc level, and set it to DVFSRC HW */ + opp = &dvfsrc->dvd->opps[dvfsrc->dram_type][level - 1]; + vcore_opp = opp->vcore_opp; + dram_opp = opp->dram_opp; + + dev_dbg(dvfsrc->dev, "vcore_opp: %d, dram_opp: %d\n", + vcore_opp, dram_opp); + dvfsrc_write(dvfsrc, DVFSRC_SW_REQ, dram_opp | vcore_opp << 2); +} + +void mtk_dvfsrc_send_request(const struct device *dev, u32 cmd, u64 data) +{ + struct mtk_dvfsrc *dvfsrc = dev_get_drvdata(dev); + + dev_dbg(dvfsrc->dev, "cmd: %d, data: %llu\n", cmd, data); + + mutex_lock(&dvfsrc->lock); + + if (dvfsrc_wait_for_idle(dvfsrc)) { + dev_warn(dvfsrc->dev, "[%s] wait idle, last: %d -> %d\n", + __func__, dvfsrc_read(dvfsrc, DVFSRC_LEVEL), + dvfsrc_read(dvfsrc, DVFSRC_LAST)); + goto out; + } + + switch (cmd) { + case MTK_DVFSRC_CMD_BW_REQUEST: + dvfsrc->dvd->set_dram_bw(dvfsrc, data); + goto out; + case MTK_DVFSRC_CMD_OPP_REQUEST: + dvfsrc->dvd->set_opp_level(dvfsrc, data); + break; + default: + dev_err(dvfsrc->dev, "unknown command: %d\n", cmd); + break; + } + + if (dvfsrc_wait_for_idle(dvfsrc)) { + dev_warn(dvfsrc->dev, "[%s] wait idle, last: %d -> %d\n", + __func__, dvfsrc_read(dvfsrc, DVFSRC_LEVEL), + dvfsrc_read(dvfsrc, DVFSRC_LAST)); + goto out; + } + +out: + mutex_unlock(&dvfsrc->lock); +} +EXPORT_SYMBOL(mtk_dvfsrc_send_request); + +static int dvfsrc_set_performance(struct notifier_block *b, + unsigned long l, void *v) +{ + int i, val, highest; + struct mtk_dvfsrc *dvfsrc; + struct scp_event_data *sc = v; + struct dvfsrc_domain *d; + + if (sc->event_type != MTK_SCPSYS_PSTATE) + return 0; + + dvfsrc = container_of(b, struct mtk_dvfsrc, scpsys_notifier); + + d = dvfsrc->dvd->domains; + + if (l > dvfsrc->dvd->num_opp) { + dev_err(dvfsrc->dev, "pstate out of range = %ld\n", l); + goto out; + } + + for (i = 0, highest = 0; i < dvfsrc->dvd->num_domains - 1; i++, d++) { + if (sc->domain_id == d->id) + d->state = l; + if (d->state > highest) + highest = d->state; + } + + if (highest == 0) { + dev_err(dvfsrc->dev, "domain not match\n"); + goto out; + } + + mtk_dvfsrc_send_request(dvfsrc->dev, MTK_DVFSRC_CMD_OPP_REQUEST, + highest); + + val = dvfsrc->dvd->get_current_level(dvfsrc); + + dev_dbg(dvfsrc->dev, "DVFSRC_LEVEL: %x, val: %x, DVFSRC_SW_REQ: %x\n", + dvfsrc_read(dvfsrc, DVFSRC_LEVEL), val, + dvfsrc_read(dvfsrc, DVFSRC_SW_REQ)); + + if (val < highest) { + dev_err(dvfsrc->dev, "current: %d < highest: %x\n", + val, highest); + goto out; + } + +out: + return 0; +} + +static void pstate_notifier_register(struct mtk_dvfsrc *dvfsrc) +{ + dvfsrc->scpsys_notifier.notifier_call = dvfsrc_set_performance; + register_scpsys_notifier(&dvfsrc->scpsys_notifier); +} + +static int mtk_dvfsrc_probe(struct platform_device *pdev) +{ + struct arm_smccc_res ares; + struct resource *res; + struct mtk_dvfsrc *dvfsrc; + int ret; + + dvfsrc = devm_kzalloc(&pdev->dev, sizeof(*dvfsrc), GFP_KERNEL); + if (!dvfsrc) + return -ENOMEM; + + dvfsrc->dvd = of_device_get_match_data(&pdev->dev); + dvfsrc->dev = &pdev->dev; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + dvfsrc->regs = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(dvfsrc->regs)) + return PTR_ERR(dvfsrc->regs); + + dvfsrc->clk_dvfsrc = devm_clk_get(dvfsrc->dev, "dvfsrc"); + if (IS_ERR(dvfsrc->clk_dvfsrc)) { + dev_err(dvfsrc->dev, "failed to get clock: %ld\n", + PTR_ERR(dvfsrc->clk_dvfsrc)); + return PTR_ERR(dvfsrc->clk_dvfsrc); + } + + ret = clk_prepare_enable(dvfsrc->clk_dvfsrc); + if (ret) + return ret; + + mutex_init(&dvfsrc->lock); + + arm_smccc_smc(MTK_SIP_SPM, MTK_SIP_SPM_DVFSRC_INIT, 0, 0, 0, 0, 0, 0, + &ares); + + if (!ares.a0) { + dvfsrc->dram_type = ares.a1; + } else { + dev_err(dvfsrc->dev, "init fails: %lu\n", ares.a0); + clk_disable_unprepare(dvfsrc->clk_dvfsrc); + return ares.a0; + } + + platform_set_drvdata(pdev, dvfsrc); + pstate_notifier_register(dvfsrc); + + return devm_of_platform_populate(&pdev->dev); +} + +static const struct dvfsrc_opp dvfsrc_opp_mt8183_lp4[] = { + {0, 0}, {0, 1}, {0, 2}, {1, 2}, +}; + +static const struct dvfsrc_opp dvfsrc_opp_mt8183_lp3[] = { + {0, 0}, {0, 1}, {1, 1}, {1, 2}, +}; + +static const struct dvfsrc_opp *dvfsrc_opp_mt8183[] = { + [MT8183_DVFSRC_OPP_LP4] = dvfsrc_opp_mt8183_lp4, + [MT8183_DVFSRC_OPP_LP4X] = dvfsrc_opp_mt8183_lp3, + [MT8183_DVFSRC_OPP_LP3] = dvfsrc_opp_mt8183_lp3, +}; + +static struct dvfsrc_domain dvfsrc_domains_mt8183[] = { + { MT8183_POWER_DOMAIN_MFG_ASYNC, 0 }, + { MT8183_POWER_DOMAIN_MFG, 0 }, + { MT8183_POWER_DOMAIN_CAM, 0 }, + { MT8183_POWER_DOMAIN_DISP, 0 }, + { MT8183_POWER_DOMAIN_ISP, 0 }, + { MT8183_POWER_DOMAIN_VDEC, 0 }, + { MT8183_POWER_DOMAIN_VENC, 0 }, +}; + +static const struct dvfsrc_soc_data mt8183_data = { + .opps = dvfsrc_opp_mt8183, + .num_opp = ARRAY_SIZE(dvfsrc_opp_mt8183_lp4), + .regs = mt8183_regs, + .domains = dvfsrc_domains_mt8183, + .num_domains = ARRAY_SIZE(dvfsrc_domains_mt8183), + .get_target_level = mt8183_get_target_level, + .get_current_level = mt8183_get_current_level, + .set_dram_bw = mt8183_set_dram_bw, + .set_opp_level = mt8183_set_opp_level, +}; + +static int mtk_dvfsrc_remove(struct platform_device *pdev) +{ + struct mtk_dvfsrc *dvfsrc = platform_get_drvdata(pdev); + + clk_disable_unprepare(dvfsrc->clk_dvfsrc); + + return 0; +} + +static const struct of_device_id mtk_dvfsrc_of_match[] = { + { + .compatible = "mediatek,mt8183-dvfsrc", + .data = &mt8183_data, + }, { + /* sentinel */ + }, +}; + +static struct platform_driver mtk_dvfsrc_driver = { + .probe = mtk_dvfsrc_probe, + .remove = mtk_dvfsrc_remove, + .driver = { + .name = "mtk-dvfsrc", + .of_match_table = of_match_ptr(mtk_dvfsrc_of_match), + }, +}; + +builtin_platform_driver(mtk_dvfsrc_driver); + +MODULE_LICENSE("GPL v2"); +MODULE_DESCRIPTION("MTK DVFSRC driver"); diff --git a/include/soc/mediatek/mtk_dvfsrc.h b/include/soc/mediatek/mtk_dvfsrc.h new file mode 100644 index 0000000..e759a65 --- /dev/null +++ b/include/soc/mediatek/mtk_dvfsrc.h @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright (c) 2018 MediaTek Inc. + */ +#ifndef __SOC_MTK_DVFSRC_H +#define __SOC_MTK_DVFSRC_H + +#define MTK_DVFSRC_CMD_BW_REQUEST 0 +#define MTK_DVFSRC_CMD_OPP_REQUEST 1 + +#if IS_ENABLED(CONFIG_MTK_DVFSRC) +void mtk_dvfsrc_send_request(const struct device *dev, u32 cmd, u64 data); + +#else + +static inline void mtk_dvfsrc_send_request(const struct device *dev, u32 cmd, + u64 data) +{ return -ENODEV; } + +#endif /* CONFIG_MTK_DVFSRC */ + +#endif From patchwork Tue Apr 30 08:51:01 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Henry Chen X-Patchwork-Id: 10923105 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id AA03A1390 for ; Tue, 30 Apr 2019 09:48:06 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 971B028A94 for ; Tue, 30 Apr 2019 09:48:06 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 8ACF128AB2; Tue, 30 Apr 2019 09:48:06 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED,UNPARSEABLE_RELAY autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 3336528A94 for ; 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Tue, 30 Apr 2019 17:45:20 +0800 From: Henry Chen To: Georgi Djakov , Rob Herring , Matthias Brugger , Viresh Kumar , Stephen Boyd Subject: [RFC V2 07/11] arm64: dts: mt8183: add dvfsrc related nodes Date: Tue, 30 Apr 2019 16:51:01 +0800 Message-ID: <1556614265-12745-8-git-send-email-henryc.chen@mediatek.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1556614265-12745-1-git-send-email-henryc.chen@mediatek.com> References: <1556614265-12745-1-git-send-email-henryc.chen@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190430_024556_840713_2A155DAC X-CRM114-Status: UNSURE ( 8.75 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: James Liao , Weiyi Lu , Nicolas Boichat , linux-kernel@vger.kernel.org, Henry Chen , Fan Chen , devicetree@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Enable dvfsrc on mt8183 platform. Signed-off-by: Henry Chen --- arch/arm64/boot/dts/mediatek/mt8183.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi index 665d561..d298013 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi @@ -134,6 +134,13 @@ clock-output-names = "clk26m"; }; + dvfsrc@10012000 { + compatible = "mediatek,mt8183-dvfsrc"; + reg = <0 0x10012000 0 0x1000>; + clocks = <&infracfg CLK_INFRA_DVFSRC>; + clock-names = "dvfsrc"; + }; + timer { compatible = "arm,armv8-timer"; interrupt-parent = <&gic>; From patchwork Tue Apr 30 08:51:02 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Henry Chen X-Patchwork-Id: 10923081 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 4D8631390 for ; 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Tue, 30 Apr 2019 09:45:30 +0000 X-UUID: cff18b7ac38d40f9bb6401b72b51a273-20190430 X-UUID: cff18b7ac38d40f9bb6401b72b51a273-20190430 Received: from mtkcas67.mediatek.inc [(172.29.193.45)] by mailgw01.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLS) with ESMTP id 1263179399; Tue, 30 Apr 2019 01:45:23 -0800 Received: from mtkmbs03n1.mediatek.inc (172.21.101.181) by MTKMBS62N2.mediatek.inc (172.29.193.42) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Tue, 30 Apr 2019 02:45:21 -0700 Received: from mtkcas09.mediatek.inc (172.21.101.178) by mtkmbs03n1.mediatek.inc (172.21.101.181) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Tue, 30 Apr 2019 17:45:20 +0800 Received: from mtkslt205.mediatek.inc (10.21.15.75) by mtkcas09.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Tue, 30 Apr 2019 17:45:20 +0800 From: Henry Chen To: Georgi Djakov , Rob Herring , Matthias Brugger , Viresh Kumar , Stephen Boyd Subject: [RFC V2 08/11] dt-bindings: interconnect: add MT8183 interconnect dt-bindings Date: Tue, 30 Apr 2019 16:51:02 +0800 Message-ID: <1556614265-12745-9-git-send-email-henryc.chen@mediatek.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1556614265-12745-1-git-send-email-henryc.chen@mediatek.com> References: <1556614265-12745-1-git-send-email-henryc.chen@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190430_024529_308304_A157973A X-CRM114-Status: GOOD ( 10.74 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: James Liao , Weiyi Lu , Nicolas Boichat , linux-kernel@vger.kernel.org, Henry Chen , Fan Chen , devicetree@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Add interconnect provider dt-bindings for MT8183. Signed-off-by: Henry Chen --- .../bindings/interconnect/mtk,mt8183.txt | 24 ++++++++++++++++++++++ 1 file changed, 24 insertions(+) create mode 100644 Documentation/devicetree/bindings/interconnect/mtk,mt8183.txt diff --git a/Documentation/devicetree/bindings/interconnect/mtk,mt8183.txt b/Documentation/devicetree/bindings/interconnect/mtk,mt8183.txt new file mode 100644 index 0000000..1cf1841 --- /dev/null +++ b/Documentation/devicetree/bindings/interconnect/mtk,mt8183.txt @@ -0,0 +1,24 @@ +Mediatek MT8183 interconnect binding + +MT8183 interconnect providers support dram bandwidth requirements. The provider +is able to communicate with the DVFSRC and send the dram bandwidth to it. +Provider nodes must reside within an DVFSRC device node. + +Required properties : +- compatible : shall contain only one of the following: + "mediatek,mt8183-emi-icc" +- #interconnect-cells : should contain 1 + +Examples: + +dvfsrc@10012000 { + compatible = "mediatek,mt8183-dvfsrc"; + reg = <0 0x10012000 0 0x1000>; + clocks = <&infracfg CLK_INFRA_DVFSRC>; + clock-names = "dvfsrc"; + ddr_emi: interconnect { + compatible = "mediatek,mt8183-emi-icc"; + #interconnect-cells = <1>; + }; +}; + From patchwork Tue Apr 30 08:51:03 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Henry Chen X-Patchwork-Id: 10923101 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 86AEB933 for ; Tue, 30 Apr 2019 09:47:39 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 73A3C28A71 for ; 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Tue, 30 Apr 2019 01:45:34 -0800 Received: from MTKMBS02N1.mediatek.inc (172.21.101.77) by MTKMBS62DR.mediatek.inc (172.29.94.18) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Tue, 30 Apr 2019 02:45:33 -0700 Received: from mtkcas09.mediatek.inc (172.21.101.178) by mtkmbs02n1.mediatek.inc (172.21.101.77) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Tue, 30 Apr 2019 17:45:20 +0800 Received: from mtkslt205.mediatek.inc (10.21.15.75) by mtkcas09.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Tue, 30 Apr 2019 17:45:20 +0800 From: Henry Chen To: Georgi Djakov , Rob Herring , Matthias Brugger , Viresh Kumar , Stephen Boyd Subject: [RFC V2 09/11] dt-bindings: interconnect: Add header for interconnect node Date: Tue, 30 Apr 2019 16:51:03 +0800 Message-ID: <1556614265-12745-10-git-send-email-henryc.chen@mediatek.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1556614265-12745-1-git-send-email-henryc.chen@mediatek.com> References: <1556614265-12745-1-git-send-email-henryc.chen@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190430_024550_752457_A5E4568A X-CRM114-Status: GOOD ( 10.26 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: James Liao , Weiyi Lu , Nicolas Boichat , linux-kernel@vger.kernel.org, Henry Chen , Fan Chen , devicetree@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Add header file for mt8183 interconnect node that could be shared between the interconeect provider driver and Device Tree source files. Signed-off-by: Henry Chen --- include/dt-bindings/interconnect/mtk,mt8183.h | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) create mode 100644 include/dt-bindings/interconnect/mtk,mt8183.h diff --git a/include/dt-bindings/interconnect/mtk,mt8183.h b/include/dt-bindings/interconnect/mtk,mt8183.h new file mode 100644 index 0000000..34adbfa --- /dev/null +++ b/include/dt-bindings/interconnect/mtk,mt8183.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +#ifndef __DT_BINDINGS_INTERCONNECT_MTK_MT8183_H +#define __DT_BINDINGS_INTERCONNECT_MTK_MT8183_H + +#define SLAVE_DDR_EMI 0 +#define MASTER_MCUSYS 1 +#define MASTER_GPU 2 +#define MASTER_MMSYS 3 +#define MASTER_MM_VPU 4 +#define MASTER_MM_DISP 5 +#define MASTER_MM_VDEC 6 +#define MASTER_MM_VENC 7 +#define MASTER_MM_CAM 8 +#define MASTER_MM_IMG 9 +#define MASTER_MM_MDP 10 + +#endif From patchwork Tue Apr 30 08:51:04 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Henry Chen X-Patchwork-Id: 10923099 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id CF19A933 for ; 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Tue, 30 Apr 2019 09:45:39 +0000 X-UUID: 16185863fe074d94a0c4161e015b0fa7-20190430 X-UUID: 16185863fe074d94a0c4161e015b0fa7-20190430 Received: from mtkcas67.mediatek.inc [(172.29.193.45)] by mailgw01.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLS) with ESMTP id 681525574; Tue, 30 Apr 2019 01:45:31 -0800 Received: from MTKMBS01N1.mediatek.inc (172.21.101.68) by MTKMBS62N1.mediatek.inc (172.29.193.41) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Tue, 30 Apr 2019 02:45:29 -0700 Received: from mtkcas09.mediatek.inc (172.21.101.178) by mtkmbs01n1.mediatek.inc (172.21.101.68) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Tue, 30 Apr 2019 17:45:20 +0800 Received: from mtkslt205.mediatek.inc (10.21.15.75) by mtkcas09.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Tue, 30 Apr 2019 17:45:20 +0800 From: Henry Chen To: Georgi Djakov , Rob Herring , Matthias Brugger , Viresh Kumar , Stephen Boyd Subject: [RFC V2 10/11] interconnect: mediatek: Add mt8183 interconnect provider driver Date: Tue, 30 Apr 2019 16:51:04 +0800 Message-ID: <1556614265-12745-11-git-send-email-henryc.chen@mediatek.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1556614265-12745-1-git-send-email-henryc.chen@mediatek.com> References: <1556614265-12745-1-git-send-email-henryc.chen@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190430_024533_210552_D38C7482 X-CRM114-Status: GOOD ( 18.37 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: James Liao , Weiyi Lu , Nicolas Boichat , linux-kernel@vger.kernel.org, Henry Chen , Fan Chen , devicetree@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Introduce Mediatek MT8183 specific provider driver using the interconnect framework. Signed-off-by: Henry Chen --- drivers/interconnect/Kconfig | 1 + drivers/interconnect/Makefile | 1 + drivers/interconnect/mediatek/Kconfig | 13 ++ drivers/interconnect/mediatek/Makefile | 5 + drivers/interconnect/mediatek/mt8183.c | 223 +++++++++++++++++++++++++++++++++ 5 files changed, 243 insertions(+) create mode 100644 drivers/interconnect/mediatek/Kconfig create mode 100644 drivers/interconnect/mediatek/Makefile create mode 100644 drivers/interconnect/mediatek/mt8183.c diff --git a/drivers/interconnect/Kconfig b/drivers/interconnect/Kconfig index 07a8276..ac41ea6 100644 --- a/drivers/interconnect/Kconfig +++ b/drivers/interconnect/Kconfig @@ -11,5 +11,6 @@ menuconfig INTERCONNECT if INTERCONNECT source "drivers/interconnect/qcom/Kconfig" +source "drivers/interconnect/mediatek/Kconfig" endif diff --git a/drivers/interconnect/Makefile b/drivers/interconnect/Makefile index 28f2ab0..253f24a3 100644 --- a/drivers/interconnect/Makefile +++ b/drivers/interconnect/Makefile @@ -4,3 +4,4 @@ icc-core-objs := core.o obj-$(CONFIG_INTERCONNECT) += icc-core.o obj-$(CONFIG_INTERCONNECT_QCOM) += qcom/ +obj-$(CONFIG_INTERCONNECT_MTK) += mediatek/ diff --git a/drivers/interconnect/mediatek/Kconfig b/drivers/interconnect/mediatek/Kconfig new file mode 100644 index 0000000..0686494 --- /dev/null +++ b/drivers/interconnect/mediatek/Kconfig @@ -0,0 +1,13 @@ +config INTERCONNECT_MTK + bool "Mediatek Network-on-Chip interconnect drivers" + depends on ARCH_MEDIATEK + help + Support for Mediatek's Network-on-Chip interconnect hardware. + +config INTERCONNECT_MTK_MT8183 + tristate "Mediatek MT8183 interconnect driver" + depends on INTERCONNECT_MTK + depends on (MTK_DVFSRC && OF) + help + This is a driver for the Mediatek Network-on-Chip on mt8183-based + platforms. diff --git a/drivers/interconnect/mediatek/Makefile b/drivers/interconnect/mediatek/Makefile new file mode 100644 index 0000000..a39ceee --- /dev/null +++ b/drivers/interconnect/mediatek/Makefile @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0 + +mtk-mt8183-objs := mt8183.o + +obj-$(CONFIG_INTERCONNECT_MTK_MT8183) += mtk-mt8183.o \ No newline at end of file diff --git a/drivers/interconnect/mediatek/mt8183.c b/drivers/interconnect/mediatek/mt8183.c new file mode 100644 index 0000000..38ffe0b --- /dev/null +++ b/drivers/interconnect/mediatek/mt8183.c @@ -0,0 +1,223 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define MT8183_MAX_LINKS 6 + +/** + * struct mtk_icc_node - Mediatek specific interconnect nodes + * @name: the node name used in debugfs + * @ep: true if the node is an end point. + * @id: a unique node identifier + * @links: an array of nodes where we can go next while traversing + * @num_links: the total number of @links + * @buswidth: width of the interconnect between a node and the bus + * @sum_avg: current sum aggregate value of all avg bw requests + * @max_peak: current max aggregate value of all peak bw requests + */ +struct mtk_icc_node { + unsigned char *name; + bool ep; + u16 id; + u16 links[MT8183_MAX_LINKS]; + u16 num_links; + u16 buswidth; + u64 sum_avg; + u64 max_peak; +}; + +struct mtk_icc_desc { + struct mtk_icc_node **nodes; + size_t num_nodes; +}; + +#define DEFINE_MNODE(_name, _id, _buswidth, _ep, _numlinks, ...) \ + static struct mtk_icc_node _name = { \ + .name = #_name, \ + .id = _id, \ + .buswidth = _buswidth, \ + .ep = _ep, \ + .num_links = _numlinks, \ + .links = { __VA_ARGS__ }, \ +} + +DEFINE_MNODE(ddr_emi, SLAVE_DDR_EMI, 1024, 1, 0, 0); +DEFINE_MNODE(mcusys, MASTER_MCUSYS, 256, 0, 1, SLAVE_DDR_EMI); +DEFINE_MNODE(gpu, MASTER_GPU, 256, 0, 1, SLAVE_DDR_EMI); +DEFINE_MNODE(mmsys, MASTER_MMSYS, 256, 0, 1, SLAVE_DDR_EMI); +DEFINE_MNODE(mm_vpu, MASTER_MM_VPU, 128, 0, 1, MASTER_MMSYS); +DEFINE_MNODE(mm_disp, MASTER_MM_DISP, 128, 0, 1, MASTER_MMSYS); +DEFINE_MNODE(mm_vdec, MASTER_MM_VDEC, 128, 0, 1, MASTER_MMSYS); +DEFINE_MNODE(mm_venc, MASTER_MM_VENC, 128, 0, 1, MASTER_MMSYS); +DEFINE_MNODE(mm_cam, MASTER_MM_CAM, 128, 0, 1, MASTER_MMSYS); +DEFINE_MNODE(mm_img, MASTER_MM_IMG, 128, 0, 1, MASTER_MMSYS); +DEFINE_MNODE(mm_mdp, MASTER_MM_MDP, 128, 0, 1, MASTER_MMSYS); + +static struct mtk_icc_node *mt8183_icc_nodes[] = { + &ddr_emi, + &mcusys, + &gpu, + &mmsys, + &mm_vpu, + &mm_disp, + &mm_vdec, + &mm_venc, + &mm_cam, + &mm_img, + &mm_mdp, +}; + +static struct mtk_icc_desc mt8183_icc = { + .nodes = mt8183_icc_nodes, + .num_nodes = ARRAY_SIZE(mt8183_icc_nodes), +}; + +static int mt8183_icc_aggregate(struct icc_node *node, u32 avg_bw, + u32 peak_bw, u32 *agg_avg, u32 *agg_peak) +{ + struct mtk_icc_node *in; + + in = node->data; + + *agg_avg += avg_bw; + *agg_peak = max_t(u32, *agg_peak, peak_bw); + + in->sum_avg = *agg_avg; + in->max_peak = *agg_peak; + + return 0; +} + +static int mt8183_icc_set(struct icc_node *src, struct icc_node *dst) +{ + int ret = 0; + struct mtk_icc_node *node; + + node = dst->data; + if (node->ep) { + pr_debug("sum_avg (%llu), max_peak (%llu)\n", + node->sum_avg, node->max_peak); + mtk_dvfsrc_send_request(src->provider->dev->parent, + MTK_DVFSRC_CMD_BW_REQUEST, + node->max_peak); + } + + return ret; +} + +static int mt8183_icc_probe(struct platform_device *pdev) +{ + int ret; + const struct mtk_icc_desc *desc; + struct icc_node *node; + struct icc_onecell_data *data; + struct icc_provider *provider; + struct mtk_icc_node **mnodes; + size_t num_nodes, i, j; + + desc = of_device_get_match_data(&pdev->dev); + if (!desc) + return -EINVAL; + + mnodes = desc->nodes; + num_nodes = desc->num_nodes; + + provider = devm_kzalloc(&pdev->dev, sizeof(*provider), GFP_KERNEL); + if (!provider) + return -ENOMEM; + + data = devm_kcalloc(&pdev->dev, num_nodes, sizeof(*node), GFP_KERNEL); + if (!data) + return -ENOMEM; + + provider->dev = &pdev->dev; + provider->set = mt8183_icc_set; + provider->aggregate = mt8183_icc_aggregate; + provider->xlate = of_icc_xlate_onecell; + INIT_LIST_HEAD(&provider->nodes); + provider->data = data; + + ret = icc_provider_add(provider); + if (ret) { + dev_err(&pdev->dev, "error adding interconnect provider\n"); + return ret; + } + + for (i = 0; i < num_nodes; i++) { + node = icc_node_create(mnodes[i]->id); + if (IS_ERR(node)) { + ret = PTR_ERR(node); + goto err; + } + + node->name = mnodes[i]->name; + node->data = mnodes[i]; + icc_node_add(node, provider); + + dev_dbg(&pdev->dev, "registered node %s, num link: %d\n", + mnodes[i]->name, mnodes[i]->num_links); + + /* populate links */ + for (j = 0; j < mnodes[i]->num_links; j++) + icc_link_create(node, mnodes[i]->links[j]); + + data->nodes[i] = node; + } + data->num_nodes = num_nodes; + + platform_set_drvdata(pdev, provider); + + return ret; +err: + list_for_each_entry(node, &provider->nodes, node_list) { + icc_node_del(node); + icc_node_destroy(node->id); + } + + icc_provider_del(provider); + return ret; +} + +static int mt8183_icc_remove(struct platform_device *pdev) +{ + struct icc_provider *provider = platform_get_drvdata(pdev); + struct icc_node *n; + + list_for_each_entry(n, &provider->nodes, node_list) { + icc_node_del(n); + icc_node_destroy(n->id); + } + + return icc_provider_del(provider); +} + +static const struct of_device_id mt8183_icc_of_match[] = { + { .compatible = "mediatek,mt8183-emi-icc", .data = &mt8183_icc }, + { }, +}; +MODULE_DEVICE_TABLE(of, mt8183_icc_of_match); + +static struct platform_driver mt8183_icc_driver = { + .probe = mt8183_icc_probe, + .remove = mt8183_icc_remove, + .driver = { + .name = "mt8183-emi-icc", + .of_match_table = mt8183_icc_of_match, + }, +}; +module_platform_driver(mt8183_icc_driver); + +MODULE_AUTHOR("Henry Chen "); +MODULE_LICENSE("GPL v2"); From patchwork Tue Apr 30 08:51:05 2019 Content-Type: text/plain; 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Tue, 30 Apr 2019 17:45:20 +0800 From: Henry Chen To: Georgi Djakov , Rob Herring , Matthias Brugger , Viresh Kumar , Stephen Boyd Subject: [RFC V2 11/11] arm64: dts: mt8183: Add interconnect provider DT nodes Date: Tue, 30 Apr 2019 16:51:05 +0800 Message-ID: <1556614265-12745-12-git-send-email-henryc.chen@mediatek.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1556614265-12745-1-git-send-email-henryc.chen@mediatek.com> References: <1556614265-12745-1-git-send-email-henryc.chen@mediatek.com> MIME-Version: 1.0 X-TM-SNTS-SMTP: 49CC5D9D103BFB28D9BFC001BF05DC1514CC9149507117BCD0812460867759DD2000:8 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190430_024556_836921_AC5CC403 X-CRM114-Status: UNSURE ( 8.95 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: James Liao , Weiyi Lu , Nicolas Boichat , linux-kernel@vger.kernel.org, Henry Chen , Fan Chen , devicetree@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Add DDR EMI provider dictating dram interconnect bus performance found on MT8183-based platforms Signed-off-by: Henry Chen --- arch/arm64/boot/dts/mediatek/mt8183.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi index d298013..ab98adb 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi @@ -10,6 +10,7 @@ #include #include #include +#include / { compatible = "mediatek,mt8183"; @@ -139,6 +140,10 @@ reg = <0 0x10012000 0 0x1000>; clocks = <&infracfg CLK_INFRA_DVFSRC>; clock-names = "dvfsrc"; + ddr_emi: interconnect { + compatible = "mediatek,mt8183-emi-icc"; + #interconnect-cells = <1>; + }; }; timer {