From patchwork Tue Apr 30 13:14:36 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 10923433 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id CAB8A933 for ; Tue, 30 Apr 2019 13:16:10 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id BA96F2893F for ; Tue, 30 Apr 2019 13:16:10 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id AED362897F; Tue, 30 Apr 2019 13:16:10 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.0 required=2.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 5A5422893F for ; Tue, 30 Apr 2019 13:16:10 +0000 (UTC) Received: from localhost ([127.0.0.1]:47147 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hLScD-0002So-H0 for patchwork-qemu-devel@patchwork.kernel.org; Tue, 30 Apr 2019 09:16:09 -0400 Received: from eggs.gnu.org ([209.51.188.92]:44524) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hLSar-00010e-0H for qemu-devel@nongnu.org; Tue, 30 Apr 2019 09:14:45 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hLSap-0002Aw-Vu for qemu-devel@nongnu.org; Tue, 30 Apr 2019 09:14:44 -0400 Received: from mail-wm1-x341.google.com ([2a00:1450:4864:20::341]:38205) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hLSap-0002AJ-Pa for qemu-devel@nongnu.org; Tue, 30 Apr 2019 09:14:43 -0400 Received: by mail-wm1-x341.google.com with SMTP id w15so3791786wmc.3 for ; Tue, 30 Apr 2019 06:14:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=U/R8O7Qr7W3Gev40Mu9XCs2DcqDhxle1cGlCTNhZ1V0=; b=Q1AiOBUhsGvl0IcKOiLai/mtenqy4Kr17qXwXw5RbT+iBk1OYQnlLt6o4LpTxPzjSd td87MSU842aTbeQWtWHjklKn2qP8eIJlXdswud2xVGarUy+9Jx9RtuZOcsSp1NuB3mBu Xf9rcgYwhP8dqWpJtLvI37VjX9iGENpCNK139NHnpcvrQ33h1tu0eJIFGmMVSyeYkTXn RA0nPQtup+N08tvyskTvCxzpDHGiqvUaIhTXOk67RGuNOLaLPP4pWyQpKtQnjfof3lkN w71P9TLydNHwbUIdZKgg6H4jvm3lmgReNUmuBa63j8NiqFJurb/Z9PFQ7UeB/w86ll0J ZeUg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=U/R8O7Qr7W3Gev40Mu9XCs2DcqDhxle1cGlCTNhZ1V0=; b=DhqKi1pSZEvY4cFXZ1L6nq7K6ZOk3h3oKoJbkGDt7Uk6mm5pOWUBXQRRQRKiZvWb/7 PSAUKJHB/eQmUL4NMUk0qWnFaTNcscXZk85a08XZqVq0UX9r631CTnMlxNXjvwhCXjJt veq2p4qlC5lJ7uvrBJ1ztfCeawlifY56m4j52NqWYzNMlpsAV3LcV3BLFKai0VgJjP3/ ApKu47HLqhVL9cx2aFmNgB/1uQzkH1nJBYrBvFSe9xMKdCgEsaRI7EIwdwyX3qPxfAw/ Dk9esSYpSFiCcTC5B8lLL+8ewQmUPTNxnnrHWQmJceP7MQi447uaOSDaNMlu7eUR1Z+G Czfg== X-Gm-Message-State: APjAAAWF5a65RzQHH0RbeC+LfwTBbiwsPLgCljpB2tEQ9UKZwhet++YH 8ZsK4B4UTEIZyKYHi3kt66AYmA== X-Google-Smtp-Source: APXvYqyW0sTuY6hcViJsEKypB8BM3Se7PQcuwyHwAntt6B5e2zeRE2VOzjATSx+EZivodfsBsMGsGg== X-Received: by 2002:a05:600c:2506:: with SMTP id d6mr450717wma.106.1556630082710; Tue, 30 Apr 2019 06:14:42 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id a12sm16557460wrh.46.2019.04.30.06.14.41 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 30 Apr 2019 06:14:42 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Tue, 30 Apr 2019 14:14:36 +0100 Message-Id: <20190430131439.25251-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190430131439.25251-1-peter.maydell@linaro.org> References: <20190430131439.25251-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::341 Subject: [Qemu-devel] [PATCH 1/4] hw/arm/armv7m_nvic: Check subpriority in nvic_recompute_state_secure() X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP Rule R_CQRV says that if two pending interrupts have the same group priority then ties are broken by looking at the subpriority. We had a comment describing this but had forgotten to actually implement the subpriority comparison. Correct the omission. (The further tie break rules of "lowest exception number" and "secure before non-secure" are handled implicitly by the order in which we iterate through the exceptions in the loops.) Signed-off-by: Peter Maydell --- hw/intc/armv7m_nvic.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index fff6e694e60..131b5938b9a 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -213,6 +213,7 @@ static void nvic_recompute_state_secure(NVICState *s) int active_prio = NVIC_NOEXC_PRIO; int pend_irq = 0; bool pending_is_s_banked = false; + int pend_subprio = 0; /* R_CQRV: precedence is by: * - lowest group priority; if both the same then @@ -226,7 +227,7 @@ static void nvic_recompute_state_secure(NVICState *s) for (i = 1; i < s->num_irq; i++) { for (bank = M_REG_S; bank >= M_REG_NS; bank--) { VecInfo *vec; - int prio; + int prio, subprio; bool targets_secure; if (bank == M_REG_S) { @@ -241,8 +242,12 @@ static void nvic_recompute_state_secure(NVICState *s) } prio = exc_group_prio(s, vec->prio, targets_secure); - if (vec->enabled && vec->pending && prio < pend_prio) { + subprio = vec->prio & ~nvic_gprio_mask(s, targets_secure); + if (vec->enabled && vec->pending && + ((prio < pend_prio) || + (prio == pend_prio && prio >= 0 && subprio < pend_subprio))) { pend_prio = prio; + pend_subprio = subprio; pend_irq = i; pending_is_s_banked = (bank == M_REG_S); } From patchwork Tue Apr 30 13:14:37 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 10923435 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 5829B1395 for ; Tue, 30 Apr 2019 13:16:12 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 481F028941 for ; Tue, 30 Apr 2019 13:16:12 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 3C0282893F; Tue, 30 Apr 2019 13:16:12 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.0 required=2.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id CECA22893F for ; Tue, 30 Apr 2019 13:16:11 +0000 (UTC) Received: from localhost ([127.0.0.1]:47149 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hLScE-0002UI-VV for patchwork-qemu-devel@patchwork.kernel.org; Tue, 30 Apr 2019 09:16:11 -0400 Received: from eggs.gnu.org ([209.51.188.92]:44544) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hLSas-00010o-4t for qemu-devel@nongnu.org; Tue, 30 Apr 2019 09:14:47 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hLSar-0002Bt-2J for qemu-devel@nongnu.org; Tue, 30 Apr 2019 09:14:46 -0400 Received: from mail-wm1-x343.google.com ([2a00:1450:4864:20::343]:55147) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hLSaq-0002BR-Ry for qemu-devel@nongnu.org; Tue, 30 Apr 2019 09:14:45 -0400 Received: by mail-wm1-x343.google.com with SMTP id b10so3765812wmj.4 for ; Tue, 30 Apr 2019 06:14:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=J4qN3maoOxdBCp6dGsG2kVhWe6RDZ8cuN7qYfzK/kww=; b=Xw6o/TsZcr61F7M74hiyYgcGKQreolkQj7x1UqCIv2lrRti8g2TRfy+8LhSo7/5v62 zbBmb0xe81L0VHwxIm7W0DZ45+HcgK4UtEUlAzW0LbfyCqvJjbqIm5e/NqSKP3H3KRKo cp49UX5G5W4qQMRdQi4dM45p/z4lKQfyNyqwcy8O4MBEnr0vIGFS+aJhYeGs10aApLoj Lum3XReywRaAxwFVAXGLqIrxLxVgFbpivtZI8t0Wnd51oesgHERBPzMlAjVtmUZ7RC5W tx93VHxBaCF01krYy1XvaWeUK+c2N5WRH+lfVGsTZfU8+QgwALEhzL8Iw33o/5HHgux6 TWWw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=J4qN3maoOxdBCp6dGsG2kVhWe6RDZ8cuN7qYfzK/kww=; b=IUM/9kOex7KduI4A9654dko8tQLWJHd4rlBqofQrar+CwQ2/1YUcupVjTxkjugU2hd VKtDP9JNO7MaJkAD9FiUXdM5E1zp+r8RxA1zAVtikDL8dinV8n4JzoOKhed80UHVIEsz DT83kWmDDsljYL6v/bqPtNiu/Z91Tq+wRvE0ydCEvgjUQ999vQQP1qN7FOSs4Cd2tREt 4oADRiexhSlT+8Xn9nwQLTgk4ttJZjAyVqYKI7dA5U3KwvAQ741mFVb6VzgWSkFdM3c8 yjQ70PZgmRpCe6ns67FPieyKKAKrimHkvd0Or8ELmWnx/7fPsP9rSNlVldP2dm2n+D9s /13Q== X-Gm-Message-State: APjAAAX4Lrtzpo7LAbrEmoHJ0IeSCHqbUwRkfUdZmQJvE9wEkYYzDKZ3 AtMNIQtJX3zOOqEkRXALJWZ8BYAMUkU= X-Google-Smtp-Source: APXvYqxNvVeF1nyxAA8ubJ4ZJ0fP2WWxoVWxhj3eSHVMwxY2Qi3HH1LaRCCxpcCl8yTg7ek9PSAbkw== X-Received: by 2002:a1c:c287:: with SMTP id s129mr3174603wmf.63.1556630084008; Tue, 30 Apr 2019 06:14:44 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id a12sm16557460wrh.46.2019.04.30.06.14.42 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 30 Apr 2019 06:14:43 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Tue, 30 Apr 2019 14:14:37 +0100 Message-Id: <20190430131439.25251-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190430131439.25251-1-peter.maydell@linaro.org> References: <20190430131439.25251-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::343 Subject: [Qemu-devel] [PATCH 2/4] hw/intc/armv7m_nvic: NS BFAR and BFSR are RAZ/WI if BFHFNMINS == 0 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP The non-secure versions of the BFAR and BFSR registers are supposed to be RAZ/WI if AICR.BFHFNMINS == 0; we were incorrectly allowing NS code to access the real values. Signed-off-by: Peter Maydell --- hw/intc/armv7m_nvic.c | 27 ++++++++++++++++++++++++--- 1 file changed, 24 insertions(+), 3 deletions(-) diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index 131b5938b9a..15cba63c964 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -1167,6 +1167,10 @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs) if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) { goto bad_offset; } + if (!attrs.secure && + !(s->cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK)) { + return 0; + } return cpu->env.v7m.bfar; case 0xd3c: /* Aux Fault Status. */ /* TODO: Implement fault status registers. */ @@ -1646,6 +1650,10 @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value, if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) { goto bad_offset; } + if (!attrs.secure && + !(s->cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK)) { + return; + } cpu->env.v7m.bfar = value; return; case 0xd3c: /* Aux Fault Status. */ @@ -2130,11 +2138,18 @@ static MemTxResult nvic_sysreg_read(void *opaque, hwaddr addr, val = 0; break; }; - /* The BFSR bits [15:8] are shared between security states - * and we store them in the NS copy + /* + * The BFSR bits [15:8] are shared between security states + * and we store them in the NS copy. They are RAZ/WI for + * NS code if AIRCR.BFHFNMINS is 0. */ val = s->cpu->env.v7m.cfsr[attrs.secure]; - val |= s->cpu->env.v7m.cfsr[M_REG_NS] & R_V7M_CFSR_BFSR_MASK; + if (!attrs.secure && + !(s->cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK)) { + val &= ~R_V7M_CFSR_BFSR_MASK; + } else { + val |= s->cpu->env.v7m.cfsr[M_REG_NS] & R_V7M_CFSR_BFSR_MASK; + } val = extract32(val, (offset - 0xd28) * 8, size * 8); break; case 0xfe0 ... 0xfff: /* ID. */ @@ -2249,6 +2264,12 @@ static MemTxResult nvic_sysreg_write(void *opaque, hwaddr addr, */ value <<= ((offset - 0xd28) * 8); + if (!attrs.secure && + !(s->cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK)) { + /* BFSR bits are RAZ/WI for NS if BFHFNMINS is set */ + value &= ~R_V7M_CFSR_BFSR_MASK; + } + s->cpu->env.v7m.cfsr[attrs.secure] &= ~value; if (attrs.secure) { /* The BFSR bits [15:8] are shared between security states From patchwork Tue Apr 30 13:14:38 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 10923437 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 7543B1395 for ; Tue, 30 Apr 2019 13:16:16 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 6557028941 for ; Tue, 30 Apr 2019 13:16:16 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 59B6228980; Tue, 30 Apr 2019 13:16:16 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.0 required=2.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 0C3DA28941 for ; Tue, 30 Apr 2019 13:16:16 +0000 (UTC) Received: from localhost ([127.0.0.1]:47151 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hLScJ-0002Xc-9f for patchwork-qemu-devel@patchwork.kernel.org; Tue, 30 Apr 2019 09:16:15 -0400 Received: from eggs.gnu.org ([209.51.188.92]:44567) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hLSat-00011F-22 for qemu-devel@nongnu.org; Tue, 30 Apr 2019 09:14:48 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hLSas-0002Ci-4n for qemu-devel@nongnu.org; Tue, 30 Apr 2019 09:14:47 -0400 Received: from mail-wr1-x444.google.com ([2a00:1450:4864:20::444]:38670) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hLSar-0002C6-Uz for qemu-devel@nongnu.org; Tue, 30 Apr 2019 09:14:46 -0400 Received: by mail-wr1-x444.google.com with SMTP id k16so20992206wrn.5 for ; Tue, 30 Apr 2019 06:14:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=I770HJlrpYyPcn2fSD+8YRmqIqI0uc6EiRRpIG177mg=; b=tOP8JPe0OmsP842zlxFqCldEBPL0wNOborCn+ovfk/7S+Xd1RatiuCilvKb4cpCr8D I8xMDb4DgZNAzBj4dgTceIqmmu/20I5CiKx4mG99HrL6K3f0ewrogSAdidxAs4kad27X jP46n2MjKk2doK6Vx7viTlfe4ZvsPri/R7nwKujiz86JBMGyTh9EXcEJfG8VIAH3XHic 0Vgg89Aj1Mo4sVARzd+w4bEzFLSVwYfmhLZeTWyWjjyo2tKC/drwpeK+BJi3xoWrSqRb Y91jnfi6DoL4jm+D636KoZg+x7J0CZexxMOANrXu71IDF3Pq+umgW7hofG+DXcIo3kdn 19/w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=I770HJlrpYyPcn2fSD+8YRmqIqI0uc6EiRRpIG177mg=; b=QvsYRGxLHQqX9M52V7YjfhQGxyA1+dsYiO0xwLzvO44rNdZpqsIlvYMih2KnLzl6h/ KvjHqXOLP02eW/LP/sfTZnDNIzRw2EXCqAYYkpQ+/XacmshuNaXwuluydPMev9zQz9sa lKL+25hh2vVb2XRRTxS/PlSDE6C423MGSxOiQJZRGsGUZe67mKKY0VWFhUYF3yKIOWTs AR7ZTlzavb/WwjYcqirYEaKhTlsVDfAQ0yL3O5ovYfa8VD2qbbJY1xT5y/y50+j4Vgab LxM07FsGp5hIqEieXVOkFGSAlVutf7vX8H0u2SXc5pGbeQ7Ccq2h3a/iU7fhP38Bo3kr bwpA== X-Gm-Message-State: APjAAAUby5jh3ciqlVe9h3vN9yBwhOg4uhdjAvS0rb4I+KFzqJzIvPyB PmXcIAFlWncxpUgZGjZjhanVZN4hlSg= X-Google-Smtp-Source: APXvYqyW8N/Da+/Voy2JopI4Qkkam6svOhkb12FH94m1vWGIbj8Pi5pRDghseF+qVavOoDWU7I9uLQ== X-Received: by 2002:adf:b611:: with SMTP id f17mr21213990wre.162.1556630085112; Tue, 30 Apr 2019 06:14:45 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id a12sm16557460wrh.46.2019.04.30.06.14.44 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 30 Apr 2019 06:14:44 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Tue, 30 Apr 2019 14:14:38 +0100 Message-Id: <20190430131439.25251-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190430131439.25251-1-peter.maydell@linaro.org> References: <20190430131439.25251-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::444 Subject: [Qemu-devel] [PATCH 3/4] hw/intc/armv7m_nvic: Don't enable ARMV7M_EXCP_DEBUG from reset X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP The M-profile architecture specifies that the DebugMonitor exception should be initially disabled, not enabled. It should be controlled by the DEMCR register's MON_EN bit, but we don't implement that register yet (like most of the debug architecture for M-profile). Note that BKPT instructions will still work, because they will be escalated to HardFault. Signed-off-by: Peter Maydell --- hw/intc/armv7m_nvic.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index 15cba63c964..3a346a682a3 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -2491,10 +2491,12 @@ static void armv7m_nvic_reset(DeviceState *dev) * the System Handler Control register */ s->vectors[ARMV7M_EXCP_SVC].enabled = 1; - s->vectors[ARMV7M_EXCP_DEBUG].enabled = 1; s->vectors[ARMV7M_EXCP_PENDSV].enabled = 1; s->vectors[ARMV7M_EXCP_SYSTICK].enabled = 1; + /* DebugMonitor is enabled via DEMCR.MON_EN */ + s->vectors[ARMV7M_EXCP_DEBUG].enabled = 0; + resetprio = arm_feature(&s->cpu->env, ARM_FEATURE_V8) ? -4 : -3; s->vectors[ARMV7M_EXCP_RESET].prio = resetprio; s->vectors[ARMV7M_EXCP_NMI].prio = -2; From patchwork Tue Apr 30 13:14:39 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 10923439 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 25E441395 for ; Tue, 30 Apr 2019 13:19:14 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 1253728941 for ; Tue, 30 Apr 2019 13:19:14 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 06AA728980; Tue, 30 Apr 2019 13:19:14 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.0 required=2.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 969EF28941 for ; Tue, 30 Apr 2019 13:19:13 +0000 (UTC) Received: from localhost ([127.0.0.1]:47173 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hLSf8-0004Yc-2N for patchwork-qemu-devel@patchwork.kernel.org; Tue, 30 Apr 2019 09:19:12 -0400 Received: from eggs.gnu.org ([209.51.188.92]:44595) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hLSau-00012m-OF for qemu-devel@nongnu.org; Tue, 30 Apr 2019 09:14:49 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hLSat-0002Du-Mg for qemu-devel@nongnu.org; Tue, 30 Apr 2019 09:14:48 -0400 Received: from mail-wr1-x442.google.com ([2a00:1450:4864:20::442]:45574) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hLSat-0002DG-GG for qemu-devel@nongnu.org; Tue, 30 Apr 2019 09:14:47 -0400 Received: by mail-wr1-x442.google.com with SMTP id s15so20931621wra.12 for ; Tue, 30 Apr 2019 06:14:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=KjnNslhjeAVB43ev2plnZmB2mvGNvdHo3ozswBo1758=; b=HsV1RfBXMD1XBjZGomeprBuZWd2xYzlQWf1PoS+CplVCmcJVGdNJSYodcPJRrXcKgf pzinhIMtpePedJDmTHjGn1qOG4fjlqH3J80si0jFhzjZFwsxISkHEfuVjHIED4p9wLL+ qOtg5Q0mvkVe0ji8YcKen1yDA73rJ8wGPIbilXpYbdMzuN1sM81cAIm57FKq0VlIHqmF sTGY1Rbr33CbktlWwjbnmrTZ+qtu5a4hvtf1QpQpWM76nQrvMnGJ2u7/pyV36Jvr6rsC ECubcTtARpa7NwZvN7rjAnqzO6dGcA8hfXe/Itd3gyrOQOKHdgbJzR/xnjYzMPDIZdOl QLRQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=KjnNslhjeAVB43ev2plnZmB2mvGNvdHo3ozswBo1758=; b=ChETVE3www5YvH0vy6MyxLTblPJQ4f0x/4EDfKFNq8XoBCl5S4JecgFGyzkqQBJbao iiZoBr4wslQZH1anWy2wiwENgGpqXr+L0/WVeFePdKpCDCjqmLKVdERIpRLKrT1PhZqi YBaKYVQrzotwJY7i7VH486AoMTmN4+VRvPUZWwDefTV8869+vMQMayVktMLphvnQVDiw umSWPhkSdI/9ixeumbLXOg/O26W/Xl5XqBz2xOzm6h0iz7hIXyvsnOmNJ7lGg0b+7KTM FjbzRMcPFTcaRPz51LrT7Qh3T3j9AWUDwcutOFIEY5rp3s5w/qrd+xsz84w0u8i3MR/A yixg== X-Gm-Message-State: APjAAAUr4WtQKVFsAj4wlfv4n/Rf48bTTJBdDIQCAGMl2AoDTr3MPBfp 6avzlO1qv+9iGDdK+jMxvZJ5ixpLwi0= X-Google-Smtp-Source: APXvYqx7GCssL3ndoRJwFTkznx94O0Hd0b8TH9R2xj8TNLUOGtt1aD56J+DCau0hIWGSb+44JBbJ6Q== X-Received: by 2002:a05:6000:11ce:: with SMTP id i14mr16693110wrx.37.1556630086557; Tue, 30 Apr 2019 06:14:46 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id a12sm16557460wrh.46.2019.04.30.06.14.45 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 30 Apr 2019 06:14:45 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Tue, 30 Apr 2019 14:14:39 +0100 Message-Id: <20190430131439.25251-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190430131439.25251-1-peter.maydell@linaro.org> References: <20190430131439.25251-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::442 Subject: [Qemu-devel] [PATCH 4/4] target/arm: Implement XPSR GE bits X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP In the M-profile architecture, if the CPU implements the DSP extension then the XPSR has GE bits, in the same way as the A-profile CPSR. When we added DSP extension support we forgot to add support for reading and writing the GE bits, which are stored in env->GE. We did put in the code to add XPSR_GE to the mask of bits to update in the v7m_msr helper, but forgot it in v7m_mrs. We also must not allow the XPSR we pull off the stack on exception return to set the nonexistent GE bits. Correct these errors: * read and write env->GE in xpsr_read() and xpsr_write() * only set GE bits on exception return if DSP present * read GE bits for MRS if DSP present Signed-off-by: Peter Maydell --- target/arm/cpu.h | 4 ++++ target/arm/helper.c | 12 ++++++++++-- 2 files changed, 14 insertions(+), 2 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 22bc6e00ab9..2ae1b36eaee 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1285,6 +1285,7 @@ static inline uint32_t xpsr_read(CPUARMState *env) | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27) | (env->thumb << 24) | ((env->condexec_bits & 3) << 25) | ((env->condexec_bits & 0xfc) << 8) + | (env->GE << 16) | env->v7m.exception; } @@ -1300,6 +1301,9 @@ static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask) if (mask & XPSR_Q) { env->QF = ((val & XPSR_Q) != 0); } + if (mask & XPSR_GE) { + env->GE = (val & XPSR_GE) >> 16; + } if (mask & XPSR_T) { env->thumb = ((val & XPSR_T) != 0); } diff --git a/target/arm/helper.c b/target/arm/helper.c index 81a92ab4911..59ee5ee7c4a 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -8704,7 +8704,7 @@ static void do_v7m_exception_exit(ARMCPU *cpu) { CPUARMState *env = &cpu->env; uint32_t excret; - uint32_t xpsr; + uint32_t xpsr, xpsr_mask; bool ufault = false; bool sfault = false; bool return_to_sp_process; @@ -9156,8 +9156,13 @@ static void do_v7m_exception_exit(ARMCPU *cpu) } *frame_sp_p = frameptr; } + + xpsr_mask = ~(XPSR_SPREALIGN | XPSR_SFPA); + if (!arm_feature(env, ARM_FEATURE_THUMB_DSP)) { + xpsr_mask &= ~XPSR_GE; + } /* This xpsr_write() will invalidate frame_sp_p as it may switch stack */ - xpsr_write(env, xpsr, ~(XPSR_SPREALIGN | XPSR_SFPA)); + xpsr_write(env, xpsr, xpsr_mask); if (env->v7m.secure) { bool sfpa = xpsr & XPSR_SFPA; @@ -12642,6 +12647,9 @@ uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg) } if (!(reg & 4)) { mask |= XPSR_NZCV | XPSR_Q; /* APSR */ + if (arm_feature(env, ARM_FEATURE_THUMB_DSP)) { + mask |= XPSR_GE; + } } /* EPSR reads as zero */ return xpsr_read(env) & mask;