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Signed-off-by: Kalyani Akula --- Documentation/devicetree/bindings/crypto/zynqmp-sha.txt | 12 ++++++++++++ 1 file changed, 12 insertions(+) create mode 100644 Documentation/devicetree/bindings/crypto/zynqmp-sha.txt diff --git a/Documentation/devicetree/bindings/crypto/zynqmp-sha.txt b/Documentation/devicetree/bindings/crypto/zynqmp-sha.txt new file mode 100644 index 0000000..8b3cc55 --- /dev/null +++ b/Documentation/devicetree/bindings/crypto/zynqmp-sha.txt @@ -0,0 +1,12 @@ +Xilinx ZynqMP SHA3(keccak-384) hw acceleration support. + +The ZynqMp PS-SHA hw accelerator is used to calculate the +SHA3(keccak-384) hash value on the given user data. + +Required properties: +- compatible: should contain "xlnx,zynqmp-sha3-384" + +Example: + xlnx_sha3_384: sha384 { + compatible = "xlnx,zynqmp-sha3-384"; + }; From patchwork Thu May 2 10:34:40 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kalyani Akula X-Patchwork-Id: 10926501 X-Patchwork-Delegate: herbert@gondor.apana.org.au Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 05851933 for ; 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Thu, 02 May 2019 03:34:57 -0700 Received: from xsj-pvapsmtp01 (mailhost.xilinx.com [149.199.38.66]) by xsj-smtp-dlp1.xlnx.xilinx.com (8.13.8/8.13.1) with ESMTP id x42AYtt9032631; Thu, 2 May 2019 03:34:55 -0700 Received: from [172.23.155.80] (helo=xhdengvm155080.xilinx.com) by xsj-pvapsmtp01 with esmtp (Exim 4.63) (envelope-from ) id 1hM93G-0007VE-Mo; Thu, 02 May 2019 03:34:54 -0700 Received: by xhdengvm155080.xilinx.com (Postfix, from userid 23151) id DFCA381417; Thu, 2 May 2019 16:04:53 +0530 (IST) From: Kalyani Akula To: , , , , , , , , CC: Kalyani Akula , Kalyani Akula Subject: [RFC PATCH V3 2/4] firmware: xilinx: Add ZynqMP sha_hash API for SHA3 functionality Date: Thu, 2 May 2019 16:04:40 +0530 Message-ID: <1556793282-17346-3-git-send-email-kalyani.akula@xilinx.com> X-Mailer: git-send-email 1.9.5 In-Reply-To: <1556793282-17346-1-git-send-email-kalyani.akula@xilinx.com> References: <1556793282-17346-1-git-send-email-kalyani.akula@xilinx.com> X-RCIS-Action: ALLOW X-TM-AS-Product-Ver: IMSS-7.1.0.1224-8.2.0.1013-23620.005 X-TM-AS-User-Approved-Sender: Yes;Yes X-EOPAttributedMessage: 0 X-MS-Office365-Filtering-HT: Tenant X-Forefront-Antispam-Report: CIP:149.199.60.100;IPV:NLI;CTRY:US;EFV:NLI;SFV:NSPM;SFS:(10009020)(376002)(396003)(136003)(346002)(39860400002)(2980300002)(189003)(199004)(446003)(478600001)(11346002)(6266002)(336012)(426003)(90966002)(26005)(51416003)(305945005)(107886003)(4326008)(14444005)(110136005)(106002)(76176011)(54906003)(47776003)(186003)(63266004)(5660300002)(36756003)(103686004)(42186006)(316002)(16586007)(50466002)(52956003)(48376002)(70586007)(70206006)(476003)(126002)(356004)(6636002)(36386004)(6666004)(50226002)(486006)(8936002)(44832011)(2616005)(81156014)(81166006)(2906002)(8676002)(2201001)(5001870100001);DIR:OUT;SFP:1101;SCL:1;SRVR:BYAPR02MB5239;H:xsj-pvapsmtpgw02;FPR:;SPF:Pass;LANG:en;PTR:unknown-60-100.xilinx.com,xapps1.xilinx.com;MX:1;A:1; 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Signed-off-by: Kalyani Akula --- drivers/firmware/xilinx/zynqmp.c | 27 +++++++++++++++++++++++++++ include/linux/firmware/xlnx-zynqmp.h | 2 ++ 2 files changed, 29 insertions(+) diff --git a/drivers/firmware/xilinx/zynqmp.c b/drivers/firmware/xilinx/zynqmp.c index 98f9361..22a062a 100644 --- a/drivers/firmware/xilinx/zynqmp.c +++ b/drivers/firmware/xilinx/zynqmp.c @@ -619,9 +619,36 @@ static int zynqmp_pm_set_requirement(const u32 node, const u32 capabilities, qos, ack, NULL); } +/** + * zynqmp_pm_sha_hash - Access the SHA engine to calculate the hash + * @address: Address of the data/ Address of output buffer where + * hash should be stored. + * @size: Size of the data. + * @flags: + * BIT(0) - for initializing csudma driver and SHA3(Here address + * and size inputs can be NULL). + * BIT(1) - to call Sha3_Update API which can be called multiple + * times when data is not contiguous. + * BIT(2) - to get final hash of the whole updated data. + * Hash will be overwritten at provided address with + * 48 bytes. + * + * Return: Returns status, either success or error code. + */ +static int zynqmp_pm_sha_hash(const u64 address, const u32 size, + const u32 flags) +{ + u32 lower_32_bits = (u32)address; + u32 upper_32_bits = (u32)(address >> 32); + + return zynqmp_pm_invoke_fn(PM_SECURE_SHA, upper_32_bits, lower_32_bits, + size, flags, NULL); +} + static const struct zynqmp_eemi_ops eemi_ops = { .get_api_version = zynqmp_pm_get_api_version, .get_chipid = zynqmp_pm_get_chipid, + .sha_hash = zynqmp_pm_sha_hash, .query_data = zynqmp_pm_query_data, .clock_enable = zynqmp_pm_clock_enable, .clock_disable = zynqmp_pm_clock_disable, diff --git a/include/linux/firmware/xlnx-zynqmp.h b/include/linux/firmware/xlnx-zynqmp.h index 642dab1..124e5f0 100644 --- a/include/linux/firmware/xlnx-zynqmp.h +++ b/include/linux/firmware/xlnx-zynqmp.h @@ -57,6 +57,7 @@ enum pm_api_id { PM_RESET_GET_STATUS, PM_PM_INIT_FINALIZE = 21, PM_GET_CHIPID = 24, + PM_SECURE_SHA = 26, PM_IOCTL = 34, PM_QUERY_DATA, PM_CLOCK_ENABLE, @@ -283,6 +284,7 @@ struct zynqmp_eemi_ops { const u32 capabilities, const u32 qos, const enum zynqmp_pm_request_ack ack); + int (*sha_hash)(const u64 address, const u32 size, const u32 flags); }; int zynqmp_pm_invoke_fn(u32 pm_api_id, u32 arg0, u32 arg1, From patchwork Thu May 2 10:34:41 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kalyani Akula X-Patchwork-Id: 10926509 X-Patchwork-Delegate: herbert@gondor.apana.org.au Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 477A3933 for ; Thu, 2 May 2019 10:35:35 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 32C6E28F4D for ; Thu, 2 May 2019 10:35:35 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 233BA2903F; Thu, 2 May 2019 10:35:35 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 602E928F4D for ; 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Signed-off-by: Kalyani Akula --- drivers/crypto/Kconfig | 10 ++ drivers/crypto/Makefile | 1 + drivers/crypto/zynqmp-sha.c | 240 ++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 251 insertions(+) create mode 100644 drivers/crypto/zynqmp-sha.c diff --git a/drivers/crypto/Kconfig b/drivers/crypto/Kconfig index 0be55fc..d9647a0 100644 --- a/drivers/crypto/Kconfig +++ b/drivers/crypto/Kconfig @@ -667,6 +667,16 @@ config CRYPTO_DEV_ROCKCHIP This driver interfaces with the hardware crypto accelerator. Supporting cbc/ecb chainmode, and aes/des/des3_ede cipher mode. +config CRYPTO_DEV_ZYNQMP_SHA3 + tristate "Support for Xilinx ZynqMP SHA3 hw accelerator" + depends on ARCH_ZYNQMP || COMPILE_TEST + select CRYPTO_HASH + help + Xilinx ZynqMP has SHA3 engine used for secure hash calculation. + This driver interfaces with SHA3 hw engine. + Select this if you want to use the ZynqMP module + for SHA3 hash computation. + config CRYPTO_DEV_MEDIATEK tristate "MediaTek's EIP97 Cryptographic Engine driver" depends on (ARM && ARCH_MEDIATEK) || COMPILE_TEST diff --git a/drivers/crypto/Makefile b/drivers/crypto/Makefile index 8e7e225..64c29fe 100644 --- a/drivers/crypto/Makefile +++ b/drivers/crypto/Makefile @@ -47,3 +47,4 @@ obj-$(CONFIG_CRYPTO_DEV_BCM_SPU) += bcm/ obj-$(CONFIG_CRYPTO_DEV_SAFEXCEL) += inside-secure/ obj-$(CONFIG_CRYPTO_DEV_ARTPEC6) += axis/ obj-y += hisilicon/ +obj-$(CONFIG_CRYPTO_DEV_ZYNQMP_SHA3) += zynqmp-sha.o diff --git a/drivers/crypto/zynqmp-sha.c b/drivers/crypto/zynqmp-sha.c new file mode 100644 index 0000000..e8efe17 --- /dev/null +++ b/drivers/crypto/zynqmp-sha.c @@ -0,0 +1,240 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Cryptographic API. + * + * Support for Xilinx ZynqMP SHA3 HW Acceleration. + * + * Copyright (c) 2018 Xilinx Inc. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define ZYNQMP_SHA3_INIT 1 +#define ZYNQMP_SHA3_UPDATE 2 +#define ZYNQMP_SHA3_FINAL 4 + +static const struct zynqmp_eemi_ops *eemi_ops; +struct zynqmp_sha_dev *sha_dd; + +struct zynqmp_sha_reqctx { + struct zynqmp_sha_dev *dd; + unsigned long flags; +}; + +struct zynqmp_sha_ctx { + struct zynqmp_sha_dev *dd; + unsigned long flags; +}; + +struct zynqmp_sha_dev { + struct device *dev; + int err; + + unsigned long flags; + struct ahash_request *req; +}; + +static int zynqmp_sha_init(struct ahash_request *req) +{ + struct crypto_ahash *tfm = crypto_ahash_reqtfm(req); + struct zynqmp_sha_ctx *tctx = crypto_ahash_ctx(tfm); + struct zynqmp_sha_reqctx *ctx = ahash_request_ctx(req); + struct zynqmp_sha_dev *dd = sha_dd; + int ret; + + if (!eemi_ops->sha_hash) + return -ENOTSUPP; + + if (!tctx->dd) + tctx->dd = dd; + else + dd = tctx->dd; + + ctx->dd = dd; + dev_dbg(dd->dev, "init: digest size: %d\n", + crypto_ahash_digestsize(tfm)); + + ret = eemi_ops->sha_hash(0, 0, ZYNQMP_SHA3_INIT); + + return ret; +} + +static int zynqmp_sha_update(struct ahash_request *req) +{ + struct zynqmp_sha_ctx *tctx = crypto_tfm_ctx(req->base.tfm); + struct zynqmp_sha_dev *dd = tctx->dd; + size_t dma_size = req->nbytes; + dma_addr_t dma_addr; + char *kbuf; + int ret; + + if (!req->nbytes) + return 0; + + if (!eemi_ops->sha_hash) + return -ENOTSUPP; + + kbuf = dma_alloc_coherent(dd->dev, dma_size, &dma_addr, GFP_KERNEL); + if (!kbuf) + return -ENOMEM; + + scatterwalk_map_and_copy(kbuf, req->src, 0, req->nbytes, 0); + ret = eemi_ops->sha_hash(dma_addr, req->nbytes, ZYNQMP_SHA3_UPDATE); + dma_free_coherent(dd->dev, dma_size, kbuf, dma_addr); + + return ret; +} + +static int zynqmp_sha_final(struct ahash_request *req) +{ + struct zynqmp_sha_ctx *tctx = crypto_tfm_ctx(req->base.tfm); + struct zynqmp_sha_dev *dd = tctx->dd; + size_t dma_size = SHA384_DIGEST_SIZE; + dma_addr_t dma_addr; + char *kbuf; + int ret; + + if (!eemi_ops->sha_hash) + return -ENOTSUPP; + + kbuf = dma_alloc_coherent(dd->dev, dma_size, &dma_addr, GFP_KERNEL); + if (!kbuf) + return -ENOMEM; + + ret = eemi_ops->sha_hash(dma_addr, dma_size, ZYNQMP_SHA3_FINAL); + memcpy(req->result, kbuf, SHA384_DIGEST_SIZE); + dma_free_coherent(dd->dev, dma_size, kbuf, dma_addr); + + return ret; +} + +static int zynqmp_sha_finup(struct ahash_request *req) +{ + zynqmp_sha_update(req); + zynqmp_sha_final(req); + + return 0; +} + +static int zynqmp_sha_digest(struct ahash_request *req) +{ + zynqmp_sha_init(req); + zynqmp_sha_update(req); + zynqmp_sha_final(req); + + return 0; +} + +static int zynqmp_sha_cra_init(struct crypto_tfm *tfm) +{ + crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm), + sizeof(struct zynqmp_sha_reqctx)); + + return 0; +} + +static struct ahash_alg sha3_alg = { + .init = zynqmp_sha_init, + .update = zynqmp_sha_update, + .final = zynqmp_sha_final, + .finup = zynqmp_sha_finup, + .digest = zynqmp_sha_digest, + .halg = { + .digestsize = SHA384_DIGEST_SIZE, + .statesize = sizeof(struct sha256_state), + .base = { + .cra_name = "xilinx-sha3-384", + .cra_driver_name = "zynqmp-sha3-384", + .cra_priority = 300, + .cra_flags = CRYPTO_ALG_ASYNC, + .cra_blocksize = SHA384_BLOCK_SIZE, + .cra_ctxsize = sizeof(struct zynqmp_sha_ctx), + .cra_alignmask = 0, + .cra_module = THIS_MODULE, + .cra_init = zynqmp_sha_cra_init, + } + } +}; + +static const struct of_device_id zynqmp_sha_dt_ids[] = { + { .compatible = "xlnx,zynqmp-sha3-384" }, + { /* sentinel */ } +}; + +MODULE_DEVICE_TABLE(of, zynqmp_sha_dt_ids); + +static int zynqmp_sha_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + int err; + + eemi_ops = zynqmp_pm_get_eemi_ops(); + if (IS_ERR(eemi_ops)) + return PTR_ERR(eemi_ops); + + sha_dd = devm_kzalloc(&pdev->dev, sizeof(*sha_dd), GFP_KERNEL); + if (!sha_dd) + return -ENOMEM; + + sha_dd->dev = dev; + platform_set_drvdata(pdev, sha_dd); + + err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(44)); + if (err < 0) { + dev_err(dev, "no usable DMA configuration"); + goto err_algs; + } + + err = crypto_register_ahash(&sha3_alg); + if (err) + goto err_algs; + + return 0; + +err_algs: + return err; +} + +static int zynqmp_sha_remove(struct platform_device *pdev) +{ + sha_dd = platform_get_drvdata(pdev); + + if (!sha_dd) + return -ENODEV; + + crypto_unregister_ahash(&sha3_alg); + + return 0; +} + +static struct platform_driver zynqmp_sha_driver = { + .probe = zynqmp_sha_probe, + .remove = zynqmp_sha_remove, + .driver = { + .name = "zynqmp-keccak-384", + .of_match_table = of_match_ptr(zynqmp_sha_dt_ids), + }, +}; + +module_platform_driver(zynqmp_sha_driver); + +MODULE_DESCRIPTION("ZynqMP SHA3 hw acceleration support."); +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Nava kishore Manne "); From patchwork Thu May 2 10:34:42 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kalyani Akula X-Patchwork-Id: 10926511 X-Patchwork-Delegate: herbert@gondor.apana.org.au Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 68B8092A for ; Thu, 2 May 2019 10:35:44 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 56F6928F4D for ; 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Thu, 2 May 2019 03:34:55 -0700 Received: from [172.23.155.80] (helo=xhdengvm155080.xilinx.com) by xsj-pvapsmtp01 with esmtp (Exim 4.63) (envelope-from ) id 1hM93G-0007VG-Nz; Thu, 02 May 2019 03:34:54 -0700 Received: by xhdengvm155080.xilinx.com (Postfix, from userid 23151) id E81F28141F; Thu, 2 May 2019 16:04:53 +0530 (IST) From: Kalyani Akula To: , , , , , , , , CC: Kalyani Akula , Kalyani Akula Subject: [RFC PATCH V3 4/4] ARM64: zynqmp: Add Xilinix SHA-384 node. Date: Thu, 2 May 2019 16:04:42 +0530 Message-ID: <1556793282-17346-5-git-send-email-kalyani.akula@xilinx.com> X-Mailer: git-send-email 1.9.5 In-Reply-To: <1556793282-17346-1-git-send-email-kalyani.akula@xilinx.com> References: <1556793282-17346-1-git-send-email-kalyani.akula@xilinx.com> X-RCIS-Action: ALLOW X-TM-AS-Product-Ver: IMSS-7.1.0.1224-8.2.0.1013-23620.005 X-TM-AS-User-Approved-Sender: Yes;Yes X-EOPAttributedMessage: 0 X-MS-Office365-Filtering-HT: Tenant X-Forefront-Antispam-Report: CIP:149.199.60.83;IPV:NLI;CTRY:US;EFV:NLI;SFV:NSPM;SFS:(10009020)(376002)(346002)(136003)(39860400002)(396003)(2980300002)(199004)(189003)(16586007)(316002)(305945005)(90966002)(70206006)(478600001)(186003)(47776003)(36756003)(4326008)(52956003)(51416003)(5660300002)(6266002)(2906002)(8936002)(42186006)(110136005)(107886003)(8676002)(63266004)(106002)(48376002)(103686004)(356004)(4744005)(54906003)(6666004)(50226002)(81156014)(76176011)(81166006)(486006)(44832011)(336012)(426003)(2201001)(446003)(26005)(476003)(70586007)(50466002)(11346002)(2616005)(36386004)(126002)(6636002);DIR:OUT;SFP:1101;SCL:1;SRVR:MWHPR0201MB3404;H:xsj-pvapsmtpgw01;FPR:;SPF:Pass;LANG:en;PTR:unknown-60-83.xilinx.com;A:1;MX:1; MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: b3b1bfd8-d9a9-40c3-24d4-08d6cee9d5fb X-Microsoft-Antispam: BCL:0;PCL:0;RULEID:(2390118)(7020095)(4652040)(8989299)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(5600141)(711020)(4605104)(4709054)(2017052603328);SRVR:MWHPR0201MB3404; X-MS-TrafficTypeDiagnostic: MWHPR0201MB3404: X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:1079; X-Forefront-PRVS: 0025434D2D X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam-Message-Info: p1zcu/vSpgKTZRadwi/nHVp1Rv0OJh61/awokMIxKB3DK9tv7A8sj+uXsvtGNyLR3dVUMjM0cTvEz7V+SlrS2RGiiuO4T7A31LyFsV/sfkP+1z0E8odDQN+xS2gQrVLYjCwtcJw3PbqbWJuu5UARa3UMfX0NbobU1TRDXp5hz16x7KJIwRU71J3Cei1LTMyqOkWCRRp2EiiQU968TWlvyKbIzJo78UpbDPPv+2OuCVMj6cCx2JvF13nG92vnxZTM7uW/bkHK9RgNgUx3T55ojEadnGQ9fcIc/dnnSsMSgrMLL/qnYUSYlupsis5xZE9+i40FrndoBaA8JX8/JYZ5JRLr/4eSXNHtIQ8BIRSNOC9FRREHdIXQ51jgpN60yulnyi9kGuXUgXuAMErH+0+J11OqMDoD1arVo9lCPukqgao= X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 May 2019 10:35:02.8268 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b3b1bfd8-d9a9-40c3-24d4-08d6cee9d5fb X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c;Ip=[149.199.60.83];Helo=[xsj-pvapsmtpgw01] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MWHPR0201MB3404 Sender: linux-crypto-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch adds a SHA3 DT node for Xilinx ZynqMP SoC. Signed-off-by: Kalyani Akula --- arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi index 9aa6734..0532de7 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi +++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi @@ -124,6 +124,10 @@ <1 10 0xf08>; }; + xlnx_sha3_384: sha384 { + compatible = "xlnx,zynqmp-sha3-384"; + }; + amba_apu: amba-apu@0 { compatible = "simple-bus"; #address-cells = <2>;