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bh=Hg7TtsEFadnOjSgx3jp2tA+2HgpI1482WNMkndbFrzE=; b=Uu7kCih40Gl1GCo+QEr2xkT+jHLApBsrrQ1sOhmMxfiQOU1ic++/SAERmswNKgq5NE 3B6yH3hwpK/+bYLlPqjnwsNpmYFIOceLzIC8L1NhG4OVs017lSVcQGEZRVlpBTAa4CkY Xd0uNSN0nP0+gQD+xS8/0jzpRL93ebrAnfv5i2obr5E2an+O7q5V2ZQaRDp0IZxaylyk diCGjofJxPUfmqSWRvdDkSs9apVSBhOo3SUB9NfQMxHGHauDPk0m1FeguoE/n20X94MJ 5tKbJm65+lqHMQvW5MCXFsuAIWHiPbn1p8tcODEzlq0FeIMkX7t7zllwt14Rd72ZtAGb ZrCA== X-Gm-Message-State: APjAAAVUJRVpheN3PCb7rJG5OFRVhN8yUYhlJViUHjMQXakbbRNGkGax gXDYB4ZS6/h3MMgZ1TfJe/w= X-Google-Smtp-Source: APXvYqzAQr8cdbmARVLcsts793hCcZltNZV1HAC1L8AIp97l0A362BaRRxyz3ih407vfAWx6P+HL6w== X-Received: by 2002:a0c:9ac1:: with SMTP id k1mr2553094qvf.36.1556796627624; Thu, 02 May 2019 04:30:27 -0700 (PDT) Received: from fabio-Latitude-E5450.am.freescale.net ([2804:14c:482:3c8:56cb:1049:60d2:137b]) by smtp.gmail.com with ESMTPSA id a15sm6787239qkk.87.2019.05.02.04.30.24 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 02 May 2019 04:30:26 -0700 (PDT) From: Fabio Estevam To: shawnguo@kernel.org Subject: [PATCH] ARM: imx: cpuidle-imx6sx: Restrict the SW2ISO increase to i.MX6SX Date: Thu, 2 May 2019 08:30:20 -0300 Message-Id: <20190502113020.8642-1-festevam@gmail.com> X-Mailer: git-send-email 2.17.1 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190502_043028_939512_25BA0B3C X-CRM114-Status: GOOD ( 13.92 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cniedermaier@dh-electronics.com, anson.huang@nxp.com, stable@vger.kernel.org, linux-imx@nxp.com, kernel@pengutronix.de, Fabio Estevam , linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Since commit 1e434b703248 ("ARM: imx: update the cpu power up timing setting on i.mx6sx") some characters loss is noticed on i.MX6ULL UART as reported by Christoph Niedermaier. The intention of such commit was to increase the SW2ISO field for i.MX6SX only, but since cpuidle-imx6sx is also used on i.MX6UL/i.MX6ULL this caused unintended side effects on other SoCs. Fix this problem by keeping the original SW2ISO value for i.MX6UL/i.MX6ULL and only increase SW2ISO in the i.MX6SX case. Cc: stable@vger.kernel.org Fixes: 1e434b703248 ("ARM: imx: update the cpu power up timing setting on i.mx6sx") Reported-by: Christoph Niedermaier Signed-off-by: Fabio Estevam Tested-by: Sébastien Szymanski Tested-by: Christoph Niedermaier --- arch/arm/mach-imx/cpuidle-imx6sx.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-imx/cpuidle-imx6sx.c b/arch/arm/mach-imx/cpuidle-imx6sx.c index fd0053e47a15..57cb9c763222 100644 --- a/arch/arm/mach-imx/cpuidle-imx6sx.c +++ b/arch/arm/mach-imx/cpuidle-imx6sx.c @@ -15,6 +15,7 @@ #include "common.h" #include "cpuidle.h" +#include "hardware.h" static int imx6sx_idle_finish(unsigned long val) { @@ -99,8 +100,12 @@ static struct cpuidle_driver imx6sx_cpuidle_driver = { .safe_state_index = 0, }; +#define SW2ISO_ORIGINAL 0x2 +#define SW2ISO_IMX6SX 0xf int __init imx6sx_cpuidle_init(void) { + u32 sw2iso = SW2ISO_ORIGINAL; + imx6_set_int_mem_clk_lpm(true); imx6_enable_rbc(false); imx_gpc_set_l2_mem_power_in_lpm(false); @@ -110,7 +115,9 @@ int __init imx6sx_cpuidle_init(void) * except for power up sw2iso which need to be * larger than LDO ramp up time. */ - imx_gpc_set_arm_power_up_timing(0xf, 1); + if (cpu_is_imx6sx()) + sw2iso = SW2ISO_IMX6SX; + imx_gpc_set_arm_power_up_timing(sw2iso, 1); imx_gpc_set_arm_power_down_timing(1, 1); return cpuidle_register(&imx6sx_cpuidle_driver, NULL);