From patchwork Mon May 6 08:25:40 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wei Li X-Patchwork-Id: 10930685 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 26636933 for ; Mon, 6 May 2019 08:21:33 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 15C3527FA1 for ; Mon, 6 May 2019 08:21:33 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 06FC3284E9; Mon, 6 May 2019 08:21:33 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 7B0D527FA1 for ; Mon, 6 May 2019 08:21:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=49N/iwXmZhIPVWUlL9BNdzuHwfkuf2qLKZyAGXi07yA=; b=gZ8YgI/lh6Dan2 /pOFyMFbsiCF8HxC3qvgdxENAj0N0o9KafmJwIIaUyVZpiiSpdg3TpKAHd5z7cE2r0eU006sos+bJ iJhIcUBZIxQ3Ee+7DN6K72Pwuuig+GiGDIqn32lJNDrcIupYU5Jc7jsAwURzxl5th5QvGYBp6M49T O1GkR2IoFxCVOfUAL5ISk4uEXWbIPCpnjGphZc5rB0R6TaYhLJHI72QVOiTZa+/yDRzRgY9aY/NwE MYAoFw2mkePuSHbuYvIiLOnxQTRrqf9LxoqzyWR6a8kM+SdGKLdvFibPSgFGDXwUXixiANXZ90cR+ o7cJcaf1Ro7agGuIAEgg==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1hNYsJ-00050k-QD; Mon, 06 May 2019 08:21:27 +0000 Received: from szxga04-in.huawei.com ([45.249.212.190] helo=huawei.com) by bombadil.infradead.org with esmtps (Exim 4.90_1 #2 (Red Hat Linux)) id 1hNYrr-0004UG-1Q for linux-arm-kernel@lists.infradead.org; Mon, 06 May 2019 08:21:01 +0000 Received: from DGGEMS408-HUB.china.huawei.com (unknown [172.30.72.58]) by Forcepoint Email with ESMTP id B907F132402CA729FF3E; Mon, 6 May 2019 16:20:43 +0800 (CST) Received: from euler.huawei.com (10.175.104.193) by DGGEMS408-HUB.china.huawei.com (10.3.19.208) with Microsoft SMTP Server id 14.3.439.0; Mon, 6 May 2019 16:20:41 +0800 From: Wei Li To: , , , , Subject: [PATCH 1/3] arm64: Add pseudo NMI support of GICv3 SGIs Date: Mon, 6 May 2019 16:25:40 +0800 Message-ID: <20190506082542.11357-2-liwei391@huawei.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190506082542.11357-1-liwei391@huawei.com> References: <20190506082542.11357-1-liwei391@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.175.104.193] X-CFilter-Loop: Reflected X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190506_012059_310757_908DAF32 X-CRM114-Status: GOOD ( 16.14 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: julien.thierry@arm.com, daniel.thompson@linaro.org, lorenzo.pieralisi@arm.com, Suzuki.Poulose@arm.com, steve.capper@arm.com, linux-kernel@vger.kernel.org, james.morse@arm.com, sudeep.holla@arm.com, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Currently, only PPIs and SPIs can be set as NMIs. IPIs being currently hardcoded IRQ numbers, there isn't a generic interface to set SGIs as NMI for now. In this patch, we do: 1. Add an interface for setting priority of SGIs. 2. Export GICD_INT_NMI_PRI for setting priority of SGIs as NMI. 3. Move the gic_enable_nmi_support() earlier to make the gic_supports_nmi() check works in gic_cpu_init(). Signed-off-by: Wei Li Cc: Julien Thierry --- arch/arm64/include/asm/smp.h | 2 ++ arch/arm64/kernel/smp.c | 4 +++ drivers/irqchip/irq-gic-v3.c | 46 +++++++++++++++++++++----- include/linux/irqchip/arm-gic-common.h | 1 + include/linux/irqchip/arm-gic-v3.h | 1 + 5 files changed, 45 insertions(+), 9 deletions(-) diff --git a/arch/arm64/include/asm/smp.h b/arch/arm64/include/asm/smp.h index 18553f399e08..84d7ea073d84 100644 --- a/arch/arm64/include/asm/smp.h +++ b/arch/arm64/include/asm/smp.h @@ -158,6 +158,8 @@ bool cpus_are_stuck_in_kernel(void); extern void crash_smp_send_stop(void); extern bool smp_crash_stop_failed(void); +extern void ipi_gic_nmi_setup(void __iomem *base); + #endif /* ifndef __ASSEMBLY__ */ #endif /* ifndef __ASM_SMP_H */ diff --git a/arch/arm64/kernel/smp.c b/arch/arm64/kernel/smp.c index 824de7038967..bd8fdf6fcd8e 100644 --- a/arch/arm64/kernel/smp.c +++ b/arch/arm64/kernel/smp.c @@ -1067,3 +1067,7 @@ bool cpus_are_stuck_in_kernel(void) return !!cpus_stuck_in_kernel || smp_spin_tables; } + +void ipi_gic_nmi_setup(void __iomem *base) +{ +} diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c index 15e55d327505..394aa5668dd6 100644 --- a/drivers/irqchip/irq-gic-v3.c +++ b/drivers/irqchip/irq-gic-v3.c @@ -42,8 +42,6 @@ #include "irq-gic-common.h" -#define GICD_INT_NMI_PRI (GICD_INT_DEF_PRI & ~0x80) - #define FLAGS_WORKAROUND_GICR_WAKER_MSM8996 (1ULL << 0) struct redist_region { @@ -324,6 +322,23 @@ static int gic_irq_get_irqchip_state(struct irq_data *d, return 0; } +void gic_sgi_set_prio(void __iomem *base, u32 irqnr, u8 prio) +{ + u32 val, offset; + + offset = GICR_IPRIORITYR0 + ((irqnr / 4) * 4); + + /* + * Using writeb here may cause hardware error on some CPUs, + * aovid this quirk by using writel. + */ + val = readl_relaxed(base + offset); + val &= ~(0xff << ((irqnr % 4) * 8)); + val |= prio << ((irqnr % 4) * 8); + + writel_relaxed(val, base + offset); +} + static void gic_irq_set_prio(struct irq_data *d, u8 prio) { void __iomem *base = gic_dist_base(d); @@ -474,6 +489,16 @@ static inline void gic_handle_nmi(u32 irqnr, struct pt_regs *regs) { int err; + if (unlikely(irqnr < 16)) { + gic_write_eoir(irqnr); + if (static_branch_likely(&supports_deactivate_key)) + gic_write_dir(irqnr); +#ifdef CONFIG_SMP + handle_IPI(irqnr, regs); +#endif + return; + } + if (static_branch_likely(&supports_deactivate_key)) gic_write_eoir(irqnr); /* @@ -859,6 +884,9 @@ static void gic_cpu_init(void) gic_cpu_config(rbase, gic_redist_wait_for_rwp); + if (gic_supports_nmi()) + ipi_gic_nmi_setup(rbase); + /* initialise system registers */ gic_cpu_sys_reg_init(); } @@ -1335,6 +1363,13 @@ static int __init gic_init_bases(void __iomem *dist_base, gic_update_vlpi_properties(); + if (gic_prio_masking_enabled()) { + if (!gic_has_group0() || gic_dist_security_disabled()) + gic_enable_nmi_support(); + else + pr_warn("SCR_EL3.FIQ is cleared, cannot enable use of pseudo-NMIs\n"); + } + gic_smp_init(); gic_dist_init(); gic_cpu_init(); @@ -1345,13 +1380,6 @@ static int __init gic_init_bases(void __iomem *dist_base, its_cpu_init(); } - if (gic_prio_masking_enabled()) { - if (!gic_has_group0() || gic_dist_security_disabled()) - gic_enable_nmi_support(); - else - pr_warn("SCR_EL3.FIQ is cleared, cannot enable use of pseudo-NMIs\n"); - } - return 0; out_free: diff --git a/include/linux/irqchip/arm-gic-common.h b/include/linux/irqchip/arm-gic-common.h index 9a1a479a2bf4..d8c973295179 100644 --- a/include/linux/irqchip/arm-gic-common.h +++ b/include/linux/irqchip/arm-gic-common.h @@ -18,6 +18,7 @@ (GICD_INT_DEF_PRI << 16) |\ (GICD_INT_DEF_PRI << 8) |\ GICD_INT_DEF_PRI) +#define GICD_INT_NMI_PRI (GICD_INT_DEF_PRI & ~0x80) enum gic_type { GIC_V2, diff --git a/include/linux/irqchip/arm-gic-v3.h b/include/linux/irqchip/arm-gic-v3.h index c848a7cc502e..dc1c418229e7 100644 --- a/include/linux/irqchip/arm-gic-v3.h +++ b/include/linux/irqchip/arm-gic-v3.h @@ -606,6 +606,7 @@ int its_cpu_init(void); int its_init(struct fwnode_handle *handle, struct rdists *rdists, struct irq_domain *domain); int mbi_init(struct fwnode_handle *fwnode, struct irq_domain *parent); +void gic_sgi_set_prio(void __iomem *base, u32 irqnr, u8 prio); static inline bool gic_enable_sre(void) { From patchwork Mon May 6 08:25:41 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wei Li X-Patchwork-Id: 10930683 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 742841390 for ; Mon, 6 May 2019 08:21:14 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 63D9727FA1 for ; Mon, 6 May 2019 08:21:14 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 57454284E9; Mon, 6 May 2019 08:21:14 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id E7FE927FA1 for ; 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Mon, 06 May 2019 08:21:13 +0000 Received: from szxga04-in.huawei.com ([45.249.212.190] helo=huawei.com) by bombadil.infradead.org with esmtps (Exim 4.90_1 #2 (Red Hat Linux)) id 1hNYrq-0004UF-Li for linux-arm-kernel@lists.infradead.org; Mon, 06 May 2019 08:21:00 +0000 Received: from DGGEMS408-HUB.china.huawei.com (unknown [172.30.72.59]) by Forcepoint Email with ESMTP id 510C3F015AB8680A8616; Mon, 6 May 2019 16:20:44 +0800 (CST) Received: from euler.huawei.com (10.175.104.193) by DGGEMS408-HUB.china.huawei.com (10.3.19.208) with Microsoft SMTP Server id 14.3.439.0; Mon, 6 May 2019 16:20:41 +0800 From: Wei Li To: , , , , Subject: [PATCH 2/3] arm64: Add support for on-demand backtrace of other CPUs Date: Mon, 6 May 2019 16:25:41 +0800 Message-ID: <20190506082542.11357-3-liwei391@huawei.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190506082542.11357-1-liwei391@huawei.com> References: <20190506082542.11357-1-liwei391@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.175.104.193] X-CFilter-Loop: Reflected X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190506_012058_940288_C784EB70 X-CRM114-Status: GOOD ( 13.13 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: julien.thierry@arm.com, daniel.thompson@linaro.org, lorenzo.pieralisi@arm.com, Suzuki.Poulose@arm.com, steve.capper@arm.com, linux-kernel@vger.kernel.org, james.morse@arm.com, sudeep.holla@arm.com, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP To support backtracing of other CPUs in the system on lockups, add the implementation of arch_trigger_cpumask_backtrace() for arm64. In this patch, we add an arm64 NMI-like IPI based backtracer, referring to the implementation on arm by Russell King and Chris Metcalf. Signed-off-by: Wei Li --- arch/arm64/include/asm/hardirq.h | 2 +- arch/arm64/include/asm/irq.h | 6 ++++++ arch/arm64/kernel/smp.c | 22 +++++++++++++++++++++- 3 files changed, 28 insertions(+), 2 deletions(-) diff --git a/arch/arm64/include/asm/hardirq.h b/arch/arm64/include/asm/hardirq.h index 89691c86640a..a5d94aa59c7c 100644 --- a/arch/arm64/include/asm/hardirq.h +++ b/arch/arm64/include/asm/hardirq.h @@ -24,7 +24,7 @@ #include #include -#define NR_IPI 7 +#define NR_IPI 8 typedef struct { unsigned int __softirq_pending; diff --git a/arch/arm64/include/asm/irq.h b/arch/arm64/include/asm/irq.h index b2b0c6405eb0..28471df488c0 100644 --- a/arch/arm64/include/asm/irq.h +++ b/arch/arm64/include/asm/irq.h @@ -13,5 +13,11 @@ static inline int nr_legacy_irqs(void) return 0; } +#ifdef CONFIG_SMP +extern void arch_trigger_cpumask_backtrace(const cpumask_t *mask, + bool exclude_self); +#define arch_trigger_cpumask_backtrace arch_trigger_cpumask_backtrace +#endif + #endif /* !__ASSEMBLER__ */ #endif diff --git a/arch/arm64/kernel/smp.c b/arch/arm64/kernel/smp.c index bd8fdf6fcd8e..7e862f9124f3 100644 --- a/arch/arm64/kernel/smp.c +++ b/arch/arm64/kernel/smp.c @@ -35,6 +35,7 @@ #include #include #include +#include #include #include #include @@ -83,7 +84,8 @@ enum ipi_msg_type { IPI_CPU_CRASH_STOP, IPI_TIMER, IPI_IRQ_WORK, - IPI_WAKEUP + IPI_WAKEUP, + IPI_CPU_BACKTRACE }; #ifdef CONFIG_HOTPLUG_CPU @@ -787,6 +789,7 @@ static const char *ipi_types[NR_IPI] __tracepoint_string = { S(IPI_TIMER, "Timer broadcast interrupts"), S(IPI_IRQ_WORK, "IRQ work interrupts"), S(IPI_WAKEUP, "CPU wake-up interrupts"), + S(IPI_CPU_BACKTRACE, "Backtrace interrupts"), }; static void smp_cross_call(const struct cpumask *target, unsigned int ipinr) @@ -946,6 +949,12 @@ void handle_IPI(int ipinr, struct pt_regs *regs) break; #endif + case IPI_CPU_BACKTRACE: + nmi_enter(); + nmi_cpu_backtrace(regs); + nmi_exit(); + break; + default: pr_crit("CPU%u: Unknown IPI message 0x%x\n", cpu, ipinr); break; @@ -1070,4 +1079,15 @@ bool cpus_are_stuck_in_kernel(void) void ipi_gic_nmi_setup(void __iomem *base) { + gic_sgi_set_prio(base, IPI_CPU_BACKTRACE, GICD_INT_NMI_PRI); +} + +static void raise_nmi(cpumask_t *mask) +{ + smp_cross_call(mask, IPI_CPU_BACKTRACE); +} + +void arch_trigger_cpumask_backtrace(const cpumask_t *mask, bool exclude_self) +{ + nmi_trigger_cpumask_backtrace(mask, exclude_self, raise_nmi); } From patchwork Mon May 6 08:25:42 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wei Li X-Patchwork-Id: 10930681 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id CE1F1924 for ; Mon, 6 May 2019 08:21:07 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id BE0BB27FA1 for ; Mon, 6 May 2019 08:21:07 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id B1C60284E9; Mon, 6 May 2019 08:21:07 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 568A727FA1 for ; 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Mon, 06 May 2019 08:21:02 +0000 Received: from szxga04-in.huawei.com ([45.249.212.190] helo=huawei.com) by bombadil.infradead.org with esmtps (Exim 4.90_1 #2 (Red Hat Linux)) id 1hNYrq-0004UI-NT for linux-arm-kernel@lists.infradead.org; Mon, 06 May 2019 08:21:00 +0000 Received: from DGGEMS408-HUB.china.huawei.com (unknown [172.30.72.59]) by Forcepoint Email with ESMTP id C774E5F37D8C6047197F; Mon, 6 May 2019 16:20:43 +0800 (CST) Received: from euler.huawei.com (10.175.104.193) by DGGEMS408-HUB.china.huawei.com (10.3.19.208) with Microsoft SMTP Server id 14.3.439.0; Mon, 6 May 2019 16:20:42 +0800 From: Wei Li To: , , , , Subject: [PATCH 3/3] arm64: Avoid entering NMI context improperly Date: Mon, 6 May 2019 16:25:42 +0800 Message-ID: <20190506082542.11357-4-liwei391@huawei.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190506082542.11357-1-liwei391@huawei.com> References: <20190506082542.11357-1-liwei391@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.175.104.193] X-CFilter-Loop: Reflected X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190506_012058_999948_228BB297 X-CRM114-Status: GOOD ( 12.25 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: julien.thierry@arm.com, daniel.thompson@linaro.org, lorenzo.pieralisi@arm.com, Suzuki.Poulose@arm.com, steve.capper@arm.com, linux-kernel@vger.kernel.org, james.morse@arm.com, sudeep.holla@arm.com, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP As the pseudo NMI can be enabled/disabled by cmdline parameter, the arch_trigger_cpumask_backtrace() may still work through a normal IPI. In this patch, we export the gic_supports_nmi() and add a check in IPI_CPU_BACKTRACE process to avoid entering NMI context when pseudo NMI is disabled. Signed-off-by: Wei Li --- arch/arm64/include/asm/arch_gicv3.h | 8 ++++++++ arch/arm64/kernel/smp.c | 14 ++++++++++++-- drivers/irqchip/irq-gic-v3.c | 8 +------- 3 files changed, 21 insertions(+), 9 deletions(-) diff --git a/arch/arm64/include/asm/arch_gicv3.h b/arch/arm64/include/asm/arch_gicv3.h index 14b41ddc68ba..6655701ea7d4 100644 --- a/arch/arm64/include/asm/arch_gicv3.h +++ b/arch/arm64/include/asm/arch_gicv3.h @@ -156,6 +156,14 @@ static inline u32 gic_read_rpr(void) #define gits_write_vpendbaser(v, c) writeq_relaxed(v, c) #define gits_read_vpendbaser(c) readq_relaxed(c) +extern struct static_key_false supports_pseudo_nmis; + +static inline bool gic_supports_nmi(void) +{ + return IS_ENABLED(CONFIG_ARM64_PSEUDO_NMI) && + static_branch_likely(&supports_pseudo_nmis); +} + static inline bool gic_prio_masking_enabled(void) { return system_uses_irq_prio_masking(); diff --git a/arch/arm64/kernel/smp.c b/arch/arm64/kernel/smp.c index 7e862f9124f3..5550951527ea 100644 --- a/arch/arm64/kernel/smp.c +++ b/arch/arm64/kernel/smp.c @@ -950,9 +950,19 @@ void handle_IPI(int ipinr, struct pt_regs *regs) #endif case IPI_CPU_BACKTRACE: - nmi_enter(); + if (gic_supports_nmi()) { + nmi_enter(); + } else { + printk_nmi_enter(); + irq_enter(); + } nmi_cpu_backtrace(regs); - nmi_exit(); + if (gic_supports_nmi()) { + nmi_exit(); + } else { + irq_exit(); + printk_nmi_exit(); + } break; default: diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c index 394aa5668dd6..b701727258b0 100644 --- a/drivers/irqchip/irq-gic-v3.c +++ b/drivers/irqchip/irq-gic-v3.c @@ -90,7 +90,7 @@ static DEFINE_STATIC_KEY_TRUE(supports_deactivate_key); * For now, we only support pseudo-NMIs if we have non-secure view of * priorities. */ -static DEFINE_STATIC_KEY_FALSE(supports_pseudo_nmis); +DEFINE_STATIC_KEY_FALSE(supports_pseudo_nmis); /* ppi_nmi_refs[n] == number of cpus having ppi[n + 16] set as NMI */ static refcount_t ppi_nmi_refs[16]; @@ -261,12 +261,6 @@ static void gic_unmask_irq(struct irq_data *d) gic_poke_irq(d, GICD_ISENABLER); } -static inline bool gic_supports_nmi(void) -{ - return IS_ENABLED(CONFIG_ARM64_PSEUDO_NMI) && - static_branch_likely(&supports_pseudo_nmis); -} - static int gic_irq_set_irqchip_state(struct irq_data *d, enum irqchip_irq_state which, bool val) {