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Mon, 6 May 2019 15:12:09 +0000 (GMT) From: Lukasz Luba To: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-samsung-soc@vger.kernel.org Cc: b.zolnierkie@samsung.com, krzk@kernel.org, kgene@kernel.org, cw00.choi@samsung.com, kyungmin.park@samsung.com, m.szyprowski@samsung.com, s.nawrocki@samsung.com, myungjoo.ham@samsung.com, keescook@chromium.org, tony@atomide.com, jroedel@suse.de, treding@nvidia.com, digetx@gmail.com, willy.mh.wolff.ml@gmail.com, Lukasz Luba Subject: [PATCH v7 01/13] clk: samsung: add needed IDs for DMC clocks in Exynos5420 Date: Mon, 6 May 2019 17:11:49 +0200 Message-Id: <1557155521-30949-2-git-send-email-l.luba@partner.samsung.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1557155521-30949-1-git-send-email-l.luba@partner.samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA0WSWUwTURSGubO002pxKCg3iEuaEBSlCDF4o8RIxGQCiTEmviAGqkwApYAd QKE+FAwIKrsLi0jhAbAIyBq2SCxlCWBBJVFZDNgILojI5kIQKVP07Tvn/P/5T24uhUs7SQcq LCKaVUUowmUCMdHY9cvo2ndyMOBAw5AHqsmtJtHrhSkSFRmMJKr4bgIop7cQQ/23lCjD9AVH AwNPhOh54rQQDWsc0auWBwI0n2YAKHfgKYYqDWNCNJJQLkAd0zdI1D7ki0aWrdFSz3twzJZZ WswmmALNC4Jpzh8TMrW6VAGTdn1GwDybacOY9HodYOr61Mx87c5TIn+xVzAbHhbLqtyOBolD q271CqJabK5mFqULNeCT9U0goiB9ECbqi8mbQExJ6XIA5/pNlmIBwMmCWsAX8wBWzNzFNyxZ 2aUYPygDcDFPi/2ztCQkrfkpSkDLYZPustlgR6vh6Ot23KzB6WkMPv/9kzAPbOkzsHhuHDMz QTvBiQ7DOktoX5he029J2wnfGlPXWUT7wZUU/fpJkH4nhI9WsgTmMEj7wK5WT15vCz931wt5 doSrzUUYzxzUpBUDnq9BU0ahRXMEdnS/WL8Zp/fC6hY3vu0NDaYGwG+3hm++2pjb+BpmN97H +bYEpiRLefUeWH970BK0DZY9vmdZzsCKzB6Cf52HAN6umsUzwa78/2FaAHTAno3hlCEs5x7B XpFzCiUXExEivxCprAVrn6vvT/dcE1h8eV4PaArINks++gwGSElFLBen1ANI4TI7iWLSGCCV BCvi4llVZKAqJpzl9GA7RcjsJWqr8bNSOkQRzV5i2ShWtTHFKJGDBoRoqxz2VfhvcUgebGzb kSuaEZ8r1y0R8aMP1JMlF4e95YEucunE1uWxGvdvdS7aWeeYO6k+ZHFQ8lTnIR/n016r5ZGT pFclUeqnyWlrjQzIqtpfaJUf9KN/2OiqOe6U7jFUgHo9vdNWyIKoD4djk3Lm8zrdL2ef2K3e tGpV0lokI7hQhbsLruIUfwHfezYOWAMAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrBIsWRmVeSWpSXmKPExsVy+t/xu7qn/C7EGCyYqGmxccZ6VovrX56z Wsw/co7VYvXHx4wWk0/NZbI4051r0f/4NbPF+fMb2C3ONr1ht7jVIGNxedccNovPvUcYLWac 38dksfbIXXaL240r2CwOv2lntdh/xcvi9m8+i28nHjE6CHt8+zqJxWN2w0UWj52z7rJ7bFrV yebR2/yOzePguz1MHn1bVjF6bD5d7fF5k1wAZ5SeTVF+aUmqQkZ+cYmtUrShhZGeoaWFnpGJ pZ6hsXmslZGpkr6dTUpqTmZZapG+XYJexrruU2wFuwQrJszvY29gfMnXxcjJISFgIjFx0jKm LkYuDiGBpYwSFxses0EkxCQm7dvODmELS/y51sUGUfSJUaJnbitQBwcHm4CexI5VhSA1IgL1 Ev1vLoHVMAs0MEus2X6VFSQhLBAssff2TDCbRUBV4uHhI0wgNq+Al0TfxjPMEAvkJG6e6wSz OQW8Jf52HGIEsYWAavZ9/M0ygZFvASPDKkaR1NLi3PTcYiO94sTc4tK8dL3k/NxNjMBY2nbs 55YdjF3vgg8xCnAwKvHwPrC9ECPEmlhWXJl7iFGCg1lJhDfx2bkYId6UxMqq1KL8+KLSnNTi Q4ymQEdNZJYSTc4HxnleSbyhqaG5haWhubG5sZmFkjhvh8DBGCGB9MSS1OzU1ILUIpg+Jg5O qQbGLVv3bKr6w+vb+kK46Yvcxkj/Uq77lfn/+A//DbohMbmp4cruqgN7Hm36o+KssVtGQMxH S7fG/VXnr6O5iqp/Lc6rSzXdquyq23/jnPcO69z2S4/PnfMLEpoT/Nnv4wydpfKaGTN0n5za uMe2TiJ+R/eVV7uPx9TLbJOcO8l9U8w2qytXTCdlKLEUZyQaajEXFScCAKFO+jC7AgAA X-CMS-MailID: 20190506151210eucas1p13c2a4b86a6f987ff34fbe1e2d705fbbf X-Msg-Generator: CA X-RootMTR: 20190506151210eucas1p13c2a4b86a6f987ff34fbe1e2d705fbbf X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20190506151210eucas1p13c2a4b86a6f987ff34fbe1e2d705fbbf References: <1557155521-30949-1-git-send-email-l.luba@partner.samsung.com> Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Define new IDs for clocks used by Dynamic Memory Controller in Exynos5422 SoC. Acked-by: Rob Herring Signed-off-by: Lukasz Luba --- include/dt-bindings/clock/exynos5420.h | 28 ++++++++++++++++++++++------ 1 file changed, 22 insertions(+), 6 deletions(-) diff --git a/include/dt-bindings/clock/exynos5420.h b/include/dt-bindings/clock/exynos5420.h index 355f469..bf50d8a 100644 --- a/include/dt-bindings/clock/exynos5420.h +++ b/include/dt-bindings/clock/exynos5420.h @@ -60,6 +60,7 @@ #define CLK_MAU_EPLL 159 #define CLK_SCLK_HSIC_12M 160 #define CLK_SCLK_MPHY_IXTAL24 161 +#define CLK_SCLK_BPLL 162 /* gate clocks */ #define CLK_UART0 257 @@ -195,6 +196,16 @@ #define CLK_ACLK432_CAM 518 #define CLK_ACLK_FL1550_CAM 519 #define CLK_ACLK550_CAM 520 +#define CLK_CLKM_PHY0 521 +#define CLK_CLKM_PHY1 522 +#define CLK_ACLK_PPMU_DREX0_0 523 +#define CLK_ACLK_PPMU_DREX0_1 524 +#define CLK_ACLK_PPMU_DREX1_0 525 +#define CLK_ACLK_PPMU_DREX1_1 526 +#define CLK_PCLK_PPMU_DREX0_0 527 +#define CLK_PCLK_PPMU_DREX0_1 528 +#define CLK_PCLK_PPMU_DREX1_0 529 +#define CLK_PCLK_PPMU_DREX1_1 530 /* mux clocks */ #define CLK_MOUT_HDMI 640 @@ -217,6 +228,8 @@ #define CLK_MOUT_EPLL 657 #define CLK_MOUT_MAU_EPLL 658 #define CLK_MOUT_USER_MAU_EPLL 659 +#define CLK_MOUT_SCLK_SPLL 660 +#define CLK_MOUT_MX_MSPLL_CCORE_PHY 661 /* divider clocks */ #define CLK_DOUT_PIXEL 768 @@ -243,13 +256,16 @@ #define CLK_DOUT_ACLK300_GSCL 789 #define CLK_DOUT_ACLK400_DISP1 790 #define CLK_DOUT_PCLK_CDREX 791 -#define CLK_DOUT_SCLK_CDREX 792 -#define CLK_DOUT_ACLK_CDREX1 793 -#define CLK_DOUT_CCLK_DREX0 794 -#define CLK_DOUT_CLK2X_PHY0 795 -#define CLK_DOUT_PCLK_CORE_MEM 796 +#define CLK_DOUT_PCLK_DREX0 792 +#define CLK_DOUT_PCLK_DREX1 793 +#define CLK_DOUT_SCLK_CDREX 794 +#define CLK_DOUT_ACLK_CDREX1 795 +#define CLK_DOUT_CCLK_DREX0 796 +#define CLK_DOUT_CLK2X_PHY0 797 +#define CLK_DOUT_PCLK_CORE_MEM 798 +#define CLK_FF_DOUT_SPLL2 799 /* must be greater than maximal clock id */ -#define CLK_NR_CLKS 797 +#define CLK_NR_CLKS 800 #endif /* _DT_BINDINGS_CLOCK_EXYNOS_5420_H */ From patchwork Mon May 6 15:11:50 2019 Content-Type: text/plain; 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Mon, 6 May 2019 15:12:10 +0000 (GMT) From: Lukasz Luba To: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-samsung-soc@vger.kernel.org Cc: b.zolnierkie@samsung.com, krzk@kernel.org, kgene@kernel.org, cw00.choi@samsung.com, kyungmin.park@samsung.com, m.szyprowski@samsung.com, s.nawrocki@samsung.com, myungjoo.ham@samsung.com, keescook@chromium.org, tony@atomide.com, jroedel@suse.de, treding@nvidia.com, digetx@gmail.com, willy.mh.wolff.ml@gmail.com, Lukasz Luba Subject: [PATCH v7 02/13] clk: samsung: add new clocks for DMC for Exynos5422 SoC Date: Mon, 6 May 2019 17:11:50 +0200 Message-Id: <1557155521-30949-3-git-send-email-l.luba@partner.samsung.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1557155521-30949-1-git-send-email-l.luba@partner.samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrCKsWRmVeSWpSXmKPExsWy7djP87pn/C7EGEw7z2WxccZ6VovrX56z Wsw/co7VYvXHx4wWk0/NZbI4051r0f/4NbPF+fMb2C3ONr1ht7jVIGNxedccNovPvUcYLWac 38dksfbIXXaL240r2CwOv2lntdh/xcvi9m8+i28nHjE6CHt8+zqJxWN2w0UWj52z7rJ7bFrV yebR2/yOzePguz1MHn1bVjF6bD5d7fF5k1wAZxSXTUpqTmZZapG+XQJXxvr7O5gLHhpW/Lix jrmBcYtWFyMnh4SAicTMNS+Yuhi5OIQEVjBKNP6ZC+V8YZToaFnMBuF8ZpRYuGUGI0zLh78/ oaqWM0o82NPJDtdyds4T1i5GDg42AT2JHasKQRpEBKol7lzfzwxSwyzwhkni7K8fLCAJYYFg iTvdTYwg9SwCqhLf3vKAmLwCXhJrf0PtkpO4ea6TGcTmFPCW+NtxiBFkjITAPXaJ1kebWSCK XCT6Nm1mhrCFJV4d38IOYctI/N85nwnCLpZo6F0INbRG4nH/XKgaa4nDxy+CncwsoCmxfpc+ RNhRouvLCrCwhACfxI23giBhZiBz0rbpzBBhXomONiGIag2JLT0XoBaJSSxfMw1quIfExSW9 0CCcxyjR8/Mp6wRG+VkIyxYwMq5iFE8tLc5NTy02zkst1ytOzC0uzUvXS87P3cQITFun/x3/ uoNx35+kQ4wCHIxKPLwTnC7ECLEmlhVX5h5ilOBgVhLhTXx2LkaINyWxsiq1KD++qDQntfgQ ozQHi5I4bzXDg2ghgfTEktTs1NSC1CKYLBMHp1QD45kmI3adRL2E32qS4QERP9q/XBPVy2DQ NAqvixCz0nS3ZwiyjuvkUZkxnTGkYIHno+SXgUrXXm4zXez7K05Ru/FlwY5l/Cm7Hs29WS82 7WjMEo2/e9n0AnpNfhXq+MfZXHzzYdMZ641yjqr+O2J23XnmrxH1Puvoqr3/ltUslG/8+cJx u0eoEktxRqKhFnNRcSIAS9IyMFcDAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrGIsWRmVeSWpSXmKPExsVy+t/xu7qn/S7EGPyYKmuxccZ6VovrX56z Wsw/co7VYvXHx4wWk0/NZbI4051r0f/4NbPF+fMb2C3ONr1ht7jVIGNxedccNovPvUcYLWac 38dksfbIXXaL240r2CwOv2lntdh/xcvi9m8+i28nHjE6CHt8+zqJxWN2w0UWj52z7rJ7bFrV yebR2/yOzePguz1MHn1bVjF6bD5d7fF5k1wAZ5SeTVF+aUmqQkZ+cYmtUrShhZGeoaWFnpGJ pZ6hsXmslZGpkr6dTUpqTmZZapG+XYJexvr7O5gLHhpW/LixjrmBcYtWFyMnh4SAicSHvz+Z uhi5OIQEljJKLFw9iwkiISYxad92dghbWOLPtS42iKJPjBIrJ+0Fcjg42AT0JHasKgSpERGo l+h/cwmshlmggVlizfarrCAJYYFAiQVn25lB6lkEVCW+veUBMXkFvCTW/maEGC8ncfNcJzOI zSngLfG34xBYXAioZN/H3ywTGPkWMDKsYhRJLS3OTc8tNtQrTswtLs1L10vOz93ECIyjbcd+ bt7BeGlj8CFGAQ5GJR7eB7YXYoRYE8uKK3MPMUpwMCuJ8CY+OxcjxJuSWFmVWpQfX1Sak1p8 iNEU6KSJzFKiyfnAGM8riTc0NTS3sDQ0NzY3NrNQEuftEDgYIySQnliSmp2aWpBaBNPHxMEp 1cA44cS+HcbqDY/t/ARZVb4KHBO05ptmMnlX37H06N/tvvMXvfWb39unO8f4+a7p//YebQ0N q77htD3p4FMNMZflF2Mm8YrkKG3V3hnj4c8ZIS7PklkYKT/L62y/5PJ/q2yfVkzfWv6aqfL6 vZ9hRhwzi8XnLvJ+bC877/KTlNVfuA07pidEblyixFKckWioxVxUnAgAikYtI7kCAAA= X-CMS-MailID: 20190506151211eucas1p2d96d7eaa4cda8f8d1787d8f1f1461b9b X-Msg-Generator: CA X-RootMTR: 20190506151211eucas1p2d96d7eaa4cda8f8d1787d8f1f1461b9b X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20190506151211eucas1p2d96d7eaa4cda8f8d1787d8f1f1461b9b References: <1557155521-30949-1-git-send-email-l.luba@partner.samsung.com> Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch provides support for clocks needed for Dynamic Memory Controller in Exynos5422 SoC. It adds CDREX base register addresses, new DIV, MUX and GATE entries. Signed-off-by: Lukasz Luba Acked-by: Chanwoo Choi --- drivers/clk/samsung/clk-exynos5420.c | 58 +++++++++++++++++++++++++++++++++--- 1 file changed, 54 insertions(+), 4 deletions(-) diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c index 34cce3c..af62b6d 100644 --- a/drivers/clk/samsung/clk-exynos5420.c +++ b/drivers/clk/samsung/clk-exynos5420.c @@ -134,6 +134,8 @@ #define SRC_CDREX 0x20200 #define DIV_CDREX0 0x20500 #define DIV_CDREX1 0x20504 +#define GATE_BUS_CDREX0 0x20700 +#define GATE_BUS_CDREX1 0x20704 #define KPLL_LOCK 0x28000 #define KPLL_CON0 0x28100 #define SRC_KFC 0x28200 @@ -248,6 +250,8 @@ static const unsigned long exynos5x_clk_regs[] __initconst = { DIV_CDREX1, SRC_KFC, DIV_KFC0, + GATE_BUS_CDREX0, + GATE_BUS_CDREX1, }; static const unsigned long exynos5800_clk_regs[] __initconst = { @@ -425,6 +429,9 @@ PNAME(mout_group13_5800_p) = { "dout_osc_div", "mout_sw_aclkfl1_550_cam" }; PNAME(mout_group14_5800_p) = { "dout_aclk550_cam", "dout_sclk_sw" }; PNAME(mout_group15_5800_p) = { "dout_osc_div", "mout_sw_aclk550_cam" }; PNAME(mout_group16_5800_p) = { "dout_osc_div", "mout_mau_epll_clk" }; +PNAME(mout_mx_mspll_ccore_phy_p) = { "sclk_bpll", "mout_sclk_dpll", + "mout_sclk_mpll", "ff_dout_spll2", + "mout_sclk_spll", "mout_sclk_epll"}; /* fixed rate clocks generated outside the soc */ static struct samsung_fixed_rate_clock @@ -450,7 +457,7 @@ static const struct samsung_fixed_factor_clock static const struct samsung_fixed_factor_clock exynos5800_fixed_factor_clks[] __initconst = { FFACTOR(0, "ff_dout_epll2", "mout_sclk_epll", 1, 2, 0), - FFACTOR(0, "ff_dout_spll2", "mout_sclk_spll", 1, 2, 0), + FFACTOR(CLK_FF_DOUT_SPLL2, "ff_dout_spll2", "mout_sclk_spll", 1, 2, 0), }; static const struct samsung_mux_clock exynos5800_mux_clks[] __initconst = { @@ -472,11 +479,14 @@ static const struct samsung_mux_clock exynos5800_mux_clks[] __initconst = { MUX(0, "mout_aclk300_disp1", mout_group5_5800_p, SRC_TOP2, 24, 2), MUX(0, "mout_aclk300_gscl", mout_group5_5800_p, SRC_TOP2, 28, 2), + MUX(CLK_MOUT_MX_MSPLL_CCORE_PHY, "mout_mx_mspll_ccore_phy", + mout_mx_mspll_ccore_phy_p, SRC_TOP7, 0, 3), + MUX(CLK_MOUT_MX_MSPLL_CCORE, "mout_mx_mspll_ccore", - mout_mx_mspll_ccore_p, SRC_TOP7, 16, 2), + mout_mx_mspll_ccore_p, SRC_TOP7, 16, 3), MUX_F(CLK_MOUT_MAU_EPLL, "mout_mau_epll_clk", mout_mau_epll_clk_5800_p, SRC_TOP7, 20, 2, CLK_SET_RATE_PARENT, 0), - MUX(0, "sclk_bpll", mout_bpll_p, SRC_TOP7, 24, 1), + MUX(CLK_SCLK_BPLL, "sclk_bpll", mout_bpll_p, SRC_TOP7, 24, 1), MUX(0, "mout_epll2", mout_epll2_5800_p, SRC_TOP7, 28, 1), MUX(0, "mout_aclk550_cam", mout_group3_5800_p, SRC_TOP8, 16, 3), @@ -648,7 +658,7 @@ static const struct samsung_mux_clock exynos5x_mux_clks[] __initconst = { MUX(0, "mout_sclk_mpll", mout_mpll_p, SRC_TOP6, 0, 1), MUX(CLK_MOUT_VPLL, "mout_sclk_vpll", mout_vpll_p, SRC_TOP6, 4, 1), - MUX(0, "mout_sclk_spll", mout_spll_p, SRC_TOP6, 8, 1), + MUX(CLK_MOUT_SCLK_SPLL, "mout_sclk_spll", mout_spll_p, SRC_TOP6, 8, 1), MUX(0, "mout_sclk_ipll", mout_ipll_p, SRC_TOP6, 12, 1), MUX(0, "mout_sclk_rpll", mout_rpll_p, SRC_TOP6, 16, 1), MUX_F(CLK_MOUT_EPLL, "mout_sclk_epll", mout_epll_p, SRC_TOP6, 20, 1, @@ -806,8 +816,21 @@ static const struct samsung_div_clock exynos5x_div_clks[] __initconst = { "mout_aclk400_disp1", DIV_TOP2, 4, 3), /* CDREX Block */ + /* + * The three clocks below are controlled using the same register and + * bits. They are put into one because there is a need of + * synchronization between the BUS and DREXs (two external memory + * interfaces). + * They are put here to show this HW assumption and for clock + * information summary completeness. + */ DIV(CLK_DOUT_PCLK_CDREX, "dout_pclk_cdrex", "dout_aclk_cdrex1", DIV_CDREX0, 28, 3), + DIV(CLK_DOUT_PCLK_DREX0, "dout_pclk_drex0", "dout_cclk_drex0", + DIV_CDREX0, 28, 3), + DIV(CLK_DOUT_PCLK_DREX1, "dout_pclk_drex1", "dout_cclk_drex0", + DIV_CDREX0, 28, 3), + DIV_F(CLK_DOUT_SCLK_CDREX, "dout_sclk_cdrex", "mout_mclk_cdrex", DIV_CDREX0, 24, 3, CLK_SET_RATE_PARENT, 0), DIV(CLK_DOUT_ACLK_CDREX1, "dout_aclk_cdrex1", "dout_clk2x_phy0", @@ -817,6 +840,7 @@ static const struct samsung_div_clock exynos5x_div_clks[] __initconst = { DIV(CLK_DOUT_CLK2X_PHY0, "dout_clk2x_phy0", "dout_sclk_cdrex", DIV_CDREX0, 3, 5), + DIV(CLK_DOUT_PCLK_CORE_MEM, "dout_pclk_core_mem", "mout_mclk_cdrex", DIV_CDREX1, 8, 3), @@ -1170,6 +1194,32 @@ static const struct samsung_gate_clock exynos5x_gate_clks[] __initconst = { GATE_TOP_SCLK_ISP, 12, CLK_SET_RATE_PARENT, 0), GATE(CLK_G3D, "g3d", "mout_user_aclk_g3d", GATE_IP_G3D, 9, 0, 0), + + /* CDREX */ + GATE(CLK_CLKM_PHY0, "clkm_phy0", "dout_sclk_cdrex", + GATE_BUS_CDREX0, 0, 0, 0), + GATE(CLK_CLKM_PHY1, "clkm_phy1", "dout_sclk_cdrex", + GATE_BUS_CDREX0, 1, 0, 0), + GATE(0, "mx_mspll_ccore_phy", "mout_mx_mspll_ccore_phy", + SRC_MASK_TOP7, 0, CLK_IGNORE_UNUSED, 0), + + GATE(CLK_ACLK_PPMU_DREX1_1, "aclk_ppmu_drex1_1", "dout_aclk_cdrex1", + GATE_BUS_CDREX1, 12, CLK_IGNORE_UNUSED, 0), + GATE(CLK_ACLK_PPMU_DREX1_0, "aclk_ppmu_drex1_0", "dout_aclk_cdrex1", + GATE_BUS_CDREX1, 13, CLK_IGNORE_UNUSED, 0), + GATE(CLK_ACLK_PPMU_DREX0_1, "aclk_ppmu_drex0_1", "dout_aclk_cdrex1", + GATE_BUS_CDREX1, 14, CLK_IGNORE_UNUSED, 0), + GATE(CLK_ACLK_PPMU_DREX0_0, "aclk_ppmu_drex0_0", "dout_aclk_cdrex1", + GATE_BUS_CDREX1, 15, CLK_IGNORE_UNUSED, 0), + + GATE(CLK_PCLK_PPMU_DREX1_1, "pclk_ppmu_drex1_1", "dout_pclk_cdrex", + GATE_BUS_CDREX1, 26, CLK_IGNORE_UNUSED, 0), + GATE(CLK_PCLK_PPMU_DREX1_0, "pclk_ppmu_drex1_0", "dout_pclk_cdrex", + GATE_BUS_CDREX1, 27, CLK_IGNORE_UNUSED, 0), + GATE(CLK_PCLK_PPMU_DREX0_1, "pclk_ppmu_drex0_1", "dout_pclk_cdrex", + GATE_BUS_CDREX1, 28, CLK_IGNORE_UNUSED, 0), + GATE(CLK_PCLK_PPMU_DREX0_0, "pclk_ppmu_drex0_0", "dout_pclk_cdrex", + GATE_BUS_CDREX1, 29, CLK_IGNORE_UNUSED, 0), }; static const struct samsung_div_clock exynos5x_disp_div_clks[] __initconst = { From patchwork Mon May 6 15:11:51 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lukasz Luba X-Patchwork-Id: 10931307 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 646BA912 for ; Mon, 6 May 2019 15:13:31 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 53AAA205AD for ; Mon, 6 May 2019 15:13:31 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 481F8287D3; Mon, 6 May 2019 15:13:31 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id E19AA205AD for ; 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Mon, 6 May 2019 15:12:11 +0000 (GMT) From: Lukasz Luba To: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-samsung-soc@vger.kernel.org Cc: b.zolnierkie@samsung.com, krzk@kernel.org, kgene@kernel.org, cw00.choi@samsung.com, kyungmin.park@samsung.com, m.szyprowski@samsung.com, s.nawrocki@samsung.com, myungjoo.ham@samsung.com, keescook@chromium.org, tony@atomide.com, jroedel@suse.de, treding@nvidia.com, digetx@gmail.com, willy.mh.wolff.ml@gmail.com, Lukasz Luba Subject: [PATCH v7 03/13] clk: samsung: add BPLL rate table for Exynos 5422 SoC Date: Mon, 6 May 2019 17:11:51 +0200 Message-Id: <1557155521-30949-4-git-send-email-l.luba@partner.samsung.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1557155521-30949-1-git-send-email-l.luba@partner.samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA0WSe0hTURzHPbu72500OV1Df9gyHAQVNIsijvQgI+KmGWWPP0qoVTeV3Kxd LU2FqfgsU5ReavmI0pZRmY0smzRHWurcKlKzVWoYmEmhadnTeRf99znfx+93OByGYlvoACZW n8Ab9No4tcxban783b6kc4sjammdBcjt8zdp0j3+gSYVNjtNrn8ZRKTk6UUJ6TipI4WDHynS 1XVLTjozRuTklVFFnt8vl5GxAhsi57ssEnLD5pKTvvRaGWkZyaFJ84sw0vfDh0y0DaB1vtzE 12IpV2Z0SrnGUpecqzflybiCzFEZ92i0ScKdbjAh7k57CjdWH7hVsdt79UE+LvYYbwheu887 xuUyS49k4qThz3m0EfUq85GCAbwCCieGJPnIm2FxLQJzmVnuNlg8juBlR7jIYwiyXkf+K2Q0 ujyFGgRORzYlHqYLw/250w7DyLAG7pmOugtzcAq87m6eyVB4RAKdU9+kbsMXbwPn0MAMS/EC KK/+MLNZicMg50mlTNwWCL32PMrNChwOv3KtyD0I8Bs5VFubaTG0ASxTzyQi+8Jwa4NcZBX8 aazw6AIYC6qQyKkwWHjRk1kFLa1O2n1pCi+Cm/eDRTkUel7dnpEB+0DPp9lumZrGYvM5SpSV kJvNiumF0HDK4VnkBzV1Zz3DOXhguuZ5z0sIJopVRWh+6f9dlQiZkD+fKOiieWG5nj+uEbQ6 IVEfrTkQr6tH01+r/Xfr13vI8nO/FWEGqWcpi9Y7olhae0xI1lkRMJR6jlI7ZI9ilQe1ySd4 Q/xeQ2IcL1jRXEaq9lemeL3bw+JobQJ/mOeP8IZ/roRRBBjRekNNfJvP58a+0Guq7Y7lQbGD EZvrwlObmE1mTVa2PuHC2q21ubu9bLsC/Vj+fZDqbkRFyHhe5MY1e69c2amcl3xopLb1uzMt yD4525B2V4EzfmlKH/aWvmHPJOHy4LK3/mPpJcK+qv56fU6klyVmx6FvK0OqJ3uazsJVy+Vg OaeWCjHaZYspg6D9C0XnGjFWAwAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrGIsWRmVeSWpSXmKPExsVy+t/xu7pn/C7EGCyeJmyxccZ6VovrX56z Wsw/co7VYvXHx4wWk0/NZbI4051r0f/4NbPF+fMb2C3ONr1ht7jVIGNxedccNovPvUcYLWac 38dksfbIXXaL240r2CwOv2lntdh/xcvi9m8+i28nHjE6CHt8+zqJxWN2w0UWj52z7rJ7bFrV yebR2/yOzePguz1MHn1bVjF6bD5d7fF5k1wAZ5SeTVF+aUmqQkZ+cYmtUrShhZGeoaWFnpGJ pZ6hsXmslZGpkr6dTUpqTmZZapG+XYJext2721gKmgUqXn3oZG1gvMnbxcjJISFgItG08y4T iC0ksJRRYs4yEYi4mMSkfdvZIWxhiT/Xutggaj4xSiyabNHFyMHBJqAnsWNVIUhYRKBeov/N JaASLg5mgQZmiTXbr7KCJIQF/CW2vPkBZrMIqErMWfQcbCavgJdE+8kFbBDz5SRunutkBrE5 Bbwl/nYcYoTY5SWx7+NvlgmMfAsYGVYxiqSWFuem5xYb6hUn5haX5qXrJefnbmIExtG2Yz83 72C8tDH4EKMAB6MSD+8D2wsxQqyJZcWVuYcYJTiYlUR4E5+dixHiTUmsrEotyo8vKs1JLT7E aAp01ERmKdHkfGCM55XEG5oamltYGpobmxubWSiJ83YIHIwREkhPLEnNTk0tSC2C6WPi4JRq YCy3cD4dUXEvsnTqS9/nd0UPPj+87MfVxB8y5sesZ8tdZSjZVs7Nxvtyqhhv6UvmruU61uvb Z/693mJy7kZK9ETVN2c+HewOm8m7/fiDgzEfP25zmvrg5gp9j08XLU9f72wJ/XBxQZ7Vw/zu fRc2n2ATK9mk+CNiwRXmT4sTP+8XqvP+8eBotWSMEktxRqKhFnNRcSIAt2X4ibkCAAA= X-CMS-MailID: 20190506151212eucas1p24110f75fa6ed945f9ae7614fbb8aa13d X-Msg-Generator: CA X-RootMTR: 20190506151212eucas1p24110f75fa6ed945f9ae7614fbb8aa13d X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20190506151212eucas1p24110f75fa6ed945f9ae7614fbb8aa13d References: <1557155521-30949-1-git-send-email-l.luba@partner.samsung.com> Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add new table rate for BPLL for Exynos5422 SoC supporting Dynamic Memory Controller frequencies for driver's DRAM timings. Signed-off-by: Lukasz Luba Acked-by: Chanwoo Choi --- drivers/clk/samsung/clk-exynos5420.c | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-) diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c index af62b6d..23c60a5 100644 --- a/drivers/clk/samsung/clk-exynos5420.c +++ b/drivers/clk/samsung/clk-exynos5420.c @@ -1335,6 +1335,17 @@ static const struct samsung_pll_rate_table exynos5420_pll2550x_24mhz_tbl[] __ini PLL_35XX_RATE(24 * MHZ, 200000000, 200, 3, 3), }; +static const struct samsung_pll_rate_table exynos5422_bpll_rate_table[] = { + PLL_35XX_RATE(24 * MHZ, 825000000, 275, 4, 1), + PLL_35XX_RATE(24 * MHZ, 728000000, 182, 3, 1), + PLL_35XX_RATE(24 * MHZ, 633000000, 211, 4, 1), + PLL_35XX_RATE(24 * MHZ, 543000000, 181, 2, 2), + PLL_35XX_RATE(24 * MHZ, 413000000, 413, 6, 2), + PLL_35XX_RATE(24 * MHZ, 275000000, 275, 3, 3), + PLL_35XX_RATE(24 * MHZ, 206000000, 206, 3, 3), + PLL_35XX_RATE(24 * MHZ, 165000000, 110, 2, 3), +}; + static const struct samsung_pll_rate_table exynos5420_epll_24mhz_tbl[] = { PLL_36XX_RATE(24 * MHZ, 600000000U, 100, 2, 1, 0), PLL_36XX_RATE(24 * MHZ, 400000000U, 200, 3, 2, 0), @@ -1477,9 +1488,13 @@ static void __init exynos5x_clk_init(struct device_node *np, exynos5x_plls[apll].rate_table = exynos5420_pll2550x_24mhz_tbl; exynos5x_plls[epll].rate_table = exynos5420_epll_24mhz_tbl; exynos5x_plls[kpll].rate_table = exynos5420_pll2550x_24mhz_tbl; - exynos5x_plls[bpll].rate_table = exynos5420_pll2550x_24mhz_tbl; } + if (soc == EXYNOS5420) + exynos5x_plls[bpll].rate_table = exynos5420_pll2550x_24mhz_tbl; + else + exynos5x_plls[bpll].rate_table = exynos5422_bpll_rate_table; + samsung_clk_register_pll(ctx, exynos5x_plls, ARRAY_SIZE(exynos5x_plls), reg_base); samsung_clk_register_fixed_rate(ctx, exynos5x_fixed_rate_clks, From patchwork Mon May 6 15:11:52 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lukasz Luba X-Patchwork-Id: 10931301 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 486FA912 for ; Mon, 6 May 2019 15:13:29 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 380F126E69 for ; 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Mon, 6 May 2019 15:12:13 +0000 (GMT) Received: from eusmgms1.samsung.com (unknown [182.198.249.179]) by eusmtrp2.samsung.com (KnoxPortal) with ESMTP id 20190506151213eusmtrp2fb5f389df628cd86efafc58d47fadd46~cILUMVFYc0409004090eusmtrp2Q; Mon, 6 May 2019 15:12:13 +0000 (GMT) X-AuditID: cbfec7f4-12dff70000001119-7f-5cd04ecd207a Received: from eusmtip1.samsung.com ( [203.254.199.221]) by eusmgms1.samsung.com (EUCPMTA) with SMTP id 8B.5D.04146.DCE40DC5; Mon, 6 May 2019 16:12:13 +0100 (BST) Received: from AMDC3778.DIGITAL.local (unknown [106.120.51.20]) by eusmtip1.samsung.com (KnoxPortal) with ESMTPA id 20190506151212eusmtip150339d5024b91c7b0c514f035abe58a9~cILTb-3ow3248532485eusmtip1s; Mon, 6 May 2019 15:12:12 +0000 (GMT) From: Lukasz Luba To: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-samsung-soc@vger.kernel.org Cc: b.zolnierkie@samsung.com, krzk@kernel.org, kgene@kernel.org, cw00.choi@samsung.com, kyungmin.park@samsung.com, m.szyprowski@samsung.com, s.nawrocki@samsung.com, myungjoo.ham@samsung.com, keescook@chromium.org, tony@atomide.com, jroedel@suse.de, treding@nvidia.com, digetx@gmail.com, willy.mh.wolff.ml@gmail.com, Lukasz Luba Subject: [PATCH v7 04/13] dt-bindings: ddr: rename lpddr2 directory Date: Mon, 6 May 2019 17:11:52 +0200 Message-Id: <1557155521-30949-5-git-send-email-l.luba@partner.samsung.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1557155521-30949-1-git-send-email-l.luba@partner.samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrMKsWRmVeSWpSXmKPExsWy7djPc7pn/S7EGNzeq2uxccZ6VovrX56z Wsw/co7VYvXHx4wWk0/NZbI4051r0f/4NbPF+fMb2C3ONr1ht7jVIGNxedccNovPvUcYLWac 38dksfbIXXaL240r2CwOv2lntdh/xcvi9m8+i28nHjE6CHt8+zqJxWN2w0UWj52z7rJ7bFrV yebR2/yOzePguz1MHn1bVjF6bD5d7fF5k1wAZxSXTUpqTmZZapG+XQJXxs3pPAVn/CpW/9rP 2MC43b6LkZNDQsBE4s2Uq2wgtpDACkaJAzvKuxi5gOwvjBIPT01mhHA+M0p8vfibEaZj2e19 UInljBKv+j6zwrXs3dHE3sXIwcEmoCexY1UhSIOIQLXEnev7mUFqmAXeMEmc/fWDBSQhLOAs 8WzxPHYQm0VAVeLDun/MIDavgJfE7G27oLbJSdw81wkW5xTwlvjbcQhss4TALXaJFa8uM0EU uUhMfzuHDcIWlnh1fAs7hC0j8X/nfKiaYomG3oVQQ2skHvfPhaqxljh8/CIryNHMApoS63fp Q4QdJRYtvwf2i4QAn8SNt4IgYWYgc9K26cwQYV6JjjYhiGoNiS09F6AWiUksXzMNqtND4t1n DkjozGOUuHriG8sERvlZCLsWMDKuYhRPLS3OTU8tNspLLdcrTswtLs1L10vOz93ECExap/8d /7KDcdefpEOMAhyMSjy8E5wuxAixJpYVV+YeYpTgYFYS4U18di5GiDclsbIqtSg/vqg0J7X4 EKM0B4uSOG81w4NoIYH0xJLU7NTUgtQimCwTB6dUA6Osqtmid1t44qXkM0WKXcS82SexChel LniZ8WLSsZq+/ntti75VfNn+73l6U4Xj/4Z76/9Z2e39rx/+TuvF+s0dnC8bkxb980mWNGd2 n7m0q32K04IbTjuWnHowjfuRvXEZT7fW9qtLtoR7fo/qsS2cwqoarOKt1mOi3mZt/kU2Mlz3 bXhHjBJLcUaioRZzUXEiAHuG1J5WAwAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrOIsWRmVeSWpSXmKPExsVy+t/xu7pn/S7EGDy/wmqxccZ6VovrX56z Wsw/co7VYvXHx4wWk0/NZbI4051r0f/4NbPF+fMb2C3ONr1ht7jVIGNxedccNovPvUcYLWac 38dksfbIXXaL240r2CwOv2lntdh/xcvi9m8+i28nHjE6CHt8+zqJxWN2w0UWj52z7rJ7bFrV yebR2/yOzePguz1MHn1bVjF6bD5d7fF5k1wAZ5SeTVF+aUmqQkZ+cYmtUrShhZGeoaWFnpGJ pZ6hsXmslZGpkr6dTUpqTmZZapG+XYJexs3pPAVn/CpW/9rP2MC43b6LkZNDQsBEYtntfYxd jFwcQgJLGSW2L3vKCJEQk5i0bzs7hC0s8edaFxtE0SdGiQUPO4GKODjYBPQkdqwqBKkREaiX 6H9zCayGWaCBWWLN9qusIAlhAWeJZ4vngQ1iEVCV+LDuHzOIzSvgJTF72y6oZXISN891gsU5 Bbwl/nYcAosLAdXs+/ibZQIj3wJGhlWMIqmlxbnpucWGesWJucWleel6yfm5mxiBkbTt2M/N OxgvbQw+xCjAwajEw/vA9kKMEGtiWXFl7iFGCQ5mJRHexGfnYoR4UxIrq1KL8uOLSnNSiw8x mgIdNZFZSjQ5HxjleSXxhqaG5haWhubG5sZmFkrivB0CB2OEBNITS1KzU1MLUotg+pg4OKUa GGtrHk3O2aPGweTv+8HaRXp/19ENnXu2SVsJPmD6HDknN7Q6+VFD0K5bhyw2Fc1aq/lAQ+bp YrXyHH6hd/8XLOe0l57eXH9EYJPhDfsCnuIFKpolkp8U1u5dF6wyJ2tXFtPJyhUZcRl/K6UV 3wTfdqqyNdc68SPRcz1nuq7a1WPnf3PnvRBKUmIpzkg01GIuKk4EACndG7S6AgAA X-CMS-MailID: 20190506151213eucas1p2ca40029d09ddbbcd11e4a1dd60ae9654 X-Msg-Generator: CA X-RootMTR: 20190506151213eucas1p2ca40029d09ddbbcd11e4a1dd60ae9654 X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20190506151213eucas1p2ca40029d09ddbbcd11e4a1dd60ae9654 References: <1557155521-30949-1-git-send-email-l.luba@partner.samsung.com> Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Change directory name to be ready for new types of memories. Signed-off-by: Lukasz Luba Reviewed-by: Rob Herring --- .../devicetree/bindings/ddr/lpddr2-timings.txt | 52 +++++++++++ Documentation/devicetree/bindings/ddr/lpddr2.txt | 102 +++++++++++++++++++++ .../devicetree/bindings/lpddr2/lpddr2-timings.txt | 52 ----------- .../devicetree/bindings/lpddr2/lpddr2.txt | 102 --------------------- 4 files changed, 154 insertions(+), 154 deletions(-) create mode 100644 Documentation/devicetree/bindings/ddr/lpddr2-timings.txt create mode 100644 Documentation/devicetree/bindings/ddr/lpddr2.txt delete mode 100644 Documentation/devicetree/bindings/lpddr2/lpddr2-timings.txt delete mode 100644 Documentation/devicetree/bindings/lpddr2/lpddr2.txt diff --git a/Documentation/devicetree/bindings/ddr/lpddr2-timings.txt b/Documentation/devicetree/bindings/ddr/lpddr2-timings.txt new file mode 100644 index 0000000..9ceb19e --- /dev/null +++ b/Documentation/devicetree/bindings/ddr/lpddr2-timings.txt @@ -0,0 +1,52 @@ +* AC timing parameters of LPDDR2(JESD209-2) memories for a given speed-bin + +Required properties: +- compatible : Should be "jedec,lpddr2-timings" +- min-freq : minimum DDR clock frequency for the speed-bin. Type is +- max-freq : maximum DDR clock frequency for the speed-bin. Type is + +Optional properties: + +The following properties represent AC timing parameters from the memory +data-sheet of the device for a given speed-bin. All these properties are +of type and the default unit is ps (pico seconds). Parameters with +a different unit have a suffix indicating the unit such as 'tRAS-max-ns' +- tRCD +- tWR +- tRAS-min +- tRRD +- tWTR +- tXP +- tRTP +- tDQSCK-max +- tFAW +- tZQCS +- tZQinit +- tRPab +- tZQCL +- tCKESR +- tRAS-max-ns +- tDQSCK-max-derated + +Example: + +timings_elpida_ECB240ABACN_400mhz: lpddr2-timings@0 { + compatible = "jedec,lpddr2-timings"; + min-freq = <10000000>; + max-freq = <400000000>; + tRPab = <21000>; + tRCD = <18000>; + tWR = <15000>; + tRAS-min = <42000>; + tRRD = <10000>; + tWTR = <7500>; + tXP = <7500>; + tRTP = <7500>; + tCKESR = <15000>; + tDQSCK-max = <5500>; + tFAW = <50000>; + tZQCS = <90000>; + tZQCL = <360000>; + tZQinit = <1000000>; + tRAS-max-ns = <70000>; +}; diff --git a/Documentation/devicetree/bindings/ddr/lpddr2.txt b/Documentation/devicetree/bindings/ddr/lpddr2.txt new file mode 100644 index 0000000..ddd4012 --- /dev/null +++ b/Documentation/devicetree/bindings/ddr/lpddr2.txt @@ -0,0 +1,102 @@ +* LPDDR2 SDRAM memories compliant to JEDEC JESD209-2 + +Required properties: +- compatible : Should be one of - "jedec,lpddr2-nvm", "jedec,lpddr2-s2", + "jedec,lpddr2-s4" + + "ti,jedec-lpddr2-s2" should be listed if the memory part is LPDDR2-S2 type + + "ti,jedec-lpddr2-s4" should be listed if the memory part is LPDDR2-S4 type + + "ti,jedec-lpddr2-nvm" should be listed if the memory part is LPDDR2-NVM type + +- density : representing density in Mb (Mega bits) + +- io-width : representing bus width. Possible values are 8, 16, and 32 + +Optional properties: + +The following optional properties represent the minimum value of some AC +timing parameters of the DDR device in terms of number of clock cycles. +These values shall be obtained from the device data-sheet. +- tRRD-min-tck +- tWTR-min-tck +- tXP-min-tck +- tRTP-min-tck +- tCKE-min-tck +- tRPab-min-tck +- tRCD-min-tck +- tWR-min-tck +- tRASmin-min-tck +- tCKESR-min-tck +- tFAW-min-tck + +Child nodes: +- The lpddr2 node may have one or more child nodes of type "lpddr2-timings". + "lpddr2-timings" provides AC timing parameters of the device for + a given speed-bin. The user may provide the timings for as many + speed-bins as is required. Please see Documentation/devicetree/ + bindings/ddr/lpddr2-timings.txt for more information on "lpddr2-timings" + +Example: + +elpida_ECB240ABACN : lpddr2 { + compatible = "Elpida,ECB240ABACN","jedec,lpddr2-s4"; + density = <2048>; + io-width = <32>; + + tRPab-min-tck = <3>; + tRCD-min-tck = <3>; + tWR-min-tck = <3>; + tRASmin-min-tck = <3>; + tRRD-min-tck = <2>; + tWTR-min-tck = <2>; + tXP-min-tck = <2>; + tRTP-min-tck = <2>; + tCKE-min-tck = <3>; + tCKESR-min-tck = <3>; + tFAW-min-tck = <8>; + + timings_elpida_ECB240ABACN_400mhz: lpddr2-timings@0 { + compatible = "jedec,lpddr2-timings"; + min-freq = <10000000>; + max-freq = <400000000>; + tRPab = <21000>; + tRCD = <18000>; + tWR = <15000>; + tRAS-min = <42000>; + tRRD = <10000>; + tWTR = <7500>; + tXP = <7500>; + tRTP = <7500>; + tCKESR = <15000>; + tDQSCK-max = <5500>; + tFAW = <50000>; + tZQCS = <90000>; + tZQCL = <360000>; + tZQinit = <1000000>; + tRAS-max-ns = <70000>; + }; + + timings_elpida_ECB240ABACN_200mhz: lpddr2-timings@1 { + compatible = "jedec,lpddr2-timings"; + min-freq = <10000000>; + max-freq = <200000000>; + tRPab = <21000>; + tRCD = <18000>; + tWR = <15000>; + tRAS-min = <42000>; + tRRD = <10000>; + tWTR = <10000>; + tXP = <7500>; + tRTP = <7500>; + tCKESR = <15000>; + tDQSCK-max = <5500>; + tFAW = <50000>; + tZQCS = <90000>; + tZQCL = <360000>; + tZQinit = <1000000>; + tRAS-max-ns = <70000>; + }; + +} diff --git a/Documentation/devicetree/bindings/lpddr2/lpddr2-timings.txt b/Documentation/devicetree/bindings/lpddr2/lpddr2-timings.txt deleted file mode 100644 index 9ceb19e..0000000 --- a/Documentation/devicetree/bindings/lpddr2/lpddr2-timings.txt +++ /dev/null @@ -1,52 +0,0 @@ -* AC timing parameters of LPDDR2(JESD209-2) memories for a given speed-bin - -Required properties: -- compatible : Should be "jedec,lpddr2-timings" -- min-freq : minimum DDR clock frequency for the speed-bin. Type is -- max-freq : maximum DDR clock frequency for the speed-bin. Type is - -Optional properties: - -The following properties represent AC timing parameters from the memory -data-sheet of the device for a given speed-bin. All these properties are -of type and the default unit is ps (pico seconds). Parameters with -a different unit have a suffix indicating the unit such as 'tRAS-max-ns' -- tRCD -- tWR -- tRAS-min -- tRRD -- tWTR -- tXP -- tRTP -- tDQSCK-max -- tFAW -- tZQCS -- tZQinit -- tRPab -- tZQCL -- tCKESR -- tRAS-max-ns -- tDQSCK-max-derated - -Example: - -timings_elpida_ECB240ABACN_400mhz: lpddr2-timings@0 { - compatible = "jedec,lpddr2-timings"; - min-freq = <10000000>; - max-freq = <400000000>; - tRPab = <21000>; - tRCD = <18000>; - tWR = <15000>; - tRAS-min = <42000>; - tRRD = <10000>; - tWTR = <7500>; - tXP = <7500>; - tRTP = <7500>; - tCKESR = <15000>; - tDQSCK-max = <5500>; - tFAW = <50000>; - tZQCS = <90000>; - tZQCL = <360000>; - tZQinit = <1000000>; - tRAS-max-ns = <70000>; -}; diff --git a/Documentation/devicetree/bindings/lpddr2/lpddr2.txt b/Documentation/devicetree/bindings/lpddr2/lpddr2.txt deleted file mode 100644 index 58354a0..0000000 --- a/Documentation/devicetree/bindings/lpddr2/lpddr2.txt +++ /dev/null @@ -1,102 +0,0 @@ -* LPDDR2 SDRAM memories compliant to JEDEC JESD209-2 - -Required properties: -- compatible : Should be one of - "jedec,lpddr2-nvm", "jedec,lpddr2-s2", - "jedec,lpddr2-s4" - - "ti,jedec-lpddr2-s2" should be listed if the memory part is LPDDR2-S2 type - - "ti,jedec-lpddr2-s4" should be listed if the memory part is LPDDR2-S4 type - - "ti,jedec-lpddr2-nvm" should be listed if the memory part is LPDDR2-NVM type - -- density : representing density in Mb (Mega bits) - -- io-width : representing bus width. Possible values are 8, 16, and 32 - -Optional properties: - -The following optional properties represent the minimum value of some AC -timing parameters of the DDR device in terms of number of clock cycles. -These values shall be obtained from the device data-sheet. -- tRRD-min-tck -- tWTR-min-tck -- tXP-min-tck -- tRTP-min-tck -- tCKE-min-tck -- tRPab-min-tck -- tRCD-min-tck -- tWR-min-tck -- tRASmin-min-tck -- tCKESR-min-tck -- tFAW-min-tck - -Child nodes: -- The lpddr2 node may have one or more child nodes of type "lpddr2-timings". - "lpddr2-timings" provides AC timing parameters of the device for - a given speed-bin. The user may provide the timings for as many - speed-bins as is required. Please see Documentation/devicetree/ - bindings/lpddr2/lpddr2-timings.txt for more information on "lpddr2-timings" - -Example: - -elpida_ECB240ABACN : lpddr2 { - compatible = "Elpida,ECB240ABACN","jedec,lpddr2-s4"; - density = <2048>; - io-width = <32>; - - tRPab-min-tck = <3>; - tRCD-min-tck = <3>; - tWR-min-tck = <3>; - tRASmin-min-tck = <3>; - tRRD-min-tck = <2>; - tWTR-min-tck = <2>; - tXP-min-tck = <2>; - tRTP-min-tck = <2>; - tCKE-min-tck = <3>; - tCKESR-min-tck = <3>; - tFAW-min-tck = <8>; - - timings_elpida_ECB240ABACN_400mhz: lpddr2-timings@0 { - compatible = "jedec,lpddr2-timings"; - min-freq = <10000000>; - max-freq = <400000000>; - tRPab = <21000>; - tRCD = <18000>; - tWR = <15000>; - tRAS-min = <42000>; - tRRD = <10000>; - tWTR = <7500>; - tXP = <7500>; - tRTP = <7500>; - tCKESR = <15000>; - tDQSCK-max = <5500>; - tFAW = <50000>; - tZQCS = <90000>; - tZQCL = <360000>; - tZQinit = <1000000>; - tRAS-max-ns = <70000>; - }; - - timings_elpida_ECB240ABACN_200mhz: lpddr2-timings@1 { - compatible = "jedec,lpddr2-timings"; - min-freq = <10000000>; - max-freq = <200000000>; - tRPab = <21000>; - tRCD = <18000>; - tWR = <15000>; - tRAS-min = <42000>; - tRRD = <10000>; - tWTR = <10000>; - tXP = <7500>; - tRTP = <7500>; - tCKESR = <15000>; - tDQSCK-max = <5500>; - tFAW = <50000>; - tZQCS = <90000>; - tZQCL = <360000>; - tZQinit = <1000000>; - tRAS-max-ns = <70000>; - }; - -} From patchwork Mon May 6 15:11:53 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lukasz Luba X-Patchwork-Id: 10931269 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 9778D912 for ; Mon, 6 May 2019 15:12:19 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 84D4A205AD for ; Mon, 6 May 2019 15:12:19 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 7901C287CF; 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Mon, 6 May 2019 15:12:14 +0000 (GMT) Received: from eusmgms1.samsung.com (unknown [182.198.249.179]) by eusmtrp2.samsung.com (KnoxPortal) with ESMTP id 20190506151213eusmtrp2fb10c26316455ab506cb8fba8c3a76b3~cILU8EWUD0409004090eusmtrp2U; Mon, 6 May 2019 15:12:13 +0000 (GMT) X-AuditID: cbfec7f4-113ff70000001119-80-5cd04eced59e Received: from eusmtip1.samsung.com ( [203.254.199.221]) by eusmgms1.samsung.com (EUCPMTA) with SMTP id EC.5D.04146.DCE40DC5; Mon, 6 May 2019 16:12:13 +0100 (BST) Received: from AMDC3778.DIGITAL.local (unknown [106.120.51.20]) by eusmtip1.samsung.com (KnoxPortal) with ESMTPA id 20190506151213eusmtip171ab8c5ad539595e8c9882e10a422c2b~cILUMQvI30071300713eusmtip1P; Mon, 6 May 2019 15:12:13 +0000 (GMT) From: Lukasz Luba To: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-samsung-soc@vger.kernel.org Cc: b.zolnierkie@samsung.com, krzk@kernel.org, kgene@kernel.org, cw00.choi@samsung.com, kyungmin.park@samsung.com, m.szyprowski@samsung.com, s.nawrocki@samsung.com, myungjoo.ham@samsung.com, keescook@chromium.org, tony@atomide.com, jroedel@suse.de, treding@nvidia.com, digetx@gmail.com, willy.mh.wolff.ml@gmail.com, Lukasz Luba Subject: [PATCH v7 05/13] dt-bindings: ddr: add LPDDR3 memories Date: Mon, 6 May 2019 17:11:53 +0200 Message-Id: <1557155521-30949-6-git-send-email-l.luba@partner.samsung.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1557155521-30949-1-git-send-email-l.luba@partner.samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA0VSaUwTURj07Xa3S7XNUoy8CGJSYzwSQQ0mz2rwjhtUYvSPQRItsgGVcnSp iHhUtByVKmqCcqloolgxyCFiY2osBTyQFoUARYWIiHITijco6xb9NzPfzDdfXh6Fy2uI2dT+ mARWE6OKVpASUWXtd/uShhBH2NLzRQiVXi4hUIurh0BXbQ0EujPSBdDF5wUYqj+jRue6+nBk t98To5cp/WLk1Pmi1+Z8Eo0abQBdtlswdNf2VozaTxaRqLo/jUCPm4JR+08Z+vL0PVjrxXwZ uyBi8nSNIuZh7lsxU2bKIBnjqUGSeTL4CGPOVpgAU/4imRkt89vuESpZHcFG7z/EagKC9kqi 2nQOIm5o/uHbz8pIHbjrZwAeFKQDYcmNFNwAJJScLgIw87qZFIgLwLTuDpFARgEc+tRDTEX0 rbliYXALwMHG+9i/yLfP9klCUSTtD6tM8XxgJp0M37Q8/tuB0/0YfPnjm4j3eNFrYG/eCd4j oudDU5NTzGMpHQzLm8dJocwPtjVk4Dz2oLfA8XQr4PdA+p0Y9gxbcMG0Edr6eoCAvWBvXYVY wL7w98OrmIA5qDMWuj1HYde5ArdnFayuayT4e3B6ESwxBwjyOug8PQh4GdIy2Drgycv4JLxQ eQkXZClMT5UL7oWwItPhLpoFbxVnu5czMMNmA8LrXAHQmN5JZIG5uf/LrgFgAt6sllNHstzy GDbRn1OpOW1MpP++WHUZmPxcLybqXFXA/CvcCmgKKGZIs9Y7wuSE6hCXpLYCSOGKmVLVx4Yw uTRClXSE1cTu0WijWc4KfCiRwluaPK1zt5yOVCWwB1k2jtVMTTHKY7YOrHQEla7/wIYo68dv WpdOSxxINGdXPzAW7JrjLM5pPv5mg/eCHdh0V07UtcJis6ch88dA7+2a6Bas+4BsZWh9/LOA n/k7thqPjflY51m3yPR6y6tgRdSmJKDf2TYh8VzUF68PNHQ4lLX6bGVO6gpl1vC2zZb0kfNt gVpXuNOi/KoQcVGqZYtxDaf6A9vhVpNYAwAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrOIsWRmVeSWpSXmKPExsVy+t/xu7pn/S7EGLxsMbfYOGM9q8X1L89Z LeYfOcdqsfrjY0aLyafmMlmc6c616H/8mtni/PkN7BZnm96wW9xqkLG4vGsOm8Xn3iOMFjPO 72OyWHvkLrvF7cYVbBaH37SzWuy/4mVx+zefxbcTjxgdhD2+fZ3E4jG74SKLx85Zd9k9Nq3q ZPPobX7H5nHw3R4mj74tqxg9Np+u9vi8SS6AM0rPpii/tCRVISO/uMRWKdrQwkjP0NJCz8jE Us/Q2DzWyshUSd/OJiU1J7MstUjfLkEv42bDBdaC96oVK09uYmtgXCvXxcjJISFgItF6YxZ7 FyMXh5DAUkaJu2uXs0EkxCQm7dvODmELS/y51sUGUfSJUeLixLusXYwcHGwCehI7VhWC1IgI 1Ev0v7kEVsMs0MAssWb7VbAaYQF7iVez60FqWARUJVZduQU2k1fAS2Lz1b9Qu+Qkbp7rZAax OQW8Jf52HGIEsYWAavZ9/M0ygZFvASPDKkaR1NLi3PTcYkO94sTc4tK8dL3k/NxNjMBI2nbs 5+YdjJc2Bh9iFOBgVOLhfWB7IUaINbGsuDL3EKMEB7OSCG/is3MxQrwpiZVVqUX58UWlOanF hxhNgY6ayCwlmpwPjPK8knhDU0NzC0tDc2NzYzMLJXHeDoGDMUIC6YklqdmpqQWpRTB9TByc Ug2MZldfph+w2jV33vaUOT9WPpgjOEd6gV2tVmv7fsfiac63E/QaV/nr+hRI/9u5McH0dluK /7MVWw+/e8sbLvJ4/51F2fsvvjh1YLqyxaNP2/cur+A99+vX55U7lT67ZB+2abtx1OaQkVbq jPhSicK7izZLdZuWlG3/ZyGbJHjprktN6k8z2WeMNUosxRmJhlrMRcWJAMP+RKy6AgAA X-CMS-MailID: 20190506151214eucas1p17114a7dce506c77ae0bb96b93fd2d838 X-Msg-Generator: CA X-RootMTR: 20190506151214eucas1p17114a7dce506c77ae0bb96b93fd2d838 X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20190506151214eucas1p17114a7dce506c77ae0bb96b93fd2d838 References: <1557155521-30949-1-git-send-email-l.luba@partner.samsung.com> Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Specifies the AC timing parameters of the LPDDR3 memory device. Signed-off-by: Lukasz Luba Reviewed-by: Rob Herring --- .../devicetree/bindings/ddr/lpddr3-timings.txt | 58 +++++++++++++ Documentation/devicetree/bindings/ddr/lpddr3.txt | 97 ++++++++++++++++++++++ 2 files changed, 155 insertions(+) create mode 100644 Documentation/devicetree/bindings/ddr/lpddr3-timings.txt create mode 100644 Documentation/devicetree/bindings/ddr/lpddr3.txt diff --git a/Documentation/devicetree/bindings/ddr/lpddr3-timings.txt b/Documentation/devicetree/bindings/ddr/lpddr3-timings.txt new file mode 100644 index 0000000..3a2ef3a --- /dev/null +++ b/Documentation/devicetree/bindings/ddr/lpddr3-timings.txt @@ -0,0 +1,58 @@ +* AC timing parameters of LPDDR3 memories for a given speed-bin. + +The structures are based on LPDDR2 and extended where needed. + +Required properties: +- compatible : Should be "jedec,lpddr3-timings" +- min-freq : minimum DDR clock frequency for the speed-bin. Type is +- reg : maximum DDR clock frequency for the speed-bin. Type is + +Optional properties: + +The following properties represent AC timing parameters from the memory +data-sheet of the device for a given speed-bin. All these properties are +of type and the default unit is ps (pico seconds). +- tRFC +- tRRD +- tRPab +- tRPpb +- tRCD +- tRC +- tRAS +- tWTR +- tWR +- tRTP +- tW2W-C2C +- tR2R-C2C +- tFAW +- tXSR +- tXP +- tCKE +- tCKESR +- tMRD + +Example: + +timings_samsung_K3QF2F20DB_800mhz: lpddr3-timings@0 { + compatible = "jedec,lpddr3-timings"; + reg = <800000000>; /* workaround: it shows max-freq */ + min-freq = <100000000>; + tRFC = <65000>; + tRRD = <6000>; + tRPab = <12000>; + tRPpb = <12000>; + tRCD = <10000>; + tRC = <33750>; + tRAS = <23000>; + tWTR = <3750>; + tWR = <7500>; + tRTP = <3750>; + tW2W-C2C = <0>; + tR2R-C2C = <0>; + tFAW = <25000>; + tXSR = <70000>; + tXP = <3750>; + tCKE = <3750>; + tCKESR = <3750>; + tMRD = <7000>; +}; diff --git a/Documentation/devicetree/bindings/ddr/lpddr3.txt b/Documentation/devicetree/bindings/ddr/lpddr3.txt new file mode 100644 index 0000000..0dc86a3 --- /dev/null +++ b/Documentation/devicetree/bindings/ddr/lpddr3.txt @@ -0,0 +1,97 @@ +* LPDDR3 SDRAM memories compliant to JEDEC JESD209-3C + +Required properties: +- compatible : Should be - "jedec,lpddr3" +- density : representing density in Mb (Mega bits) +- io-width : representing bus width. Possible values are 8, 16, 32, 64 +- #address-cells: Must be set to 1 +- #size-cells: Must be set to 0 + +Optional properties: + +The following optional properties represent the minimum value of some AC +timing parameters of the DDR device in terms of number of clock cycles. +These values shall be obtained from the device data-sheet. +- tRFC-min-tck +- tRRD-min-tck +- tRPab-min-tck +- tRPpb-min-tck +- tRCD-min-tck +- tRC-min-tck +- tRAS-min-tck +- tWTR-min-tck +- tWR-min-tck +- tRTP-min-tck +- tW2W-C2C-min-tck +- tR2R-C2C-min-tck +- tWL-min-tck +- tDQSCK-min-tck +- tRL-min-tck +- tFAW-min-tck +- tXSR-min-tck +- tXP-min-tck +- tCKE-min-tck +- tCKESR-min-tck +- tMRD-min-tck + +Child nodes: +- The lpddr3 node may have one or more child nodes of type "lpddr3-timings". + "lpddr3-timings" provides AC timing parameters of the device for + a given speed-bin. Please see Documentation/devicetree/ + bindings/ddr/lpddr3-timings.txt for more information on "lpddr3-timings" + +Example: + +samsung_K3QF2F20DB: lpddr3 { + compatible = "Samsung,K3QF2F20DB", "jedec,lpddr3"; + density = <16384>; + io-width = <32>; + #address-cells = <1>; + #size-cells = <0>; + + tRFC-min-tck = <17>; + tRRD-min-tck = <2>; + tRPab-min-tck = <2>; + tRPpb-min-tck = <2>; + tRCD-min-tck = <3>; + tRC-min-tck = <6>; + tRAS-min-tck = <5>; + tWTR-min-tck = <2>; + tWR-min-tck = <7>; + tRTP-min-tck = <2>; + tW2W-C2C-min-tck = <0>; + tR2R-C2C-min-tck = <0>; + tWL-min-tck = <8>; + tDQSCK-min-tck = <5>; + tRL-min-tck = <14>; + tFAW-min-tck = <5>; + tXSR-min-tck = <12>; + tXP-min-tck = <2>; + tCKE-min-tck = <2>; + tCKESR-min-tck = <2>; + tMRD-min-tck = <5>; + + timings_samsung_K3QF2F20DB_800mhz: lpddr3-timings@0 { + compatible = "jedec,lpddr3-timings"; + reg = <800000000>; /* workaround: it shows max-freq */ + min-freq = <100000000>; + tRFC = <65000>; + tRRD = <6000>; + tRPab = <12000>; + tRPpb = <12000>; + tRCD = <10000>; + tRC = <33750>; + tRAS = <23000>; + tWTR = <3750>; + tWR = <7500>; + tRTP = <3750>; + tW2W-C2C = <0>; + tR2R-C2C = <0>; + tFAW = <25000>; + tXSR = <70000>; + tXP = <3750>; + tCKE = <3750>; + tCKESR = <3750>; + tMRD = <7000>; + }; +} From patchwork Mon May 6 15:11:54 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lukasz Luba X-Patchwork-Id: 10931309 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 786A81575 for ; Mon, 6 May 2019 15:13:31 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 66CFA205AD for ; Mon, 6 May 2019 15:13:31 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 5AE98287E0; Mon, 6 May 2019 15:13:31 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 9971A26E69 for ; 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Mon, 6 May 2019 15:12:13 +0000 (GMT) From: Lukasz Luba To: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-samsung-soc@vger.kernel.org Cc: b.zolnierkie@samsung.com, krzk@kernel.org, kgene@kernel.org, cw00.choi@samsung.com, kyungmin.park@samsung.com, m.szyprowski@samsung.com, s.nawrocki@samsung.com, myungjoo.ham@samsung.com, keescook@chromium.org, tony@atomide.com, jroedel@suse.de, treding@nvidia.com, digetx@gmail.com, willy.mh.wolff.ml@gmail.com, Lukasz Luba Subject: [PATCH v7 06/13] drivers: memory: extend of_memory by LPDDR3 support Date: Mon, 6 May 2019 17:11:54 +0200 Message-Id: <1557155521-30949-7-git-send-email-l.luba@partner.samsung.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1557155521-30949-1-git-send-email-l.luba@partner.samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA0WSe0hTURzHPbu723U0uW6SJwurQVhRmjLiQCGGEZeJJhQEKdjM2xTdtF1n mREr05ylCwsTzSzD11ZZc/kiFac403Lay172sjRyWfkYtjJz3kX/fX7fx+8Hh0Ngok7cj0hS pdNqlTxFwhNwG3t+2jbbogZjt9S+XYvulNTjaHhmHEcV3QM4Mv4YBehCXzkHPTirRPrRCQzZ bLf56OEpOx+91K5Cj1sv89B0QTdAJbZ2DrrZPcJHr07W8lCX/QyOOp7I0KtfXsjR+wGEiSnH bBGXKtMOcamW0hE+ZTLoeFRB9iSP6py8x6EKzQZANfRnUdMm/2jP/YLtCXRKUgatDgo9IEgc K23gpQ3Ljjb9ngJacDI0H3gSkJTCT1YHyAcCQkTWAnir7jnODjMA5kx0u4dpAF98z8H/VZy6 Xj5r1ABo7JnHXMZSpapelA8IgkcGwmbDYZfsQ2bB18MdmCuPkXYOfOic47oMMbkbTuofLDGX XAfvOz9irq6QlEH7/Ar2lj98MaBbWu9JRsD5PAtg9Td8WNq1j+WdME/fxGFZDL9YzXyWV8GF lgq3zkBtwTV39zgc1Ze7M9tgl3UId53FyA2wvjXIhZDcAcuMMha94POv3q4wtohFjZcwVhbC vFwRu2M9NJ8bdN9ZDmtuFPPZCAUNlkj2ma4A+DM7m3cerC79f+oqAAbgS2sYpYJmglX0kUBG rmQ0KkXgwVSlCSx+rP4/1qlmMPso3gJIAkiWCT/vHIwV4fIMJlNpAZDAJD5C+dhArEiYIM88 RqtT49SaFJqxgJUEV+IrzPJ4FyMiFfJ0Opmm02j1P5dDePppgWrcWyoICw2vDIkrLj4Ukzue G7EJ2/W+Tbq12XvCmuEQYw6pYmY6YC9HE/7mbvncN9/oDudIctQcskV35RSeDlwgh7Hr+rpw U9WaEyFtjX3Pcp2qkADF76cCc2p1e+bLxPgK8UXKuWtPS+svGzBWm0oiE7/r1soq+6Y8zP0e Ei6TKA/eiKkZ+V/sPm8jVAMAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrOIsWRmVeSWpSXmKPExsVy+t/xu7rn/C7EGDydo22xccZ6VovrX56z Wsw/co7VYvXHx4wWk0/NZbI4051r0f/4NbPF+fMb2C3ONr1ht7jVIGNxedccNovPvUcYLWac 38dksfbIXXaL240r2CwOv2lntdh/xcvi9m8+i28nHjE6CHt8+zqJxWN2w0UWj52z7rJ7bFrV yebR2/yOzePguz1MHn1bVjF6bD5d7fF5k1wAZ5SeTVF+aUmqQkZ+cYmtUrShhZGeoaWFnpGJ pZ6hsXmslZGpkr6dTUpqTmZZapG+XYJexrNZm9kKrntVbP/zibGBsdGui5GTQ0LAROJX5wn2 LkYuDiGBpYwSl5/8YIVIiElM2redHcIWlvhzrYsNougTo8TO58eBijg42AT0JHasKgSpERGo l+h/cwmshlmggVlizfarYIOEBXwl+pa3sYHYLAKqEid/PWEG6eUV8JJ481cSYr6cxM1zncwg NqeAt8TfjkOMILYQUMm+j79ZJjDyLWBkWMUoklpanJueW2yoV5yYW1yal66XnJ+7iREYSduO /dy8g/HSxuBDjAIcjEo8vA9sL8QIsSaWFVfmHmKU4GBWEuFNfHYuRog3JbGyKrUoP76oNCe1 +BCjKdBNE5mlRJPzgVGeVxJvaGpobmFpaG5sbmxmoSTO2yFwMEZIID2xJDU7NbUgtQimj4mD U6qB0UejLeJDcebz3DCH7CNV03b8mJJZ2DV7/bzubRvrjh/yz1oVG/0g/nfXqtsBB2x/xztz aS1sm2OYKLrzSqiU9bb7tu4PxNbPfrb3ToxVzOKczyG7Jx2ZxKPKPl1Qdbv9w9Mqzy3O77d3 K/Xs4eQ3s2Vdwse43/ulMXNCjfbObPX1KreKF+y7o8RSnJFoqMVcVJwIAG+8QNm6AgAA X-CMS-MailID: 20190506151214eucas1p2e87194b1ce66f7184d6770818d02814d X-Msg-Generator: CA X-RootMTR: 20190506151214eucas1p2e87194b1ce66f7184d6770818d02814d X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20190506151214eucas1p2e87194b1ce66f7184d6770818d02814d References: <1557155521-30949-1-git-send-email-l.luba@partner.samsung.com> Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The patch adds AC timings information needed to support LPDDR3 and memory controllers. The structure is used in of_memory and currently in Exynos 5422 DMC. Add parsing data needed for LPDDR3 support. It is currently used in Exynos5422 Dynamic Memory Controller. Signed-off-by: Lukasz Luba --- drivers/memory/of_memory.c | 148 +++++++++++++++++++++++++++++++++++++++++++++ drivers/memory/of_memory.h | 20 +++++- include/memory/jedec_ddr.h | 62 +++++++++++++++++++ 3 files changed, 229 insertions(+), 1 deletion(-) diff --git a/drivers/memory/of_memory.c b/drivers/memory/of_memory.c index 2f5ed73..19fbbcd 100644 --- a/drivers/memory/of_memory.c +++ b/drivers/memory/of_memory.c @@ -2,6 +2,7 @@ * OpenFirmware helpers for memory drivers * * Copyright (C) 2012 Texas Instruments, Inc. + * Copyright (C) 2019 Samsung Electronics Co., Ltd. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -152,3 +153,150 @@ const struct lpddr2_timings *of_get_ddr_timings(struct device_node *np_ddr, return lpddr2_jedec_timings; } EXPORT_SYMBOL(of_get_ddr_timings); + +/** + * of_lpddr3_get_min_tck() - extract min timing values for lpddr3 + * @np: pointer to ddr device tree node + * @device: device requesting for min timing values + * + * Populates the lpddr3_min_tck structure by extracting data + * from device tree node. Returns a pointer to the populated + * structure. If any error in populating the structure, returns NULL. + */ +const struct lpddr3_min_tck *of_lpddr3_get_min_tck(struct device_node *np, + struct device *dev) +{ + int ret = 0; + struct lpddr3_min_tck *min; + + min = devm_kzalloc(dev, sizeof(*min), GFP_KERNEL); + if (!min) + goto default_min_tck; + + ret |= of_property_read_u32(np, "tRFC-min-tck", &min->tRFC); + ret |= of_property_read_u32(np, "tRRD-min-tck", &min->tRRD); + ret |= of_property_read_u32(np, "tRPab-min-tck", &min->tRPab); + ret |= of_property_read_u32(np, "tRPpb-min-tck", &min->tRPpb); + ret |= of_property_read_u32(np, "tRCD-min-tck", &min->tRCD); + ret |= of_property_read_u32(np, "tRC-min-tck", &min->tRC); + ret |= of_property_read_u32(np, "tRAS-min-tck", &min->tRAS); + ret |= of_property_read_u32(np, "tWTR-min-tck", &min->tWTR); + ret |= of_property_read_u32(np, "tWR-min-tck", &min->tWR); + ret |= of_property_read_u32(np, "tRTP-min-tck", &min->tRTP); + ret |= of_property_read_u32(np, "tW2W-C2C-min-tck", &min->tW2W_C2C); + ret |= of_property_read_u32(np, "tR2R-C2C-min-tck", &min->tR2R_C2C); + ret |= of_property_read_u32(np, "tWL-min-tck", &min->tWL); + ret |= of_property_read_u32(np, "tDQSCK-min-tck", &min->tDQSCK); + ret |= of_property_read_u32(np, "tRL-min-tck", &min->tRL); + ret |= of_property_read_u32(np, "tFAW-min-tck", &min->tFAW); + ret |= of_property_read_u32(np, "tXSR-min-tck", &min->tXSR); + ret |= of_property_read_u32(np, "tXP-min-tck", &min->tXP); + ret |= of_property_read_u32(np, "tCKE-min-tck", &min->tCKE); + ret |= of_property_read_u32(np, "tCKESR-min-tck", &min->tCKESR); + ret |= of_property_read_u32(np, "tMRD-min-tck", &min->tMRD); + + if (ret) { + dev_warn(dev, "%s: errors while parsing min-tck values\n", + __func__); + devm_kfree(dev, min); + goto default_min_tck; + } + + return min; + +default_min_tck: + dev_warn(dev, "%s: using default min-tck values\n", __func__); + return NULL; +} +EXPORT_SYMBOL(of_lpddr3_get_min_tck); + +static int of_lpddr3_do_get_timings(struct device_node *np, + struct lpddr3_timings *tim) +{ + int ret; + + /* The 'reg' param required since DT has changed, used as 'max-freq' */ + ret = of_property_read_u32(np, "reg", &tim->max_freq); + ret |= of_property_read_u32(np, "min-freq", &tim->min_freq); + ret |= of_property_read_u32(np, "tRFC", &tim->tRFC); + ret |= of_property_read_u32(np, "tRRD", &tim->tRRD); + ret |= of_property_read_u32(np, "tRPab", &tim->tRPab); + ret |= of_property_read_u32(np, "tRPpb", &tim->tRPpb); + ret |= of_property_read_u32(np, "tRCD", &tim->tRCD); + ret |= of_property_read_u32(np, "tRC", &tim->tRC); + ret |= of_property_read_u32(np, "tRAS", &tim->tRAS); + ret |= of_property_read_u32(np, "tWTR", &tim->tWTR); + ret |= of_property_read_u32(np, "tWR", &tim->tWR); + ret |= of_property_read_u32(np, "tRTP", &tim->tRTP); + ret |= of_property_read_u32(np, "tW2W-C2C", &tim->tW2W_C2C); + ret |= of_property_read_u32(np, "tR2R-C2C", &tim->tR2R_C2C); + ret |= of_property_read_u32(np, "tFAW", &tim->tFAW); + ret |= of_property_read_u32(np, "tXSR", &tim->tXSR); + ret |= of_property_read_u32(np, "tXP", &tim->tXP); + ret |= of_property_read_u32(np, "tCKE", &tim->tCKE); + ret |= of_property_read_u32(np, "tCKESR", &tim->tCKESR); + ret |= of_property_read_u32(np, "tMRD", &tim->tMRD); + + return ret; +} + +/** + * of_lpddr3_get_ddr_timings() - extracts the lpddr3 timings and updates no of + * frequencies available. + * @np_ddr: Pointer to ddr device tree node + * @dev: Device requesting for ddr timings + * @device_type: Type of ddr + * @nr_frequencies: No of frequencies available for ddr + * (updated by this function) + * + * Populates lpddr3_timings structure by extracting data from device + * tree node. Returns pointer to populated structure. If any error + * while populating, returns NULL. + */ +const struct lpddr3_timings *of_lpddr3_get_ddr_timings(struct device_node *np_ddr, + struct device *dev, u32 device_type, u32 *nr_frequencies) +{ + struct lpddr3_timings *timings = NULL; + u32 arr_sz = 0, i = 0; + struct device_node *np_tim; + char *tim_compat = NULL; + + switch (device_type) { + case DDR_TYPE_LPDDR3: + tim_compat = "jedec,lpddr3-timings"; + break; + default: + dev_warn(dev, "%s: un-supported memory type\n", __func__); + } + + for_each_child_of_node(np_ddr, np_tim) + if (of_device_is_compatible(np_tim, tim_compat)) + arr_sz++; + + if (arr_sz) + timings = devm_kcalloc(dev, arr_sz, sizeof(*timings), + GFP_KERNEL); + + if (!timings) + goto default_timings; + + for_each_child_of_node(np_ddr, np_tim) { + if (of_device_is_compatible(np_tim, tim_compat)) { + if (of_lpddr3_do_get_timings(np_tim, &timings[i])) { + devm_kfree(dev, timings); + goto default_timings; + } + i++; + } + } + + *nr_frequencies = arr_sz; + + return timings; + +default_timings: + dev_warn(dev, "%s: using default timings\n", __func__); + *nr_frequencies = 0; + return NULL; +} +EXPORT_SYMBOL(of_lpddr3_get_ddr_timings); diff --git a/drivers/memory/of_memory.h b/drivers/memory/of_memory.h index ef2514f..8cf2ce6 100644 --- a/drivers/memory/of_memory.h +++ b/drivers/memory/of_memory.h @@ -18,6 +18,11 @@ extern const struct lpddr2_min_tck *of_get_min_tck(struct device_node *np, extern const struct lpddr2_timings *of_get_ddr_timings(struct device_node *np_ddr, struct device *dev, u32 device_type, u32 *nr_frequencies); +extern const struct lpddr3_min_tck + *of_lpddr3_get_min_tck(struct device_node *np, struct device *dev); +extern const struct lpddr3_timings + *of_lpddr3_get_ddr_timings(struct device_node *np_ddr, + struct device *dev, u32 device_type, u32 *nr_frequencies); #else static inline const struct lpddr2_min_tck *of_get_min_tck(struct device_node *np, struct device *dev) @@ -31,6 +36,19 @@ static inline const struct lpddr2_timings { return NULL; } -#endif /* CONFIG_OF && CONFIG_DDR */ + +static inline const struct lpddr3_min_tck + *of_lpddr3_get_min_tck(struct device_node *np, struct device *dev) +{ + return NULL; +} + +static inline const struct lpddr3_timings + *of_lpddr3_get_ddr_timings(struct device_node *np_ddr, + struct device *dev, u32 device_type, u32 *nr_frequencies) +{ + return NULL; +} +#endif #endif /* __LINUX_MEMORY_OF_REG_ */ diff --git a/include/memory/jedec_ddr.h b/include/memory/jedec_ddr.h index ddad0f8..3601825 100644 --- a/include/memory/jedec_ddr.h +++ b/include/memory/jedec_ddr.h @@ -32,6 +32,7 @@ #define DDR_TYPE_LPDDR2_S4 3 #define DDR_TYPE_LPDDR2_S2 4 #define DDR_TYPE_LPDDR2_NVM 5 +#define DDR_TYPE_LPDDR3 6 /* DDR IO width */ #define DDR_IO_WIDTH_4 1 @@ -172,4 +173,65 @@ extern const struct lpddr2_timings lpddr2_jedec_timings[NUM_DDR_TIMING_TABLE_ENTRIES]; extern const struct lpddr2_min_tck lpddr2_jedec_min_tck; + +/* + * Structure for timings for LPDDR3 based on LPDDR2 plus additional fields. + * All parameters are in pico seconds(ps) unless explicitly indicated + * with a suffix like tRAS_max_ns below + */ +struct lpddr3_timings { + u32 max_freq; + u32 min_freq; + u32 tRFC; + u32 tRRD; + u32 tRPab; + u32 tRPpb; + u32 tRCD; + u32 tRC; + u32 tRAS; + u32 tWTR; + u32 tWR; + u32 tRTP; + u32 tW2W_C2C; + u32 tR2R_C2C; + u32 tWL; + u32 tDQSCK; + u32 tRL; + u32 tFAW; + u32 tXSR; + u32 tXP; + u32 tCKE; + u32 tCKESR; + u32 tMRD; +}; + +/* + * Min value for some parameters in terms of number of tCK cycles(nCK) + * Please set to zero parameters that are not valid for a given memory + * type + */ +struct lpddr3_min_tck { + u32 tRFC; + u32 tRRD; + u32 tRPab; + u32 tRPpb; + u32 tRCD; + u32 tRC; + u32 tRAS; + u32 tWTR; + u32 tWR; + u32 tRTP; + u32 tW2W_C2C; + u32 tR2R_C2C; + u32 tWL; + u32 tDQSCK; + u32 tRL; + u32 tFAW; + u32 tXSR; + u32 tXP; + u32 tCKE; + u32 tCKESR; + u32 tMRD; +}; + #endif /* __LINUX_JEDEC_DDR_H */ From patchwork Mon May 6 15:11:55 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lukasz Luba X-Patchwork-Id: 10931297 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 216E5912 for ; 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Mon, 6 May 2019 15:12:14 +0000 (GMT) From: Lukasz Luba To: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-samsung-soc@vger.kernel.org Cc: b.zolnierkie@samsung.com, krzk@kernel.org, kgene@kernel.org, cw00.choi@samsung.com, kyungmin.park@samsung.com, m.szyprowski@samsung.com, s.nawrocki@samsung.com, myungjoo.ham@samsung.com, keescook@chromium.org, tony@atomide.com, jroedel@suse.de, treding@nvidia.com, digetx@gmail.com, willy.mh.wolff.ml@gmail.com, Lukasz Luba Subject: [PATCH v7 07/13] dt-bindings: memory-controllers: add Exynos5422 DMC device description Date: Mon, 6 May 2019 17:11:55 +0200 Message-Id: <1557155521-30949-8-git-send-email-l.luba@partner.samsung.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1557155521-30949-1-git-send-email-l.luba@partner.samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrMKsWRmVeSWpSXmKPExsWy7djP87oX/C7EGCy9w2OxccZ6VovrX56z Wsw/co7VYvXHx4wWk0/NZbI4051r0f/4NbPF+fMb2C3ONr1ht7jVIGNxedccNovPvUcYLWac 38dksfbIXXaL240r2CwOv2lntdh/xcvi9m8+i28nHjE6CHt8+zqJxWN2w0UWj52z7rJ7bFrV yebR2/yOzePguz1MHn1bVjF6bD5d7fF5k1wAZxSXTUpqTmZZapG+XQJXxvQlz9gKNstUfOv3 aWA8IN7FyMkhIWAi8WLXZfYuRi4OIYEVjBKL3pxmhHC+MEq87zrAAuF8ZpT4vfgUK0xL05ZL UFXLgVrmHmSDa5m+pZO5i5GDg01AT2LHqkKQBhGBaok71/czg9QwC7xhkjj76wcLSEJYIEli 2onDYDaLgKpE1+3/TCA2r4CXxLwtd5kgtslJ3DwHMpOTg1PAW+JvxyFGiPg9donHXa4QtovE yrknmCFsYYlXx7ewQ9gyEv93zoeaUyzR0LsQqrdG4nH/XKgaa4nDxy+ygtzMLKApsX6XPogp IeAosf5cCITJJ3HjrSBIMTOQOWnbdGaIMK9ER5sQxAwNiS09F6D2iEksXzMNaraHxPyHH1gh gTOPUWLV9gnMExjlZyHsWsDIuIpRPLW0ODc9tdgoL7Vcrzgxt7g0L10vOT93EyMwaZ3+d/zL DsZdf5IOMQpwMCrx8E5wuhAjxJpYVlyZe4hRgoNZSYQ38dm5GCHelMTKqtSi/Pii0pzU4kOM 0hwsSuK81QwPooUE0hNLUrNTUwtSi2CyTBycUg2MBVdeHb7Qpn5qh7CVcmLrOiXB973nZ1Z9 ChXrE363np+dw/vH9TV/5DM912zcw/bvh8nJ0358K1fcfsXc9e/qxN07Nzmc+7pSS71lR1vu 1GSZ/XYC7hOtI3eFbP2qUXlyQdveI1Mik7Znhl03yDX6ZLlO/9TM/C38Srv/nes3e7jydaf+ zI85P5VYijMSDbWYi4oTAaaEn29WAwAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrOIsWRmVeSWpSXmKPExsVy+t/xu7rn/S7EGDw7K2exccZ6VovrX56z Wsw/co7VYvXHx4wWk0/NZbI4051r0f/4NbPF+fMb2C3ONr1ht7jVIGNxedccNovPvUcYLWac 38dksfbIXXaL240r2CwOv2lntdh/xcvi9m8+i28nHjE6CHt8+zqJxWN2w0UWj52z7rJ7bFrV yebR2/yOzePguz1MHn1bVjF6bD5d7fF5k1wAZ5SeTVF+aUmqQkZ+cYmtUrShhZGeoaWFnpGJ pZ6hsXmslZGpkr6dTUpqTmZZapG+XYJexvQlz9gKNstUfOv3aWA8IN7FyMkhIWAi0bTlEmMX IxeHkMBSRomnbZMZIRJiEpP2bWeHsIUl/lzrYoMo+sQo0bb1ElCCg4NNQE9ix6pCkBoRgXqJ /jeXwGqYBRqYJdZsv8oKkhAWSJC4c3EGmM0ioCrRdfs/E4jNK+AlMW/LXSaIBXISN891MoPY nALeEn87DoEdIQRUs+/jb5YJjHwLGBlWMYqklhbnpucWG+oVJ+YWl+al6yXn525iBEbStmM/ N+9gvLQx+BCjAAejEg/vA9sLMUKsiWXFlbmHGCU4mJVEeBOfnYsR4k1JrKxKLcqPLyrNSS0+ xGgKdNREZinR5HxglOeVxBuaGppbWBqaG5sbm1koifN2CByMERJITyxJzU5NLUgtgulj4uCU amAs3vX2RUIAf22yPcd0zaYFgj+Vl2WsXfDGfVv3ZsX3WkVTXjBkvfbM2CDEm71ct3DztVvL vX5I8CeecytSZ9ZcU5Dzb+KTPWZBp9ib5P9pqMss8da2OPJ0R0DtD/Pu9sO5uh+XcsS8V1i5 fNpvv5QIsbpQ94dGeyMvLKxpSH3j2jZF3cMob40SS3FGoqEWc1FxIgD79POiugIAAA== X-CMS-MailID: 20190506151215eucas1p2c57147edac5671c5ec9a223efb6b4adc X-Msg-Generator: CA X-RootMTR: 20190506151215eucas1p2c57147edac5671c5ec9a223efb6b4adc X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20190506151215eucas1p2c57147edac5671c5ec9a223efb6b4adc References: <1557155521-30949-1-git-send-email-l.luba@partner.samsung.com> Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The patch adds description for DT binding for a new Exynos5422 Dynamic Memory Controller device. Signed-off-by: Lukasz Luba --- .../bindings/memory-controllers/exynos5422-dmc.txt | 74 ++++++++++++++++++++++ 1 file changed, 74 insertions(+) create mode 100644 Documentation/devicetree/bindings/memory-controllers/exynos5422-dmc.txt diff --git a/Documentation/devicetree/bindings/memory-controllers/exynos5422-dmc.txt b/Documentation/devicetree/bindings/memory-controllers/exynos5422-dmc.txt new file mode 100644 index 0000000..be602a9 --- /dev/null +++ b/Documentation/devicetree/bindings/memory-controllers/exynos5422-dmc.txt @@ -0,0 +1,74 @@ +* Exynos5422 frequency and voltage scaling for Dynamic Memory Controller device + +The Samsung Exynos5422 SoC has DMC (Dynamic Memory Controller) to which the DRAM +memory chips are connected. The driver is to monitor the controller in runtime +and switch frequency and voltage. To monitor the usage of the controller in +runtime, the driver uses the PPMU (Platform Performance Monitoring Unit), which +is able to measure the current load of the memory. +When 'userspace' governor is used for the driver, an application is able to +switch the DMC and memory frequency. + +Required properties for DMC device for Exynos5422: +- compatible: Should be "samsung,exynos5422-dmc". +- clock-names : the name of clock used by the controller. +- clocks : phandles for clock specified in "clock-names" property. +- devfreq-events : phandles for PPMU devices connected to this DMC. +- vdd-supply : phandle for voltage regulator which is connected. +- reg : registers of two CDREX controllers. +- operating-points-v2 : phandle for OPPs described in v2 definition. +- device-handle : phandle of the connected DRAM memory device. For more + information please refer to Documentation +- devfreq-events : phandles of the PPMU events used by the controller. +- samsung,syscon-chipid : phandle of the ChipID used by the controller. +- samsung,syscon-clk : phandle of the clock register set used by the controller. + +Example: + + ppmu_dmc0_0: ppmu@10d00000 { + compatible = "samsung,exynos-ppmu"; + reg = <0x10d00000 0x2000>; + clocks = <&clock CLK_PCLK_PPMU_DREX0_0>; + clock-names = "ppmu"; + events { + ppmu_event_dmc0_0: ppmu-event3-dmc0_0 { + event-name = "ppmu-event3-dmc0_0"; + }; + }; + }; + + dmc: memory-controller@10c20000 { + compatible = "samsung,exynos5422-dmc"; + reg = <0x10c20000 0x100>, <0x10c30000 0x100>, + clocks = <&clock CLK_FOUT_SPLL>, + <&clock CLK_MOUT_SCLK_SPLL>, + <&clock CLK_FF_DOUT_SPLL2>, + <&clock CLK_FOUT_BPLL>, + <&clock CLK_MOUT_BPLL>, + <&clock CLK_SCLK_BPLL>, + <&clock CLK_MOUT_MX_MSPLL_CCORE>, + <&clock CLK_MOUT_MX_MSPLL_CCORE_PHY>, + <&clock CLK_MOUT_MCLK_CDREX>, + <&clock CLK_DOUT_CLK2X_PHY0>, + <&clock CLK_CLKM_PHY0>, + <&clock CLK_CLKM_PHY1>; + clock-names = "fout_spll", + "mout_sclk_spll", + "ff_dout_spll2", + "fout_bpll", + "mout_bpll", + "sclk_bpll", + "mout_mx_mspll_ccore", + "mout_mx_mspll_ccore_phy", + "mout_mclk_cdrex", + "dout_clk2x_phy0", + "clkm_phy0", + "clkm_phy1"; + operating-points-v2 = <&dmc_opp_table>; + devfreq-events = <&ppmu_event3_dmc0_0>, <&ppmu_event3_dmc0_1>, + <&ppmu_event3_dmc1_0>, <&ppmu_event3_dmc1_1>; + operating-points-v2 = <&dmc_opp_table>; + device-handle = <&samsung_K3QF2F20DB>; + vdd-supply = <&buck1_reg>; + samsung,syscon-clk = <&clock>; + samsung,syscon-chipid = <&chipid>; + }; From patchwork Mon May 6 15:11:56 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lukasz Luba X-Patchwork-Id: 10931283 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 8F70813AD for ; Mon, 6 May 2019 15:12:56 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 78CCF205AD for ; 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Mon, 6 May 2019 15:12:16 +0000 (GMT) Received: from eusmgms1.samsung.com (unknown [182.198.249.179]) by eusmtrp2.samsung.com (KnoxPortal) with ESMTP id 20190506151216eusmtrp2b300a5abf10d8d2cb92cdaa663941844~cILXROWkc0409004090eusmtrp2b; Mon, 6 May 2019 15:12:16 +0000 (GMT) X-AuditID: cbfec7f2-f13ff700000010ca-3b-5cd04ed12819 Received: from eusmtip1.samsung.com ( [203.254.199.221]) by eusmgms1.samsung.com (EUCPMTA) with SMTP id A0.6D.04146.0DE40DC5; Mon, 6 May 2019 16:12:16 +0100 (BST) Received: from AMDC3778.DIGITAL.local (unknown [106.120.51.20]) by eusmtip1.samsung.com (KnoxPortal) with ESMTPA id 20190506151215eusmtip1e8c9fa4f4bc00c2fbde7b7154346499c~cILWcGnpr3248532485eusmtip1t; Mon, 6 May 2019 15:12:15 +0000 (GMT) From: Lukasz Luba To: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-samsung-soc@vger.kernel.org Cc: b.zolnierkie@samsung.com, krzk@kernel.org, kgene@kernel.org, cw00.choi@samsung.com, kyungmin.park@samsung.com, m.szyprowski@samsung.com, s.nawrocki@samsung.com, myungjoo.ham@samsung.com, keescook@chromium.org, tony@atomide.com, jroedel@suse.de, treding@nvidia.com, digetx@gmail.com, willy.mh.wolff.ml@gmail.com, Lukasz Luba Subject: [PATCH v7 08/13] drivers: memory: add DMC driver for Exynos5422 Date: Mon, 6 May 2019 17:11:56 +0200 Message-Id: <1557155521-30949-9-git-send-email-l.luba@partner.samsung.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1557155521-30949-1-git-send-email-l.luba@partner.samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA0VSe0hTURzu7N7d3Zkbp03ypOFoUGQ2HxRxIImihEtlVFCECXXLi4/ctF21 hxVLo3ykllGTLCv6o5qVaWtohuYmaumcWlCpy9DoYSaZD5yS5vUu+u873/f9vu93DocmVA5p AJ1oSOOMBjZZS/mQtiaPS9e5oyM2/HO5H64sqZDid2NfpfhWY7sUl48MAHzl9U0JbsvX46KB HwR2uZ7IsDNrSIa7TUvxm+c3KDxa0AhwiatOgh81umW45+x9CjuGLkhx/dutuGdaiSda+sFG NTMxXkwypaZOkqm57pYxVZZciinIHqaYhuEXEqbQagHM09ZMZrQqaKc8xicyjktOzOCMYRsO +iQ0fTRLUmsriOM/iy5QJmBzS/KAnEZwLcq1FpJ5wIdWwfsAfZu+TAqCCo4B1OHYLQqjALmy u+cEen6i9/Eukb8H0PnpaZl4mBvos9ZJBRMFQ1G15agQ5AczUe+7ekLwEHBIgpxTk/MNasig 7PIJQvCTcDmaKvUToAJuRb22M+JyQehDey4hYDnchv7k2IEQg2C/DI08+iwT99mCui4D0a9G g81WmYiXotmaW95L8shUcMfrOYUGim56PeuRo7lzfmMCBqOK52EivQk5n7UBMV2J3v9cJNDE HCy2mQmRVqCc8yrRvRJZL3Z4ixajew+vecMZNDjbQohvUwZQYf44dQlorv8vuw2ABfhz6bw+ nuMjDNyxUJ7V8+mG+NDDKfoqMPe1Wmeaf1eD8a5DdgBpoPVVfNvSEauSshn8Cb0dIJrQ+inY L+2xKkUce+IkZ0w5YExP5ng7CKRJrb8ic8Gn/SoYz6ZxRzgulTP+UyW0PMAEorPNOo095CC9 t8Edtf3o7VlHjCY4vzbRNBLQp7Erh6+dzN0TFOFsXX3Vo0la4+5J81Uv+7ONWrCkLFAZGaUs NT+A0dATYuoJ2VfWlEVHT61YWHz47rruzct0lVfDMUFGvyrOgdT3mJkSj66s7txpdv/kQFLg r64ZS97Li4PPtCSfwEasIow8+xexH9hIVgMAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrOIsWRmVeSWpSXmKPExsVy+t/xu7oX/C7EGKyfL26xccZ6VovrX56z Wsw/co7VYvXHx4wWk0/NZbI4051r0f/4NbPF+fMb2C3ONr1ht7jVIGNxedccNovPvUcYLWac 38dksfbIXXaL240r2CwOv2lntdh/xcvi9m8+i28nHjE6CHt8+zqJxWN2w0UWj52z7rJ7bFrV yebR2/yOzePguz1MHn1bVjF6bD5d7fF5k1wAZ5SeTVF+aUmqQkZ+cYmtUrShhZGeoaWFnpGJ pZ6hsXmslZGpkr6dTUpqTmZZapG+XYJexrF705kKdq9nrnjb387WwLjtLlMXIweHhICJxJ11 gV2MXBxCAksZJd6vOMvSxcgJFBeTmLRvOzuELSzx51oXG0TRJ0aJlXOes4M0swnoSexYVQhS IyJQL9H/5hJYDbNAA7PEmu1XWUESwgIeEs2rvzGD1LMIqEr8mi0CYvIKeEnc2VYHMV5O4ua5 TmYQm1PAW+JvxyFGEFsIqGTfx98sExj5FjAyrGIUSS0tzk3PLTbUK07MLS7NS9dLzs/dxAiM pG3Hfm7ewXhpY/AhRgEORiUe3ge2F2KEWBPLiitzDzFKcDArifAmPjsXI8SbklhZlVqUH19U mpNafIjRFOikicxSosn5wCjPK4k3NDU0t7A0NDc2NzazUBLn7RA4GCMkkJ5YkpqdmlqQWgTT x8TBKdXAyOKgEB0tyyW5dEPlFVmeA2sj1LsORz3mUIhOtFvNNKdDJOwU90Of5TXPQ5vKHUqk QyfOnbt+UvvGnr8+rY+UGKXuHNjdLl14/+kz6cTpQm+D5v4JLGi5z/dnjl+QWPgklme55flb OD9b3d2Qtkb83Dfh0CB5dWeRTc/99v67KxA5I2ixa+RyJZbijERDLeai4kQAqyqjGLoCAAA= X-CMS-MailID: 20190506151216eucas1p2f0c5ba0920b256789240b87fbb88f3fe X-Msg-Generator: CA X-RootMTR: 20190506151216eucas1p2f0c5ba0920b256789240b87fbb88f3fe X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20190506151216eucas1p2f0c5ba0920b256789240b87fbb88f3fe References: <1557155521-30949-1-git-send-email-l.luba@partner.samsung.com> Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch adds driver for Exynos5422 Dynamic Memory Controller. The driver provides support for dynamic frequency and voltage scaling for DMC and DRAM. It supports changing timings of DRAM running with different frequency. There is also an algorithm to calculate timigns based on memory description provided in DT. The patch also contains needed MAINTAINERS file update. Signed-off-by: Lukasz Luba --- MAINTAINERS | 8 + drivers/memory/samsung/Kconfig | 17 + drivers/memory/samsung/Makefile | 1 + drivers/memory/samsung/exynos5422-dmc.c | 1761 +++++++++++++++++++++++++++++++ 4 files changed, 1787 insertions(+) create mode 100644 drivers/memory/samsung/exynos5422-dmc.c diff --git a/MAINTAINERS b/MAINTAINERS index 8ac65e4..c7abb73 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -3396,6 +3396,14 @@ S: Maintained F: drivers/devfreq/exynos-bus.c F: Documentation/devicetree/bindings/devfreq/exynos-bus.txt +DMC FREQUENCY DRIVER FOR SAMSUNG EXYNOS5422 +M: Lukasz Luba +L: linux-pm@vger.kernel.org +L: linux-samsung-soc@vger.kernel.org +S: Maintained +F: drivers/memory/samsung/exynos5422-dmc.c +F: Documentation/devicetree/bindings/memory-controllers/exynos5422-dmc.txt + BUSLOGIC SCSI DRIVER M: Khalid Aziz L: linux-scsi@vger.kernel.org diff --git a/drivers/memory/samsung/Kconfig b/drivers/memory/samsung/Kconfig index 79ce7ea..202972b 100644 --- a/drivers/memory/samsung/Kconfig +++ b/drivers/memory/samsung/Kconfig @@ -5,6 +5,23 @@ config SAMSUNG_MC Support for the Memory Controller (MC) devices found on Samsung Exynos SoCs. +config ARM_EXYNOS5422_DMC + tristate "ARM EXYNOS5422 Dynamic Memory Controller driver" + depends on ARCH_EXYNOS || COMPILE_TEST + select DDR + select PM_DEVFREQ + select DEVFREQ_GOV_SIMPLE_ONDEMAND + select DEVFREQ_GOV_USERSPACE + select PM_DEVFREQ_EVENT + select PM_OPP + help + This adds driver for Exynos5422 DMC (Dynamic Memory Controller). + The driver provides support for Dynamic Voltage and Frequency Scaling in + DMC and DRAM. It also supports changing timings of DRAM running with + different frequency. The timings are calculated based on DT memory + information. + + if SAMSUNG_MC config EXYNOS_SROM diff --git a/drivers/memory/samsung/Makefile b/drivers/memory/samsung/Makefile index 00587be..4f6e438 100644 --- a/drivers/memory/samsung/Makefile +++ b/drivers/memory/samsung/Makefile @@ -1,2 +1,3 @@ # SPDX-License-Identifier: GPL-2.0 +obj-$(CONFIG_ARM_EXYNOS5422_DMC) += exynos5422-dmc.o obj-$(CONFIG_EXYNOS_SROM) += exynos-srom.o diff --git a/drivers/memory/samsung/exynos5422-dmc.c b/drivers/memory/samsung/exynos5422-dmc.c new file mode 100644 index 0000000..64e99b1 --- /dev/null +++ b/drivers/memory/samsung/exynos5422-dmc.c @@ -0,0 +1,1761 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2019 Samsung Electronics Co., Ltd. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "../of_memory.h" + +#define EXYNOS5_DREXI_TIMINGAREF (0x0030) +#define EXYNOS5_DREXI_TIMINGROW0 (0x0034) +#define EXYNOS5_DREXI_TIMINGDATA0 (0x0038) +#define EXYNOS5_DREXI_TIMINGPOWER0 (0x003C) +#define EXYNOS5_DREXI_TIMINGROW1 (0x00E4) +#define EXYNOS5_DREXI_TIMINGDATA1 (0x00E8) +#define EXYNOS5_DREXI_TIMINGPOWER1 (0x00EC) +#define CDREX_PAUSE (0x91c) +#define CDREX_LPDDR3PHY_CON3 (0xa20) +#define EXYNOS5_TIMING_SET_SWI (1UL << 28) +#define USE_MX_MSPLL_TIMINGS (1) +#define USE_BPLL_TIMINGS (0) + +#define EXYNOS5_AREF_NORMAL (0x2e) + +#define IS_MEM_2GB(val) \ + ( \ + (((val) & 0xf0) & 0x20) ? 1 : \ + (((val) & 0xf0) & 0x30) ? 1 : 0 \ + ) + +#define EXYNOS5_POP_OPTIONS(val) (((val >> 4) & 0x3UL) << 4) +#define EXYNOS5_DDR_TYPE(val) (((val >> 14) & 0x1UL)) + +#define EXYNOS5_CHIP_PROD_ID (0) +#define EXYNOS5_CHIP_PKG_ID (4) + +#define PPMU_PMCNT_CONST_RATIO_MUL 15 +#define PPMU_PMCNT_CONST_RATIO_DIV 10 + +#define AXI_BUS_WIDTH_BYTES (128 >> 3) + +enum dmc_slot_id { + DMC0_0, + DMC0_1, + DMC1_0, + DMC1_1, + DMC_SLOTS_END +}; + +/** + * struct dmc_slot_info - Describes DMC's slot + * + * The structure holds DMC's slot name which is part of the device name + * provided in DT. Each slot has particular share of the DMC bandwidth. + * To abstract the model performance and values in performance counters, + * fields 'ratio_mul' and 'ratio_div' are used in calculation algorithm + * for each slot. Please check the corresponding function with the algorithm, + * to see how these variables are used. + */ +struct dmc_slot_info { + char *name; + int id; + int ratio_mul; + int ratio_div; +}; + +/** + * struct dmc_opp_table - Operating level desciption + * + * Covers frequency and voltage settings of the DMC operating mode. + */ +struct dmc_opp_table { + u32 freq_hz; + u32 volt_uv; +}; + +/** + * struct exynos5_dmc - main structure describing DMC device + * + * The main structure for the Dynamic Memory Controller which covers clocks, + * memory regions, HW information, parameters and current operating mode. + */ +struct exynos5_dmc { + struct device *dev; + struct devfreq *df; + struct devfreq_simple_ondemand_data gov_data; + void __iomem *base_drexi0; + void __iomem *base_drexi1; + struct regmap *clk_regmap; + struct regmap *chipid_regmap; + struct mutex lock; + unsigned long curr_rate; + unsigned long curr_volt; + unsigned long bypass_rate; + struct dmc_opp_table *opp; + struct dmc_opp_table opp_bypass; + int opp_count; + u32 timings_arr_size; + u32 *timing_row; + u32 *timing_data; + u32 *timing_power; + const struct lpddr3_timings *timings; + const struct lpddr3_min_tck *min_tck; + u32 bypass_timing_row; + u32 bypass_timing_data; + u32 bypass_timing_power; + unsigned int prod_rev; + unsigned int pkg_rev; + unsigned int mem_info; + struct regulator *vdd_mif; + struct clk *fout_spll; + struct clk *fout_bpll; + struct clk *mout_spll; + struct clk *mout_bpll; + struct clk *mout_mclk_cdrex; + struct clk *dout_clk2x_phy0; + struct clk *mout_mx_mspll_ccore; + struct clk *mx_mspll_ccore_phy; + struct clk *mout_mx_mspll_ccore_phy; + struct devfreq_event_dev **counter; + int num_counters; +#ifdef CONFIG_DEBUG_FS + struct dentry *dbg_root; +#endif +}; + +#define TIMING_FIELD(t_name, t_bit_beg, t_bit_end) \ + { .name = t_name, .bit_beg = t_bit_beg, .bit_end = t_bit_end } + +#define TIMING_VAL(timing_array, id, t_val) \ +({ \ + u32 __val; \ + __val = t_val << timing_array[id].bit_beg; \ + __val; \ +}) + +#define TIMING_VAL2REG(timing, t_val) \ +({ \ + u32 __val; \ + __val = t_val << timing->bit_beg; \ + __val; \ +}) + +#define TIMING_REG2VAL(reg, timing) \ +({ \ + u32 __val; \ + reg <<= (31 - timing->bit_end); \ + reg >>= (31 - timing->bit_end); \ + __val = reg >> timing->bit_beg; \ + __val; \ +}) + +struct timing_reg { + char *name; + int bit_beg; + int bit_end; + unsigned int val; +}; + +static const struct timing_reg timing_row[] = { + TIMING_FIELD("tRFC", 24, 31), + TIMING_FIELD("tRRD", 20, 23), + TIMING_FIELD("tRP", 16, 19), + TIMING_FIELD("tRCD", 12, 15), + TIMING_FIELD("tRC", 6, 11), + TIMING_FIELD("tRAS", 0, 5), +}; + +static const struct timing_reg timing_data[] = { + TIMING_FIELD("tWTR", 28, 31), + TIMING_FIELD("tWR", 24, 27), + TIMING_FIELD("tRTP", 20, 23), + TIMING_FIELD("tW2W-C2C", 14, 14), + TIMING_FIELD("tR2R-C2C", 12, 12), + TIMING_FIELD("WL", 8, 11), + TIMING_FIELD("tDQSCK", 4, 7), + TIMING_FIELD("RL", 0, 3), +}; + +static const struct timing_reg timing_power[] = { + TIMING_FIELD("tFAW", 26, 31), + TIMING_FIELD("tXSR", 16, 25), + TIMING_FIELD("tXP", 8, 15), + TIMING_FIELD("tCKE", 4, 7), + TIMING_FIELD("tMRD", 0, 3), +}; + +#define TIMING_COUNT (ARRAY_SIZE(timing_row) + ARRAY_SIZE(timing_data) + \ + ARRAY_SIZE(timing_power)) + +static int exynos5_counters_set_event(struct exynos5_dmc *dmc) +{ + int i, ret; + + for (i = 0; i < dmc->num_counters; i++) { + if (!dmc->counter[i]) + continue; + ret = devfreq_event_set_event(dmc->counter[i]); + if (ret < 0) + return ret; + } + return 0; +} + +static int exynos5_counters_enable_edev(struct exynos5_dmc *dmc) +{ + int i, ret; + + for (i = 0; i < dmc->num_counters; i++) { + if (!dmc->counter[i]) + continue; + ret = devfreq_event_enable_edev(dmc->counter[i]); + if (ret < 0) + return ret; + } + return 0; +} + +static int exynos5_counters_disable_edev(struct exynos5_dmc *dmc) +{ + int i, ret; + + for (i = 0; i < dmc->num_counters; i++) { + if (!dmc->counter[i]) + continue; + ret = devfreq_event_disable_edev(dmc->counter[i]); + if (ret < 0) + return ret; + } + return 0; +} + +/* Event names to DMC channel and slot with proper data count type */ +static const char *event_name[] = { + /* Counters for DMC0 slot 0 */ + "ppmu-event0-dmc0_0", + "DMC0_0-Read", + "ppmu-event1-dmc0_0", + "DMC0_0-Write", + "ppmu-event3-dmc0_0", + "DMC0_0-Read+Write", + /* Counters for DMC0 slot 1 */ + "ppmu-event0-dmc0_1", + "DMC0_1-Read", + "ppmu-event1-dmc0_1", + "DMC0_1-Write", + "ppmu-event3-dmc0_1", + "DMC0_1-Read+Write", + /* Counters for DMC1 slot 0 */ + "ppmu-event0-dmc1_0", + "DMC1_0-Read", + "ppmu-event1-dmc1_0", + "DMC1_0-Write", + "ppmu-event3-dmc1_0", + "DMC1_0-Read+Write", + /* Counters for DMC1 slot 0 */ + "ppmu-event0-dmc1_1", + "DMC1_1-Read", + "ppmu-event1-dmc1_1", + "DMC1_1-Write", + "ppmu-event3-dmc1_1", + "DMC1_1-Read+Write", +}; + +/** + * find_target_freq_id() - Finds requested frequency in local DMC configuration + * @dmc: device for which the information is checked + * @target_rate: requested frequency in KHz + * + * Seeks in the local DMC driver structure for the requested frequency value + * and returns index or error value. + */ +static int find_target_freq_idx(struct exynos5_dmc *dmc, + unsigned long target_rate) +{ + int i; + + for (i = dmc->opp_count - 1; i >= 0; i--) + if (dmc->opp[i].freq_hz <= target_rate) + return i; + + return -EINVAL; +} + +/** + * exynos5_dmc_chip_revision_settings() - Chooses proper DMC's configuration + * @dmc: device for which is going to be checked and configured + * + * Function checks the HW product information in order to choose proper + * configuration for DMC frequency, voltage and DRAM timings. + */ +static int exynos5_dmc_chip_revision_settings(struct exynos5_dmc *dmc) +{ + unsigned int val; + + regmap_read(dmc->chipid_regmap, EXYNOS5_CHIP_PROD_ID, &val); + dmc->prod_rev = val; + + regmap_read(dmc->chipid_regmap, EXYNOS5_CHIP_PKG_ID, &val); + dmc->pkg_rev = val; + + dmc->mem_info = EXYNOS5_POP_OPTIONS(val); + dmc->mem_info |= EXYNOS5_DDR_TYPE(val); + + if (!IS_MEM_2GB(dmc->mem_info)) { + dev_warn(dmc->dev, "DRAM memory type not supported\n"); + return -EINVAL; + } + + return 0; +} + +/** + * exynos5_switch_timing_regs() - Changes bank register set for DRAM timings + * @dmc: device for which the new settings is going to be applied + * @set: boolean variable passing set value + * + * Changes the register set, which holds timing parameters. + * There is two register sets: 0 and 1. The register set 0 + * is used in normal operation when the clock is provided from main PLL. + * The bank register set 1 is used when the main PLL frequency is going to be + * changed and the clock is taken from alternative, stable source. + * This function switches between these banks according to the + * currently used clock source. + */ +static void exynos5_switch_timing_regs(struct exynos5_dmc *dmc, bool set) +{ + unsigned int reg; + int ret; + + ret = regmap_read(dmc->clk_regmap, CDREX_LPDDR3PHY_CON3, ®); + + if (set) + reg |= EXYNOS5_TIMING_SET_SWI; + else + reg &= ~EXYNOS5_TIMING_SET_SWI; + + regmap_write(dmc->clk_regmap, CDREX_LPDDR3PHY_CON3, reg); +} + +/** + * exynos5_init_freq_table() - Initialized PM OPP framework + * @dev: devfreq device for which the OPP table is going to be + * initialized + * @dmc: DMC device for which the frequencies are used for OPP init + * @profile: devfreq device's profile + * + * Populate the devfreq device's OPP table based on current frequency, voltage. + */ +static int exynos5_init_freq_table(struct device *dev, struct exynos5_dmc *dmc, + struct devfreq_dev_profile *profile) +{ + int i, ret; + int idx; + unsigned long freq; + + ret = dev_pm_opp_of_add_table(dev); + if (ret < 0) { + dev_err(dev, "Failed to get OPP table\n"); + return ret; + } + + dmc->opp_count = dev_pm_opp_get_opp_count(dev); + + dmc->opp = devm_kmalloc_array(dmc->dev, dmc->opp_count, + sizeof(struct dmc_opp_table), GFP_KERNEL); + if (!dmc->opp) + goto err_opp; + + idx = dmc->opp_count - 1; + for (i = 0, freq = ULONG_MAX; i < dmc->opp_count; i++, freq--) { + struct dev_pm_opp *opp; + + opp = dev_pm_opp_find_freq_floor(dev, &freq); + if (IS_ERR(opp)) + goto err_free_tables; + + dmc->opp[idx - i].freq_hz = freq; + dmc->opp[idx - i].volt_uv = dev_pm_opp_get_voltage(opp); + + dev_pm_opp_put(opp); + } + + return 0; + +err_free_tables: + kfree(dmc->opp); +err_opp: + dev_pm_opp_of_remove_table(dev); + + return -EINVAL; +} + +/** + * exynos5_set_bypass_dram_timings() - Low-level changes of the DRAM timings + * @dmc: device for which the new settings is going to be applied + * @param: DRAM parameters which passes timing data + * + * Low-level function for changing timings for DRAM memory clocking from + * 'bypass' clock source (fixed frequency @400MHz). + * It uses timing bank registers set 1. + */ +static void exynos5_set_bypass_dram_timings(struct exynos5_dmc *dmc) +{ + writel(EXYNOS5_AREF_NORMAL, + dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGAREF); + + writel(dmc->bypass_timing_row, + dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGROW1); + writel(dmc->bypass_timing_row, + dmc->base_drexi1 + EXYNOS5_DREXI_TIMINGROW1); + writel(dmc->bypass_timing_data, + dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGDATA1); + writel(dmc->bypass_timing_data, + dmc->base_drexi1 + EXYNOS5_DREXI_TIMINGDATA1); + writel(dmc->bypass_timing_power, + dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGPOWER1); + writel(dmc->bypass_timing_power, + dmc->base_drexi1 + EXYNOS5_DREXI_TIMINGPOWER1); +} + +/** + * exynos5_dram_change_timings() - Low-level changes of the DRAM final timings + * @dmc: device for which the new settings is going to be applied + * @target_rate: target frequency of the DMC + * + * Low-level function for changing timings for DRAM memory operating from main + * clock source (BPLL), which can have different frequencies. Thus, each + * frequency must have corresponding timings register values in order to keep + * the needed delays. + * It uses timing bank registers set 0. + */ +static int exynos5_dram_change_timings(struct exynos5_dmc *dmc, + unsigned long target_rate) +{ + int idx; + + for (idx = dmc->opp_count - 1; idx >= 0; idx--) + if (dmc->opp[idx].freq_hz <= target_rate) + break; + + if (idx < 0) + return -EINVAL; + + writel(EXYNOS5_AREF_NORMAL, + dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGAREF); + + writel(dmc->timing_row[idx], + dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGROW0); + writel(dmc->timing_row[idx], + dmc->base_drexi1 + EXYNOS5_DREXI_TIMINGROW0); + writel(dmc->timing_data[idx], + dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGDATA0); + writel(dmc->timing_data[idx], + dmc->base_drexi1 + EXYNOS5_DREXI_TIMINGDATA0); + writel(dmc->timing_power[idx], + dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGPOWER0); + writel(dmc->timing_power[idx], + dmc->base_drexi1 + EXYNOS5_DREXI_TIMINGPOWER0); + + return 0; +} + +/** + * exynos5_dmc_align_target_voltage() - Sets the final voltage for the DMC + * @dmc: device for which it is going to be set + * @target_volt: new voltage which is chosen to be final + * + * Function tries to align voltage to the safe level for 'normal' mode. + * It checks the need of higher voltage and changes the value. The target + * voltage might be lower that currently set and still the system will be + * stable. + */ +static int exynos5_dmc_align_target_voltage(struct exynos5_dmc *dmc, + unsigned long target_volt) +{ + int ret = 0; + + if (dmc->curr_volt > target_volt) { + ret = regulator_set_voltage(dmc->vdd_mif, target_volt, + target_volt); + if (!ret) + dmc->curr_volt = target_volt; + } + + return ret; +} + +/** + * exynos5_dmc_align_bypass_voltage() - Sets the voltage for the DMC + * @dmc: device for which it is going to be set + * @target_volt: new voltage which is chosen to be final + * + * Function tries to align voltage to the safe level for the 'bypass' mode. + * It checks the need of higher voltage and changes the value. + * The target voltage must not be less than currently needed, because + * for current frequency the device might become unstable. + */ +static int exynos5_dmc_align_bypass_voltage(struct exynos5_dmc *dmc, + unsigned long target_volt) +{ + int ret = 0; + unsigned long bypass_volt = dmc->opp_bypass.volt_uv; + + target_volt = max(bypass_volt, target_volt); + + if (dmc->curr_volt >= target_volt) + return 0; + + ret = regulator_set_voltage(dmc->vdd_mif, target_volt, + target_volt); + if (!ret) + dmc->curr_volt = target_volt; + + return ret; +} + +/** + * exynos5_dmc_align_bypass_dram_timings() - Chooses and sets DRAM timings + * @dmc: device for which it is going to be set + * @target_rate: new frequency which is chosen to be final + * + * Function changes the DRAM timings for the temporary 'bypass' mode. + */ +static int exynos5_dmc_align_bypass_dram_timings(struct exynos5_dmc *dmc, + unsigned long target_rate) +{ + int idx = find_target_freq_idx(dmc, target_rate); + + if (idx < 0) + return -EINVAL; + + exynos5_set_bypass_dram_timings(dmc); + + return 0; +} + +/** + * exynos5_dmc_switch_to_bypass_configuration() - Switching to temporary clock + * @dmc: DMC device for which the switching is going to happen + * @target_rate: new frequency which is going to be set as a final + * @target_volt: new voltage which is going to be set as a final + * + * Function configures DMC and clocks for operating in temporary 'bypass' mode. + * This mode is used only temporary but if required, changes voltage and timings + * for DRAM chips. It switches the main clock to stable clock source for the + * period of the main PLL reconfiguration. + */ +static int exynos5_dmc_switch_to_bypass_configuration(struct exynos5_dmc *dmc, + unsigned long target_rate, + unsigned long target_volt) +{ + int ret; + + /* + * Having higher voltage for a particular frequency does not harm + * the chip. Use it for the temporary frequency change when one + * voltage manipulation might be avoided. + */ + ret = exynos5_dmc_align_bypass_voltage(dmc, target_volt); + if (ret) + return ret; + + /* + * Longer delays for DRAM does not cause crash, the opposite does. + */ + ret = exynos5_dmc_align_bypass_dram_timings(dmc, target_rate); + if (ret) + return ret; + + /* + * Delays are long enough, so use them for the new coming clock. + */ + exynos5_switch_timing_regs(dmc, USE_MX_MSPLL_TIMINGS); + + return ret; +} + +/** + * exynos5_dmc_change_freq_and_volt() - Changes voltage and frequency of the DMC + * using safe procedure + * @dmc: device for which the frequency is going to be changed + * @target_rate: requested new frequency + * @target_volt: requested voltage which corresponds to the new frequency + * + * The DMC frequency change procedure requires a few steps. + * The main requirement is to change the clock source in the clk mux + * for the time of main clock PLL locking. The assumption is that the + * alternative clock source set as parent is stable. + * The second parent's clock frequency is fixed to 400MHz, it is named 'bypass' + * clock. This requires alignment in DRAM timing parameters for the new + * T-period. There is two bank sets for keeping DRAM + * timings: set 0 and set 1. The set 0 is used when main clock source is + * chosen. The 2nd set of regs is used for 'bypass' clock. Switching between + * the two bank sets is part of the process. + * The voltage must also be aligned to the minimum required level. There is + * this intermediate step with switching to 'bypass' parent clock source. + * if the old voltage is lower, it requires an increase of the voltage level. + * The complexity of the voltage manipulation is hidden in low level function. + * In this function there is last alignment of the voltage level at the end. + */ +static int +exynos5_dmc_change_freq_and_volt(struct exynos5_dmc *dmc, + unsigned long target_rate, + unsigned long target_volt) +{ + int ret; + + ret = exynos5_dmc_switch_to_bypass_configuration(dmc, target_rate, + target_volt); + if (ret) + return ret; + + /* + * Voltage is set at least to a level needed for this frequency, + * so switching clock source is safe now. + */ + clk_prepare_enable(dmc->fout_spll); + clk_prepare_enable(dmc->mout_spll); + clk_prepare_enable(dmc->mout_mx_mspll_ccore); + + ret = clk_set_parent(dmc->mout_mclk_cdrex, dmc->mout_mx_mspll_ccore); + if (ret) + return ret; + + /* + * We are safe to increase the timings for current bypass frequency. + * Thanks to this the settings we be ready for the upcoming clock source + * change. + */ + exynos5_dram_change_timings(dmc, target_rate); + + clk_set_rate(dmc->fout_bpll, target_rate); + + exynos5_switch_timing_regs(dmc, USE_BPLL_TIMINGS); + + ret = clk_set_parent(dmc->mout_mclk_cdrex, dmc->mout_bpll); + if (ret) + return ret; + + clk_disable_unprepare(dmc->mout_mx_mspll_ccore); + clk_disable_unprepare(dmc->mout_spll); + clk_disable_unprepare(dmc->fout_spll); + /* + * Make sure if the voltage is not from 'bypass' settings and align to + * the right level for power efficiency. + */ + ret = exynos5_dmc_align_target_voltage(dmc, target_volt); + + return ret; +} + +/** + * exynos5_dmc_get_volt_freq() - Gets the frequency and voltage from the OPP + * table. + * @dev: device for which the frequency is going to be changed + * @freq: requested frequency in KHz + * @target_rate: returned frequency which is the same or lower than + * requested + * @target_volt: returned voltage which corresponds to the returned + * frequency + * + * Function gets requested frequency and checks OPP framework for needed + * frequency and voltage. It populates the values 'target_rate' and + * 'target_volt' or returns error value when OPP framework fails. + */ +static int exynos5_dmc_get_volt_freq(struct device *dev, unsigned long *freq, + unsigned long *target_rate, + unsigned long *target_volt, u32 flags) +{ + struct dev_pm_opp *opp; + + opp = devfreq_recommended_opp(dev, freq, flags); + if (IS_ERR(opp)) + return PTR_ERR(opp); + + *target_rate = dev_pm_opp_get_freq(opp); + *target_volt = dev_pm_opp_get_voltage(opp); + dev_pm_opp_put(opp); + + return 0; +} + +/** + * exynos5_dmc_target() - Function responsible for changing frequency of DMC + * @dev: device for which the frequency is going to be changed + * @freq: requested frequency in KHz + * @flags: flags provided for this frequency change request + * + * An entry function provided to the devfreq framework which provides frequency + * change of the DMC. The function gets the possible rate from OPP table based + * on requested frequency. It calls the next function responsible for the + * frequency and voltage change. In case of failure, does not set 'curr_rate' + * and returns error value to the framework. + */ +static int exynos5_dmc_target(struct device *dev, unsigned long *freq, + u32 flags) +{ + struct exynos5_dmc *dmc = dev_get_drvdata(dev); + unsigned long target_rate = 0; + unsigned long target_volt = 0; + int ret; + + ret = exynos5_dmc_get_volt_freq(dev, freq, &target_rate, &target_volt, + flags); + + if (ret) + return ret; + + if (target_rate == dmc->curr_rate) + return 0; + + mutex_lock(&dmc->lock); + + ret = exynos5_dmc_change_freq_and_volt(dmc, target_rate, target_volt); + + if (ret) { + mutex_unlock(&dmc->lock); + return ret; + } + + dmc->curr_rate = target_rate; + + mutex_unlock(&dmc->lock); + return 0; +} + +/** + * exynos5_counters_get() - Gets the performance counters values. + * @dmc: device for which the counters are going to be checked + * @load_count: variable which is populated with counter value + * @total_count: variable which is used as 'wall clock' reference + * + * Function which provides performance counters values. It sums up counters for + * two DMC channels. The 'total_count' is used as a reference and max value. + * The ratio 'load_count/total_count' shows the busy percentage [0%, 100%]. + */ +static int exynos5_counters_get(struct exynos5_dmc *dmc, + unsigned long *load_count, + unsigned long *total_count) +{ + unsigned long total = 0; + struct devfreq_event_data event; + int ret, i; + + *load_count = 0; + + /* Take into account only read+write counters, but stop all */ + for (i = 0; i < dmc->num_counters; i++) { + if (!dmc->counter[i]) + continue; + + ret = devfreq_event_get_event(dmc->counter[i], &event); + if (ret < 0) + return ret; + + if (i % 3 != 2) + continue; + + *load_count += event.load_count; + + if (total < event.total_count) + total = event.total_count; + } + + *total_count = total; + + return 0; +} + +/** + * exynos5_dmc_get_status() - Read current DMC performance statistics. + * @dev: device for which the statistics are requested + * @stat: structure which has statistic fields + * + * Function reads the DMC performance counters and calculates 'busy_time' + * and 'total_time'. To protect from overflow, the values are shifted right + * by 10. After read out the counters are setup to count again. + */ +static int exynos5_dmc_get_status(struct device *dev, + struct devfreq_dev_status *stat) +{ + struct exynos5_dmc *dmc = dev_get_drvdata(dev); + unsigned long load, total; + int ret; + + ret = exynos5_counters_get(dmc, &load, &total); + if (ret < 0) + return -EINVAL; + + /* To protect from overflow in calculation ratios, divide by 1024 */ + stat->busy_time = load >> 10; + stat->total_time = total >> 10; + + ret = exynos5_counters_set_event(dmc); + if (ret < 0) { + dev_err(dmc->dev, "could not set event counter\n"); + return ret; + } + + return 0; +} + +/** + * exynos5_dmc_get_cur_freq() - Function returns current DMC frequency + * @dev: device for which the framework checks operating frequency + * @freq: returned frequency value + * + * It returns the currently used frequency of the DMC. The real operating + * frequency might be lower when the clock source value could not be divided + * to the requested value. + */ +static int exynos5_dmc_get_cur_freq(struct device *dev, unsigned long *freq) +{ + struct exynos5_dmc *dmc = dev_get_drvdata(dev); + + mutex_lock(&dmc->lock); + *freq = dmc->curr_rate; + mutex_unlock(&dmc->lock); + + return 0; +} + +/** + * exynos5_dmc_df_profile - Devfreq governor's profile structure + * + * It provides to the devfreq framework needed functions and polling period. + */ +static struct devfreq_dev_profile exynos5_dmc_df_profile = { + .polling_ms = 500, + .target = exynos5_dmc_target, + .get_dev_status = exynos5_dmc_get_status, + .get_cur_freq = exynos5_dmc_get_cur_freq, +}; + +/** + * exynos5_dmc_align_initial_frequency() - Align initial frequency value + * @dmc: device for which the frequency is going to be set + * @bootloader_init_freq: initial frequency set by the bootloader in KHz + * + * The initial bootloader frequency, which is present during boot, might be + * different that supported frequency values in the driver. It is possible + * due to different PLL settings or used PLL as a source. + * This function provides the 'initial_freq' for the devfreq framework + * statistics engine which supports only registered values. Thus, some alignment + * must be made. + */ +unsigned long +exynos5_dmc_align_init_freq(struct exynos5_dmc *dmc, + unsigned long bootloader_init_freq) +{ + unsigned long aligned_freq; + int idx; + + idx = find_target_freq_idx(dmc, bootloader_init_freq); + if (idx >= 0) + aligned_freq = dmc->opp[idx].freq_hz; + else + aligned_freq = dmc->opp[dmc->opp_count - 1].freq_hz; + + return aligned_freq; +} + +/** + * create_timings_aligned() - Create register values and align with standard + * @dmc: device for which the frequency is going to be set + * @idx: speed bin in the OPP table + * @clk_period_ps: the period of the clock, known as tCK + * + * The function calculates timings and creates a register value ready for + * a frequency transition. The register contains a few timings. They are + * shifted by a known offset. The timing value is calculated based on memory + * specyfication: minimal time required and minimal cycles required. + */ +static int create_timings_aligned(struct exynos5_dmc *dmc, u32 *reg_timing_row, + u32 *reg_timing_data, u32 *reg_timing_power, + u32 clk_period_ps) +{ + u32 val; + const struct timing_reg *reg; + + if (clk_period_ps == 0) + return -EINVAL; + + *reg_timing_row = 0; + *reg_timing_data = 0; + *reg_timing_power = 0; + + val = dmc->timings->tRFC / clk_period_ps; + val += dmc->timings->tRFC % clk_period_ps ? 1 : 0; + val = max(val, dmc->min_tck->tRFC); + reg = &timing_row[0]; + *reg_timing_row |= TIMING_VAL2REG(reg, val); + + val = dmc->timings->tRRD / clk_period_ps; + val += dmc->timings->tRRD % clk_period_ps ? 1 : 0; + val = max(val, dmc->min_tck->tRRD); + reg = &timing_row[1]; + *reg_timing_row |= TIMING_VAL2REG(reg, val); + + val = dmc->timings->tRPab / clk_period_ps; + val += dmc->timings->tRPab % clk_period_ps ? 1 : 0; + val = max(val, dmc->min_tck->tRPab); + reg = &timing_row[2]; + *reg_timing_row |= TIMING_VAL2REG(reg, val); + + val = dmc->timings->tRCD / clk_period_ps; + val += dmc->timings->tRCD % clk_period_ps ? 1 : 0; + val = max(val, dmc->min_tck->tRCD); + reg = &timing_row[3]; + *reg_timing_row |= TIMING_VAL2REG(reg, val); + + val = dmc->timings->tRC / clk_period_ps; + val += dmc->timings->tRC % clk_period_ps ? 1 : 0; + val = max(val, dmc->min_tck->tRC); + reg = &timing_row[4]; + *reg_timing_row |= TIMING_VAL2REG(reg, val); + + val = dmc->timings->tRAS / clk_period_ps; + val += dmc->timings->tRAS % clk_period_ps ? 1 : 0; + val = max(val, dmc->min_tck->tRAS); + reg = &timing_row[5]; + *reg_timing_row |= TIMING_VAL2REG(reg, val); + + /* data related timings */ + val = dmc->timings->tWTR / clk_period_ps; + val += dmc->timings->tWTR % clk_period_ps ? 1 : 0; + val = max(val, dmc->min_tck->tWTR); + reg = &timing_data[0]; + *reg_timing_data |= TIMING_VAL2REG(reg, val); + + val = dmc->timings->tWR / clk_period_ps; + val += dmc->timings->tWR % clk_period_ps ? 1 : 0; + val = max(val, dmc->min_tck->tWR); + reg = &timing_data[1]; + *reg_timing_data |= TIMING_VAL2REG(reg, val); + + val = dmc->timings->tRTP / clk_period_ps; + val += dmc->timings->tRTP % clk_period_ps ? 1 : 0; + val = max(val, dmc->min_tck->tRTP); + reg = &timing_data[2]; + *reg_timing_data |= TIMING_VAL2REG(reg, val); + + val = dmc->timings->tW2W_C2C / clk_period_ps; + val += dmc->timings->tW2W_C2C % clk_period_ps ? 1 : 0; + val = max(val, dmc->min_tck->tW2W_C2C); + reg = &timing_data[3]; + *reg_timing_data |= TIMING_VAL2REG(reg, val); + + val = dmc->timings->tR2R_C2C / clk_period_ps; + val += dmc->timings->tR2R_C2C % clk_period_ps ? 1 : 0; + val = max(val, dmc->min_tck->tR2R_C2C); + reg = &timing_data[4]; + *reg_timing_data |= TIMING_VAL2REG(reg, val); + + val = dmc->timings->tWL / clk_period_ps; + val += dmc->timings->tWL % clk_period_ps ? 1 : 0; + val = max(val, dmc->min_tck->tWL); + reg = &timing_data[5]; + *reg_timing_data |= TIMING_VAL2REG(reg, val); + + val = dmc->timings->tDQSCK / clk_period_ps; + val += dmc->timings->tDQSCK % clk_period_ps ? 1 : 0; + val = max(val, dmc->min_tck->tDQSCK); + reg = &timing_data[6]; + *reg_timing_data |= TIMING_VAL2REG(reg, val); + + val = dmc->timings->tRL / clk_period_ps; + val += dmc->timings->tRL % clk_period_ps ? 1 : 0; + val = max(val, dmc->min_tck->tRL); + reg = &timing_data[7]; + *reg_timing_data |= TIMING_VAL2REG(reg, val); + + /* power related timings */ + val = dmc->timings->tFAW / clk_period_ps; + val += dmc->timings->tFAW % clk_period_ps ? 1 : 0; + val = max(val, dmc->min_tck->tXP); + reg = &timing_power[0]; + *reg_timing_power |= TIMING_VAL2REG(reg, val); + + val = dmc->timings->tXSR / clk_period_ps; + val += dmc->timings->tXSR % clk_period_ps ? 1 : 0; + val = max(val, dmc->min_tck->tXSR); + reg = &timing_power[1]; + *reg_timing_power |= TIMING_VAL2REG(reg, val); + + val = dmc->timings->tXP / clk_period_ps; + val += dmc->timings->tXP % clk_period_ps ? 1 : 0; + val = max(val, dmc->min_tck->tXP); + reg = &timing_power[2]; + *reg_timing_power |= TIMING_VAL2REG(reg, val); + + val = dmc->timings->tCKE / clk_period_ps; + val += dmc->timings->tCKE % clk_period_ps ? 1 : 0; + val = max(val, dmc->min_tck->tCKE); + reg = &timing_power[3]; + *reg_timing_power |= TIMING_VAL2REG(reg, val); + + val = dmc->timings->tMRD / clk_period_ps; + val += dmc->timings->tMRD % clk_period_ps ? 1 : 0; + val = max(val, dmc->min_tck->tMRD); + reg = &timing_power[4]; + *reg_timing_power |= TIMING_VAL2REG(reg, val); + + return 0; +} + +/** + * of_get_dram_timings() - helper function for parsing DT settings for DRAM + * @dmc: device for which the frequency is going to be set + * + * The function parses DT entries with DRAM information. + */ +static int of_get_dram_timings(struct exynos5_dmc *dmc) +{ + int ret = 0; + int idx; + struct device_node *np_ddr; + u32 freq_mhz, clk_period_ps; + + np_ddr = of_parse_phandle(dmc->dev->of_node, "device-handle", 0); + if (!np_ddr) { + dev_warn(dmc->dev, "could not find 'device-handle' in DT\n"); + return -EINVAL; + } + + dmc->timing_row = devm_kmalloc_array(dmc->dev, TIMING_COUNT, + sizeof(u32), GFP_KERNEL); + if (!dmc->timing_row) + return -ENOMEM; + + dmc->timing_data = devm_kmalloc_array(dmc->dev, TIMING_COUNT, + sizeof(u32), GFP_KERNEL); + if (!dmc->timing_data) + return -ENOMEM; + + dmc->timing_power = devm_kmalloc_array(dmc->dev, TIMING_COUNT, + sizeof(u32), GFP_KERNEL); + if (!dmc->timing_power) + return -ENOMEM; + + dmc->timings = of_lpddr3_get_ddr_timings(np_ddr, dmc->dev, + DDR_TYPE_LPDDR3, + &dmc->timings_arr_size); + if (!dmc->timings) { + of_node_put(np_ddr); + dev_warn(dmc->dev, "could not get timings from DT\n"); + return -EINVAL; + } + + dmc->min_tck = of_lpddr3_get_min_tck(np_ddr, dmc->dev); + if (!dmc->min_tck) { + of_node_put(np_ddr); + dev_warn(dmc->dev, "could not get tck from DT\n"); + return -EINVAL; + } + + /* Sorted array of OPPs with frequency ascending */ + for (idx = 0; idx < dmc->opp_count; idx++) { + freq_mhz = dmc->opp[idx].freq_hz / 1000000; + clk_period_ps = 1000000 / freq_mhz; + + ret = create_timings_aligned(dmc, &dmc->timing_row[idx], + &dmc->timing_data[idx], + &dmc->timing_power[idx], + clk_period_ps); + } + + of_node_put(np_ddr); + + /* Take the highest frequency's timings as 'bypass' */ + dmc->bypass_timing_row = dmc->timing_row[idx - 1]; + dmc->bypass_timing_data = dmc->timing_data[idx - 1]; + dmc->bypass_timing_power = dmc->timing_power[idx - 1]; + + return ret; +} + +/** + * exynos5_dmc_init_clks() - Initialize clocks needed for DMC operation. + * @dev: device for which the clocks are setup + * @dmc: DMC structure containing needed fields + * + * Get the needed clocks defined in DT device, enable and set the right parents. + * Read current frequency and initialize the initial rate for governor. + */ +static int exynos5_dmc_init_clks(struct device *dev, struct exynos5_dmc *dmc) +{ + int ret; + unsigned long target_volt = 0; + unsigned long target_rate = 0; + + dmc->fout_spll = devm_clk_get(dev, "fout_spll"); + if (IS_ERR(dmc->fout_spll)) + return PTR_ERR(dmc->fout_spll); + + dmc->fout_bpll = devm_clk_get(dev, "fout_bpll"); + if (IS_ERR(dmc->fout_bpll)) + return PTR_ERR(dmc->fout_bpll); + + dmc->mout_mclk_cdrex = devm_clk_get(dev, "mout_mclk_cdrex"); + if (IS_ERR(dmc->mout_mclk_cdrex)) + return PTR_ERR(dmc->mout_mclk_cdrex); + + dmc->mout_bpll = devm_clk_get(dev, "mout_bpll"); + if (IS_ERR(dmc->mout_bpll)) + return PTR_ERR(dmc->mout_bpll); + + dmc->mout_mx_mspll_ccore = devm_clk_get(dev, "mout_mx_mspll_ccore"); + if (IS_ERR(dmc->mout_mx_mspll_ccore)) + return PTR_ERR(dmc->mout_mx_mspll_ccore); + + dmc->dout_clk2x_phy0 = devm_clk_get(dev, "dout_clk2x_phy0"); + if (IS_ERR(dmc->dout_clk2x_phy0)) + return PTR_ERR(dmc->dout_clk2x_phy0); + + dmc->mout_spll = devm_clk_get(dev, "ff_dout_spll2"); + if (IS_ERR(dmc->mout_spll)) { + dmc->mout_spll = devm_clk_get(dev, "mout_sclk_spll"); + if (IS_ERR(dmc->mout_spll)) + return PTR_ERR(dmc->mout_spll); + } + + /* + * Convert frequency to KHz values and set it for the governor. + */ + dmc->curr_rate = clk_get_rate(dmc->mout_mclk_cdrex); + dmc->curr_rate = exynos5_dmc_align_init_freq(dmc, dmc->curr_rate); + exynos5_dmc_df_profile.initial_freq = dmc->curr_rate; + + ret = exynos5_dmc_get_volt_freq(dev, &dmc->curr_rate, &target_rate, + &target_volt, 0); + if (ret) + return ret; + + dmc->curr_volt = target_volt; + + clk_prepare_enable(dmc->mout_spll); + clk_set_parent(dmc->mout_mx_mspll_ccore, dmc->mout_spll); + clk_prepare_enable(dmc->mout_mx_mspll_ccore); + + dmc->bypass_rate = clk_get_rate(dmc->mout_mx_mspll_ccore); + + clk_prepare_enable(dmc->fout_bpll); + clk_prepare_enable(dmc->mout_bpll); + + return 0; +} + +/** + * exynos5_performance_counters_init() - Initializes performance DMC's counters + * @dmc: DMC for which it does the setup + * + * Initialization of performance counters in DMC for estimating usage. + * The counter's values are used for calculation of a memory bandwidth and based + * on that the governor changes the frequency. + * The counters are not used when the governor is GOVERNOR_USERSPACE. + */ +static int exynos5_performance_counters_init(struct exynos5_dmc *dmc) +{ + int counters_size; + int ret, i; + + dmc->num_counters = devfreq_event_get_edev_count(dmc->dev); + if (dmc->num_counters < 0) { + dev_err(dmc->dev, "could not get devfreq-event counters\n"); + return dmc->num_counters; + } + + counters_size = sizeof(struct devfreq_event_dev) * dmc->num_counters; + dmc->counter = devm_kzalloc(dmc->dev, counters_size, GFP_KERNEL); + if (!dmc->counter) + return -ENOMEM; + + for (i = 0; i < dmc->num_counters; i++) { + dmc->counter[i] = + devfreq_event_get_edev_by_phandle(dmc->dev, i); + if (IS_ERR_OR_NULL(dmc->counter[i])) + return -EPROBE_DEFER; + } + + ret = exynos5_counters_enable_edev(dmc); + if (ret < 0) { + dev_err(dmc->dev, "could not enable event counter\n"); + return ret; + } + + ret = exynos5_counters_set_event(dmc); + if (ret < 0) { + dev_err(dmc->dev, "counld not set event counter\n"); + return ret; + } + + return 0; +} + +#ifdef CONFIG_DEBUG_FS + +static int dmc_dbg_show_timings(struct seq_file *seq, void *na) +{ + struct exynos5_dmc *dmc = seq->private; + int i, j; + u32 val; + const struct timing_reg *reg; + + seq_printf(seq, "timings for each frequency\n"); + for (j = dmc->opp_count - 1; j >= 0; j--) { + seq_printf(seq, "frequency = %uMHz\n", + dmc->opp[j].freq_hz / 1000000); + seq_printf(seq, "timing_row, timing_data, timing_power\n"); + seq_printf(seq, "0x%08X, 0x%08X, 0x%08X\n", dmc->timing_row[j], + dmc->timing_data[j], dmc->timing_power[j]); + } + + for (j = dmc->opp_count - 1; j >= 0; j--) { + seq_printf(seq, "frequency [MHz] = %u\n", + dmc->opp[j].freq_hz / 1000000); + + for (i = 0; i < ARRAY_SIZE(timing_row); i++) { + reg = &timing_row[i]; + val = TIMING_REG2VAL(dmc->timing_row[j], reg); + seq_printf(seq, "%s = %u\n", reg->name, val); + } + + for (i = 0; i < ARRAY_SIZE(timing_data); i++) { + reg = &timing_data[i]; + val = TIMING_REG2VAL(dmc->timing_data[j], reg); + seq_printf(seq, "%s = %u\n", reg->name, val); + } + + for (i = 0; i < ARRAY_SIZE(timing_power); i++) { + reg = &timing_power[i]; + val = TIMING_REG2VAL(dmc->timing_power[j], reg); + seq_printf(seq, "%s = %u\n", reg->name, val); + } + } + + return 0; +} + +static int dmc_dbg_open_timings(struct inode *inode, struct file *f) +{ + return single_open(f, dmc_dbg_show_timings, inode->i_private); +} + +static const char *event_get_name(const char *evt) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(event_name); i += 2) { + if (!strcmp(event_name[i], evt)) + return event_name[i + 1]; + } + + return "Unknown"; +} + +static int dmc_dbg_show_cnt(struct seq_file *seq, void *na) +{ + struct exynos5_dmc *dmc = seq->private; + int i; + struct devfreq_event_data event; + struct devfreq_event_dev *edev; + int ret; + const char *evt_name; + u64 ts_new, delta; + static u64 ts; + + seq_printf(seq, "Performance based on PMU counters\n"); + seq_printf(seq, "The counters could overflow every ~9.2 sec\n"); + + ts_new = ktime_get_ns(); + delta = ts_new - ts; + + for (i = 0; i < dmc->num_counters; i++) { + edev = dmc->counter[i]; + if (!edev) + continue; + + evt_name = event_get_name(edev->desc->name); + + ret = devfreq_event_get_event(edev, &event); + if (ret < 0) + return ret; + + seq_printf(seq, "%s = %lu / %lu\n", evt_name, event.load_count, + event.total_count); + } + + seq_printf(seq, "For last %llu ms\n", + div64_u64(delta, 1000000UL)); + + ts = ktime_get_ns(); + ret = exynos5_counters_set_event(dmc); + if (ret < 0) { + dev_err(dmc->dev, "could not set event counter\n"); + return ret; + } + + return 0; +} + +static int dmc_dbg_open_cnt(struct inode *inode, struct file *f) +{ + return single_open(f, dmc_dbg_show_cnt, inode->i_private); +} + +struct counter { + u64 load; + u64 total; +}; + +static int dmc_dbg_show_cnt_100ms(struct seq_file *seq, void *na) +{ + struct exynos5_dmc *dmc = seq->private; + int i; + u64 bandwidth = 0; + struct devfreq_event_data event; + struct devfreq_event_dev *edev; + int ret; + const char *evt_name; + u64 ts_new, delta; + static u64 ts; + struct counter *cnt; + u64 total[3] = {0, 0, 0 }; /* read, write, read+write data*/ + const char *type[3] = {"read", "write", "read+write"}; + u64 bus_cyc_count = 0; + int offset = 0; + char *s; + + s = kzalloc(PAGE_SIZE * sizeof(char), GFP_KERNEL); + if (!s) + return -ENOMEM; + + cnt = kcalloc(dmc->num_counters, sizeof(struct counter), GFP_KERNEL); + if (!cnt) + return -ENOMEM; + + ret = exynos5_counters_set_event(dmc); + if (ret < 0) { + dev_err(dmc->dev, "could not set event counter\n"); + return ret; + } + + ts = ktime_get_ns(); + msleep(100); + + /* Seprate data acquisition from presentation due to some + overheads. */ + for (i = 0; i < dmc->num_counters; i++) { + edev = dmc->counter[i]; + if (!edev) + continue; + + ret = devfreq_event_get_event(edev, &event); + if (ret < 0) + return ret; + + total[i % 3] += event.load_count; + cnt[i].load = event.load_count; + cnt[i].total = event.total_count; + + if (bus_cyc_count < event.total_count) + bus_cyc_count = event.total_count; + } + + ts_new = ktime_get_ns(); + delta = ts_new - ts; + if (delta == 0) + delta = 1; + + for (i = 0; i < dmc->num_counters; i++) { + edev = dmc->counter[i]; + if (!edev) + continue; + + evt_name = event_get_name(edev->desc->name); + + bandwidth = (u64)cnt[i].load * AXI_BUS_WIDTH_BYTES * 1000; + bandwidth = div64_u64(bandwidth, delta); + + offset += sprintf(s + offset, "%s\t\t%llu MB/s\n", + evt_name, bandwidth); + } + + for (i = 0; i < 3; i++) { + bandwidth = (u64)total[i] * AXI_BUS_WIDTH_BYTES * 1000; + bandwidth = div64_u64(bandwidth, delta); + + offset += sprintf(s + offset, "total\t%s\t\t%llu MB/s\n", + type[i], bandwidth); + } + + /* AXI speed is presented in MHz*/ + bus_cyc_count *= 1000; + + seq_printf(seq, "Performance based on PMU counters\n"); + seq_printf(seq, "The counters will overflow every ~9.2 sec\n"); + seq_printf(seq, "%s", s); + seq_printf(seq, "AXI bus frequency %llu MHz, width %u B, SDR mode\n", + div64_u64(bus_cyc_count, delta), AXI_BUS_WIDTH_BYTES); + seq_printf(seq, "For last %llu ms\n", + div64_u64(delta, 1000000UL)); + + kfree(cnt); + kfree(s); + + return 0; +} + +static int dmc_dbg_show_cnt_100ms_raw(struct seq_file *seq, void *na) +{ + struct exynos5_dmc *dmc = seq->private; + int i; + struct devfreq_event_data event; + struct devfreq_event_dev *edev; + int ret; + const char *evt_name; + u64 ts_new, delta; + static u64 ts; + struct counter *cnt; + const char *type[3] = {"read", "write", "read+write"}; + int offset = 0; + char *s; + + s = kzalloc(PAGE_SIZE * sizeof(char), GFP_KERNEL); + if (!s) + return -ENOMEM; + + cnt = kcalloc(dmc->num_counters, sizeof(struct counter), GFP_KERNEL); + if (!cnt) + return -ENOMEM; + + ret = exynos5_counters_set_event(dmc); + if (ret < 0) { + dev_err(dmc->dev, "could not set event counter\n"); + return ret; + } + + ts = ktime_get_ns(); + msleep(100); + + /* Seprate data acquisition from presentation due to some + overheads. */ + for (i = 0; i < dmc->num_counters; i++) { + edev = dmc->counter[i]; + if (!edev) + continue; + + ret = devfreq_event_get_event(edev, &event); + if (ret < 0) + return ret; + + cnt[i].load = event.load_count; + cnt[i].total = event.total_count; + } + + ts_new = ktime_get_ns(); + delta = ts_new - ts; + if (delta == 0) + delta = 1; + + for (i = 0; i < dmc->num_counters; i++) { + edev = dmc->counter[i]; + if (!edev) + continue; + + evt_name = event_get_name(edev->desc->name); + + offset += sprintf(s + offset, "%s (%s)\t\t%llu / %llu\n", + evt_name, type[i % 3], cnt[i].load, + cnt[i].total); + } + + seq_printf(seq, "Performance based on PMU counters ('load'/'total')\n"); + seq_printf(seq, "The counters will overflow every ~9.2 sec\n"); + seq_printf(seq, "%s", s); + seq_printf(seq, "For last %llu ms\n", + div64_u64(delta, 1000000UL)); + + kfree(cnt); + kfree(s); + + return 0; +} + +static int dmc_dbg_open_cnt_100ms(struct inode *inode, struct file *f) +{ + return single_open(f, dmc_dbg_show_cnt_100ms, inode->i_private); +} + +static int dmc_dbg_open_cnt_100ms_raw(struct inode *inode, struct file *f) +{ + return single_open(f, dmc_dbg_show_cnt_100ms_raw, inode->i_private); +} + +static const struct file_operations dmc_debugfs_ops_timings = { + .open = dmc_dbg_open_timings, + .read = seq_read, + .release = single_release, +}; + +static const struct file_operations dmc_debugfs_ops_cnt = { + .open = dmc_dbg_open_cnt, + .read = seq_read, + .release = single_release, +}; + +static const struct file_operations dmc_debugfs_ops_cnt_100ms = { + .open = dmc_dbg_open_cnt_100ms, + .read = seq_read, + .release = single_release, +}; + +static const struct file_operations dmc_debugfs_ops_cnt_100ms_raw = { + .open = dmc_dbg_open_cnt_100ms_raw, + .read = seq_read, + .release = single_release, +}; + +static void exynos5_dmc_debugfs_init(struct exynos5_dmc *dmc) +{ + struct dentry *dentry; + + dmc->dbg_root = debugfs_create_dir(dev_name(dmc->dev), NULL); + if (!dmc->dbg_root) + return; + + dentry = debugfs_create_file("timings", 0444, dmc->dbg_root, dmc, + &dmc_debugfs_ops_timings); + if (!dentry) + goto clean_debugfs; + + dentry = debugfs_create_file("counters", 0444, dmc->dbg_root, dmc, + &dmc_debugfs_ops_cnt); + if (!dentry) + goto clean_debugfs; + + dentry = debugfs_create_file("100ms_counters", 0444, dmc->dbg_root, dmc, + &dmc_debugfs_ops_cnt_100ms); + if (!dentry) + goto clean_debugfs; + + dentry = debugfs_create_file("100ms_raw_counters", 0444, dmc->dbg_root, + dmc, &dmc_debugfs_ops_cnt_100ms_raw); + if (!dentry) + goto clean_debugfs; + + return; + +clean_debugfs: + debugfs_remove_recursive(dmc->dbg_root); +} +#else +static void exynos5_dmc_debugfs_init(struct exynos5_dmc *dmc) +{} +#endif + +/** + * exynos5_dmc_set_pause_on_switching() - Controls a pause feature in DMC + * @dmc: device which is used for changing this feature + * @set: a boolean state passing enable/disable request + * + * There is a need of pausing DREX DMC when divider or MUX in clock tree + * changes its configuration. In such situation access to the memory is blocked + * in DMC automatically. This feature is used when clock frequency change + * request appears and touches clock tree. + */ +static inline int exynos5_dmc_set_pause_on_switching(struct exynos5_dmc *dmc) +{ + unsigned int val; + int ret; + + ret = regmap_read(dmc->clk_regmap, CDREX_PAUSE, &val); + if (ret) + return ret; + + val |= 1UL; + regmap_write(dmc->clk_regmap, CDREX_PAUSE, val); + + return 0; +} + +/** + * exynos5_dmc_probe() - Probe function for the DMC driver + * @pdev: platform device for which the driver is going to be initialized + * + * Initialize basic components: clocks, regulators, performance counters, etc. + * Read out product version and based on the information setup + * internal structures for the controller (frequency and voltage) and for DRAM + * memory parameters: timings for each operating frequency. + * Register new devfreq device for controlling DVFS of the DMC. + */ +static int exynos5_dmc_probe(struct platform_device *pdev) +{ + int ret = 0; + struct exynos5_dmc *dmc; + struct device *dev = &pdev->dev; + struct device_node *np = dev->of_node; + struct resource *res; + + dmc = devm_kzalloc(dev, sizeof(*dmc), GFP_KERNEL); + if (!dmc) + return -ENOMEM; + + mutex_init(&dmc->lock); + + dmc->dev = dev; + platform_set_drvdata(pdev, dmc); + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + dmc->base_drexi0 = devm_ioremap_resource(dev, res); + if (IS_ERR(dmc->base_drexi0)) + return PTR_ERR(dmc->base_drexi0); + + res = platform_get_resource(pdev, IORESOURCE_MEM, 1); + dmc->base_drexi1 = devm_ioremap_resource(dev, res); + if (IS_ERR(dmc->base_drexi1)) + return PTR_ERR(dmc->base_drexi1); + + dmc->chipid_regmap = syscon_regmap_lookup_by_phandle(np, + "samsung,syscon-chipid"); + if (IS_ERR(dmc->chipid_regmap)) + return PTR_ERR(dmc->chipid_regmap); + + dmc->clk_regmap = syscon_regmap_lookup_by_phandle(np, + "samsung,syscon-clk"); + if (IS_ERR(dmc->clk_regmap)) + return PTR_ERR(dmc->clk_regmap); + + ret = exynos5_dmc_chip_revision_settings(dmc); + if (ret) + return ret; + + ret = exynos5_init_freq_table(dev, dmc, &exynos5_dmc_df_profile); + if (ret) { + dev_warn(dev, "couldn't initialize frequency settings\n"); + return ret; + } + + dmc->vdd_mif = devm_regulator_get(dev, "vdd"); + if (IS_ERR(dmc->vdd_mif)) { + ret = PTR_ERR(dmc->vdd_mif); + dev_warn(dev, "couldn't get regulator\n"); + return ret; + } + + ret = exynos5_dmc_init_clks(dev, dmc); + if (ret) { + dev_warn(dev, "couldn't initialize clocks\n"); + return ret; + } + + ret = of_get_dram_timings(dmc); + if (ret) { + dev_warn(dev, "couldn't initialize timings settings\n"); + return ret; + } + + ret = exynos5_performance_counters_init(dmc); + if (ret) { + dev_warn(dev, "couldn't probe performance counters\n"); + goto remove_clocks; + } + + ret = exynos5_dmc_set_pause_on_switching(dmc); + if (ret) { + dev_warn(dev, "couldn't get access to PAUSE register\n"); + goto remove_clocks; + } + + + /* + * Setup default thresholds for the devfreq governor. + * The values are chosen based on experiments. + */ + dmc->gov_data.upthreshold = 30; + dmc->gov_data.downdifferential = 5; + + dmc->df = devm_devfreq_add_device(dev, &exynos5_dmc_df_profile, + DEVFREQ_GOV_USERSPACE, + &dmc->gov_data); + + if (IS_ERR(dmc->df)) { + ret = PTR_ERR(dmc->df); + goto err_devfreq_add; + } + + exynos5_dmc_debugfs_init(dmc); + + dev_info(&pdev->dev, "DMC init for prod_id=0x%08x pkg_id=0x%08x\n", + dmc->prod_rev, dmc->pkg_rev); + + return 0; + +err_devfreq_add: + exynos5_counters_disable_edev(dmc); +remove_clocks: + clk_disable_unprepare(dmc->mout_mx_mspll_ccore); + clk_disable_unprepare(dmc->mout_spll); + + return ret; +} + +/** + * exynos5_dmc_remove() - Remove function for the platform device + * @pdev: platform device which is going to be removed + * + * The function relies on 'devm' framework function which automatically + * clean the device's resources. It just calls explicitly disable function for + * the performance counters. + */ +static int exynos5_dmc_remove(struct platform_device *pdev) +{ + struct exynos5_dmc *dmc = dev_get_drvdata(&pdev->dev); + + exynos5_counters_disable_edev(dmc); + + clk_disable_unprepare(dmc->mout_mx_mspll_ccore); + clk_disable_unprepare(dmc->mout_spll); + + dev_pm_opp_remove_table(&pdev->dev); + + dev_info(&pdev->dev, "DMC removed\n"); + + return 0; +} + +static const struct of_device_id exynos5_dmc_of_match[] = { + { .compatible = "samsung,exynos5422-dmc", }, + { }, +}; +MODULE_DEVICE_TABLE(of, exynos5_dmc_of_match); + +static struct platform_driver exynos5_dmc_platdrv = { + .probe = exynos5_dmc_probe, + .remove = exynos5_dmc_remove, + .driver = { + .name = "exynos5-dmc", + .of_match_table = exynos5_dmc_of_match, + }, +}; +module_platform_driver(exynos5_dmc_platdrv); +MODULE_DESCRIPTION("Driver for Exynos5422 Dynamic Memory Controller dynamic frequency and voltage change"); +MODULE_LICENSE("GPL v2"); +MODULE_AUTHOR("Samsung"); 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Mon, 6 May 2019 15:12:16 +0000 (GMT) From: Lukasz Luba To: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-samsung-soc@vger.kernel.org Cc: b.zolnierkie@samsung.com, krzk@kernel.org, kgene@kernel.org, cw00.choi@samsung.com, kyungmin.park@samsung.com, m.szyprowski@samsung.com, s.nawrocki@samsung.com, myungjoo.ham@samsung.com, keescook@chromium.org, tony@atomide.com, jroedel@suse.de, treding@nvidia.com, digetx@gmail.com, willy.mh.wolff.ml@gmail.com, Lukasz Luba Subject: [PATCH v7 09/13] drivers: devfreq: events: add Exynos PPMU new events Date: Mon, 6 May 2019 17:11:57 +0200 Message-Id: <1557155521-30949-10-git-send-email-l.luba@partner.samsung.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1557155521-30949-1-git-send-email-l.luba@partner.samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA0VSa0hTYRjuO+fs7Exanabmp4bBQkjBmVD5RSEVBqei258ClWzlSS03dcdL ZsFSNK8pJWqWXbR0mGFNGyqWOkdW5ryVd0MaapdlpGZ20zydWf+e97m8z8vHR+Eyk8iFClfH sBq1MkJO2hGGp987vLr3dwZtKDVi6GFhlQj1zUyI0E2TWYTufbEAdOVFMYZeZqpQjuUjjjo6 HohRe5JVjAa1a1BP/XUSTWebACrseIKh+6YRMRq6oCNRi/WiCDW+2oOGfq5As8/egu32zOzX ywRzTdtFMHVFI2JGX5FOMtnJkyTTPNmAMZdqKgBT3ZbITOvdDkoC7LaFsBHhcazG2++YXdj8 8AIRNUme+VRWALTgsygDSChIb4Stj6axDGBHyWgdgJnphUAYZgAculZtG6YBvHM3S7wUyezt IgWhHMCy1BTyX2S+LG/RRVEkrYC1FdF8wIFOhMN9jTjvwWkrBtt/zBG8YE8fhOaGFoL3E7Q7 bCsK56GU3gtz3wChyw0OmNNxHksW6d9pxr8HQXpQDAcmrIRg8oeljaO4gO3hh9Ya26Fr4ELd TUzAHNRm37YtPQctOcU2z1bY0tol4ntx2gNW1XsL9A7YO5YDeBrSK2D/p1U8jS/Cy4YCXKCl MC1VJrjXw5qsTlvRalhemW9bzsCJhnHbE94AsOnXNzIXrC36X3YLgArgxMZyqlCW81Gz8QpO qeJi1aGKE5EqPVj8W23zrVO14Gv3cSOgKSBfLn3n3xkkEynjuASVEUAKlztIlePmIJk0RJlw ltVEBmtiI1jOCFwpQu4kTVw2GiijQ5Ux7GmWjWI1SypGSVy0wNC8rN+5RDfz2rFZ1+R26bah qZY54ksf6svDkDPlHVkSMoVOer/fvO/qqRzXwvzGqDLTat8d6mT2sV+BZee4u2N80lGN8/Dz LSaJR/LYFBMdrNvgdeDwXEpM5JBPcWBq+I+AdWddnlYO6nv8dhHnd9OWTZ3qIk9JlKu5VMGW r5QTXJjSxxPXcMo/hn8dJFcDAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrGIsWRmVeSWpSXmKPExsVy+t/xu7oX/S7EGOyYx2uxccZ6VovrX56z Wsw/co7VYvXHx4wWk0/NZbI4051r0f/4NbPF+fMb2C3ONr1ht7jVIGNxedccNovPvUcYLWac 38dksfbIXXaL240r2CwOv2lntdh/xcvi9m8+i28nHjE6CHt8+zqJxWN2w0UWj52z7rJ7bFrV yebR2/yOzePguz1MHn1bVjF6bD5d7fF5k1wAZ5SeTVF+aUmqQkZ+cYmtUrShhZGeoaWFnpGJ pZ6hsXmslZGpkr6dTUpqTmZZapG+XYJexr87/1kK3rFVvF02nbGB8T1rFyMnh4SAiUT3tYts XYxcHEICSxklvk7+BJUQk5i0bzs7hC0s8edaF1TRJ0aJzZfWAiU4ONgE9CR2rCoEqRERqJfo f3MJrIZZoIFZYs32q2CDhAX8JO72TmIBqWcRUJU4PSsTxOQV8JaYcI8RYrycxM1zncwgNidQ +G/HIbC4kICXxL6Pv1kmMPItYGRYxSiSWlqcm55bbKhXnJhbXJqXrpecn7uJERhH24793LyD 8dLG4EOMAhyMSjy8D2wvxAixJpYVV+YeYpTgYFYS4U18di5GiDclsbIqtSg/vqg0J7X4EKMp 0EkTmaVEk/OBMZ5XEm9oamhuYWlobmxubGahJM7bIXAwRkggPbEkNTs1tSC1CKaPiYNTqoGR y0zkFLvC8dVPnScmTD4ZPflwldTfTrNfK1MlQ0o2eyj9fSUivL70R6bYtheNi7MWqa5uXrB4 6T2DEMOPRdvuhzd+mqpnlb8mab9kVWTFHS3jwDg5haJ6Y6PKQ9MnsAvFTWKa/9lG7321+0+O 6GNFa6cdcboRsU7npSHTxrg9n3ZyN02uNzmkxFKckWioxVxUnAgAdPENpbkCAAA= X-CMS-MailID: 20190506151217eucas1p2c9348f2766870e7c22c2dabaab5d57a1 X-Msg-Generator: CA X-RootMTR: 20190506151217eucas1p2c9348f2766870e7c22c2dabaab5d57a1 X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20190506151217eucas1p2c9348f2766870e7c22c2dabaab5d57a1 References: <1557155521-30949-1-git-send-email-l.luba@partner.samsung.com> Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Define new performance events supported by Exynos5422 SoC counters. The counters are built-in in Dynamic Memory Controller and provide information regarding memory utilization. Signed-off-by: Lukasz Luba --- drivers/devfreq/event/exynos-ppmu.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/devfreq/event/exynos-ppmu.c b/drivers/devfreq/event/exynos-ppmu.c index 7ebe4d4..81361ea 100644 --- a/drivers/devfreq/event/exynos-ppmu.c +++ b/drivers/devfreq/event/exynos-ppmu.c @@ -96,6 +96,12 @@ static struct __exynos_ppmu_events { PPMU_EVENT(d1-cpu), PPMU_EVENT(d1-general), PPMU_EVENT(d1-rt), + + /* For Exynos5422 SoC */ + PPMU_EVENT(dmc0_0), + PPMU_EVENT(dmc0_1), + PPMU_EVENT(dmc1_0), + PPMU_EVENT(dmc1_1), }; static int exynos_ppmu_find_ppmu_id(struct devfreq_event_dev *edev) From patchwork Mon May 6 15:11:58 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lukasz Luba X-Patchwork-Id: 10931289 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 02E0313AD for ; Mon, 6 May 2019 15:13:06 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id E540026E69 for ; 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Mon, 6 May 2019 15:12:18 +0000 (GMT) Received: from eusmgms1.samsung.com (unknown [182.198.249.179]) by eusmtrp2.samsung.com (KnoxPortal) with ESMTP id 20190506151218eusmtrp236e672c5ad255ffec09c9304fd591767~cILYzW0ZA0409004090eusmtrp2g; Mon, 6 May 2019 15:12:18 +0000 (GMT) X-AuditID: cbfec7f4-113ff70000001119-8a-5cd04ed39ff2 Received: from eusmtip1.samsung.com ( [203.254.199.221]) by eusmgms1.samsung.com (EUCPMTA) with SMTP id 53.6D.04146.2DE40DC5; Mon, 6 May 2019 16:12:18 +0100 (BST) Received: from AMDC3778.DIGITAL.local (unknown [106.120.51.20]) by eusmtip1.samsung.com (KnoxPortal) with ESMTPA id 20190506151217eusmtip166d04db1fad6bc53dd22f48c755dd3aa~cILYBuLWF3136331363eusmtip18; Mon, 6 May 2019 15:12:17 +0000 (GMT) From: Lukasz Luba To: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-samsung-soc@vger.kernel.org Cc: b.zolnierkie@samsung.com, krzk@kernel.org, kgene@kernel.org, cw00.choi@samsung.com, kyungmin.park@samsung.com, m.szyprowski@samsung.com, s.nawrocki@samsung.com, myungjoo.ham@samsung.com, keescook@chromium.org, tony@atomide.com, jroedel@suse.de, treding@nvidia.com, digetx@gmail.com, willy.mh.wolff.ml@gmail.com, Lukasz Luba Subject: [PATCH v7 10/13] ARM: dts: exynos: add chipid label and syscon compatible Date: Mon, 6 May 2019 17:11:58 +0200 Message-Id: <1557155521-30949-11-git-send-email-l.luba@partner.samsung.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1557155521-30949-1-git-send-email-l.luba@partner.samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrKKsWRmVeSWpSXmKPExsWy7djP87qX/S7EGJy9LWqxccZ6VovrX56z Wsw/co7VYvXHx4wWk0/NZbI4051r0f/4NbPF+fMb2C3ONr1ht7jVIGNxedccNovPvUcYLWac 38dksfbIXXaL240r2CwOv2lntdh/xcvi9m8+i28nHjE6CHt8+zqJxWN2w0UWj52z7rJ7bFrV yebR2/yOzePguz1MHn1bVjF6bD5d7fF5k1wAZxSXTUpqTmZZapG+XQJXxroW/oKDbBVbbp9m a2BcydrFyMkhIWAi8fHmJZYuRi4OIYEVjBJH3p9ng3C+MEqcOL6MCcL5zCixZ/YsZpiWBysu QCWWM0osufkPoeVv/0agDAcHm4CexI5VhSANIgLVEneu72cGqWEWeMMkcfbXDxaQhLBAiMS/ HS/BprIIqErcfbIILM4r4C3x6cVjdohtchI3z3WC1XACxf92HGIEGSQhcI9d4vC0R0wQRS4S 698ugLKFJV4d3wLVLCPxf+d8qHixREPvQkYIu0bicf9cqBpricPHL7KCHM0soCmxfpc+RNhR YvOiBjaQsIQAn8SNt4IgYWYgc9K26cwQYV6JjjYhiGoNiS09F6AWiUksXzMNariHRM/pY9Cw msco8fL/XOYJjPKzEJYtYGRcxSieWlqcm55abJSXWq5XnJhbXJqXrpecn7uJEZi4Tv87/mUH 464/SYcYBTgYlXh4JzhdiBFiTSwrrsw9xCjBwawkwpv47FyMEG9KYmVValF+fFFpTmrxIUZp DhYlcd5qhgfRQgLpiSWp2ampBalFMFkmDk6pBsYpUZ6OV91WfkwxXMn29t5f1tb6kx6tFvZa 8zbmnGj7G2xkKMtbwyDXE3X8zwvxqoBsrzed8zV9G/iqWz5ZO7efqBPmiXi6m/vl1QqlkteR a0+wbc2a84h739vgpQ4JQjYBx7xU3BxThB0k2Cq4f4e1h+18c7DyYkudh9rjSo4tW/Jf95ll K7EUZyQaajEXFScCAEMUu/dYAwAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrOIsWRmVeSWpSXmKPExsVy+t/xu7qX/C7EGJyfzGyxccZ6VovrX56z Wsw/co7VYvXHx4wWk0/NZbI4051r0f/4NbPF+fMb2C3ONr1ht7jVIGNxedccNovPvUcYLWac 38dksfbIXXaL240r2CwOv2lntdh/xcvi9m8+i28nHjE6CHt8+zqJxWN2w0UWj52z7rJ7bFrV yebR2/yOzePguz1MHn1bVjF6bD5d7fF5k1wAZ5SeTVF+aUmqQkZ+cYmtUrShhZGeoaWFnpGJ pZ6hsXmslZGpkr6dTUpqTmZZapG+XYJexroW/oKDbBVbbp9ma2BcydrFyMkhIWAi8WDFBaYu Ri4OIYGljBJb3uxlgkiISUzat50dwhaW+HOtiw2i6BOjxPmvkxi7GDk42AT0JHasKgSpERGo l+h/cwmshlmggVlizfarYBuEBYIkWt58BBvKIqAqcffJIhYQm1fAW+LTi8dQC+Qkbp7rZAax OYHifzsOMYLYQgJeEvs+/maZwMi3gJFhFaNIamlxbnpusaFecWJucWleul5yfu4mRmAkbTv2 c/MOxksbgw8xCnAwKvHwPrC9ECPEmlhWXJl7iFGCg1lJhDfx2bkYId6UxMqq1KL8+KLSnNTi Q4ymQEdNZJYSTc4HRnleSbyhqaG5haWhubG5sZmFkjhvh8DBGCGB9MSS1OzU1ILUIpg+Jg5O qQZGn42vJvgd/RSfvVKMlc1ck6mDe6lL7NHnWz9ftcu/Jfhz/f/dr4JPXRZoErl878LS49P2 9E07/0nyqXG9X7gVC5Ot1GPt4z9bmjzFFp66cGXWEqWT/1evVql+qPRn6lsJpw8931wPBtzR mz1jAWOX8Z4vMbYVNw7+EpRZaikj2RD244e9pJXzWyWW4oxEQy3mouJEAKz9DPO6AgAA X-CMS-MailID: 20190506151218eucas1p1f3bf0b48470595537a893bd0b39e75b7 X-Msg-Generator: CA X-RootMTR: 20190506151218eucas1p1f3bf0b48470595537a893bd0b39e75b7 X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20190506151218eucas1p1f3bf0b48470595537a893bd0b39e75b7 References: <1557155521-30949-1-git-send-email-l.luba@partner.samsung.com> Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add the chipid label which allows to use it in phandle from other device. Use syscon in compatible to get the regmap of the device register set. The chipid is used in DMC during initialization to compare compatibility. Signed-off-by: Lukasz Luba --- arch/arm/boot/dts/exynos5.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/exynos5.dtsi b/arch/arm/boot/dts/exynos5.dtsi index 67f9b45..4801ca7 100644 --- a/arch/arm/boot/dts/exynos5.dtsi +++ b/arch/arm/boot/dts/exynos5.dtsi @@ -35,8 +35,8 @@ #size-cells = <1>; ranges; - chipid@10000000 { - compatible = "samsung,exynos4210-chipid"; + chipid: chipid@10000000 { + compatible = "samsung,exynos4210-chipid", "syscon"; reg = <0x10000000 0x100>; }; From patchwork Mon May 6 15:11:59 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lukasz Luba X-Patchwork-Id: 10931279 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 7D607912 for ; Mon, 6 May 2019 15:12:48 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 6DDC5287CF for ; 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Mon, 6 May 2019 15:12:19 +0000 (GMT) Received: from eusmgms1.samsung.com (unknown [182.198.249.179]) by eusmtrp2.samsung.com (KnoxPortal) with ESMTP id 20190506151219eusmtrp2d4d981889c14ce9781907d4b1ac72e03~cILZuUENA0466604666eusmtrp2B; Mon, 6 May 2019 15:12:18 +0000 (GMT) X-AuditID: cbfec7f5-b8fff700000010e5-85-5cd04ed35c65 Received: from eusmtip1.samsung.com ( [203.254.199.221]) by eusmgms1.samsung.com (EUCPMTA) with SMTP id E4.6D.04146.2DE40DC5; Mon, 6 May 2019 16:12:18 +0100 (BST) Received: from AMDC3778.DIGITAL.local (unknown [106.120.51.20]) by eusmtip1.samsung.com (KnoxPortal) with ESMTPA id 20190506151218eusmtip15991e59e1f91f843d9c6b28dec5aa295~cILYzyJsI3142531425eusmtip1O; Mon, 6 May 2019 15:12:18 +0000 (GMT) From: Lukasz Luba To: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-samsung-soc@vger.kernel.org Cc: b.zolnierkie@samsung.com, krzk@kernel.org, kgene@kernel.org, cw00.choi@samsung.com, kyungmin.park@samsung.com, m.szyprowski@samsung.com, s.nawrocki@samsung.com, myungjoo.ham@samsung.com, keescook@chromium.org, tony@atomide.com, jroedel@suse.de, treding@nvidia.com, digetx@gmail.com, willy.mh.wolff.ml@gmail.com, Lukasz Luba Subject: [PATCH v7 11/13] ARM: dts: exynos: add syscon to clock compatible Date: Mon, 6 May 2019 17:11:59 +0200 Message-Id: <1557155521-30949-12-git-send-email-l.luba@partner.samsung.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1557155521-30949-1-git-send-email-l.luba@partner.samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA0VSaUgUUQDu7czszoor0yr5MFNaSExqrbR4kIQdxLiCmtCfFGrLwXPVdtQ0 pVaLUvPKrGS9UhNFk12PTMUj1yu8xcjKI1Os8CrzKC0r19nq3/e+k/d4JCZuISxI/+AwRhks D5LwjfCajrW+/UNuA94HZmYPo4pMDYGGlz8SKK+tj0Bli1MA3evK4aGeOwqUOjWLof5+rQD1 xs0J0FuVJRqqz+ajpeQ2gDL7m3iovG1MgEZiS/iode42gZpfytDIDxO0+mISOJvSqyvpOJ2l GsTpOvWYgK4sTeDTyTcW+HTLQgOPTqkuBXRVdzS9VGnlITxn5OTDBPlHMEr7YxeM/IYy7wtC XxGR31JOq8AonghIElKOMEMVkAiEpJgqAfCdWpkIjDbxMoBNqUk87rAEYNbXLELv0gcKsicJ TigGcPhuEfgX6Sh6ulXLp6SwtvSyPmBGRcPR4WZM78GoOR7sXf+O6wVTSgbXphu3ME7tgdrn sVsLIsoVqqaaBdyaFXzTl4DpsXCT34jXAY4fF8D8cXPuCqdgUbaBNoUzndWGqCX8XZfH4zAL Vcn5Bk8MnErNMXiOwtbOQUJfg1F7oabenqOPw4ZiLcG1m8DX89v1NLYJ02seYhwtgvG3xJzb FlYnDRiGdsDiJw8M5TT8HK8RcI+TC+DE2jRIA9bq/2OPACgF5kw4q/BlWIdg5oqUlSvY8GBf 6aUQRSXY/FjdvzpXakHTz4s6QJFAYixKOzHgLSbkEWyUQgcgiUnMRPIPfd5ikY886iqjDDmv DA9iWB3YSeISc1H0tgkvMeUrD2MCGSaUUf5VeaTQQgU8ZIoCV43ycW5uwe4MZ7XUzfOQ1DEX t3Q/66LVFerqLXp2uSzVy7xs3ocotEEaauVMMWVVnu8eIwpbd+0cXWyPO9LalVUV8Myp0fe6 aN9od4mng9orxjnetqJ9Y964XROZVBY9XygN9E8nbOy+3PTMM5axYepPVsy1k9PWwnYJzvrJ D9phSlb+B5lMdQFUAwAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrOIsWRmVeSWpSXmKPExsVy+t/xu7qX/C7EGPRvNLPYOGM9q8X1L89Z LeYfOcdqsfrjY0aLyafmMlmc6c616H/8mtni/PkN7BZnm96wW9xqkLG4vGsOm8Xn3iOMFjPO 72OyWHvkLrvF7cYVbBaH37SzWuy/4mVx+zefxbcTjxgdhD2+fZ3E4jG74SKLx85Zd9k9Nq3q ZPPobX7H5nHw3R4mj74tqxg9Np+u9vi8SS6AM0rPpii/tCRVISO/uMRWKdrQwkjP0NJCz8jE Us/Q2DzWyshUSd/OJiU1J7MstUjfLkEv4/KMqewF11grvve5NTDeYeli5OSQEDCRWDTnEWsX IxeHkMBSRon+I0eYIRJiEpP2bWeHsIUl/lzrYoMo+sQocWbpOcYuRg4ONgE9iR2rCkFqRATq JfrfXAKrYRZoYJZYs/0qK0hCWMBL4ufTvWDbWARUJTYcaASL8wp4SzQ83g+1QE7i5rlOsMWc QPG/HYcYQWwhoN59H3+zTGDkW8DIsIpRJLW0ODc9t9hQrzgxt7g0L10vOT93EyMwkrYd+7l5 B+OljcGHGAU4GJV4eB/YXogRYk0sK67MPcQowcGsJMKb+OxcjBBvSmJlVWpRfnxRaU5q8SFG U6CjJjJLiSbnA6M8ryTe0NTQ3MLS0NzY3NjMQkmct0PgYIyQQHpiSWp2ampBahFMHxMHp1QD o+AEvgOd7mYz3LxuFKhN0Ljme+VTsVy65+63fqdsvBYJee052pYVV2qjmvx76u1Flqu4V/8+ dePLMt/5yx6LnctdX3hnLYvb68fyU5Te9j15nHy96N/sd6wyn9f+73n9bu5JLe4nu275mr2Z dfW7RUaILRPnRpF7bdstF3NGK7d+YxDzidx84pISS3FGoqEWc1FxIgAgNvkTugIAAA== X-CMS-MailID: 20190506151219eucas1p2feab00f7b7c1c5fdd5614423fb38eae2 X-Msg-Generator: CA X-RootMTR: 20190506151219eucas1p2feab00f7b7c1c5fdd5614423fb38eae2 X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20190506151219eucas1p2feab00f7b7c1c5fdd5614423fb38eae2 References: <1557155521-30949-1-git-send-email-l.luba@partner.samsung.com> Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP In order get the clock by phandle and use it with regmap it needs to be compatible with syscon. The DMC driver uses two registers from clock register set and needs the regmap of them. Signed-off-by: Lukasz Luba --- arch/arm/boot/dts/exynos5800.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/exynos5800.dtsi b/arch/arm/boot/dts/exynos5800.dtsi index 57d3b31..0a2b328 100644 --- a/arch/arm/boot/dts/exynos5800.dtsi +++ b/arch/arm/boot/dts/exynos5800.dtsi @@ -17,7 +17,7 @@ }; &clock { - compatible = "samsung,exynos5800-clock"; + compatible = "samsung,exynos5800-clock", "syscon"; }; &cluster_a15_opp_table { From patchwork Mon May 6 15:12:00 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lukasz Luba X-Patchwork-Id: 10931281 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id B1E81912 for ; Mon, 6 May 2019 15:12:53 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 9FB3A205AD for ; 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Mon, 6 May 2019 15:12:19 +0000 (GMT) Received: from eusmgms2.samsung.com (unknown [182.198.249.180]) by eusmtrp2.samsung.com (KnoxPortal) with ESMTP id 20190506151219eusmtrp2a4b018adb61f9eda2f86d9333f1a7d95~cILaWe1g90466604666eusmtrp2C; Mon, 6 May 2019 15:12:19 +0000 (GMT) X-AuditID: cbfec7f4-113ff70000001119-8e-5cd04ed4b2d0 Received: from eusmtip1.samsung.com ( [203.254.199.221]) by eusmgms2.samsung.com (EUCPMTA) with SMTP id A6.4B.04140.3DE40DC5; Mon, 6 May 2019 16:12:19 +0100 (BST) Received: from AMDC3778.DIGITAL.local (unknown [106.120.51.20]) by eusmtip1.samsung.com (KnoxPortal) with ESMTPA id 20190506151218eusmtip1cf33cb301b625102f58e232a9b8f3396~cILZmE7Ka0071300713eusmtip1R; Mon, 6 May 2019 15:12:18 +0000 (GMT) From: Lukasz Luba To: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-samsung-soc@vger.kernel.org Cc: b.zolnierkie@samsung.com, krzk@kernel.org, kgene@kernel.org, cw00.choi@samsung.com, kyungmin.park@samsung.com, m.szyprowski@samsung.com, s.nawrocki@samsung.com, myungjoo.ham@samsung.com, keescook@chromium.org, tony@atomide.com, jroedel@suse.de, treding@nvidia.com, digetx@gmail.com, willy.mh.wolff.ml@gmail.com, Lukasz Luba Subject: [PATCH v7 12/13] ARM: dts: exynos: add DMC device for exynos5422 Date: Mon, 6 May 2019 17:12:00 +0200 Message-Id: <1557155521-30949-13-git-send-email-l.luba@partner.samsung.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1557155521-30949-1-git-send-email-l.luba@partner.samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA0WSWUwTURSGvZ12ZtpQMhYiN0BQm2hwAzE+3EQkQHwYMTEYfRAl0QoTFlvA Djs8VAgIFCyCYZXFYAIWCVvDFgOBIiAIFAQBAYMQxCCgLCKLqJQp8e3k/79z/nNuLolJ9AJr MiAolFEGyeRSXMSv69jsPzN01eB9Nu+tNarOqRSgkbU5ASpq7xOg8uUZgDK7C3jonVqBNDPf MNTfX0Wg3rgFAn1U2aL3Tc9wtJrWDlBOfzMPVbRPEmj8YRmO9AuPBKhlyAONb5uj9a5p4GpB r//M4NP5qgE+3Zg3SdA12mScTotfwunWpdc8+rFOC+janhh6tcbOU3hL5OzLyAPCGaWjy12R /2xRWEiOW+TOiBZTgRmnFCAkIXUeJhTreClAREqoMgDX6rsFRkNCrQGYkBrIGasAJtYuY/sd c7p6goNKAWwddOKg3YaB7BI8BZAkTjnABu0DI2NJxcCJkRbMyGDUAg/2bm3wjYYFdRlu6JP2 0vjUMTg6Nrw3VExdgS9zn+JcmB0c60veCxbu6jtJbcA4CFKfCNj9QUNw0CU4q241bWcB5zt1 Jt0W/m0s4nE1C1VpzwFXx8IZTYGJuQD1nQMC49IYdQJWNjlyshus6BveuwVS5nB08aBRxnbL jLpsjJPFMClRwtH2UJdqMAUdgqWvskzDaRhXXgy45ykE8HNWIZEODuf9DysGQAusmDBW4cew 54KYCAdWpmDDgvwcfIIVNWD3a/X86VxrAE2/77UBigRSM3G6u8FbIpCFs1GKNgBJTGopln3p 85aIfWVR0Ywy+I4yTM6wbcCG5EutxDEHpm5LKD9ZKHOfYUIY5b7LI4XWKpC7STjfFAXazHvg 9ga18qKrZ/Tpkl6NOvL4UsdXny15R3WovPWoOqVxNi3WtSsqtOuU+5FYr6k4NmKz3Wb8icRq siSjseuFh+XWtpdhSli5/GYlv2TcrNl9JbPpR0dV943BX5NyzfS1ic6JKaLQJul64OK8iz47 zje+Tvh9NaNBymf9ZU4nMSUr+wd7tpvMVgMAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrOIsWRmVeSWpSXmKPExsVy+t/xu7qX/S7EGOzv0rbYOGM9q8X1L89Z LeYfOcdqsfrjY0aLyafmMlmc6c616H/8mtni/PkN7BZnm96wW9xqkLG4vGsOm8Xn3iOMFjPO 72OyWHvkLrvF7cYVbBaH37SzWuy/4mVx+zefxbcTjxgdhD2+fZ3E4jG74SKLx85Zd9k9Nq3q ZPPobX7H5nHw3R4mj74tqxg9Np+u9vi8SS6AM0rPpii/tCRVISO/uMRWKdrQwkjP0NJCz8jE Us/Q2DzWyshUSd/OJiU1J7MstUjfLkEv4+n80oIZjhV/r69ibmB8bNjFyMkhIWAi8XzLdvYu Ri4OIYGljBKTZzQwQSTEJCbtA0mA2MISf651sUEUfWKUuNe1hLGLkYODTUBPYseqQpAaEYF6 if43l8BqmAUamCXWbL/KCpIQFvCU+HG4A8xmEVCVuHHzKthQXgFviZUzp7BBLJCTuHmukxnE 5gSK/+04xAhiCwl4Sez7+JtlAiPfAkaGVYwiqaXFuem5xUZ6xYm5xaV56XrJ+bmbGIGRtO3Y zy07GLveBR9iFOBgVOLhfWB7IUaINbGsuDL3EKMEB7OSCG/is3MxQrwpiZVVqUX58UWlOanF hxhNgY6ayCwlmpwPjPK8knhDU0NzC0tDc2NzYzMLJXHeDoGDMUIC6YklqdmpqQWpRTB9TByc Ug2Mh/u2BsrcPbZ0c/ezxIBvr33eKMW5bBOavGOBoKpE3nKHOzpbj5w9pGFUsE+zkCeiSO+3 yeTzk+LEA5TmxuetnvynQvxoYdvXpdJ7Amu+Ve0Ij7Dy3XfqXgu/TtMNubsZ66c8Wtl9RPdm 8IWaxKib+mKHPuorMwo6llyeW1ZyuUffx2ziuT3RSizFGYmGWsxFxYkABZtspboCAAA= X-CMS-MailID: 20190506151219eucas1p2b5c3368873696f51e7d0d3a3e6d6bf1e X-Msg-Generator: CA X-RootMTR: 20190506151219eucas1p2b5c3368873696f51e7d0d3a3e6d6bf1e X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20190506151219eucas1p2b5c3368873696f51e7d0d3a3e6d6bf1e References: <1557155521-30949-1-git-send-email-l.luba@partner.samsung.com> Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add description of Dynamic Memory Controller and PPMU counters. They are used by exynos5422-dmc driver. There is a definition of the memory chip, which is then used during calculation of timings for each OPP. The algorithm in the driver needs these two sets to bound the timings. Signed-off-by: Lukasz Luba --- arch/arm/boot/dts/exynos5420.dtsi | 121 +++++++++++++++++++++++++ arch/arm/boot/dts/exynos5422-odroid-core.dtsi | 122 ++++++++++++++++++++++++++ 2 files changed, 243 insertions(+) diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi index aaff158..1b66601 100644 --- a/arch/arm/boot/dts/exynos5420.dtsi +++ b/arch/arm/boot/dts/exynos5420.dtsi @@ -14,6 +14,7 @@ #include #include #include +#include / { compatible = "samsung,exynos5420", "samsung,exynos5"; @@ -235,6 +236,38 @@ status = "disabled"; }; + dmc: memory-controller@10c20000 { + compatible = "samsung,exynos5422-dmc"; + reg = <0x10c20000 0x100>, <0x10c30000 0x100>; + clocks = <&clock CLK_FOUT_SPLL>, + <&clock CLK_MOUT_SCLK_SPLL>, + <&clock CLK_FF_DOUT_SPLL2>, + <&clock CLK_FOUT_BPLL>, + <&clock CLK_MOUT_BPLL>, + <&clock CLK_SCLK_BPLL>, + <&clock CLK_MOUT_MX_MSPLL_CCORE>, + <&clock CLK_MOUT_MX_MSPLL_CCORE_PHY>, + <&clock CLK_MOUT_MCLK_CDREX>, + <&clock CLK_DOUT_CLK2X_PHY0>, + <&clock CLK_CLKM_PHY0>, + <&clock CLK_CLKM_PHY1>; + clock-names = "fout_spll", + "mout_sclk_spll", + "ff_dout_spll2", + "fout_bpll", + "mout_bpll", + "sclk_bpll", + "mout_mx_mspll_ccore", + "mout_mx_mspll_ccore_phy", + "mout_mclk_cdrex", + "dout_clk2x_phy0", + "clkm_phy0", + "clkm_phy1"; + samsung,syscon-clk = <&clock>; + samsung,syscon-chipid = <&chipid>; + status = "disabled"; + }; + nocp_mem0_0: nocp@10ca1000 { compatible = "samsung,exynos5420-nocp"; reg = <0x10CA1000 0x200>; @@ -271,6 +304,94 @@ status = "disabled"; }; + ppmu_dmc0_0: ppmu@10d00000 { + compatible = "samsung,exynos-ppmu"; + reg = <0x10d00000 0x2000>; + clocks = <&clock CLK_PCLK_PPMU_DREX0_0>; + clock-names = "ppmu"; + events { + ppmu_event0_dmc0_0: ppmu-event0-dmc0_0 { + event-name = "ppmu-event0-dmc0_0"; + event-data-type = ; + }; + ppmu_event1_dmc0_0: ppmu-event1-dmc0_0 { + event-name = "ppmu-event1-dmc0_0"; + event-data-type = ; + }; + ppmu_event3_dmc0_0: ppmu-event3-dmc0_0 { + event-name = "ppmu-event3-dmc0_0"; + event-data-type = <(PPMU_RO_DATA_CNT | + PPMU_WO_DATA_CNT)>; + }; + }; + }; + + ppmu_dmc0_1: ppmu@10d10000 { + compatible = "samsung,exynos-ppmu"; + reg = <0x10d10000 0x2000>; + clocks = <&clock CLK_PCLK_PPMU_DREX0_1>; + clock-names = "ppmu"; + events { + ppmu_event0_dmc0_1: ppmu-event0-dmc0_1 { + event-name = "ppmu-event0-dmc0_1"; + event-data-type = ; + }; + ppmu_event1_dmc0_1: ppmu-event1-dmc0_1 { + event-name = "ppmu-event1-dmc0_1"; + event-data-type = ; + }; + ppmu_event3_dmc0_1: ppmu-event3-dmc0_1 { + event-name = "ppmu-event3-dmc0_1"; + event-data-type = <(PPMU_RO_DATA_CNT | + PPMU_WO_DATA_CNT)>; + }; + }; + }; + + ppmu_dmc1_0: ppmu@10d60000 { + compatible = "samsung,exynos-ppmu"; + reg = <0x10d60000 0x2000>; + clocks = <&clock CLK_PCLK_PPMU_DREX1_0>; + clock-names = "ppmu"; + events { + ppmu_event0_dmc1_0: ppmu-event0-dmc1_0 { + event-name = "ppmu-event0-dmc1_0"; + event-data-type = ; + }; + ppmu_event1_dmc1_0: ppmu-event1-dmc1_0 { + event-name = "ppmu-event1-dmc1_0"; + event-data-type = ; + }; + ppmu_event3_dmc1_0: ppmu-event3-dmc1_0 { + event-name = "ppmu-event3-dmc1_0"; + event-data-type = <(PPMU_RO_DATA_CNT | + PPMU_WO_DATA_CNT)>; + }; + }; + }; + + ppmu_dmc1_1: ppmu@10d70000 { + compatible = "samsung,exynos-ppmu"; + reg = <0x10d70000 0x2000>; + clocks = <&clock CLK_PCLK_PPMU_DREX1_1>; + clock-names = "ppmu"; + events { + ppmu_event0_dmc1_1: ppmu-event0-dmc1_1 { + event-name = "ppmu-event0-dmc1_1"; + event-data-type = ; + }; + ppmu_event1_dmc1_1: ppmu-event1-dmc1_1 { + event-name = "ppmu-event1-dmc1_1"; + event-data-type = ; + }; + ppmu_event3_dmc1_1: ppmu-event3-dmc1_1 { + event-name = "ppmu-event3-dmc1_1"; + event-data-type = <(PPMU_RO_DATA_CNT | + PPMU_WO_DATA_CNT)>; + }; + }; + }; + gsc_pd: power-domain@10044000 { compatible = "samsung,exynos4210-pd"; reg = <0x10044000 0x20>; diff --git a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi index 25d95de1..76abf03 100644 --- a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi +++ b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi @@ -34,6 +34,97 @@ clock-frequency = <24000000>; }; }; + + dmc_opp_table: opp_table2 { + compatible = "operating-points-v2"; + + opp00 { + opp-hz = /bits/ 64 <165000000>; + opp-microvolt = <875000>; + }; + opp01 { + opp-hz = /bits/ 64 <206000000>; + opp-microvolt = <875000>; + }; + opp02 { + opp-hz = /bits/ 64 <275000000>; + opp-microvolt = <875000>; + }; + opp03 { + opp-hz = /bits/ 64 <413000000>; + opp-microvolt = <887500>; + }; + opp04 { + opp-hz = /bits/ 64 <543000000>; + opp-microvolt = <937500>; + }; + opp05 { + opp-hz = /bits/ 64 <633000000>; + opp-microvolt = <1012500>; + }; + opp06 { + opp-hz = /bits/ 64 <728000000>; + opp-microvolt = <1037500>; + }; + opp07 { + opp-hz = /bits/ 64 <825000000>; + opp-microvolt = <1050000>; + }; + }; + + samsung_K3QF2F20DB: lpddr3 { + compatible = "Samsung,K3QF2F20DB", "jedec,lpddr3"; + density = <16384>; + io-width = <32>; + #address-cells = <1>; + #size-cells = <0>; + + tRFC-min-tck = <17>; + tRRD-min-tck = <2>; + tRPab-min-tck = <2>; + tRPpb-min-tck = <2>; + tRCD-min-tck = <3>; + tRC-min-tck = <6>; + tRAS-min-tck = <5>; + tWTR-min-tck = <2>; + tWR-min-tck = <7>; + tRTP-min-tck = <2>; + tW2W-C2C-min-tck = <0>; + tR2R-C2C-min-tck = <0>; + tWL-min-tck = <8>; + tDQSCK-min-tck = <5>; + tRL-min-tck = <14>; + tFAW-min-tck = <5>; + tXSR-min-tck = <12>; + tXP-min-tck = <2>; + tCKE-min-tck = <2>; + tCKESR-min-tck = <2>; + tMRD-min-tck = <5>; + + timings_samsung_K3QF2F20DB_800mhz: lpddr3-timings@0 { + compatible = "jedec,lpddr3-timings"; + reg = <800000000>; /* workaround: it shows max-freq */ + min-freq = <100000000>; + tRFC = <65000>; + tRRD = <6000>; + tRPab = <12000>; + tRPpb = <12000>; + tRCD = <10000>; + tRC = <33750>; + tRAS = <23000>; + tWTR = <3750>; + tWR = <7500>; + tRTP = <3750>; + tW2W-C2C = <0>; + tR2R-C2C = <0>; + tFAW = <25000>; + tXSR = <70000>; + tXP = <3750>; + tCKE = <3750>; + tCKESR = <3750>; + tMRD = <7000>; + }; + }; }; &adc { @@ -132,6 +223,21 @@ cpu-supply = <&buck2_reg>; }; +&dmc { + devfreq-events = <&ppmu_event0_dmc0_0>, <&ppmu_event1_dmc0_0>, + <&ppmu_event3_dmc0_0>, + <&ppmu_event0_dmc0_1>,<&ppmu_event1_dmc0_1>, + <&ppmu_event3_dmc0_1>, + <&ppmu_event0_dmc1_0>, <&ppmu_event1_dmc1_0>, + <&ppmu_event3_dmc1_0>, + <&ppmu_event0_dmc1_1>,<&ppmu_event1_dmc1_1>, + <&ppmu_event3_dmc1_1>; + device-handle = <&samsung_K3QF2F20DB>; + operating-points-v2 = <&dmc_opp_table>; + vdd-supply = <&buck1_reg>; + status = "okay"; +}; + &hsi2c_4 { status = "okay"; @@ -540,6 +646,22 @@ }; }; +&ppmu_dmc0_0 { + status = "okay"; +}; + +&ppmu_dmc0_1 { + status = "okay"; +}; + +&ppmu_dmc1_0 { + status = "okay"; +}; + +&ppmu_dmc1_1 { + status = "okay"; +}; + &tmu_cpu0 { vtmu-supply = <&ldo7_reg>; }; From patchwork Mon May 6 15:12:01 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lukasz Luba X-Patchwork-Id: 10931277 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id EB65D912 for ; Mon, 6 May 2019 15:12:46 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id DB3F826E69 for ; Mon, 6 May 2019 15:12:46 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id CF050287D3; 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Mon, 6 May 2019 15:12:20 +0000 (GMT) Received: from eusmgms2.samsung.com (unknown [182.198.249.180]) by eusmtrp2.samsung.com (KnoxPortal) with ESMTP id 20190506151220eusmtrp252f6bb72edeeb979e0d41df8943bc6a7~cILbMNsGG0466604666eusmtrp2G; Mon, 6 May 2019 15:12:20 +0000 (GMT) X-AuditID: cbfec7f4-12dff70000001119-8f-5cd04ed57c8d Received: from eusmtip1.samsung.com ( [203.254.199.221]) by eusmgms2.samsung.com (EUCPMTA) with SMTP id 08.4B.04140.4DE40DC5; Mon, 6 May 2019 16:12:20 +0100 (BST) Received: from AMDC3778.DIGITAL.local (unknown [106.120.51.20]) by eusmtip1.samsung.com (KnoxPortal) with ESMTPA id 20190506151219eusmtip159b84e00dfbff6cfab9b019c8653957e~cILaWzORs3138931389eusmtip13; Mon, 6 May 2019 15:12:19 +0000 (GMT) From: Lukasz Luba To: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-samsung-soc@vger.kernel.org Cc: b.zolnierkie@samsung.com, krzk@kernel.org, kgene@kernel.org, cw00.choi@samsung.com, kyungmin.park@samsung.com, m.szyprowski@samsung.com, s.nawrocki@samsung.com, myungjoo.ham@samsung.com, keescook@chromium.org, tony@atomide.com, jroedel@suse.de, treding@nvidia.com, digetx@gmail.com, willy.mh.wolff.ml@gmail.com, Lukasz Luba Subject: [PATCH v7 13/13] ARM: exynos_defconfig: enable DMC driver Date: Mon, 6 May 2019 17:12:01 +0200 Message-Id: <1557155521-30949-14-git-send-email-l.luba@partner.samsung.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1557155521-30949-1-git-send-email-l.luba@partner.samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA0WSaUwTQRiGnT3aBS1ZlypDNZBUMS2J4BknAS/UZNVEMcYYAcGqKyAUsMuh 4o8qyI0QSARUDn8oWFSkIEc9aQnIUW6jgiQiUROsBMIRxZNlIf575p3n+95kMhTOmEkFFRoR zekiNOFKiT1R0/SjY+3rA10B6yxNTqgyv4JEbya/kKi4sYNE5ePDAOW2FmKoPV2Lsoa/4qiz 85EUWa/YpKhfvxL1mm5J0ERmI0D5nc8x9KBxUIoGLpdJkMWWTKIXffvQwE8HNP3qI9jhyE5P 5RDsTX03wdbfGJSyRkOqhM1MGJWwDaNPMfZatQGwVW3x7ITRxdfOz977NBceGsvpPLedsA9p zTgc9Yk8X/09hdCDdDIN2FGQ3gTNd2qJNGBPMXQZgCkvb2LiYRLAzME0qWAx9ASAOQUeCxMF d/PmpVIAkx6aCFGanShvCUsDFCWhPWCd4ZwQy+l4+P7NC1zwcdqGQevM9znfkfaBVXU/MIEJ 2g3m37s+xzJ6P+x7NkWIZS7wXUcqLrDdbP47xQyERZDul8KRJ0OEUAbp3VCfKBd9RzjSXC0V eSX8W1+MicxDfeZtIPIlOJxVOO94QUtzNymswWk1rDB5ivFOaG23AnG7A3z7bakQ47OYU5OH i7EMpiQxoq2C1Rld80XLYen96/PLWfg6IUkivlQRgPWmEiIbuN74X1YCgAE4cTG8NpjjN0Rw cR68RsvHRAR7nIrUGsHsz2r70zxZB0y/TpoBTQHlElm2T1cAQ2pi+QtaM4AUrpTLNJ87AhjZ ac2Fi5wuMkgXE87xZrCCIpROsvhFH/wZOlgTzYVxXBSnW7jFKDuFHux1mXm86siI81FV8Jr6 za7qKkODOsBz6Ng405ju7X/IEq+K7a+Z0m3F8tWvzi4+vkdx0G/7mdE1UYxfS1xPoG/ZyLjX /cChscTkNreCih1Vxl3ysXJVj3uRJNfBed8yxdWNBv+cwdogH1vpTHJbU4N3b3Zvf21lT+Lq gS2259O9CiXBh2jWu+M6XvMP6SBQLVUDAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrOIsWRmVeSWpSXmKPExsVy+t/xu7pX/C7EGOy7qWixccZ6VovrX56z Wsw/co7VYvXHx4wWk0/NZbI4051r0f/4NbPF+fMb2C3ONr1ht7jVIGNxedccNovPvUcYLWac 38dksfbIXXaL240r2CwOv2lntdh/xcvi9m8+i28nHjE6CHt8+zqJxWN2w0UWj52z7rJ7bFrV yebR2/yOzePguz1MHn1bVjF6bD5d7fF5k1wAZ5SeTVF+aUmqQkZ+cYmtUrShhZGeoaWFnpGJ pZ6hsXmslZGpkr6dTUpqTmZZapG+XYJexqme4IKnrBVbfnSwNDB2s3YxcnJICJhIzFw2namL kYtDSGApo8S1nhaohJjEpH3b2SFsYYk/17rYIIo+MUo8a/sF1MHBwSagJ7FjVSFIjYhAvUT/ m0tgNcwCDcwSa7ZfBRskLOAksXnHTyYQm0VAVWLGymlgNq+At8SVvV9ZIBbISdw818kMYnMC xf92HGIEsYUEvCT2ffzNMoGRbwEjwypGkdTS4tz03GIjveLE3OLSvHS95PzcTYzASNp27OeW HYxd74IPMQpwMCrx8D6wvRAjxJpYVlyZe4hRgoNZSYQ38dm5GCHelMTKqtSi/Pii0pzU4kOM pkBHTWSWEk3OB0Z5Xkm8oamhuYWlobmxubGZhZI4b4fAwRghgfTEktTs1NSC1CKYPiYOTqkG xgnXz8rfN7llarElcK0Ky7LIg0UXg5JZsiu5/Xy7Q02Ct2dNOP7hT4Ari5bGgYUVzj3ZwZU6 bb1vv4Zk/9r7+3n8DIvJ63okP307Ixg+9b7ygknHlDnuaRWJnxbb87roTUBmj3n9lccL0pNC wrWzcydo7XpjcH+bsYTF+z+7j3j2ZshundOsoMRSnJFoqMVcVJwIAFAUA6a6AgAA X-CMS-MailID: 20190506151220eucas1p237812f2420594eb651d80cf91076510c X-Msg-Generator: CA X-RootMTR: 20190506151220eucas1p237812f2420594eb651d80cf91076510c X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20190506151220eucas1p237812f2420594eb651d80cf91076510c References: <1557155521-30949-1-git-send-email-l.luba@partner.samsung.com> Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Enable driver for Exynos5422 Dynamic Memory Controller supporting dynamic frequency and voltage scaling in Exynos5422 SoCs. Signed-off-by: Lukasz Luba --- arch/arm/configs/exynos_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/configs/exynos_defconfig b/arch/arm/configs/exynos_defconfig index d635edf..04c076e 100644 --- a/arch/arm/configs/exynos_defconfig +++ b/arch/arm/configs/exynos_defconfig @@ -291,6 +291,7 @@ CONFIG_DEVFREQ_GOV_PERFORMANCE=y CONFIG_DEVFREQ_GOV_POWERSAVE=y CONFIG_DEVFREQ_GOV_USERSPACE=y CONFIG_ARM_EXYNOS_BUS_DEVFREQ=y +CONFIG_ARM_EXYNOS5422_DMC=y CONFIG_DEVFREQ_EVENT_EXYNOS_NOCP=y CONFIG_EXYNOS_IOMMU=y CONFIG_EXTCON=y