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Thu, 16 May 2019 00:04:48 -0700 Received: from saturn.analog.com (10.50.1.244) by NWD2HUBCAS7.ad.analog.com (10.64.69.107) with Microsoft SMTP Server id 14.3.408.0; Thu, 16 May 2019 03:04:47 -0400 From: Alexandru Ardelean To: CC: Dragos Bogdan , Alexandru Ardelean Subject: [PATCH] dmaengine: axi-dmac: Add support for interleaved cyclic transfers Date: Thu, 16 May 2019 10:04:43 +0300 Message-ID: <20190516070443.16219-1-alexandru.ardelean@analog.com> X-Mailer: git-send-email 2.17.1 MIME-Version: 1.0 X-ADIRoutedOnPrem: True X-EOPAttributedMessage: 0 X-MS-Office365-Filtering-HT: Tenant X-Forefront-Antispam-Report: CIP:137.71.25.55;IPV:NLI;CTRY:US;EFV:NLI;SFV:NSPM;SFS:(10009020)(346002)(396003)(376002)(39860400002)(136003)(2980300002)(199004)(189003)(47776003)(2616005)(476003)(486006)(70586007)(86362001)(126002)(36756003)(50466002)(53416004)(77096007)(8676002)(26005)(186003)(246002)(7636002)(305945005)(107886003)(51416003)(48376002)(5660300002)(8936002)(44832011)(356004)(6666004)(6916009)(50226002)(7696005)(316002)(2906002)(478600001)(4326008)(106002)(16586007)(70206006)(1076003)(426003)(336012)(2351001)(54906003);DIR:OUT;SFP:1101;SCL:1;SRVR:BLUPR03MB549;H:nwd2mta1.analog.com;FPR:;SPF:Pass;LANG:en;PTR:nwd2mail10.analog.com;A:1;MX:1; X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 14b7ba8b-7d3d-4761-4047-08d6d9ccc919 X-Microsoft-Antispam: BCL:0;PCL:0;RULEID:(2390118)(7020095)(4652040)(8989299)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(5600141)(711020)(4605104)(4709054)(2017052603328);SRVR:BLUPR03MB549; X-MS-TrafficTypeDiagnostic: BLUPR03MB549: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:6790; X-Forefront-PRVS: 0039C6E5C5 X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam-Message-Info: qXnkm/gjxTPSz+DZ7qOHzsxRzO05hjWgHDBtlEA/Mv+/WEW98dW70IHCV8Ox79pYoZfIBvLZ5rI4ZNCGNhMtuDqKIrfBz6N4PF7vzQTVUQTbRsLTH3hOjAAuhNxn2BqbuNqjK73h6NP/+SaGPG875dDcwqLFXGccyyZZvgWnGBZX8wE5SECQKo/XiXiLfGDQPGCDWZm1ptjIr1ztl78KlRycooPkyFWt+kitV94IUAcQ4QQD0QD1Y8fmjq57ePM3ZJKZCy8UGmCiWIJ5y/b+rxMyAaXo3hS7kPZB9tbZB/Vro3R20UH88fnzjToCUHQYVqN3LcpRXQ5cR+8xUCl14vvPTjqTGEck9M+pJdVPPgo8h6dJU5v4b7rQjqCc+w+ClPG7gK548r/NxSNrDVwzPPAa9bWjV9domsIeIZGGWTc= X-OriginatorOrg: analog.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 May 2019 07:04:48.9014 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 14b7ba8b-7d3d-4761-4047-08d6d9ccc919 X-MS-Exchange-CrossTenant-Id: eaa689b4-8f87-40e0-9c6f-7228de4d754a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=eaa689b4-8f87-40e0-9c6f-7228de4d754a;Ip=[137.71.25.55];Helo=[nwd2mta1.analog.com] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BLUPR03MB549 Sender: dmaengine-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: dmaengine@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Dragos Bogdan The DMAC HDL core supports interleaved & cyclic transfers. An example use-case for this mode is when the controller is used as a video DMA. This change sets the `cyclic` field to true, so that when the IRQ comes and the `axi_dmac_transfer_done()` callback is called (from the interrupt handler) the proper `vchan_cyclic_callback()` is called. This way the DMAEngine framework will process data correctly for interleaved + cyclic transfers. This doesn't fix anything. It's an enhancement to the driver. Signed-off-by: Dragos Bogdan Signed-off-by: Alexandru Ardelean --- drivers/dma/dma-axi-dmac.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/dma/dma-axi-dmac.c b/drivers/dma/dma-axi-dmac.c index f32fdf21edbd..4d2cae0bebb5 100644 --- a/drivers/dma/dma-axi-dmac.c +++ b/drivers/dma/dma-axi-dmac.c @@ -562,6 +562,9 @@ static struct dma_async_tx_descriptor *axi_dmac_prep_interleaved( desc->sg[0].y_len = 1; } + if (flags & DMA_CYCLIC) + desc->cyclic = true; + return vchan_tx_prep(&chan->vchan, &desc->vdesc, flags); }