From patchwork Thu May 16 09:08:38 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "andrew-sh.cheng" X-Patchwork-Id: 10946049 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 171841515 for ; Thu, 16 May 2019 09:09:00 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 059FC201F5 for ; Thu, 16 May 2019 09:09:00 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id ECF2A204FD; Thu, 16 May 2019 09:08:59 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED,UNPARSEABLE_RELAY autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 9F66028711 for ; Thu, 16 May 2019 09:08:59 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=d5ii5Pa8CM74knBUGH99PZDKHSxano1OSqkDLPxw0ts=; b=c4bsj2wccUzVk8 LOzP7t8mlviG0dH7gvHGx4c0iCMRDlRfL56DIr3JU3slMfVGdytEPs+WewmfGqpQ9sQa0lSa0hkTR GSPdR4mFn3ASJcaxOW/PnHpasAZGNajFQqgfLIpJkLYmHqf5wAT/Dq5SdoD/Yv61Cq6rixrwo4ZGE Kx/rjQ1q8D7Wz8zDjtdXeZQ1xwUuYSjIj7kbPAxhv7H6swTcJmhty8GGdinLSRB8H4dWmAM3jjsy+ TeGZCwpSRQaDmUE7kf8yUbdKuAtLLALMXs+yzzy3FgHLMx8rKr2yPofEnGnI1tdDUnEGJfxJh05uW uAY4X1VQeKsQC/a0kHAg==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1hRCNm-0000lw-UG; Thu, 16 May 2019 09:08:58 +0000 Received: from mailgw02.mediatek.com ([216.200.240.185]) by bombadil.infradead.org with esmtps (Exim 4.90_1 #2 (Red Hat Linux)) id 1hRCNk-0000kF-EC; Thu, 16 May 2019 09:08:57 +0000 X-UUID: 9787825880404b54852acd1239990df0-20190516 X-UUID: 9787825880404b54852acd1239990df0-20190516 Received: from mtkcas66.mediatek.inc [(172.29.193.44)] by mailgw02.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLS) with ESMTP id 1620524660; Thu, 16 May 2019 01:08:51 -0800 Received: from MTKMBS01N1.mediatek.inc (172.21.101.68) by MTKMBS62DR.mediatek.inc (172.29.94.18) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Thu, 16 May 2019 02:08:49 -0700 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs01n1.mediatek.inc (172.21.101.68) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Thu, 16 May 2019 17:08:48 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Thu, 16 May 2019 17:08:48 +0800 From: Andrew-sh.Cheng To: MyungJoo Ham , Kyungmin Park , Chanwoo Choi , "Rob Herring" , Mark Rutland , "Matthias Brugger" , "Rafael J. Wysocki" , Viresh Kumar , Nishanth Menon , "Stephen Boyd" Subject: [PATCH 1/8] cpufreq: mediatek: change to regulator_get_optional Date: Thu, 16 May 2019 17:08:38 +0800 Message-ID: <1557997725-12178-2-git-send-email-andrew-sh.cheng@mediatek.com> X-Mailer: git-send-email 1.8.1.1.dirty In-Reply-To: <1557997725-12178-1-git-send-email-andrew-sh.cheng@mediatek.com> References: <1557997725-12178-1-git-send-email-andrew-sh.cheng@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190516_020856_486571_0CB854BD X-CRM114-Status: GOOD ( 10.75 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, "Andrew-sh.Cheng" , srv_heupstream@mediatek.com, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, fan.chen@mediatek.com, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+patchwork-linux-mediatek=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP From: "Andrew-sh.Cheng" For new mediatek chip mt8183, cci and little cluster share the same buck, so need to modify the attribute of regulator from exclusive to optional Signed-off-by: Andrew-sh.Cheng --- drivers/cpufreq/mediatek-cpufreq.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/cpufreq/mediatek-cpufreq.c b/drivers/cpufreq/mediatek-cpufreq.c index 48e9829274c6..f2464c1ff17c 100644 --- a/drivers/cpufreq/mediatek-cpufreq.c +++ b/drivers/cpufreq/mediatek-cpufreq.c @@ -346,7 +346,7 @@ static int mtk_cpu_dvfs_info_init(struct mtk_cpu_dvfs_info *info, int cpu) goto out_free_resources; } - proc_reg = regulator_get_exclusive(cpu_dev, "proc"); + proc_reg = regulator_get_optional(cpu_dev, "proc"); if (IS_ERR(proc_reg)) { if (PTR_ERR(proc_reg) == -EPROBE_DEFER) pr_warn("proc regulator for cpu%d not ready, retry.\n", From patchwork Thu May 16 09:08:39 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "andrew-sh.cheng" X-Patchwork-Id: 10946079 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 855C214DB for ; Thu, 16 May 2019 09:11:21 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 7444528889 for ; Thu, 16 May 2019 09:11:21 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 68B82288F8; Thu, 16 May 2019 09:11:21 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED,UNPARSEABLE_RELAY autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 16A1228889 for ; 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Thu, 16 May 2019 17:08:49 +0800 From: Andrew-sh.Cheng To: MyungJoo Ham , Kyungmin Park , Chanwoo Choi , "Rob Herring" , Mark Rutland , "Matthias Brugger" , "Rafael J. Wysocki" , Viresh Kumar , Nishanth Menon , "Stephen Boyd" Subject: [PATCH 2/8] cpufreq: mediatek: add clock enable for intermediate clock Date: Thu, 16 May 2019 17:08:39 +0800 Message-ID: <1557997725-12178-3-git-send-email-andrew-sh.cheng@mediatek.com> X-Mailer: git-send-email 1.8.1.1.dirty In-Reply-To: <1557997725-12178-1-git-send-email-andrew-sh.cheng@mediatek.com> References: <1557997725-12178-1-git-send-email-andrew-sh.cheng@mediatek.com> MIME-Version: 1.0 X-TM-SNTS-SMTP: 6F28F1D5E6D5DE97D8C9949A162A499AD158DFFF8FC9560F33C18CF77BA29D212000:8 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190516_021053_165967_98AE86F5 X-CRM114-Status: GOOD ( 11.90 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, "Andrew-sh.Cheng" , srv_heupstream@mediatek.com, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, fan.chen@mediatek.com, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+patchwork-linux-mediatek=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP From: "Andrew-sh.Cheng" Intermediate clock is not always enabled by ccf in different projects, so cpufreq should always enable it by itself. Signed-off-by: Andrew-sh.Cheng --- drivers/cpufreq/mediatek-cpufreq.c | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/drivers/cpufreq/mediatek-cpufreq.c b/drivers/cpufreq/mediatek-cpufreq.c index f2464c1ff17c..b2fc01b17b57 100644 --- a/drivers/cpufreq/mediatek-cpufreq.c +++ b/drivers/cpufreq/mediatek-cpufreq.c @@ -376,13 +376,17 @@ static int mtk_cpu_dvfs_info_init(struct mtk_cpu_dvfs_info *info, int cpu) goto out_free_resources; } + ret = clk_prepare_enable(inter_clk); + if (ret) + goto out_free_opp_table; + /* Search a safe voltage for intermediate frequency. */ rate = clk_get_rate(inter_clk); opp = dev_pm_opp_find_freq_ceil(cpu_dev, &rate); if (IS_ERR(opp)) { pr_err("failed to get intermediate opp for cpu%d\n", cpu); ret = PTR_ERR(opp); - goto out_free_opp_table; + goto out_disable_clock; } info->intermediate_voltage = dev_pm_opp_get_voltage(opp); dev_pm_opp_put(opp); @@ -401,6 +405,9 @@ static int mtk_cpu_dvfs_info_init(struct mtk_cpu_dvfs_info *info, int cpu) return 0; +out_disable_clock: + clk_disable_unprepare(inter_clk); + out_free_opp_table: dev_pm_opp_of_cpumask_remove_table(&info->cpus); @@ -427,6 +434,10 @@ static void mtk_cpu_dvfs_info_release(struct mtk_cpu_dvfs_info *info) clk_put(info->cpu_clk); if (!IS_ERR(info->inter_clk)) clk_put(info->inter_clk); + if (!IS_ERR(info->inter_clk)) { + clk_disable_unprepare(info->inter_clk); + clk_put(info->inter_clk); + } dev_pm_opp_of_cpumask_remove_table(&info->cpus); } From patchwork Thu May 16 09:08:40 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "andrew-sh.cheng" X-Patchwork-Id: 10946071 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 2D57C14DB for ; Thu, 16 May 2019 09:10:56 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 1A42D288AD for ; Thu, 16 May 2019 09:10:56 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 0BC07288C5; Thu, 16 May 2019 09:10:56 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED,UNPARSEABLE_RELAY autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 9E15328893 for ; Thu, 16 May 2019 09:10:55 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=xy5kX4SkYN4FcuIlXmjABgetrtoYYoAIUroNNn2QhZo=; b=bEgPoT8NcD3HdY 776PivAKNERWnRa2WViepGiJNX4gfzTXoAJPyaz767n8EaHQR8POstqMTg6W/yHIiq1weZeym60w8 hb77OiR/W/ws4VidZJXX5U1CL++2HSwU+i2GCm5m3W4q/7Tzeee6GQMKOvrzluf+TYyyuOlldz9VI uL0KCaejJ1l5iWI9mHboPPTh4v2qpCJnP4izk7Bq++jpvln5CXOyDr3jQXFTt6INzDL6tXFr7P1QC UuBxEYStmKDy19FB24XuuFhKMH92H5XO9iWumlLNbUOgyQrghIKUHzDEchgV0y2vj0NpVflYVA99q OVoJhZRMAICv/3s9qX2Q==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1hRCPe-00046K-NA; Thu, 16 May 2019 09:10:54 +0000 Received: from mailgw01.mediatek.com ([216.200.240.184]) by bombadil.infradead.org with esmtps (Exim 4.90_1 #2 (Red Hat Linux)) id 1hRCPX-0003yL-E6; Thu, 16 May 2019 09:10:52 +0000 X-UUID: 27edfcfa7148444ca9322070442b9b12-20190516 X-UUID: 27edfcfa7148444ca9322070442b9b12-20190516 Received: from mtkcas67.mediatek.inc [(172.29.193.45)] by mailgw01.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLS) with ESMTP id 1266198607; Thu, 16 May 2019 01:08:52 -0800 Received: from mtkmbs03n1.mediatek.inc (172.21.101.181) by MTKMBS62DR.mediatek.inc (172.29.94.18) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Thu, 16 May 2019 02:08:51 -0700 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs03n1.mediatek.inc (172.21.101.181) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Thu, 16 May 2019 17:08:50 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Thu, 16 May 2019 17:08:49 +0800 From: Andrew-sh.Cheng To: MyungJoo Ham , Kyungmin Park , Chanwoo Choi , "Rob Herring" , Mark Rutland , "Matthias Brugger" , "Rafael J. Wysocki" , Viresh Kumar , Nishanth Menon , "Stephen Boyd" Subject: [PATCH 3/8] cpufreq: mediatek: Add support for mt8183 Date: Thu, 16 May 2019 17:08:40 +0800 Message-ID: <1557997725-12178-4-git-send-email-andrew-sh.cheng@mediatek.com> X-Mailer: git-send-email 1.8.1.1.dirty In-Reply-To: <1557997725-12178-1-git-send-email-andrew-sh.cheng@mediatek.com> References: <1557997725-12178-1-git-send-email-andrew-sh.cheng@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190516_021048_130849_0B44EC37 X-CRM114-Status: UNSURE ( 9.68 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, "Andrew-sh.Cheng" , srv_heupstream@mediatek.com, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, fan.chen@mediatek.com, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+patchwork-linux-mediatek=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP From: "Andrew-sh.Cheng" Add compatible string for mediatek mt8183 Signed-off-by: Andrew-sh.Cheng --- drivers/cpufreq/cpufreq-dt-platdev.c | 1 + drivers/cpufreq/mediatek-cpufreq.c | 1 + 2 files changed, 2 insertions(+) diff --git a/drivers/cpufreq/cpufreq-dt-platdev.c b/drivers/cpufreq/cpufreq-dt-platdev.c index 47729a22c159..53ea52b1602e 100644 --- a/drivers/cpufreq/cpufreq-dt-platdev.c +++ b/drivers/cpufreq/cpufreq-dt-platdev.c @@ -117,6 +117,7 @@ static const struct of_device_id blacklist[] __initconst = { { .compatible = "mediatek,mt817x", }, { .compatible = "mediatek,mt8173", }, { .compatible = "mediatek,mt8176", }, + { .compatible = "mediatek,mt8183", }, { .compatible = "nvidia,tegra124", }, { .compatible = "nvidia,tegra210", }, diff --git a/drivers/cpufreq/mediatek-cpufreq.c b/drivers/cpufreq/mediatek-cpufreq.c index b2fc01b17b57..022d86757327 100644 --- a/drivers/cpufreq/mediatek-cpufreq.c +++ b/drivers/cpufreq/mediatek-cpufreq.c @@ -554,6 +554,7 @@ static const struct of_device_id mtk_cpufreq_machines[] __initconst = { { .compatible = "mediatek,mt817x", }, { .compatible = "mediatek,mt8173", }, { .compatible = "mediatek,mt8176", }, + { .compatible = "mediatek,mt8183", }, { } }; From patchwork Thu May 16 09:08:41 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "andrew-sh.cheng" X-Patchwork-Id: 10946055 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 886006C5 for ; Thu, 16 May 2019 09:09:24 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 75B2820500 for ; Thu, 16 May 2019 09:09:24 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 69F6628733; Thu, 16 May 2019 09:09:24 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED,UNPARSEABLE_RELAY autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 2133528711 for ; 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Thu, 16 May 2019 17:08:50 +0800 From: Andrew-sh.Cheng To: MyungJoo Ham , Kyungmin Park , Chanwoo Choi , "Rob Herring" , Mark Rutland , "Matthias Brugger" , "Rafael J. Wysocki" , Viresh Kumar , Nishanth Menon , "Stephen Boyd" Subject: [PATCH 4/8] dt-bindings: devfreq: add compatible for mt8183 cci devfreq Date: Thu, 16 May 2019 17:08:41 +0800 Message-ID: <1557997725-12178-5-git-send-email-andrew-sh.cheng@mediatek.com> X-Mailer: git-send-email 1.8.1.1.dirty In-Reply-To: <1557997725-12178-1-git-send-email-andrew-sh.cheng@mediatek.com> References: <1557997725-12178-1-git-send-email-andrew-sh.cheng@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190516_020908_964066_1AB47978 X-CRM114-Status: UNSURE ( 9.83 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, "Andrew-sh.Cheng" , srv_heupstream@mediatek.com, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, fan.chen@mediatek.com, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+patchwork-linux-mediatek=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP From: "Andrew-sh.Cheng" This adds dt-binding documentation of cci devfreq for Mediatek MT8183 SoC platform. Signed-off-by: Andrew-sh.Cheng --- .../bindings/devfreq/mt8183-cci-devfreq.txt | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) create mode 100644 Documentation/devicetree/bindings/devfreq/mt8183-cci-devfreq.txt diff --git a/Documentation/devicetree/bindings/devfreq/mt8183-cci-devfreq.txt b/Documentation/devicetree/bindings/devfreq/mt8183-cci-devfreq.txt new file mode 100644 index 000000000000..3189902902e0 --- /dev/null +++ b/Documentation/devicetree/bindings/devfreq/mt8183-cci-devfreq.txt @@ -0,0 +1,20 @@ +* Mediatek Cache Coherent Interconnect(CCI) frequency device + +Required properties: +- compatible: should contain "mediatek,mt8183-cci" for frequency scaling of CCI +- clocks: for frequency scaling of CCI +- clock-names: for frequency scaling of CCI driver to reference +- regulator: for voltage scaling of CCI +- operating-points-v2: for frequency scaling of CCI opp table + +Example: + cci: cci { + compatible = "mediatek,cci"; + clocks = <&apmixedsys CLK_APMIXED_CCIPLL>; + clock-names = "cci_clock"; + operating-points-v2 = <&cci_opp>; + }; + + &cci { + proc-supply = <&mt6358_vproc12_reg>; + }; \ No newline at end of file From patchwork Thu May 16 09:08:42 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "andrew-sh.cheng" X-Patchwork-Id: 10946063 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 313DF6C5 for ; Thu, 16 May 2019 09:09:54 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 1E4DA201F5 for ; Thu, 16 May 2019 09:09:54 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 129C520500; Thu, 16 May 2019 09:09:54 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED,UNPARSEABLE_RELAY autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 68E31201F5 for ; Thu, 16 May 2019 09:09:53 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=Isn/wELsLqd+Ss/qkv4Z/u7aVkiZypoYJPRrpMoyqNE=; b=Z9r4HP26LAarmz MgP21hMccX3S1VwedB1e1N2TvrnMSZqFym4+wqlEQjNkX0nBMSNW/6LSoKAqH/3w5xTEw7Fzc+rYc t07TC/BxngzJnXira6+OFmQrCqL6Euw0BiafYP6bNqo1UW0qUwwkrA7nbVMOLC1X6OfQRoiWuSSlL 1XOSH5TEBwLt7wK4MRnG4w1ufAAKqM11FGYQKhEby6sIFpe3lDpRpW9XA92WPXRjnLve2JrbcisRf OqWBQ1PWycsr46f3nTzzmr97tHfoMlx1GF7s22tV9ActdjRXlcGXmRTs+JQLAy9Io4APASrkmuIa+ ZYdNFLSR4aZx8yRmohQA==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1hRCOd-0001qZ-Jr; Thu, 16 May 2019 09:09:51 +0000 Received: from mailgw02.mediatek.com ([216.200.240.185]) by bombadil.infradead.org with esmtps (Exim 4.90_1 #2 (Red Hat Linux)) id 1hRCO1-0000xD-3E; Thu, 16 May 2019 09:09:26 +0000 X-UUID: 230a1cc2fcd94d7e9dd63a697e255d68-20190516 X-UUID: 230a1cc2fcd94d7e9dd63a697e255d68-20190516 Received: from mtkcas68.mediatek.inc [(172.29.94.19)] by mailgw02.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLS) with ESMTP id 1855848502; Thu, 16 May 2019 01:09:01 -0800 Received: from MTKMBS02N2.mediatek.inc (172.21.101.101) by MTKMBS62DR.mediatek.inc (172.29.94.18) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Thu, 16 May 2019 02:09:00 -0700 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs02n2.mediatek.inc (172.21.101.101) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Thu, 16 May 2019 17:08:51 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Thu, 16 May 2019 17:08:51 +0800 From: Andrew-sh.Cheng To: MyungJoo Ham , Kyungmin Park , Chanwoo Choi , "Rob Herring" , Mark Rutland , "Matthias Brugger" , "Rafael J. Wysocki" , Viresh Kumar , Nishanth Menon , "Stephen Boyd" Subject: [PATCH 5/8] devfreq: add mediatek cci devfreq Date: Thu, 16 May 2019 17:08:42 +0800 Message-ID: <1557997725-12178-6-git-send-email-andrew-sh.cheng@mediatek.com> X-Mailer: git-send-email 1.8.1.1.dirty In-Reply-To: <1557997725-12178-1-git-send-email-andrew-sh.cheng@mediatek.com> References: <1557997725-12178-1-git-send-email-andrew-sh.cheng@mediatek.com> MIME-Version: 1.0 X-TM-SNTS-SMTP: E9902185452695BACCA4D4D68D1EFBD67C3393E7917808A8569C0D5776023BF92000:8 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190516_020913_819922_3DE63B8D X-CRM114-Status: GOOD ( 18.69 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, "Andrew-sh.Cheng" , srv_heupstream@mediatek.com, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, fan.chen@mediatek.com, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+patchwork-linux-mediatek=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP From: "Andrew-sh.Cheng" This adds a devfreq driver for the Cache Coherent Interconnect (CCI) of the Mediatek MT8183. On the MT8183 the CCI is supplied by the same regulator as the LITTLE cores. The driver is notified when the regulator voltage changes (driven by cpufreq) and adjusts the CCI frequency to the maximum possible value. Signed-off-by: Andrew-sh.Cheng --- drivers/devfreq/Kconfig | 10 ++ drivers/devfreq/Makefile | 1 + drivers/devfreq/mt8183-cci-devfreq.c | 247 +++++++++++++++++++++++++++++++++++ 3 files changed, 258 insertions(+) create mode 100644 drivers/devfreq/mt8183-cci-devfreq.c diff --git a/drivers/devfreq/Kconfig b/drivers/devfreq/Kconfig index 6a172d338f6d..da2f8ec18369 100644 --- a/drivers/devfreq/Kconfig +++ b/drivers/devfreq/Kconfig @@ -91,6 +91,16 @@ config ARM_EXYNOS_BUS_DEVFREQ and adjusts the operating frequencies and voltages with OPP support. This does not yet operate with optimal voltages. +config ARM_MT8183_CCI_DEVFREQ + tristate "MT8183 CCI DEVFREQ Driver" + depends on ARM_MEDIATEK_CPUFREQ + help + This adds a devfreq driver for Cache Coherent Interconnect + of Mediatek MT8183, which is shared the same regulator + with cpu cluster. + It can track buck voltage and update a proper cci frequency. + Use notification to get regulator status. + config ARM_TEGRA_DEVFREQ tristate "Tegra DEVFREQ Driver" depends on ARCH_TEGRA_124_SOC diff --git a/drivers/devfreq/Makefile b/drivers/devfreq/Makefile index 32b8d4d3f12c..817dde779f16 100644 --- a/drivers/devfreq/Makefile +++ b/drivers/devfreq/Makefile @@ -9,6 +9,7 @@ obj-$(CONFIG_DEVFREQ_GOV_PASSIVE) += governor_passive.o # DEVFREQ Drivers obj-$(CONFIG_ARM_EXYNOS_BUS_DEVFREQ) += exynos-bus.o +obj-$(CONFIG_ARM_MT8183_CCI_DEVFREQ) += mt8183-cci-devfreq.o obj-$(CONFIG_ARM_RK3399_DMC_DEVFREQ) += rk3399_dmc.o obj-$(CONFIG_ARM_TEGRA_DEVFREQ) += tegra-devfreq.o diff --git a/drivers/devfreq/mt8183-cci-devfreq.c b/drivers/devfreq/mt8183-cci-devfreq.c new file mode 100644 index 000000000000..818a167c442f --- /dev/null +++ b/drivers/devfreq/mt8183-cci-devfreq.c @@ -0,0 +1,247 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2019 MediaTek Inc. + + * Author: Andrew-sh.Cheng + */ + +#include +#include +#include +#include +#include +#include + +#include "governor.h" + +struct cci_devfreq { + struct devfreq *devfreq; + struct regulator *proc_reg; + unsigned long proc_reg_uV; + struct clk *cci_clk; + struct notifier_block nb; +}; + +static int cci_devfreq_regulator_notifier(struct notifier_block *nb, + unsigned long val, void *data) +{ + int ret; + struct cci_devfreq *cci_df = + container_of(nb, struct cci_devfreq, nb); + + /* deal with reduce frequency */ + if (val & REGULATOR_EVENT_PRE_VOLTAGE_CHANGE) { + struct pre_voltage_change_data *pvc_data = data; + + if (pvc_data->min_uV < pvc_data->old_uV) { + cci_df->proc_reg_uV = + (unsigned long)(pvc_data->min_uV); + mutex_lock(&cci_df->devfreq->lock); + ret = update_devfreq(cci_df->devfreq); + if (ret) + pr_err("Fail to reduce cci frequency: %d\n", + ret); + mutex_unlock(&cci_df->devfreq->lock); + } + } else if ((val & REGULATOR_EVENT_ABORT_VOLTAGE_CHANGE) && + ((unsigned long)data > cci_df->proc_reg_uV)) { + cci_df->proc_reg_uV = (unsigned long)data; + mutex_lock(&cci_df->devfreq->lock); + ret = update_devfreq(cci_df->devfreq); + if (ret) + pr_err("Fail to raise cci frequency back: %d\n", ret); + mutex_unlock(&cci_df->devfreq->lock); + } else if ((val & REGULATOR_EVENT_VOLTAGE_CHANGE) && + (cci_df->proc_reg_uV < (unsigned long)data)) { + /* deal with increase frequency */ + cci_df->proc_reg_uV = (unsigned long)data; + mutex_lock(&cci_df->devfreq->lock); + ret = update_devfreq(cci_df->devfreq); + if (ret) + pr_err("Fail to raise cci frequency: %d\n", ret); + mutex_unlock(&cci_df->devfreq->lock); + } + + return 0; +} + +static int mtk_cci_governor_get_target(struct devfreq *devfreq, + unsigned long *freq) +{ + struct cci_devfreq *cci_df; + struct dev_pm_opp *opp; + + cci_df = dev_get_drvdata(devfreq->dev.parent); + + /* find available frequency */ + opp = dev_pm_opp_find_freq_ceil_by_volt(devfreq->dev.parent, + cci_df->proc_reg_uV); + *freq = dev_pm_opp_get_freq(opp); + + return 0; +} + +static int mtk_cci_governor_event_handler(struct devfreq *devfreq, + unsigned int event, void *data) +{ + int ret; + struct cci_devfreq *cci_df; + struct notifier_block *nb; + + cci_df = dev_get_drvdata(devfreq->dev.parent); + nb = &cci_df->nb; + + switch (event) { + case DEVFREQ_GOV_START: + case DEVFREQ_GOV_RESUME: + nb->notifier_call = cci_devfreq_regulator_notifier; + ret = regulator_register_notifier(cci_df->proc_reg, + nb); + if (ret) + pr_err("%s: failed to add governor: %d\n", __func__, + ret); + break; + + case DEVFREQ_GOV_STOP: + case DEVFREQ_GOV_SUSPEND: + ret = regulator_unregister_notifier(cci_df->proc_reg, + nb); + if (ret) + pr_err("%s: failed to add governor: %d\n", __func__, + ret); + break; + + default: + break; + } + + return 0; +} + +static struct devfreq_governor mtk_cci_devfreq_governor = { + .name = "mtk_cci_vmon", + .get_target_freq = mtk_cci_governor_get_target, + .event_handler = mtk_cci_governor_event_handler, + .immutable = true +}; + +static int mtk_cci_devfreq_target(struct device *dev, unsigned long *freq, + u32 flags) +{ + int ret; + struct cci_devfreq *cci_df = dev_get_drvdata(dev); + + if (!cci_df) + return -EINVAL; + + ret = clk_set_rate(cci_df->cci_clk, *freq); + if (ret) { + pr_err("%s: failed cci to set rate: %d\n", __func__, + ret); + return ret; + } + + return 0; +} + +static struct devfreq_dev_profile cci_devfreq_profile = { + .target = mtk_cci_devfreq_target, +}; + +static int mtk_cci_devfreq_probe(struct platform_device *pdev) +{ + struct device *cci_dev = &pdev->dev; + struct cci_devfreq *cci_df; + int ret; + + cci_df = devm_kzalloc(cci_dev, sizeof(*cci_df), GFP_KERNEL); + if (!cci_df) + return -ENOMEM; + + cci_df->cci_clk = devm_clk_get(cci_dev, "cci_clock"); + ret = PTR_ERR_OR_ZERO(cci_df->cci_clk); + if (ret) { + if (ret != -EPROBE_DEFER) + dev_err(cci_dev, "failed to get clock for CCI: %d\n", + ret); + return ret; + } + cci_df->proc_reg = devm_regulator_get_optional(cci_dev, "proc"); + ret = PTR_ERR_OR_ZERO(cci_df->proc_reg); + if (ret) { + if (ret != -EPROBE_DEFER) + dev_err(cci_dev, "failed to get regulator for CCI: %d\n", + ret); + return ret; + } + + ret = dev_pm_opp_of_add_table(cci_dev); + if (ret) { + dev_err(cci_dev, "Fail to init CCI OPP table: %d\n", ret); + return ret; + } + + platform_set_drvdata(pdev, cci_df); + + cci_df->devfreq = devm_devfreq_add_device(cci_dev, + &cci_devfreq_profile, + "mtk_cci_vmon", + NULL); + if (IS_ERR(cci_df->devfreq)) { + ret = PTR_ERR(cci_df->devfreq); + dev_err(cci_dev, "cannot create cci devfreq device:%d\n", ret); + dev_pm_opp_of_remove_table(cci_dev); + return ret; + } + + return 0; +} + +static const __maybe_unused struct of_device_id + mediatek_cci_devfreq_of_match[] = { + { .compatible = "mediatek,mt8183-cci" }, + { }, +}; +MODULE_DEVICE_TABLE(of, mediatek_cci_devfreq_of_match); + +static struct platform_driver cci_devfreq_driver = { + .probe = mtk_cci_devfreq_probe, + .driver = { + .name = "mediatek-cci-devfreq", + .of_match_table = of_match_ptr(mediatek_cci_devfreq_of_match), + }, +}; + +static int __init mtk_cci_devfreq_init(void) +{ + int ret; + + ret = devfreq_add_governor(&mtk_cci_devfreq_governor); + if (ret) { + pr_err("%s: failed to add governor: %d\n", __func__, ret); + return ret; + } + + ret = platform_driver_register(&cci_devfreq_driver); + if (ret) + devfreq_remove_governor(&mtk_cci_devfreq_governor); + + return ret; +} +module_init(mtk_cci_devfreq_init) + +static void __exit mtk_cci_devfreq_exit(void) +{ + int ret; + + ret = devfreq_remove_governor(&mtk_cci_devfreq_governor); + if (ret) + pr_err("%s: failed to remove governor: %d\n", __func__, ret); + + platform_driver_unregister(&cci_devfreq_driver); +} +module_exit(mtk_cci_devfreq_exit) + +MODULE_DESCRIPTION("Mediatek CCI devfreq driver"); +MODULE_AUTHOR("Andrew-sh.Cheng "); +MODULE_LICENSE("GPL v2"); From patchwork Thu May 16 09:08:43 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "andrew-sh.cheng" X-Patchwork-Id: 10946069 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id A2CB014DB for ; Thu, 16 May 2019 09:10:28 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 8C8A827D29 for ; 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Thu, 16 May 2019 01:09:32 -0800 Received: from mtkmbs08n2.mediatek.inc (172.21.101.56) by MTKMBS62N1.mediatek.inc (172.29.193.41) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Thu, 16 May 2019 02:09:31 -0700 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs08n2.mediatek.inc (172.21.101.56) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Thu, 16 May 2019 17:08:52 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Thu, 16 May 2019 17:08:52 +0800 From: Andrew-sh.Cheng To: MyungJoo Ham , Kyungmin Park , Chanwoo Choi , "Rob Herring" , Mark Rutland , "Matthias Brugger" , "Rafael J. Wysocki" , Viresh Kumar , Nishanth Menon , "Stephen Boyd" Subject: [PATCH 6/8] PM / OPP: Support adjusting OPP voltages at runtime Date: Thu, 16 May 2019 17:08:43 +0800 Message-ID: <1557997725-12178-7-git-send-email-andrew-sh.cheng@mediatek.com> X-Mailer: git-send-email 1.8.1.1.dirty In-Reply-To: <1557997725-12178-1-git-send-email-andrew-sh.cheng@mediatek.com> References: <1557997725-12178-1-git-send-email-andrew-sh.cheng@mediatek.com> MIME-Version: 1.0 X-TM-SNTS-SMTP: E0DEB3833EAD9912F130270ECCD6A64BEFFD3A54B599CC841847DA7BC76D256C2000:8 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190516_020934_496396_897EB6C5 X-CRM114-Status: GOOD ( 17.46 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, srv_heupstream@mediatek.com, linux-pm@vger.kernel.org, Roger Lu , Stephen Boyd , linux-kernel@vger.kernel.org, fan.chen@mediatek.com, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+patchwork-linux-mediatek=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP From: Stephen Boyd On some SoCs the Adaptive Voltage Scaling (AVS) technique is employed to optimize the operating voltage of a device. At a given frequency, the hardware monitors dynamic factors and either makes a suggestion for how much to adjust a voltage for the current frequency, or it automatically adjusts the voltage without software intervention. Add an API to the OPP library for the former case, so that AVS type devices can update the voltages for an OPP when the hardware determines the voltage should change. The assumption is that drivers like CPUfreq or devfreq will register for the OPP notifiers and adjust the voltage according to suggestions that AVS makes. This patch is devired from [1] submitted by Stephen. [1] https://lore.kernel.org/patchwork/patch/599279/ Signed-off-by: Stephen Boyd Signed-off-by: Roger Lu --- drivers/opp/core.c | 78 ++++++++++++++++++++++++++++++++++++++++++++++++++ include/linux/pm_opp.h | 11 +++++++ 2 files changed, 89 insertions(+) diff --git a/drivers/opp/core.c b/drivers/opp/core.c index 0420f7e8ad5b..879ca5f50d1a 100644 --- a/drivers/opp/core.c +++ b/drivers/opp/core.c @@ -1946,6 +1946,84 @@ static int _opp_set_availability(struct device *dev, unsigned long freq, return r; } +/* + * dev_pm_opp_adjust_voltage() - helper to change the voltage of an OPP + * @dev: device for which we do this operation + * @freq: OPP frequency to adjust voltage of + * @u_volt: new OPP voltage + * + * Change the voltage of an OPP with an RCU operation. + * + * Return: -EINVAL for bad pointers, -ENOMEM if no memory available for the + * copy operation, returns 0 if no modifcation was done OR modification was + * successful. + * + * Locking: The internal device_opp and opp structures are RCU protected. + * Hence this function internally uses RCU updater strategy with mutex locks to + * keep the integrity of the internal data structures. Callers should ensure + * that this function is *NOT* called under RCU protection or in contexts where + * mutex locking or synchronize_rcu() blocking calls cannot be used. + */ +int dev_pm_opp_adjust_voltage(struct device *dev, unsigned long freq, + unsigned long u_volt) +{ + struct opp_table *opp_table; + struct dev_pm_opp *new_opp, *tmp_opp, *opp = ERR_PTR(-ENODEV); + int r = 0; + + /* Find the opp_table */ + opp_table = _find_opp_table(dev); + if (IS_ERR(opp_table)) { + r = PTR_ERR(opp_table); + dev_warn(dev, "%s: Device OPP not found (%d)\n", __func__, r); + return r; + } + + /* keep the node allocated */ + new_opp = kmalloc(sizeof(*new_opp), GFP_KERNEL); + if (!new_opp) + return -ENOMEM; + + mutex_lock(&opp_table->lock); + + /* Do we have the frequency? */ + list_for_each_entry(tmp_opp, &opp_table->opp_list, node) { + if (tmp_opp->rate == freq) { + opp = tmp_opp; + break; + } + } + + if (IS_ERR(opp)) { + r = PTR_ERR(opp); + goto unlock; + } + + /* Is update really needed? */ + if (opp->supplies->u_volt == u_volt) + goto unlock; + + /* copy the old data over */ + *new_opp = *opp; + + /* plug in new node */ + new_opp->supplies->u_volt = u_volt; + + list_replace_rcu(&opp->node, &new_opp->node); + mutex_unlock(&opp_table->lock); + + /* Notify the change of the OPP */ + blocking_notifier_call_chain(&opp_table->head, OPP_EVENT_ADJUST_VOLTAGE, + opp); + + return 0; + +unlock: + mutex_unlock(&opp_table->lock); + kfree(new_opp); + return r; +} + /** * dev_pm_opp_enable() - Enable a specific OPP * @dev: device for which we do this operation diff --git a/include/linux/pm_opp.h b/include/linux/pm_opp.h index 24c757a32a7b..70219fe3ca20 100644 --- a/include/linux/pm_opp.h +++ b/include/linux/pm_opp.h @@ -25,6 +25,7 @@ struct opp_table; enum dev_pm_opp_event { OPP_EVENT_ADD, OPP_EVENT_REMOVE, OPP_EVENT_ENABLE, OPP_EVENT_DISABLE, + OPP_EVENT_ADJUST_VOLTAGE, }; /** @@ -112,6 +113,9 @@ int dev_pm_opp_add(struct device *dev, unsigned long freq, void dev_pm_opp_remove(struct device *dev, unsigned long freq); void dev_pm_opp_remove_all_dynamic(struct device *dev); +int dev_pm_opp_adjust_voltage(struct device *dev, unsigned long freq, + unsigned long u_volt); + int dev_pm_opp_enable(struct device *dev, unsigned long freq); int dev_pm_opp_disable(struct device *dev, unsigned long freq); @@ -229,6 +233,13 @@ static inline void dev_pm_opp_remove_all_dynamic(struct device *dev) { } +static inline int +dev_pm_opp_adjust_voltage(struct device *dev, unsigned long freq, + unsigned long u_volt) +{ + return 0; +} + static inline int dev_pm_opp_enable(struct device *dev, unsigned long freq) { return 0; From patchwork Thu May 16 09:08:44 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "andrew-sh.cheng" X-Patchwork-Id: 10946059 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 1D4E414DB for ; Thu, 16 May 2019 09:09:42 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 0B806201F5 for ; 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Thu, 16 May 2019 01:09:06 -0800 Received: from MTKMBS02N1.mediatek.inc (172.21.101.77) by MTKMBS62N2.mediatek.inc (172.29.193.42) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Thu, 16 May 2019 02:09:05 -0700 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs02n1.mediatek.inc (172.21.101.77) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Thu, 16 May 2019 17:08:53 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Thu, 16 May 2019 17:08:53 +0800 From: Andrew-sh.Cheng To: MyungJoo Ham , Kyungmin Park , Chanwoo Choi , "Rob Herring" , Mark Rutland , "Matthias Brugger" , "Rafael J. Wysocki" , Viresh Kumar , Nishanth Menon , "Stephen Boyd" Subject: [PATCH 7/8] cpufreq: mediatek: add opp notification for SVS support Date: Thu, 16 May 2019 17:08:44 +0800 Message-ID: <1557997725-12178-8-git-send-email-andrew-sh.cheng@mediatek.com> X-Mailer: git-send-email 1.8.1.1.dirty In-Reply-To: <1557997725-12178-1-git-send-email-andrew-sh.cheng@mediatek.com> References: <1557997725-12178-1-git-send-email-andrew-sh.cheng@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190516_020909_565573_9B252B09 X-CRM114-Status: GOOD ( 13.31 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, "Andrew-sh.Cheng" , srv_heupstream@mediatek.com, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, fan.chen@mediatek.com, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+patchwork-linux-mediatek=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP From: "Andrew-sh.Cheng" cpufreq should listen opp notification and do proper actions when receiving disable and voltage adjustment events, which are triggered when SVS is enabled. Signed-off-by: Andrew-sh.Cheng --- drivers/cpufreq/mediatek-cpufreq.c | 72 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 72 insertions(+) diff --git a/drivers/cpufreq/mediatek-cpufreq.c b/drivers/cpufreq/mediatek-cpufreq.c index 022d86757327..6514187a43f4 100644 --- a/drivers/cpufreq/mediatek-cpufreq.c +++ b/drivers/cpufreq/mediatek-cpufreq.c @@ -50,6 +50,10 @@ struct mtk_cpu_dvfs_info { struct list_head list_head; int intermediate_voltage; bool need_voltage_tracking; + struct mutex lock; /* avoid notify and policy race condition */ + struct notifier_block opp_nb; + int opp_cpu; + unsigned long opp_freq; }; static LIST_HEAD(dvfs_info_list); @@ -239,6 +243,7 @@ static int mtk_cpufreq_set_target(struct cpufreq_policy *policy, vproc = dev_pm_opp_get_voltage(opp); dev_pm_opp_put(opp); + mutex_lock(&info->lock); /* * If the new voltage or the intermediate voltage is higher than the * current voltage, scale up voltage first. @@ -250,6 +255,7 @@ static int mtk_cpufreq_set_target(struct cpufreq_policy *policy, pr_err("cpu%d: failed to scale up voltage!\n", policy->cpu); mtk_cpufreq_set_voltage(info, old_vproc); + mutex_unlock(&info->lock); return ret; } } @@ -261,6 +267,7 @@ static int mtk_cpufreq_set_target(struct cpufreq_policy *policy, policy->cpu); mtk_cpufreq_set_voltage(info, old_vproc); WARN_ON(1); + mutex_unlock(&info->lock); return ret; } @@ -271,6 +278,7 @@ static int mtk_cpufreq_set_target(struct cpufreq_policy *policy, policy->cpu); clk_set_parent(cpu_clk, armpll); mtk_cpufreq_set_voltage(info, old_vproc); + mutex_unlock(&info->lock); return ret; } @@ -281,6 +289,7 @@ static int mtk_cpufreq_set_target(struct cpufreq_policy *policy, policy->cpu); mtk_cpufreq_set_voltage(info, inter_vproc); WARN_ON(1); + mutex_unlock(&info->lock); return ret; } @@ -296,15 +305,69 @@ static int mtk_cpufreq_set_target(struct cpufreq_policy *policy, clk_set_parent(cpu_clk, info->inter_clk); clk_set_rate(armpll, old_freq_hz); clk_set_parent(cpu_clk, armpll); + mutex_unlock(&info->lock); return ret; } } + info->opp_freq = freq_hz; + mutex_unlock(&info->lock); + return 0; } #define DYNAMIC_POWER "dynamic-power-coefficient" +static int mtk_cpufreq_opp_notifier(struct notifier_block *nb, + unsigned long event, void *data) +{ + struct dev_pm_opp *opp = data; + struct dev_pm_opp *opp_item; + struct mtk_cpu_dvfs_info *info = + container_of(nb, struct mtk_cpu_dvfs_info, opp_nb); + unsigned long freq, volt; + int ret = 0; + + if (event == OPP_EVENT_ADJUST_VOLTAGE) { + freq = dev_pm_opp_get_freq(opp); + + mutex_lock(&info->lock); + if (info->opp_freq == freq) { + volt = dev_pm_opp_get_voltage(opp); + ret = mtk_cpufreq_set_voltage(info, volt); + if (ret) + dev_err(info->cpu_dev, "failed to scale voltage: %d\n", + ret); + } + mutex_unlock(&info->lock); + } else if (event == OPP_EVENT_DISABLE) { + freq = info->opp_freq; + opp_item = dev_pm_opp_find_freq_ceil(info->cpu_dev, &freq); + if (!IS_ERR(opp_item)) + dev_pm_opp_put(opp_item); + else + freq = 0; + + /* case of current opp is disabled */ + if (freq == 0 || freq != info->opp_freq) { + // find an enable opp item + freq = 1; + opp_item = dev_pm_opp_find_freq_ceil(info->cpu_dev, + &freq); + if (!IS_ERR(opp_item)) { + dev_pm_opp_put(opp_item); + cpufreq_driver_target( + cpufreq_cpu_get(info->opp_cpu), + freq / 1000, CPUFREQ_RELATION_L); + } else + pr_err("%s: all opp items are disabled\n", + __func__); + } + } + + return notifier_from_errno(ret); +} + static int mtk_cpu_dvfs_info_init(struct mtk_cpu_dvfs_info *info, int cpu) { struct device *cpu_dev; @@ -391,11 +454,20 @@ static int mtk_cpu_dvfs_info_init(struct mtk_cpu_dvfs_info *info, int cpu) info->intermediate_voltage = dev_pm_opp_get_voltage(opp); dev_pm_opp_put(opp); + info->opp_cpu = cpu; + info->opp_nb.notifier_call = mtk_cpufreq_opp_notifier; + ret = dev_pm_opp_register_notifier(cpu_dev, &info->opp_nb); + if (ret) { + pr_warn("cannot register opp notification\n"); + goto out_free_opp_table; + } + info->cpu_dev = cpu_dev; info->proc_reg = proc_reg; info->sram_reg = IS_ERR(sram_reg) ? NULL : sram_reg; info->cpu_clk = cpu_clk; info->inter_clk = inter_clk; + info->opp_freq = clk_get_rate(cpu_clk); /* * If SRAM regulator is present, software "voltage tracking" is needed From patchwork Thu May 16 09:08:45 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "andrew-sh.cheng" X-Patchwork-Id: 10946075 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 00F8F6C5 for ; Thu, 16 May 2019 09:11:08 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id E292928893 for ; Thu, 16 May 2019 09:11:07 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id D665E28899; Thu, 16 May 2019 09:11:07 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED,UNPARSEABLE_RELAY autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 69CCA28880 for ; Thu, 16 May 2019 09:11:07 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=dVMqohjleLJqnlwZufzcFCTyCkpkEVJikLUuLYdIeSs=; b=YrBraE1fYES+lA 3bigYBw8GF2I1oI4hEQ38Vu9Tv/ZhGJxHvMTQ9+zpJlEIT5obQgiWNYCRuYJGi5SKRZmsOB6ML7Jl aDLG6qIoxgCsqCLMTszxBZuk3+c1qfx1OXIDmU2U4+lxi0JEdARjRCMhCgDdXg1gBanVLQn/mga11 MIdM7jTSB9bbSmr1jU27JLSkCSZBaFexIFymDwODxwRBeMkZyp8hR5rto7QDAbCfAhZ/HiqWI+gxY vTbSzDRW9cUhYvGMn/64IiMg4DRjtqA63jMtJxApEraFkVmQkH3LF8RvkpsKuaW7Pxs48Yrz4b4sl ljn0sY2dGasi+8ZrolxA==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1hRCPp-0004Hs-Of; Thu, 16 May 2019 09:11:05 +0000 Received: from mailgw01.mediatek.com ([216.200.240.184]) by bombadil.infradead.org with esmtps (Exim 4.90_1 #2 (Red Hat Linux)) id 1hRCPX-0003x1-Dn; Thu, 16 May 2019 09:10:54 +0000 X-UUID: 370caefb420b4d14846412d929716594-20190516 X-UUID: 370caefb420b4d14846412d929716594-20190516 Received: from mtkcas67.mediatek.inc [(172.29.193.45)] by mailgw01.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLS) with ESMTP id 582888598; Thu, 16 May 2019 01:08:58 -0800 Received: from mtkmbs03n2.mediatek.inc (172.21.101.182) by MTKMBS62N2.mediatek.inc (172.29.193.42) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Thu, 16 May 2019 02:08:57 -0700 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs03n2.mediatek.inc (172.21.101.182) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Thu, 16 May 2019 17:08:54 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Thu, 16 May 2019 17:08:54 +0800 From: Andrew-sh.Cheng To: MyungJoo Ham , Kyungmin Park , Chanwoo Choi , "Rob Herring" , Mark Rutland , "Matthias Brugger" , "Rafael J. Wysocki" , Viresh Kumar , Nishanth Menon , "Stephen Boyd" Subject: [PATCH 8/8] devfreq: mediatek: cci devfreq register opp notification for SVS support Date: Thu, 16 May 2019 17:08:45 +0800 Message-ID: <1557997725-12178-9-git-send-email-andrew-sh.cheng@mediatek.com> X-Mailer: git-send-email 1.8.1.1.dirty In-Reply-To: <1557997725-12178-1-git-send-email-andrew-sh.cheng@mediatek.com> References: <1557997725-12178-1-git-send-email-andrew-sh.cheng@mediatek.com> MIME-Version: 1.0 X-TM-SNTS-SMTP: 62CC2EE68B25C65BA0EF7B7202A11B5471CAE6A481855F75FFF3832C060DAEC82000:8 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190516_021048_097263_D49DABC9 X-CRM114-Status: GOOD ( 13.19 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, "Andrew-sh.Cheng" , srv_heupstream@mediatek.com, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, fan.chen@mediatek.com, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+patchwork-linux-mediatek=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP From: "Andrew-sh.Cheng" SVS will change the voltage of opp item. CCI devfreq need to react to change frequency. Signed-off-by: Andrew-sh.Cheng --- drivers/devfreq/mt8183-cci-devfreq.c | 63 ++++++++++++++++++++++++++++++++++++ 1 file changed, 63 insertions(+) diff --git a/drivers/devfreq/mt8183-cci-devfreq.c b/drivers/devfreq/mt8183-cci-devfreq.c index 818a167c442f..250c963789f3 100644 --- a/drivers/devfreq/mt8183-cci-devfreq.c +++ b/drivers/devfreq/mt8183-cci-devfreq.c @@ -19,7 +19,10 @@ struct cci_devfreq { struct regulator *proc_reg; unsigned long proc_reg_uV; struct clk *cci_clk; + unsigned long freq; struct notifier_block nb; + struct notifier_block opp_nb; + int cci_min_freq; }; static int cci_devfreq_regulator_notifier(struct notifier_block *nb, @@ -65,17 +68,62 @@ static int cci_devfreq_regulator_notifier(struct notifier_block *nb, return 0; } +static int ccidevfreq_opp_notifier(struct notifier_block *nb, +unsigned long event, void *data) +{ + int ret; + struct dev_pm_opp *opp = data; + struct cci_devfreq *cci_df = container_of(nb, struct cci_devfreq, + opp_nb); + unsigned long freq, volt, cur_volt; + + if (event == OPP_EVENT_ADJUST_VOLTAGE) { + freq = dev_pm_opp_get_freq(opp); + /* current opp item is changed */ + if (freq == cci_df->freq) { + volt = dev_pm_opp_get_voltage(opp); + cur_volt = regulator_get_voltage(cci_df->proc_reg); + + if (volt > cur_volt) { + /* need reduce freq */ + mutex_lock(&cci_df->devfreq->lock); + ret = update_devfreq(cci_df->devfreq); + if (ret) + pr_err("Fail to reduce cci frequency by opp notification: %d\n", + ret); + mutex_unlock(&cci_df->devfreq->lock); + } + } + + if (freq == cci_df->cci_min_freq) { + volt = dev_pm_opp_get_voltage(opp); + regulator_set_voltage(cci_df->proc_reg, volt, INT_MAX); + } + } else if (event == OPP_EVENT_DISABLE) { + } + + return 0; +} + + static int mtk_cci_governor_get_target(struct devfreq *devfreq, unsigned long *freq) { struct cci_devfreq *cci_df; struct dev_pm_opp *opp; + int ret; cci_df = dev_get_drvdata(devfreq->dev.parent); /* find available frequency */ opp = dev_pm_opp_find_freq_ceil_by_volt(devfreq->dev.parent, cci_df->proc_reg_uV); + ret = PTR_ERR_OR_ZERO(opp); + if (ret) { + pr_err("%s[%d], cannot find opp with voltage=%d: %d\n", + __func__, __LINE__, cci_df->proc_reg_uV, ret); + return ret; + } *freq = dev_pm_opp_get_freq(opp); return 0; @@ -87,9 +135,11 @@ static int mtk_cci_governor_event_handler(struct devfreq *devfreq, int ret; struct cci_devfreq *cci_df; struct notifier_block *nb; + struct notifier_block *opp_nb; cci_df = dev_get_drvdata(devfreq->dev.parent); nb = &cci_df->nb; + opp_nb = &cci_df->opp_nb; switch (event) { case DEVFREQ_GOV_START: @@ -100,6 +150,8 @@ static int mtk_cci_governor_event_handler(struct devfreq *devfreq, if (ret) pr_err("%s: failed to add governor: %d\n", __func__, ret); + opp_nb->notifier_call = ccidevfreq_opp_notifier; + dev_pm_opp_register_notifier(devfreq->dev.parent, opp_nb); break; case DEVFREQ_GOV_STOP: @@ -141,6 +193,8 @@ static int mtk_cci_devfreq_target(struct device *dev, unsigned long *freq, return ret; } + cci_df->freq = *freq; + return 0; } @@ -152,6 +206,8 @@ static int mtk_cci_devfreq_probe(struct platform_device *pdev) { struct device *cci_dev = &pdev->dev; struct cci_devfreq *cci_df; + unsigned long freq, volt; + struct dev_pm_opp *opp; int ret; cci_df = devm_kzalloc(cci_dev, sizeof(*cci_df), GFP_KERNEL); @@ -181,6 +237,13 @@ static int mtk_cci_devfreq_probe(struct platform_device *pdev) return ret; } + /* set voltage lower bound */ + freq = 1; + opp = dev_pm_opp_find_freq_ceil(cci_dev, &freq); + cci_df->cci_min_freq = dev_pm_opp_get_freq(opp); + volt = dev_pm_opp_get_voltage(opp); + dev_pm_opp_put(opp); + platform_set_drvdata(pdev, cci_df); cci_df->devfreq = devm_devfreq_add_device(cci_dev,