From patchwork Mon May 20 10:13:36 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Andrew Cooper X-Patchwork-Id: 10950777 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id D067B112C for ; Mon, 20 May 2019 10:15:47 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id BE34A28774 for ; Mon, 20 May 2019 10:15:47 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id B199A2877E; Mon, 20 May 2019 10:15:47 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id C1F8B28774 for ; Mon, 20 May 2019 10:15:46 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1hSfId-0007tW-Gq; Mon, 20 May 2019 10:13:43 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57] helo=us1-amaz-eas2.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1hSfId-0007tQ-3L for xen-devel@lists.xenproject.org; Mon, 20 May 2019 10:13:43 +0000 X-Inumbo-ID: f06674dc-7ae7-11e9-af9b-a3075a055f09 Received: from esa5.hc3370-68.iphmx.com (unknown [216.71.155.168]) by us1-amaz-eas2.inumbo.com (Halon) with ESMTPS id f06674dc-7ae7-11e9-af9b-a3075a055f09; Mon, 20 May 2019 10:13:40 +0000 (UTC) Authentication-Results: esa5.hc3370-68.iphmx.com; dkim=none (message not signed) header.i=none; spf=None smtp.pra=andrew.cooper3@citrix.com; spf=SoftFail smtp.mailfrom=Andrew.Cooper3@citrix.com; spf=None smtp.helo=postmaster@MIAPEX02MSOL02.citrite.net Received-SPF: None (esa5.hc3370-68.iphmx.com: no sender authenticity information available from domain of andrew.cooper3@citrix.com) identity=pra; client-ip=23.29.105.83; receiver=esa5.hc3370-68.iphmx.com; envelope-from="Andrew.Cooper3@citrix.com"; x-sender="andrew.cooper3@citrix.com"; x-conformance=sidf_compatible Received-SPF: SoftFail (esa5.hc3370-68.iphmx.com: domain of Andrew.Cooper3@citrix.com is inclined to not designate 23.29.105.83 as permitted sender) identity=mailfrom; client-ip=23.29.105.83; receiver=esa5.hc3370-68.iphmx.com; envelope-from="Andrew.Cooper3@citrix.com"; x-sender="Andrew.Cooper3@citrix.com"; x-conformance=sidf_compatible; x-record-type="v=spf1"; x-record-text="v=spf1 include:spf.citrix.com include:spf2.citrix.com include:ironport.citrix.com exists:%{i}._spf.mta.salesforce.com ~all" Received-SPF: None (esa5.hc3370-68.iphmx.com: no sender authenticity information available from domain of postmaster@MIAPEX02MSOL02.citrite.net) identity=helo; client-ip=23.29.105.83; receiver=esa5.hc3370-68.iphmx.com; envelope-from="Andrew.Cooper3@citrix.com"; x-sender="postmaster@MIAPEX02MSOL02.citrite.net"; x-conformance=sidf_compatible IronPort-SDR: 6bUFQLSLEZfv8tEm/hNXox9POIEvjyfqELyKvQi4sC4XjXlg09ubnelpSyx0pTKAf6wWEGqTJR KYFrmrz5YPueiItdZJqnk+hD4UnZPhKSSKEDqe1md3QHARI7r5t8uYyOvEdF2MqO98EsCKo/Kl qnPIuphx6uMGQyjcNhiwWrKGVTU6royLNBGgbp5DXivpwMoN6hG9QycWE82gt4+VSItHgnCX39 yIjIOkuutLnc0YP085TT6JFMJ4qnTRGmQ9HfsCGna4qO5GL7Si5NMyCKony6G+BZFPVsNY8bEh ebQ= X-SBRS: 2.7 X-MesageID: 627302 X-Ironport-Server: esa5.hc3370-68.iphmx.com X-Remote-IP: 23.29.105.83 X-Policy: $RELAYED X-IronPort-AV: E=Sophos;i="5.60,491,1549947600"; d="scan'208";a="627302" From: Andrew Cooper To: Xen-devel Date: Mon, 20 May 2019 11:13:36 +0100 Message-ID: <1558347216-19179-1-git-send-email-andrew.cooper3@citrix.com> X-Mailer: git-send-email 2.1.4 MIME-Version: 1.0 Subject: [Xen-devel] [PATCH] x86/svm: Drop support for AMD's Lightweight Profiling X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Wei Liu , Jan Beulich , Andrew Cooper , Suravee Suthikulpanit , Boris Ostrovsky , Brian Woods , =?utf-8?q?Roger_Pau_Monn=C3=A9?= Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" X-Virus-Scanned: ClamAV using ClamSMTP Lightweight Profiling was introduced in Bulldozer (Fam15h), but was dropped from Zen (Fam17h) processors. Furthermore, LWP was dropped from Fam15/16 CPUs when IBPB for Spectre v2 was introduced in microcode, owing to LWP not being used in practice. As a result, CPUs which are operating within specification (i.e. with up to date microcode) no longer have this feature, and therefore are not using it. Drop support from Xen. The main motivation here is to remove unnecessary complexity from CPUID handling, but it also tidies up the SVM code nicely. Signed-off-by: Andrew Cooper Reviewed-by: Jan Beulich Acked-by: Brian Woods --- CC: Jan Beulich CC: Wei Liu CC: Roger Pau Monné CC: Boris Ostrovsky CC: Suravee Suthikulpanit CC: Brian Woods --- xen/arch/x86/cpuid.c | 22 +-------- xen/arch/x86/hvm/svm/svm.c | 77 ----------------------------- xen/arch/x86/hvm/svm/vmcb.c | 5 -- xen/arch/x86/msr.c | 4 ++ xen/arch/x86/xstate.c | 3 +- xen/include/asm-x86/cpufeature.h | 1 - xen/include/asm-x86/hvm/svm/vmcb.h | 4 -- xen/include/asm-x86/xstate.h | 3 +- xen/include/public/arch-x86/cpufeatureset.h | 2 +- 9 files changed, 8 insertions(+), 113 deletions(-) diff --git a/xen/arch/x86/cpuid.c b/xen/arch/x86/cpuid.c index 6f59325..666fbbb 100644 --- a/xen/arch/x86/cpuid.c +++ b/xen/arch/x86/cpuid.c @@ -163,14 +163,6 @@ static void recalculate_xstate(struct cpuid_policy *p) xstate_sizes[X86_XCR0_PKRU_POS]); } - if ( p->extd.lwp ) - { - xstates |= X86_XCR0_LWP; - xstate_size = max(xstate_size, - xstate_offsets[X86_XCR0_LWP_POS] + - xstate_sizes[X86_XCR0_LWP_POS]); - } - p->xstate.max_size = xstate_size; p->xstate.xcr0_low = xstates & ~XSTATE_XSAVES_ONLY; p->xstate.xcr0_high = (xstates & ~XSTATE_XSAVES_ONLY) >> 32; @@ -265,8 +257,7 @@ static void recalculate_misc(struct cpuid_policy *p) zero_leaves(p->extd.raw, 0xb, 0x18); p->extd.raw[0x1b] = EMPTY_LEAF; /* IBS - not supported. */ - - p->extd.raw[0x1c].a = 0; /* LWP.a entirely dynamic. */ + p->extd.raw[0x1c] = EMPTY_LEAF; /* LWP - not supported. */ break; } } @@ -581,11 +572,6 @@ void recalculate_cpuid_policy(struct domain *d) if ( !p->extd.page1gb ) p->extd.raw[0x19] = EMPTY_LEAF; - - if ( p->extd.lwp ) - p->extd.raw[0x1c].d &= max->extd.raw[0x1c].d; - else - p->extd.raw[0x1c] = EMPTY_LEAF; } int init_domain_cpuid_policy(struct domain *d) @@ -972,12 +958,6 @@ void guest_cpuid(const struct vcpu *v, uint32_t leaf, res->d |= cpufeat_mask(X86_FEATURE_MTRR); } break; - - case 0x8000001c: - if ( (v->arch.xcr0 & X86_XCR0_LWP) && cpu_has_svm ) - /* Turn on available bit and other features specified in lwp_cfg. */ - res->a = (res->d & v->arch.hvm.svm.guest_lwp_cfg) | 1; - break; } } diff --git a/xen/arch/x86/hvm/svm/svm.c b/xen/arch/x86/hvm/svm/svm.c index 0beb31b..9f26493 100644 --- a/xen/arch/x86/hvm/svm/svm.c +++ b/xen/arch/x86/hvm/svm/svm.c @@ -939,72 +939,6 @@ static void svm_init_hypercall_page(struct domain *d, void *hypercall_page) *(u16 *)(hypercall_page + (__HYPERVISOR_iret * 32)) = 0x0b0f; /* ud2 */ } -static void svm_lwp_interrupt(struct cpu_user_regs *regs) -{ - struct vcpu *curr = current; - - ack_APIC_irq(); - vlapic_set_irq( - vcpu_vlapic(curr), - (curr->arch.hvm.svm.guest_lwp_cfg >> 40) & 0xff, - 0); -} - -static inline void svm_lwp_save(struct vcpu *v) -{ - /* Don't mess up with other guests. Disable LWP for next VCPU. */ - if ( v->arch.hvm.svm.guest_lwp_cfg ) - { - wrmsrl(MSR_AMD64_LWP_CFG, 0x0); - wrmsrl(MSR_AMD64_LWP_CBADDR, 0x0); - } -} - -static inline void svm_lwp_load(struct vcpu *v) -{ - /* Only LWP_CFG is reloaded. LWP_CBADDR will be reloaded via xrstor. */ - if ( v->arch.hvm.svm.guest_lwp_cfg ) - wrmsrl(MSR_AMD64_LWP_CFG, v->arch.hvm.svm.cpu_lwp_cfg); -} - -/* Update LWP_CFG MSR (0xc0000105). Return -1 if error; otherwise returns 0. */ -static int svm_update_lwp_cfg(struct vcpu *v, uint64_t msr_content) -{ - uint32_t msr_low; - static uint8_t lwp_intr_vector; - - if ( xsave_enabled(v) && cpu_has_lwp ) - { - msr_low = (uint32_t)msr_content; - - /* generate #GP if guest tries to turn on unsupported features. */ - if ( msr_low & ~v->domain->arch.cpuid->extd.raw[0x1c].d ) - return -1; - - v->arch.hvm.svm.guest_lwp_cfg = msr_content; - - /* setup interrupt handler if needed */ - if ( (msr_content & 0x80000000) && ((msr_content >> 40) & 0xff) ) - { - alloc_direct_apic_vector(&lwp_intr_vector, svm_lwp_interrupt); - v->arch.hvm.svm.cpu_lwp_cfg = (msr_content & 0xffff00ffffffffffULL) - | ((uint64_t)lwp_intr_vector << 40); - } - else - { - /* otherwise disable it */ - v->arch.hvm.svm.cpu_lwp_cfg = msr_content & 0xffff00ff7fffffffULL; - } - - wrmsrl(MSR_AMD64_LWP_CFG, v->arch.hvm.svm.cpu_lwp_cfg); - - /* track nonalzy state if LWP_CFG is non-zero. */ - v->arch.nonlazy_xstate_used = !!(msr_content); - } - - return 0; -} - static inline void svm_tsc_ratio_save(struct vcpu *v) { /* Other vcpus might not have vtsc enabled. So disable TSC_RATIO here. */ @@ -1034,7 +968,6 @@ static void svm_ctxt_switch_from(struct vcpu *v) svm_fpu_leave(v); svm_save_dr(v); - svm_lwp_save(v); svm_tsc_ratio_save(v); svm_sync_vmcb(v, vmcb_needs_vmload); @@ -1066,7 +999,6 @@ static void svm_ctxt_switch_to(struct vcpu *v) svm_vmsave_pa(per_cpu(host_vmcb, cpu)); vmcb->cleanbits.bytes = 0; - svm_lwp_load(v); svm_tsc_ratio_load(v); if ( cpu_has_msr_tsc_aux ) @@ -2002,10 +1934,6 @@ static int svm_msr_read_intercept(unsigned int msr, uint64_t *msr_content) *msr_content = vmcb_get_lastinttoip(vmcb); break; - case MSR_AMD64_LWP_CFG: - *msr_content = v->arch.hvm.svm.guest_lwp_cfg; - break; - case MSR_K7_PERFCTR0: case MSR_K7_PERFCTR1: case MSR_K7_PERFCTR2: @@ -2177,11 +2105,6 @@ static int svm_msr_write_intercept(unsigned int msr, uint64_t msr_content) vmcb_set_lastinttoip(vmcb, msr_content); break; - case MSR_AMD64_LWP_CFG: - if ( svm_update_lwp_cfg(v, msr_content) < 0 ) - goto gpf; - break; - case MSR_K7_PERFCTR0: case MSR_K7_PERFCTR1: case MSR_K7_PERFCTR2: diff --git a/xen/arch/x86/hvm/svm/vmcb.c b/xen/arch/x86/hvm/svm/vmcb.c index 9d1c5bf..71ee710 100644 --- a/xen/arch/x86/hvm/svm/vmcb.c +++ b/xen/arch/x86/hvm/svm/vmcb.c @@ -100,11 +100,6 @@ static int construct_vmcb(struct vcpu *v) svm_disable_intercept_for_msr(v, MSR_STAR); svm_disable_intercept_for_msr(v, MSR_SYSCALL_MASK); - /* LWP_CBADDR MSR is saved and restored by FPU code. So SVM doesn't need to - * intercept it. */ - if ( cpu_has_lwp ) - svm_disable_intercept_for_msr(v, MSR_AMD64_LWP_CBADDR); - vmcb->_msrpm_base_pa = virt_to_maddr(svm->msrpm); vmcb->_iopm_base_pa = __pa(v->domain->arch.hvm.io_bitmap); diff --git a/xen/arch/x86/msr.c b/xen/arch/x86/msr.c index 883b57b..5a2ef78 100644 --- a/xen/arch/x86/msr.c +++ b/xen/arch/x86/msr.c @@ -132,6 +132,8 @@ int guest_rdmsr(struct vcpu *v, uint32_t msr, uint64_t *val) case MSR_FLUSH_CMD: /* Write-only */ case MSR_TSX_FORCE_ABORT: + case MSR_AMD64_LWP_CFG: + case MSR_AMD64_LWP_CBADDR: /* Not offered to guests. */ goto gp_fault; @@ -272,6 +274,8 @@ int guest_wrmsr(struct vcpu *v, uint32_t msr, uint64_t val) case MSR_ARCH_CAPABILITIES: /* Read-only */ case MSR_TSX_FORCE_ABORT: + case MSR_AMD64_LWP_CFG: + case MSR_AMD64_LWP_CBADDR: /* Not offered to guests. */ goto gp_fault; diff --git a/xen/arch/x86/xstate.c b/xen/arch/x86/xstate.c index 858d1a6..3da609a 100644 --- a/xen/arch/x86/xstate.c +++ b/xen/arch/x86/xstate.c @@ -725,8 +725,7 @@ int handle_xsetbv(u32 index, u64 new_bv) curr->arch.xcr0 = new_bv; curr->arch.xcr0_accum |= new_bv; - /* LWP sets nonlazy_xstate_used independently. */ - if ( new_bv & (XSTATE_NONLAZY & ~X86_XCR0_LWP) ) + if ( new_bv & XSTATE_NONLAZY ) curr->arch.nonlazy_xstate_used = 1; mask &= curr->fpu_dirtied ? ~XSTATE_FP_SSE : XSTATE_NONLAZY; diff --git a/xen/include/asm-x86/cpufeature.h b/xen/include/asm-x86/cpufeature.h index 745801f..e4f0343 100644 --- a/xen/include/asm-x86/cpufeature.h +++ b/xen/include/asm-x86/cpufeature.h @@ -78,7 +78,6 @@ #define cpu_has_svm boot_cpu_has(X86_FEATURE_SVM) #define cpu_has_sse4a boot_cpu_has(X86_FEATURE_SSE4A) #define cpu_has_xop boot_cpu_has(X86_FEATURE_XOP) -#define cpu_has_lwp boot_cpu_has(X86_FEATURE_LWP) #define cpu_has_fma4 boot_cpu_has(X86_FEATURE_FMA4) #define cpu_has_tbm boot_cpu_has(X86_FEATURE_TBM) diff --git a/xen/include/asm-x86/hvm/svm/vmcb.h b/xen/include/asm-x86/hvm/svm/vmcb.h index 7017705..5c71028 100644 --- a/xen/include/asm-x86/hvm/svm/vmcb.h +++ b/xen/include/asm-x86/hvm/svm/vmcb.h @@ -534,10 +534,6 @@ struct svm_vcpu { uint64_t guest_sysenter_cs; uint64_t guest_sysenter_esp; uint64_t guest_sysenter_eip; - - /* AMD lightweight profiling MSR */ - uint64_t guest_lwp_cfg; /* guest version */ - uint64_t cpu_lwp_cfg; /* CPU version */ }; struct vmcb_struct *alloc_vmcb(void); diff --git a/xen/include/asm-x86/xstate.h b/xen/include/asm-x86/xstate.h index 47f602b..7ab0bdd 100644 --- a/xen/include/asm-x86/xstate.h +++ b/xen/include/asm-x86/xstate.h @@ -35,8 +35,7 @@ extern uint32_t mxcsr_mask; XSTATE_NONLAZY) #define XSTATE_ALL (~(1ULL << 63)) -#define XSTATE_NONLAZY (X86_XCR0_LWP | X86_XCR0_BNDREGS | X86_XCR0_BNDCSR | \ - X86_XCR0_PKRU) +#define XSTATE_NONLAZY (X86_XCR0_BNDREGS | X86_XCR0_BNDCSR | X86_XCR0_PKRU) #define XSTATE_LAZY (XSTATE_ALL & ~XSTATE_NONLAZY) #define XSTATE_XSAVES_ONLY 0 #define XSTATE_COMPACTION_ENABLED (1ULL << 63) diff --git a/xen/include/public/arch-x86/cpufeatureset.h b/xen/include/public/arch-x86/cpufeatureset.h index 55231d4..727f482 100644 --- a/xen/include/public/arch-x86/cpufeatureset.h +++ b/xen/include/public/arch-x86/cpufeatureset.h @@ -176,7 +176,7 @@ XEN_CPUFEATURE(IBS, 3*32+10) /* Instruction Based Sampling */ XEN_CPUFEATURE(XOP, 3*32+11) /*A extended AVX instructions */ XEN_CPUFEATURE(SKINIT, 3*32+12) /* SKINIT/STGI instructions */ XEN_CPUFEATURE(WDT, 3*32+13) /* Watchdog timer */ -XEN_CPUFEATURE(LWP, 3*32+15) /*S Light Weight Profiling */ +XEN_CPUFEATURE(LWP, 3*32+15) /* Light Weight Profiling */ XEN_CPUFEATURE(FMA4, 3*32+16) /*A 4 operands MAC instructions */ XEN_CPUFEATURE(NODEID_MSR, 3*32+19) /* NodeId MSR */ XEN_CPUFEATURE(TBM, 3*32+21) /*A trailing bit manipulations */