From patchwork Wed May 22 23:45:44 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krish Sadhukhan X-Patchwork-Id: 10956795 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 30411933 for ; Thu, 23 May 2019 00:12:40 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 2ED9D2793A for ; Thu, 23 May 2019 00:12:40 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 23406279E0; Thu, 23 May 2019 00:12:40 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id BC4582793A for ; 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Thu, 23 May 2019 00:12:03 +0000 Received: from pps.filterd (aserp3030.oracle.com [127.0.0.1]) by aserp3030.oracle.com (8.16.0.27/8.16.0.27) with SMTP id x4N0C3jU033982; Thu, 23 May 2019 00:12:03 GMT Received: from userv0121.oracle.com (userv0121.oracle.com [156.151.31.72]) by aserp3030.oracle.com with ESMTP id 2smsgswxy5-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Thu, 23 May 2019 00:12:02 +0000 Received: from abhmp0017.oracle.com (abhmp0017.oracle.com [141.146.116.23]) by userv0121.oracle.com (8.14.4/8.13.8) with ESMTP id x4N0C164003375; Thu, 23 May 2019 00:12:01 GMT Received: from ban25x6uut29.us.oracle.com (/10.153.73.29) by default (Oracle Beehive Gateway v4.0) with ESMTP ; Thu, 23 May 2019 00:12:01 +0000 From: Krish Sadhukhan To: kvm@vger.kernel.org Cc: rkrcmar@redhat.com, pbonzini@redhat.com, jmattson@google.com Subject: [PATCH 1/2] kvm-unit-test: x86: Add a wrapper to check if the CPU supports NX bit in MSR_EFER Date: Wed, 22 May 2019 19:45:44 -0400 Message-Id: <20190522234545.5930-2-krish.sadhukhan@oracle.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190522234545.5930-1-krish.sadhukhan@oracle.com> References: <20190522234545.5930-1-krish.sadhukhan@oracle.com> MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=nai engine=6000 definitions=9265 signatures=668687 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 suspectscore=13 malwarescore=0 phishscore=0 bulkscore=0 spamscore=0 mlxscore=0 mlxlogscore=999 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1810050000 definitions=main-1905220168 X-Proofpoint-Virus-Version: vendor=nai engine=6000 definitions=9265 signatures=668687 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 priorityscore=1501 malwarescore=0 suspectscore=13 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=999 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1810050000 definitions=main-1905220168 Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Signed-off-by: Krish Sadhukhan Reviewed-by: Karl Heubaum --- lib/x86/processor.h | 8 ++++++++ x86/vmexit.c | 2 +- 2 files changed, 9 insertions(+), 1 deletion(-) diff --git a/lib/x86/processor.h b/lib/x86/processor.h index 15237a5..2ca988e 100644 --- a/lib/x86/processor.h +++ b/lib/x86/processor.h @@ -476,4 +476,12 @@ static inline void set_bit(int bit, u8 *addr) : "+m" (*addr) : "Ir" (bit) : "cc", "memory"); } +static inline int efer_nx_enabled(void) +{ + if (cpuid(0x80000001).d & (1 << 20)) + return 1; + else + return 0; +} + #endif diff --git a/x86/vmexit.c b/x86/vmexit.c index c12dd24..7053a46 100644 --- a/x86/vmexit.c +++ b/x86/vmexit.c @@ -526,7 +526,7 @@ static bool do_test(struct test *test) static void enable_nx(void *junk) { - if (cpuid(0x80000001).d & (1 << 20)) + if (efer_nx_enabled()) wrmsr(MSR_EFER, rdmsr(MSR_EFER) | EFER_NX_MASK); } From patchwork Wed May 22 23:45:45 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Krish Sadhukhan X-Patchwork-Id: 10956797 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id EABD9933 for ; Thu, 23 May 2019 00:12:55 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id E7B3E26E82 for ; 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Thu, 23 May 2019 00:12:02 GMT Received: from aserv0122.oracle.com (aserv0122.oracle.com [141.146.126.236]) by userp3020.oracle.com with ESMTP id 2smsgv5vwc-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Thu, 23 May 2019 00:12:02 +0000 Received: from abhmp0017.oracle.com (abhmp0017.oracle.com [141.146.116.23]) by aserv0122.oracle.com (8.14.4/8.14.4) with ESMTP id x4N0C1Ir020256; Thu, 23 May 2019 00:12:01 GMT Received: from ban25x6uut29.us.oracle.com (/10.153.73.29) by default (Oracle Beehive Gateway v4.0) with ESMTP ; Thu, 23 May 2019 00:12:01 +0000 From: Krish Sadhukhan To: kvm@vger.kernel.org Cc: rkrcmar@redhat.com, pbonzini@redhat.com, jmattson@google.com Subject: [PATCH 2/2] kvm-unit-test: nVMX: Test "Load IA32_EFER" VM-exit control on vmentry of nested guests Date: Wed, 22 May 2019 19:45:45 -0400 Message-Id: <20190522234545.5930-3-krish.sadhukhan@oracle.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190522234545.5930-1-krish.sadhukhan@oracle.com> References: <20190522234545.5930-1-krish.sadhukhan@oracle.com> MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=nai engine=6000 definitions=9265 signatures=668687 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 suspectscore=13 malwarescore=0 phishscore=0 bulkscore=0 spamscore=0 mlxscore=0 mlxlogscore=999 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1810050000 definitions=main-1905220168 X-Proofpoint-Virus-Version: vendor=nai engine=6000 definitions=9265 signatures=668687 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 priorityscore=1501 malwarescore=0 suspectscore=13 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=999 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1810050000 definitions=main-1905220168 Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP ..to verify KVM performs the appropriate consistency checks for loading IA32_EFER VM-exit control as part of running a nested guest. According to section "Checks on Host Control Registers and MSRs" in Intel SDM vol 3C, the following checks are performed on vmentry of nested guests: If the “load IA32_EFER” VM-exit control is 1, bits reserved in the IA32_EFER MSR must be 0 in the field for that register. In addition, the values of the LMA and LME bits in the field must each be that of the “host address-space size” VM-exit control. Signed-off-by: Krish Sadhukhan Reviewed-by: Karl Heubaum --- x86/vmx_tests.c | 121 ++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 121 insertions(+) diff --git a/x86/vmx_tests.c b/x86/vmx_tests.c index 8cb1708..32fa16d 100644 --- a/x86/vmx_tests.c +++ b/x86/vmx_tests.c @@ -5136,6 +5136,126 @@ static void test_guest_perf_global_ctl(void) ENT_CONTROLS, ENT_LOAD_PERF); } +static void test_efer_bit(u32 fld, const char * fld_name, u32 ctrl_fld, + u64 ctrl_bit, u64 efer_bit, + const char *efer_bit_name) +{ + u64 efer_saved = vmcs_read(fld); + u32 ctrl_saved = vmcs_read(ctrl_fld); + u64 host_addr_size = ctrl_saved & EXI_HOST_64; + u64 efer; + + vmcs_write(ctrl_fld, ctrl_saved & ~ctrl_bit); + efer = efer_saved & ~efer_bit; + vmcs_write(fld, efer); + report_prefix_pushf("%s bit turned off, %s %lx", efer_bit_name, + fld_name, efer); + test_vmx_vmlaunch(0, false); + report_prefix_pop(); + + efer = efer_saved | efer_bit; + vmcs_write(fld, efer); + report_prefix_pushf("%s bit turned on, %s %lx", efer_bit_name, + fld_name, efer); + test_vmx_vmlaunch(0, false); + report_prefix_pop(); + + vmcs_write(ctrl_fld, ctrl_saved | ctrl_bit); + efer = efer_saved & ~efer_bit; + vmcs_write(fld, efer); + report_prefix_pushf("%s bit turned off, %s %lx", efer_bit_name, + fld_name, efer); + if (host_addr_size) + test_vmx_vmlaunch(VMXERR_ENTRY_INVALID_HOST_STATE_FIELD, + false); + else + test_vmx_vmlaunch(0, false); + report_prefix_pop(); + + efer = efer_saved | efer_bit; + vmcs_write(fld, efer); + report_prefix_pushf("%s bit turned on, %s %lx", efer_bit_name, + fld_name, efer); + if (host_addr_size) + test_vmx_vmlaunch(0, false); + else + test_vmx_vmlaunch(VMXERR_ENTRY_INVALID_HOST_STATE_FIELD, + false); + report_prefix_pop(); + + vmcs_write(ctrl_fld, ctrl_saved); + vmcs_write(fld, efer_saved); +} + +static void test_efer(u32 fld, const char * fld_name, u32 ctrl_fld, + u64 ctrl_bit) +{ + u64 efer_saved = vmcs_read(fld); + u32 ctrl_saved = vmcs_read(ctrl_fld); + u64 efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA)); + u64 i; + u64 efer; + + if (efer_nx_enabled()) + efer_reserved_bits &= ~EFER_NX; + + /* + * Check reserved bits + */ + vmcs_write(ctrl_fld, ctrl_saved & ~ctrl_bit); + for (i = 0; i < 64; i++) { + if ((1ull << i) & efer_reserved_bits) { + efer = efer_saved | (1ull << i); + vmcs_write(fld, efer); + report_prefix_pushf("%s %lx", fld_name, efer); + test_vmx_vmlaunch(0, false); + report_prefix_pop(); + } + } + + vmcs_write(ctrl_fld, ctrl_saved | ctrl_bit); + for (i = 0; i < 64; i++) { + if ((1ull << i) & efer_reserved_bits) { + efer = efer_saved | (1ull << i); + vmcs_write(fld, efer); + report_prefix_pushf("%s %lx", fld_name, efer); + test_vmx_vmlaunch( + VMXERR_ENTRY_INVALID_HOST_STATE_FIELD, + false); + report_prefix_pop(); + } + } + + vmcs_write(ctrl_fld, ctrl_saved); + vmcs_write(fld, efer_saved); + + /* + * Check LMA and LME bits + */ + test_efer_bit(fld, fld_name, ctrl_fld, ctrl_bit, EFER_LMA, + "EFER_LMA"); + test_efer_bit(fld, fld_name, ctrl_fld, ctrl_bit, EFER_LME, + "EFER_LME"); +} + +/* + * If the “load IA32_EFER” VM-exit control is 1, bits reserved in the + * IA32_EFER MSR must be 0 in the field for that register. In addition, + * the values of the LMA and LME bits in the field must each be that of + * the “host address-space size” VM-exit control. + * + * [Intel SDM] + */ +static void test_host_efer(void) +{ + if (!(ctrl_exit_rev.clr & EXI_LOAD_EFER)) { + printf("\"Load-IA32-EFER\" exit control not supported\n"); + return; + } + + test_efer(HOST_EFER, "HOST_EFER", EXI_CONTROLS, EXI_LOAD_EFER); +} + /* * PAT values higher than 8 are uninteresting since they're likely lumped * in with "8". We only test values above 8 one bit at a time, @@ -5268,6 +5388,7 @@ static void vmx_host_state_area_test(void) test_sysenter_field(HOST_SYSENTER_ESP, "HOST_SYSENTER_ESP"); test_sysenter_field(HOST_SYSENTER_EIP, "HOST_SYSENTER_EIP"); + test_host_efer(); test_host_perf_global_ctl(); test_load_host_pat(); }