From patchwork Fri May 24 23:45:37 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alistair Francis X-Patchwork-Id: 10960609 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id B2D3C76 for ; Sat, 25 May 2019 00:19:40 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id A1E6120453 for ; Sat, 25 May 2019 00:19:40 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 962A6289C0; Sat, 25 May 2019 00:19:40 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.0 required=2.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 4548320453 for ; Sat, 25 May 2019 00:19:40 +0000 (UTC) Received: from localhost ([127.0.0.1]:33742 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hUKPT-0006qm-I9 for patchwork-qemu-devel@patchwork.kernel.org; Fri, 24 May 2019 20:19:39 -0400 Received: from eggs.gnu.org ([209.51.188.92]:60227) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hUK4C-0005Im-Cz for qemu-devel@nongnu.org; Fri, 24 May 2019 19:57:41 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hUJuU-00048m-B1 for qemu-devel@nongnu.org; Fri, 24 May 2019 19:47:39 -0400 Received: from esa5.hgst.iphmx.com ([216.71.153.144]:51627) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1hUJuU-00046f-0J; Fri, 24 May 2019 19:47:38 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1558741659; x=1590277659; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Afx3i4e+/e/6vVqAletdTzpjrs6vkjl1vDNfsdulAjY=; b=JQ6Ozg0pdlrtLcDrYdQAuH619iAtDRjuVKDrWnEIVnqChjgDZUBhhl1k TxNSRyiL2eWGie8RYQjYbAdFqk+5wny04Bf77ggTDRiiYg9lILoxQVAUj 0q248wq+U7bOF8iqJJNWcpHPAM9K9sR4gvEKM6+XzZzhkH627GiWWICXQ FWGj/6n1XDAFidxZC+4rbuQrrjhh8qCj8WO5/l2FvXW+KarQZiPs4IEz+ 4u2PSqLLr1PX1Ww/JMOgHIhX23duFKlMXPWhjbT6+MC/PFFEx0J6GM2VV TTzgfuta0CBnSsiZljhm0jpCbgtclhFrGn9QenYFe7uM5R6Zg/rU4HPt7 w==; X-IronPort-AV: E=Sophos;i="5.60,508,1549900800"; d="scan'208";a="110307754" Received: from h199-255-45-14.hgst.com (HELO uls-op-cesaep01.wdc.com) ([199.255.45.14]) by ob1.hgst.iphmx.com with ESMTP; 25 May 2019 07:47:33 +0800 IronPort-SDR: FkAcRe98pwH2icirvF/sqLrqcGL3aUBrt2xK4L/Mg8Itw/EfsLZPnbq4UZdJH/D5jlH9Ha+Ob8 Q7J3ix3tLTLNMgMvIRtGQyw85RVbES6yDGavDF4uX8IaopRDKu4cssj9mlNp3132dutXICawE8 4HT0si9SAYkGb12nPMk7awv+H6gbsVk8lBrsBwg81KgKYYqYpun0rcHmmV78lTBUGHpKkKyNiI dwjfQ9DJpXylPBJV914cdv6T9pfmDZOPKVXu50prpk+bMBHcvZ8cmIweeNqURVF076rQhpGxsK Ys1+Lxqc/2Dyh8u8HNnB/h0+ Received: from uls-op-cesaip02.wdc.com ([10.248.3.37]) by uls-op-cesaep01.wdc.com with ESMTP; 24 May 2019 16:22:51 -0700 IronPort-SDR: 5TTr37oCle647gG7iHm3tJP6HuZTxzsH0P3pNdgd7kiL4NzQ5I2gMsk5ZbaA7fi4u6rU33ijul jEjh5QAyChG0mMEfaTMk/S8BkqnQJluA9vihsgbxK6Kr2eecB2K5h3eoBM0myLDzHF0fDUL5lA 1vj+deQ5VvSRDXZZK23bleIF9gzsdkVgANa8G0CdKmk4Qa0xOp4fr+bDN2Og21oPKSnZtU7ynB 2h1fAmxC2e98c63b7LdoXU6u6lcqs17xjB7WhdqJMQdeInhpfwxOwBhui0eFx7QisJpVsg2JJK q5c= Received: from risc6-mainframe.sdcorp.global.sandisk.com (HELO risc6-mainframe.int.fusionio.com) ([10.196.157.140]) by uls-op-cesaip02.wdc.com with ESMTP; 24 May 2019 16:47:32 -0700 From: Alistair Francis To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Date: Fri, 24 May 2019 16:45:37 -0700 Message-Id: <5b489a8f97b84a7c1b428b9deb2ceef2f04a8de6.1558741334.git.alistair.francis@wdc.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: References: MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 216.71.153.144 Subject: [Qemu-devel] [RFC v1 01/23] target/riscv: Don't set write permissions on dirty PTEs X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair23@gmail.com, palmer@sifive.com, alistair.francis@wdc.com Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP Setting write permission on dirty PTEs results in userspace inside a Hypervisor guest (VU) becoming corrupted. This appears to be becuase it ends up with write permission in the second stage translation in cases where we aren't doing a store. Signed-off-by: Alistair Francis --- target/riscv/cpu_helper.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index b1bee3d45d..872835177a 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -326,10 +326,8 @@ restart: if ((pte & PTE_X)) { *prot |= PAGE_EXEC; } - /* add write permission on stores or if the page is already dirty, - so that we TLB miss on later writes to update the dirty bit */ - if ((pte & PTE_W) && - (access_type == MMU_DATA_STORE || (pte & PTE_D))) { + /* add write permission on stores */ + if ((pte & PTE_W) && (access_type == MMU_DATA_STORE)) { *prot |= PAGE_WRITE; } return TRANSLATE_SUCCESS; From patchwork Fri May 24 23:45:40 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alistair Francis X-Patchwork-Id: 10960599 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 7782F933 for ; Sat, 25 May 2019 00:13:40 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 67731289A9 for ; Sat, 25 May 2019 00:13:40 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 5BFC3289AB; Sat, 25 May 2019 00:13:40 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.0 required=2.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 16563289A9 for ; Sat, 25 May 2019 00:13:39 +0000 (UTC) Received: from localhost ([127.0.0.1]:33654 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hUKJf-0002yd-7a for patchwork-qemu-devel@patchwork.kernel.org; Fri, 24 May 2019 20:13:39 -0400 Received: from eggs.gnu.org ([209.51.188.92]:60399) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hUK4B-0005au-SD for qemu-devel@nongnu.org; Fri, 24 May 2019 19:57:40 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hUJuV-00049B-1K for qemu-devel@nongnu.org; Fri, 24 May 2019 19:47:39 -0400 Received: from esa5.hgst.iphmx.com ([216.71.153.144]:51624) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1hUJuU-00043c-Mo; Fri, 24 May 2019 19:47:38 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1558741660; x=1590277660; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Ao9gCKvSoFwU8QM28M/2smcm/7HnPQ04kDU0bSYTT4c=; b=LjpxKAVl59GihkIhlDqlGxptAk7eFT41ajImGuDiN1hvp44H2vEMMudD xlGjnl7fYIx9jD06F43VX7MOqdVlDP+KPbKz8RcaY0HqIwOITYgSNePSU OUNJ5jQlwmiFBIHL02d8y2n9v4E9tO9/v57/m5XuQ6O+zjAHSOtdy/ixD MnY/KyXN9o87HfyQYJRifvIQuPdBgmTiUFB9AclvLs5bW1OL11WhiDjqH 5o5Z6KmNq8ZRLjKZk1DhNgLMbZJHmLF2llKuiwB2GDyAI995DZYXuvC3l 692dyUlf2siGciNQoZYR+3HWAn7bhoSRKR9JGlMLRR4jc793m93lY5ZI2 A==; X-IronPort-AV: E=Sophos;i="5.60,508,1549900800"; d="scan'208";a="110307756" Received: from h199-255-45-14.hgst.com (HELO uls-op-cesaep01.wdc.com) ([199.255.45.14]) by ob1.hgst.iphmx.com with ESMTP; 25 May 2019 07:47:36 +0800 IronPort-SDR: M4vZR1WT3BnaDfJn6gm5ZrtaWUWxrGlajA66TCYNwu7ZQ/x7Nai3ZQp1O/tNxedV7jCqOsbtw2 jqF0iKreY0/Gia7bVKxhIN0LrNqQThmjUAUCF1NfwreoHzO7MRzoP6jN2Hli048gJipqs/TzFU KWZdRYi2a3jSX5/cnKq97jH8IhFbAOD+vpoaPx4Ka/d/iNitxfLYBR08saLzEPCsew/5pi2lQU oz+IJ+p4NCKIy0+o5QGdQvxeTddTyvEQ/KpJp2/WhD57eRml/rr0hJiv9S+ECzj25YIQwtNWi2 lS+iA+KvNNrym3vT/71eI2AZ Received: from uls-op-cesaip02.wdc.com ([10.248.3.37]) by uls-op-cesaep01.wdc.com with ESMTP; 24 May 2019 16:22:53 -0700 IronPort-SDR: Z9W+cSivcv6Qg7ANGLOVFQAudsfnCj9b17C38Ak/aZJSvs6TwyudBf9emLGuUGhgvvYDeWn+S0 wQhdCC2HiFh//oVaLxY0u/fSJxZcV4qYVPncTVO36O80RLzWygs0nw2n+ncAa3MKJHhszLPmwH va17x86+kd9sFE19QsaEh5zAPEEJ9rK9qlQlZM7+5Zu83qFkQogfheRYt6hUchERzbJZ7v2okH CBJb7Vt60XzuC/KdIINYr6Gsyszo6voyb76ZcQUHCfqazXAf0CKcGyZc/EZuYpKVCV4udAyR5G 0iI= Received: from risc6-mainframe.sdcorp.global.sandisk.com (HELO risc6-mainframe.int.fusionio.com) ([10.196.157.140]) by uls-op-cesaip02.wdc.com with ESMTP; 24 May 2019 16:47:34 -0700 From: Alistair Francis To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Date: Fri, 24 May 2019 16:45:40 -0700 Message-Id: <668f55005ffe96a231306ba4d8022e43142b25f5.1558741334.git.alistair.francis@wdc.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: References: MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 216.71.153.144 Subject: [Qemu-devel] [RFC v1 02/23] target/riscv: Add the Hypervisor extension X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair23@gmail.com, palmer@sifive.com, alistair.francis@wdc.com Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 1 + 1 file changed, 1 insertion(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 8937bda918..3337d1aef3 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -81,6 +81,7 @@ #define RVC RV('C') #define RVS RV('S') #define RVU RV('U') +#define RVH RV('H') /* S extension denotes that Supervisor mode exists, however it is possible to have a core that support S mode but does not have an MMU and there From patchwork Fri May 24 23:45:43 2019 Content-Type: text/plain; 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24 May 2019 16:22:56 -0700 IronPort-SDR: 52HxRoIK83FXMmBgnXauBoo2AWL+DxFiO8hleuX9iT/Gzt0FL0mg4vcqY/PkdS+5+6bM5upiD8 C/hgCkbnzUg/I+xTEd7Ornr261adobfoBmXwIDNGRi8UMsVsRUlks0QbPokYbAZ1YkGehPl5u0 JfH9Q01ohSt9Z/8/5z/U02r1BZlcfhYZqVHdVyuepGIbg/4J0BI3rgVYCzB6QJG/Bwr3WOes9J sXvgI/foLrqrcOg4kXf4IoWvFom5B4TftxP5d6YLhB+dsAA/Nfu4sh7yPPMVM8pKgDSYSV2hCd /xs= Received: from risc6-mainframe.sdcorp.global.sandisk.com (HELO risc6-mainframe.int.fusionio.com) ([10.196.157.140]) by uls-op-cesaip02.wdc.com with ESMTP; 24 May 2019 16:47:37 -0700 From: Alistair Francis To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Date: Fri, 24 May 2019 16:45:43 -0700 Message-Id: <6ac178e4f6ce4a8286ccf015b3f7b5c42277b3db.1558741334.git.alistair.francis@wdc.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: References: MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 216.71.153.144 Subject: [Qemu-devel] [RFC v1 03/23] target/riscv: Add the virtulisation mode X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair23@gmail.com, palmer@sifive.com, alistair.francis@wdc.com Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 4 ++++ target/riscv/cpu_bits.h | 6 ++++++ target/riscv/cpu_helper.c | 23 +++++++++++++++++++++++ 3 files changed, 33 insertions(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 3337d1aef3..de4843b879 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -132,6 +132,8 @@ struct CPURISCVState { #ifndef CONFIG_USER_ONLY target_ulong priv; + /* This contains QEMU specific information about the virt state. */ + target_ulong virt; target_ulong resetvec; target_ulong mhartid; @@ -278,6 +280,8 @@ void riscv_cpu_do_interrupt(CPUState *cpu); int riscv_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request); +bool riscv_cpu_virt_enabled(CPURISCVState *env); +void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable); int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch); hwaddr riscv_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index dc9d53d4be..07c95e8d2c 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -417,6 +417,12 @@ #define PRV_H 2 /* Reserved */ #define PRV_M 3 +/* Virtulisation modes */ +#define VIRT_OFF 0 +#define VIRT_ON 1 +#define VIRT_MODE_SHIFT 0 +#define VIRT_MODE_MASK (1 << VIRT_MODE_SHIFT) + /* RV32 satp CSR field masks */ #define SATP32_MODE 0x80000000 #define SATP32_ASID 0x7fc00000 diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 872835177a..5912ae63b7 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -71,6 +71,29 @@ bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request) #if !defined(CONFIG_USER_ONLY) +bool riscv_cpu_virt_enabled(CPURISCVState *env) +{ + bool tmp; + + if (!riscv_has_ext(env, RVH)) { + return false; + } + + tmp = (env->virt & VIRT_MODE_MASK) >> VIRT_MODE_SHIFT; + + return tmp == VIRT_ON; +} + +void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable) +{ + if (!riscv_has_ext(env, RVH)) { + return; + } + + env->virt &= ~VIRT_MODE_MASK; + env->virt |= enable << VIRT_MODE_SHIFT; +} + int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint32_t interrupts) { CPURISCVState *env = &cpu->env; From patchwork Fri May 24 23:45:45 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alistair Francis X-Patchwork-Id: 10960577 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 27A19933 for ; Sat, 25 May 2019 00:05:21 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 17D8C28831 for ; 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24 May 2019 16:47:41 -0700 From: Alistair Francis To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Date: Fri, 24 May 2019 16:45:45 -0700 Message-Id: X-Mailer: git-send-email 2.21.0 In-Reply-To: References: MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 216.71.153.144 Subject: [Qemu-devel] [RFC v1 04/23] target/riscv: Add the force HS exception mode X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair23@gmail.com, palmer@sifive.com, alistair.francis@wdc.com Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 2 ++ target/riscv/cpu_bits.h | 6 ++++++ target/riscv/cpu_helper.c | 23 +++++++++++++++++++++++ 3 files changed, 31 insertions(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index de4843b879..eeb3756c91 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -282,6 +282,8 @@ int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request); bool riscv_cpu_virt_enabled(CPURISCVState *env); void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable); +bool riscv_cpu_force_hs_excep_enabled(CPURISCVState *env); +void riscv_cpu_set_force_hs_excep(CPURISCVState *env, bool enable); int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch); hwaddr riscv_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 07c95e8d2c..c898bb1102 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -423,6 +423,12 @@ #define VIRT_MODE_SHIFT 0 #define VIRT_MODE_MASK (1 << VIRT_MODE_SHIFT) +/* HS-level exceptions modes */ +#define CLEAR_HS_EXCEP 0 +#define FORCE_HS_EXCEP 1 +#define FORCE_HS_EXCEP_SHIFT 1 +#define FORCE_HS_EXCEP_MASK (1 << FORCE_HS_EXCEP_SHIFT) + /* RV32 satp CSR field masks */ #define SATP32_MODE 0x80000000 #define SATP32_ASID 0x7fc00000 diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 5912ae63b7..0fdc81f71f 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -94,6 +94,29 @@ void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable) env->virt |= enable << VIRT_MODE_SHIFT; } +bool riscv_cpu_force_hs_excep_enabled(CPURISCVState *env) +{ + bool tmp; + + if (!riscv_has_ext(env, RVH)) { + return false; + } + + tmp = (env->virt & FORCE_HS_EXCEP_MASK) >> FORCE_HS_EXCEP_SHIFT; + + return tmp == FORCE_HS_EXCEP; +} + +void riscv_cpu_set_force_hs_excep(CPURISCVState *env, bool enable) +{ + if (!riscv_has_ext(env, RVH)) { + return; + } + + env->virt &= ~FORCE_HS_EXCEP_MASK; + env->virt |= enable << FORCE_HS_EXCEP_SHIFT; +} + int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint32_t interrupts) { CPURISCVState *env = &cpu->env; From patchwork Fri May 24 23:45:48 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alistair Francis X-Patchwork-Id: 10960605 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 9D2DC76 for ; Sat, 25 May 2019 00:17:21 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 8B332289AA for ; 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24 May 2019 16:47:43 -0700 From: Alistair Francis To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Date: Fri, 24 May 2019 16:45:48 -0700 Message-Id: X-Mailer: git-send-email 2.21.0 In-Reply-To: References: MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 216.71.153.144 Subject: [Qemu-devel] [RFC v1 05/23] target/riscv: Add the Hypervisor CSRs to CPUState X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair23@gmail.com, palmer@sifive.com, alistair.francis@wdc.com Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index eeb3756c91..b99d2b7af2 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -169,12 +169,29 @@ struct CPURISCVState { target_ulong mcause; target_ulong mtval; /* since: priv-1.10.0 */ + /* Hypervisor CSRs */ + target_ulong hstatus; + target_ulong hedeleg; + target_ulong hideleg; + target_ulong hgatp; + target_ulong scounteren; target_ulong mcounteren; target_ulong sscratch; target_ulong mscratch; + /* Background CSRs */ + target_ulong bsstatus; + target_ulong bsip; + target_ulong bsie; + target_ulong bstvec; + target_ulong bsscratch; + target_ulong bsepc; + target_ulong bscause; + target_ulong bstval; + target_ulong bsatp; + /* temporary htif regs */ uint64_t mfromhost; uint64_t mtohost; From patchwork Fri May 24 23:45:51 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alistair Francis X-Patchwork-Id: 10960603 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id D01DF76 for ; Sat, 25 May 2019 00:16:14 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id BE76120453 for ; Sat, 25 May 2019 00:16:14 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id B069B289AA; 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X-Received-From: 216.71.153.144 Subject: [Qemu-devel] [RFC v1 06/23] target/riscv: Dump Hypervisor registers if enabled X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair23@gmail.com, palmer@sifive.com, alistair.francis@wdc.com Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP Signed-off-by: Alistair Francis --- target/riscv/cpu.c | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 65556ac543..c1495ef037 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -220,14 +220,41 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags) #ifndef CONFIG_USER_ONLY qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mhartid ", env->mhartid); qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatus ", env->mstatus); + if (riscv_has_ext(env, RVH)) { + qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "hstatus ", env->hstatus); + qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "bstatus ", env->bsstatus); + } qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mip ", (target_ulong)atomic_read(&env->mip)); + if (riscv_has_ext(env, RVH)) { + qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "bsip ", + (target_ulong)atomic_read(&env->bsip)); + } qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mie ", env->mie); + if (riscv_has_ext(env, RVH)) { + qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "bsie ", env->bsie); + } qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mideleg ", env->mideleg); + if (riscv_has_ext(env, RVH)) { + qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "hideleg ", env->hideleg); + } qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "medeleg ", env->medeleg); + if (riscv_has_ext(env, RVH)) { + qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "hedeleg ", env->hedeleg); + } qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mtvec ", env->mtvec); + if (riscv_has_ext(env, RVH)) { + qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "bstvec ", env->bstvec); + } qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mepc ", env->mepc); + qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "sepc ", env->sepc); + if (riscv_has_ext(env, RVH)) { + qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "bsepc ", env->bsepc); + } qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mcause ", env->mcause); + if (riscv_has_ext(env, RVH)) { + qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "bscause ", env->bscause); + } #endif for (i = 0; i < 32; i++) { From patchwork Fri May 24 23:45:53 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alistair Francis X-Patchwork-Id: 10960591 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id DCBA5933 for ; Sat, 25 May 2019 00:10:42 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id CAAFB289C4 for ; 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24 May 2019 16:47:48 -0700 From: Alistair Francis To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Date: Fri, 24 May 2019 16:45:53 -0700 Message-Id: <6706cf56683e5a934ca90f0ea09d03987d86b608.1558741334.git.alistair.francis@wdc.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: References: MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 216.71.153.144 Subject: [Qemu-devel] [RFC v1 07/23] target/riscv: Remove strict perm checking for CSR R/W X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair23@gmail.com, palmer@sifive.com, alistair.francis@wdc.com Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP The privledge check based on the CSR address mask 0x300 doesn't work when using Hypervisor extensions so remove the check Signed-off-by: Alistair Francis --- target/riscv/csr.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index e6d68a9956..c1fcb795cd 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -771,9 +771,8 @@ int riscv_csrrw(CPURISCVState *env, int csrno, target_ulong *ret_value, /* check privileges and return -1 if check fails */ #if !defined(CONFIG_USER_ONLY) - int csr_priv = get_field(csrno, 0x300); int read_only = get_field(csrno, 0xC00) == 3; - if ((write_mask && read_only) || (env->priv < csr_priv)) { + if (write_mask && read_only) { return -1; } #endif From patchwork Fri May 24 23:45:56 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alistair Francis X-Patchwork-Id: 10960583 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id E61C813AD for ; Sat, 25 May 2019 00:07:51 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id D69D5288BC for ; Sat, 25 May 2019 00:07:51 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id CB09D28999; Sat, 25 May 2019 00:07:51 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.0 required=2.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 67239289B5 for ; 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X-Received-From: 216.71.153.141 Subject: [Qemu-devel] [RFC v1 08/23] target/riscv: Add support for background interrupt setting X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair23@gmail.com, palmer@sifive.com, alistair.francis@wdc.com Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP Signed-off-by: Alistair Francis --- target/riscv/cpu_helper.c | 19 +++++++++++++++++-- 1 file changed, 17 insertions(+), 2 deletions(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 0fdc81f71f..1f466effcf 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -38,12 +38,27 @@ static int riscv_cpu_local_irq_pending(CPURISCVState *env) { target_ulong mstatus_mie = get_field(env->mstatus, MSTATUS_MIE); target_ulong mstatus_sie = get_field(env->mstatus, MSTATUS_SIE); + target_ulong bsstatus_sie = get_field(env->bsstatus, MSTATUS_SIE); + target_ulong pending = atomic_read(&env->mip) & env->mie; - target_ulong mie = env->priv < PRV_M || (env->priv == PRV_M && mstatus_mie); - target_ulong sie = env->priv < PRV_S || (env->priv == PRV_S && mstatus_sie); + target_ulong hspending = atomic_read(&env->bsip) & env->bsie; + + target_ulong mie = env->priv < PRV_M || (env->priv == PRV_M && mstatus_mie); + target_ulong sie = env->priv < PRV_S || (env->priv == PRV_S && mstatus_sie); + target_ulong bsie = env->priv < PRV_S || (env->priv == PRV_S && bsstatus_sie); + target_ulong irqs = (pending & ~env->mideleg & -mie) | (pending & env->mideleg & -sie); + if (riscv_cpu_virt_enabled(env)) { + target_ulong pending_hs_irq = hspending & -bsie; + + if (pending_hs_irq) { + riscv_cpu_set_force_hs_excep(env, FORCE_HS_EXCEP); + return ctz64(pending_hs_irq); + } + } + if (irqs) { return ctz64(irqs); /* since non-zero */ } else { From patchwork Fri May 24 23:45:58 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alistair Francis X-Patchwork-Id: 10960601 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 40EDA76 for ; Sat, 25 May 2019 00:15:04 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 30D38289BC for ; Sat, 25 May 2019 00:15:04 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 25468289BF; Sat, 25 May 2019 00:15:04 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.0 required=2.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id A7E59287C5 for ; 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24 May 2019 16:25:32 -0700 IronPort-SDR: Z9hnk5mJfGfa5kUfWqU0jXKJtKjnH2NBQJ0EqyELhlXBn7Wg0zunv/aBM6SN9CQmpzkHm3PI2M QjYX1RaYK/01otSUApQzai/gxuglQ7l4aFbXWvEi4wajPb2hqmVQQa5vfQ7FYjaWmqF5FADqSj D7gdUuR2MyXEIG2QzcWdH6bE9Ptu1kkcoXDYFnqmbUYiJrxCCHxhx7L1/sHRyC5FOQbpVfH0mT s9SAdGQRiRq79uvozIXqAndyvXehymrHG6NqVTOnnIs1ejaX4VXBydBKMsgFO0LE1cliTmavh4 MOw= Received: from risc6-mainframe.sdcorp.global.sandisk.com (HELO risc6-mainframe.int.fusionio.com) ([10.196.157.140]) by uls-op-cesaip01.wdc.com with ESMTP; 24 May 2019 16:47:54 -0700 From: Alistair Francis To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Date: Fri, 24 May 2019 16:45:58 -0700 Message-Id: X-Mailer: git-send-email 2.21.0 In-Reply-To: References: MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 216.71.153.144 Subject: [Qemu-devel] [RFC v1 09/23] target/riscv: Add Hypervisor CSR access functions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair23@gmail.com, palmer@sifive.com, alistair.francis@wdc.com Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP Signed-off-by: Alistair Francis --- target/riscv/csr.c | 68 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 68 insertions(+) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index c1fcb795cd..c52fde6e7f 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -82,6 +82,20 @@ static int smode(CPURISCVState *env, int csrno) return -!riscv_has_ext(env, RVS); } +static int hmode(CPURISCVState *env, int csrno) +{ + if (riscv_has_ext(env, RVS) && + riscv_has_ext(env, RVH)) { + /* Hypervisor extension is supported */ + if ((env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) || + env->priv == PRV_M) { + return 0; + } + } + + return -1; +} + static int pmp(CPURISCVState *env, int csrno) { return -!riscv_feature(env, RISCV_FEATURE_PMP); @@ -727,6 +741,55 @@ static int write_satp(CPURISCVState *env, int csrno, target_ulong val) return 0; } +/* Hypervisor Extensions */ +static int read_hstatus(CPURISCVState *env, int csrno, target_ulong *val) +{ + *val = env->hstatus; + return 0; +} + +static int write_hstatus(CPURISCVState *env, int csrno, target_ulong val) +{ + env->hstatus = val; + return 0; +} + +static int read_hedeleg(CPURISCVState *env, int csrno, target_ulong *val) +{ + *val = env->hedeleg; + return 0; +} + +static int write_hedeleg(CPURISCVState *env, int csrno, target_ulong val) +{ + env->hedeleg = val; + return 0; +} + +static int read_hideleg(CPURISCVState *env, int csrno, target_ulong *val) +{ + *val = env->hideleg; + return 0; +} + +static int write_hideleg(CPURISCVState *env, int csrno, target_ulong val) +{ + env->hideleg = val; + return 0; +} + +static int read_hgatp(CPURISCVState *env, int csrno, target_ulong *val) +{ + *val = env->hgatp; + return 0; +} + +static int write_hgatp(CPURISCVState *env, int csrno, target_ulong val) +{ + env->hgatp = val; + return 0; +} + /* Physical Memory Protection */ static int read_pmpcfg(CPURISCVState *env, int csrno, target_ulong *val) { @@ -910,6 +973,11 @@ static riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { /* Supervisor Protection and Translation */ [CSR_SATP] = { smode, read_satp, write_satp }, + [CSR_HSTATUS] = { hmode, read_hstatus, write_hstatus }, + [CSR_HEDELEG] = { hmode, read_hedeleg, write_hedeleg }, + [CSR_HIDELEG] = { hmode, read_hideleg, write_hideleg }, + [CSR_HGATP] = { hmode, read_hgatp, write_hgatp }, + /* Physical Memory Protection */ [CSR_PMPCFG0 ... CSR_PMPADDR9] = { pmp, read_pmpcfg, write_pmpcfg }, [CSR_PMPADDR0 ... CSR_PMPADDR15] = { pmp, read_pmpaddr, write_pmpaddr }, From patchwork Fri May 24 23:46:01 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alistair Francis X-Patchwork-Id: 10960569 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id DF391933 for ; Sat, 25 May 2019 00:02:00 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id CE5172888D for ; Sat, 25 May 2019 00:02:00 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id C083928998; Sat, 25 May 2019 00:02:00 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.0 required=2.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id A58002898C for ; Sat, 25 May 2019 00:01:59 +0000 (UTC) Received: from localhost ([127.0.0.1]:33442 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hUK8M-0001cE-VW for patchwork-qemu-devel@patchwork.kernel.org; Fri, 24 May 2019 20:01:59 -0400 Received: from eggs.gnu.org ([209.51.188.92]:60254) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hUK43-0005Kz-Lx for qemu-devel@nongnu.org; Fri, 24 May 2019 19:57:32 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hUJun-0004Mj-2P for qemu-devel@nongnu.org; Fri, 24 May 2019 19:48:00 -0400 Received: from esa5.hgst.iphmx.com ([216.71.153.144]:51627) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1hUJum-00046f-K6; Fri, 24 May 2019 19:47:57 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1558741677; x=1590277677; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=6UOMESq+sGSeNp31YuaAf4E6LnUDjRVfecs88kpoRRw=; b=SzpT+bCc9eQhK+Ohv7ilck76v3Cz+p4warf/FvvvWsRPJls5vCI91XDZ MIpFdUsNyVMC3DW+rFvgO0V5KSxeIQ6B3YIuCl+jNCf4B8+VTfC3PmQ+c PS0IYT40Ax1ItxR8sjii4332o+FPCL0rACLX73jZFVjE/3+5oBFx154yq 7TREDxWoW7pHwhZpf8OkkO3tS3TT0ZpwzlyeWJ83cIrUWmw0LAcD/lkzJ iGMEybeqz01fONT9BQ5uTM1YJMh8Eeadvs3OaFh7mBi8D/eQEGOyP5M3P y/5CaXsSu5jBla6ijQ5W03V77FCXCSpQp8rVnnqgZKpRV8T9sU5eFCWH6 Q==; X-IronPort-AV: E=Sophos;i="5.60,508,1549900800"; d="scan'208";a="110307767" Received: from uls-op-cesaip02.wdc.com (HELO uls-op-cesaep02.wdc.com) ([199.255.45.15]) by ob1.hgst.iphmx.com with ESMTP; 25 May 2019 07:47:57 +0800 IronPort-SDR: b9YU08yZ1e/cDm7n2RYhU3DfylGXyfyKWZLMwaaihyLDR7HkXTqEC550pACmOJmwJUJ9PI1FWl BITucjTTXaHpRrLaunUf3A6TKw6+8i61erufGrrPxKE4gfbKoQVSQjMK5yCugsOeEVA2LrDduE W27H89zjvY/tkGmdKFKairn2cAprgsqSDn5oWsZX3prAy/hVnbU5Dpyvs+H1yPqh4tfJ0rs2rs zzq4pmTqpSQqgtWolkT5aU65K6V1f/RZPZYIkOdVWZcWKa3wfcoBEeiYIdQXou87T5SeWP9WBF 2sBpa46QizNzwsaTH4dHfxhN Received: from uls-op-cesaip01.wdc.com ([10.248.3.36]) by uls-op-cesaep02.wdc.com with ESMTP; 24 May 2019 16:25:35 -0700 IronPort-SDR: 4GHc4TPyVjiu0qyZGLftRQE4HpABb+v1Yx4ocqa7NDLrD/Yjj6NAAkhhuaAeScwuHZWsU6gkuT 4fGELERE/hP9JFJJ5E+3vuIRFYitpJZSM5ED/UCbtnUBM9klak/GwAM6JwUxyBy1Gc9HBZHzEU 4x34nLJuWORDZfV6nCnaeclHmg8Wl6LHgmE1ZL5SCnWW3XoF9MKeSWdN8WjVwyDFIwJxgxDS/a V3e/GgDPbd1WZ/yJS03Nsm0c1LRkq0qXOIPTzR+1Lp7FXk2oW8Bp2SmzmHIDf4Jaau36Q2UD9Z kqk= Received: from risc6-mainframe.sdcorp.global.sandisk.com (HELO risc6-mainframe.int.fusionio.com) ([10.196.157.140]) by uls-op-cesaip01.wdc.com with ESMTP; 24 May 2019 16:47:56 -0700 From: Alistair Francis To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Date: Fri, 24 May 2019 16:46:01 -0700 Message-Id: X-Mailer: git-send-email 2.21.0 In-Reply-To: References: MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 216.71.153.144 Subject: [Qemu-devel] [RFC v1 10/23] target/riscv: Add background CSRs accesses X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair23@gmail.com, palmer@sifive.com, alistair.francis@wdc.com Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP Signed-off-by: Alistair Francis --- target/riscv/cpu_bits.h | 11 ++++ target/riscv/csr.c | 119 ++++++++++++++++++++++++++++++++++++++++ 2 files changed, 130 insertions(+) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index c898bb1102..9c27727e6f 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -169,6 +169,17 @@ #define CSR_SPTBR 0x180 #define CSR_SATP 0x180 +/* Background CSRs */ +#define CSR_BSSTATUS 0x200 +#define CSR_BSIE 0x204 +#define CSR_BSTVEC 0x205 +#define CSR_BSSCRATCH 0x240 +#define CSR_BSEPC 0x241 +#define CSR_BSCAUSE 0x242 +#define CSR_BSTVAL 0x243 +#define CSR_BSIP 0x244 +#define CSR_BSATP 0x280 + /* Physical Memory Protection */ #define CSR_PMPCFG0 0x3a0 #define CSR_PMPCFG1 0x3a1 diff --git a/target/riscv/csr.c b/target/riscv/csr.c index c52fde6e7f..908e166426 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -790,6 +790,115 @@ static int write_hgatp(CPURISCVState *env, int csrno, target_ulong val) return 0; } +/* Background CSR Registers */ +static int read_bsstatus(CPURISCVState *env, int csrno, target_ulong *val) +{ + *val = env->bsstatus; + return 0; +} + +static int write_bsstatus(CPURISCVState *env, int csrno, target_ulong val) +{ + env->bsstatus = val; + return 0; +} + +static int read_bsie(CPURISCVState *env, int csrno, target_ulong *val) +{ + *val = env->bsie; + return 0; +} + +static int write_bsie(CPURISCVState *env, int csrno, target_ulong val) +{ + env->bsie = val; + return 0; +} + +static int read_bstvec(CPURISCVState *env, int csrno, target_ulong *val) +{ + *val = env->bstvec; + return 0; +} + +static int write_bstvec(CPURISCVState *env, int csrno, target_ulong val) +{ + env->bstvec = val; + return 0; +} + +static int read_bsscratch(CPURISCVState *env, int csrno, target_ulong *val) +{ + *val = env->bsscratch; + return 0; +} + +static int write_bsscratch(CPURISCVState *env, int csrno, target_ulong val) +{ + env->bsscratch = val; + return 0; +} + +static int read_bsepc(CPURISCVState *env, int csrno, target_ulong *val) +{ + *val = env->bsepc; + return 0; +} + +static int write_bsepc(CPURISCVState *env, int csrno, target_ulong val) +{ + env->bsepc = val; + return 0; +} + +static int read_bscause(CPURISCVState *env, int csrno, target_ulong *val) +{ + *val = env->bscause; + return 0; +} + +static int write_bscause(CPURISCVState *env, int csrno, target_ulong val) +{ + env->bscause = val; + return 0; +} + +static int read_bstval(CPURISCVState *env, int csrno, target_ulong *val) +{ + *val = env->bstval; + return 0; +} + +static int write_bstval(CPURISCVState *env, int csrno, target_ulong val) +{ + env->bstval = val; + return 0; +} + +static int read_bsip(CPURISCVState *env, int csrno, target_ulong *val) +{ + *val = (target_ulong)atomic_read(&env->bsip); + return 0; +} + +static int write_bsip(CPURISCVState *env, int csrno, target_ulong val) +{ + atomic_set(&env->bsip, val); + return 0; +} + +static int read_bsatp(CPURISCVState *env, int csrno, target_ulong *val) +{ + *val = env->bsatp; + return 0; +} + +static int write_bsatp(CPURISCVState *env, int csrno, target_ulong val) +{ + env->bsatp = val; + return 0; +} + /* Physical Memory Protection */ static int read_pmpcfg(CPURISCVState *env, int csrno, target_ulong *val) { @@ -978,6 +1087,16 @@ static riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { [CSR_HIDELEG] = { hmode, read_hideleg, write_hideleg }, [CSR_HGATP] = { hmode, read_hgatp, write_hgatp }, + [CSR_BSSTATUS] = { hmode, read_bsstatus, write_bsstatus }, + [CSR_BSIE] = { hmode, read_bsie, write_bsie }, + [CSR_BSTVEC] = { hmode, read_bstvec, write_bstvec }, + [CSR_BSSCRATCH] = { hmode, read_bsscratch, write_bsscratch }, + [CSR_BSEPC] = { hmode, read_bsepc, write_bsepc }, + [CSR_BSCAUSE] = { hmode, read_bscause, write_bscause }, + [CSR_BSTVAL] = { hmode, read_bstval, write_bstval }, + [CSR_BSIP] = { hmode, read_bsip, write_bsip }, + [CSR_BSATP] = { hmode, read_bsatp, write_bsatp }, + /* Physical Memory Protection */ [CSR_PMPCFG0 ... CSR_PMPADDR9] = { pmp, read_pmpcfg, write_pmpcfg }, [CSR_PMPADDR0 ... CSR_PMPADDR15] = { pmp, read_pmpaddr, write_pmpaddr }, From patchwork Fri May 24 23:46:04 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alistair Francis X-Patchwork-Id: 10960597 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 48D2C933 for ; Sat, 25 May 2019 00:13:21 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 2E6EB21FAD for ; Sat, 25 May 2019 00:13:21 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 23291289A9; Sat, 25 May 2019 00:13:21 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.0 required=2.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id B40E221FAD for ; Sat, 25 May 2019 00:13:20 +0000 (UTC) Received: from localhost ([127.0.0.1]:33652 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hUKJL-0002lb-Rv for patchwork-qemu-devel@patchwork.kernel.org; Fri, 24 May 2019 20:13:19 -0400 Received: from eggs.gnu.org ([209.51.188.92]:60227) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hUK43-0005Im-Uo for qemu-devel@nongnu.org; Fri, 24 May 2019 19:57:33 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hUJup-0004Pn-KM for qemu-devel@nongnu.org; Fri, 24 May 2019 19:48:00 -0400 Received: from esa5.hgst.iphmx.com ([216.71.153.144]:51627) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1hUJup-00046f-9T; Fri, 24 May 2019 19:47:59 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1558741680; x=1590277680; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=al8LxCnIVbOOxV+CyVlDV2vfxMzKewDCHGGm9YaIPx8=; b=qk7ieMjJMmcupPcrKB5VoMNFPOtFjUQNWa8ofJdYX9hqNXRfBGrDMvvy Cz4tHx38/CL08bd9546e3H2xWhihqTxPSY1Xv595jbMg8ONw86lyqj+EW sTqKW8/dmTIvhunpCHiTj6Pc67qO3oVZH5uvpN/TtPFYbr4BS0iOyeHpJ Wr63rvXM4HY7Bhm8R1u9Cq0JYjMpH6u7rv2CFIKILx9BKnXy6CngtH0+/ y7zWlM2zwS7GvhgwXR9x1nqGxYMTmVW1xN9SufBO1T/3lYIXgizi23V96 pvehgBM31EDduiE25WS/NS3nsl9J8zXPFUm5xW+PB83FP3AxdJMgEOKqx Q==; X-IronPort-AV: E=Sophos;i="5.60,508,1549900800"; d="scan'208";a="110307768" Received: from uls-op-cesaip02.wdc.com (HELO uls-op-cesaep02.wdc.com) ([199.255.45.15]) by ob1.hgst.iphmx.com with ESMTP; 25 May 2019 07:47:59 +0800 IronPort-SDR: KgtMtEoXYCkJJxzZmvKUg2rmvtu9pUqBnIQiR0zXFyV1Cy4XZcbYi1/hIaPPk2CYhpsrpNFydX CiNqC07sKxCnAB8fE0QAWyrRiGoHhTK2iyl5kNmu7aB7HFn7yvHw+SK9iL7vgvY6nqXu+eupPR a1T3JYTvGa8/Mq17YwxEuESJtkdWFPtGJERyy4BmWM5HOO9oU+UxtnEQmifM+k3WL5MVqSnkHa qOx1so3cp21YExekbmzgNeIXWglVeVdQ09HtptqFalecR1TweTNCSWV5vqD228RQUhockR29wt rrLjEjlRAG0ibpl8VcxX7BLw Received: from uls-op-cesaip01.wdc.com ([10.248.3.36]) by uls-op-cesaep02.wdc.com with ESMTP; 24 May 2019 16:25:38 -0700 IronPort-SDR: UNkXA2uZYN8Ntjqye84htA1ZmgQ6WCZfSpvGc0aW7/SqXxT1hc3WiaE+/TNTYvjkVm9P8A5Ey+ WW6QdQt343l7RsLMtHGRr3sq7qfYdI72eTdbNtjQJ85asM5fLe+EaTDZwehLOlbg2Q+Sk7+seU /GYNK2KjQic80R4Cl4oHEkuHhWLzhA0l1gqKGLmxkyX5lAgFUBoTKOvdZiOxStA1PPCHnHiU9i ALyPDMmFkJghmDqOPYBTJLJMhC3vLEYQde+D4812eGtRzYskV3Md2D8cp3p/J3VtKyGzPyPuQX S6A= Received: from risc6-mainframe.sdcorp.global.sandisk.com (HELO risc6-mainframe.int.fusionio.com) ([10.196.157.140]) by uls-op-cesaip01.wdc.com with ESMTP; 24 May 2019 16:47:59 -0700 From: Alistair Francis To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Date: Fri, 24 May 2019 16:46:04 -0700 Message-Id: <65714aac56e24d23840b733f0245f9d0b5ecf450.1558741334.git.alistair.francis@wdc.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: References: MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 216.71.153.144 Subject: [Qemu-devel] [RFC v1 11/23] target/riscv: Add background register swapping function X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair23@gmail.com, palmer@sifive.com, alistair.francis@wdc.com Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 1 + target/riscv/cpu_bits.h | 5 ++++ target/riscv/cpu_helper.c | 52 +++++++++++++++++++++++++++++++++++++++ 3 files changed, 58 insertions(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index b99d2b7af2..9897392ab7 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -319,6 +319,7 @@ void riscv_cpu_list(void); #define cpu_mmu_index riscv_cpu_mmu_index #ifndef CONFIG_USER_ONLY +void riscv_cpu_swap_background_regs(CPURISCVState *env); int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint32_t interrupts); uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value); #define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value */ diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 9c27727e6f..28117bdd32 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -550,3 +550,8 @@ #define SIP_SSIP MIP_SSIP #define SIP_STIP MIP_STIP #define SIP_SEIP MIP_SEIP + +/* MIE masks */ +#define MIE_SEIE (1 << IRQ_S_EXT) +#define MIE_STIE (1 << IRQ_S_TIMER) +#define MIE_SSIE (1 << IRQ_S_SOFT) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 1f466effcf..0128546e6a 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -86,6 +86,58 @@ bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request) #if !defined(CONFIG_USER_ONLY) +void riscv_cpu_swap_background_regs(CPURISCVState *env) +{ + RISCVCPU *cpu = riscv_env_get_cpu(env); + target_ulong tmp; + target_ulong mstatus_mask = MSTATUS_MXR | MSTATUS_SUM | MSTATUS_FS | + MSTATUS_SPP | MSTATUS_SPIE | MSTATUS_SIE; + target_ulong sie_mask = MIE_SEIE | MIE_STIE | MIE_SSIE; + + g_assert(riscv_has_ext(env, RVH)); + +#if defined(TARGET_RISCV64) + mstatus_mask |= MSTATUS64_UXL; +#endif + + tmp = env->bsstatus & mstatus_mask; + env->bsstatus = env->mstatus & mstatus_mask; + env->mstatus = (env->mstatus & ~mstatus_mask) | tmp; + + tmp = env->bsie & sie_mask; + env->bsie = env->mie & sie_mask; + env->mie = (env->mie & ~sie_mask) | tmp; + + tmp = env->bstvec; + env->bstvec = env->stvec; + env->stvec = tmp; + + tmp = env->bsscratch; + env->bsscratch = env->sscratch; + env->sscratch = tmp; + + tmp = env->bsepc; + env->bsepc = env->sepc; + env->sepc = tmp; + + tmp = env->bscause; + env->bscause = env->scause; + env->scause = tmp; + + tmp = env->bstval; + env->bstval = env->sbadaddr; + env->sbadaddr = tmp; + + tmp = env->bsatp; + env->bsatp = env->satp; + env->satp = tmp; + + tmp = (target_ulong)atomic_read(&env->bsip); + tmp = riscv_cpu_update_mip(cpu, (MIP_SSIP | MIP_STIP | MIP_SEIP), tmp); + tmp &= MIP_SSIP | MIP_STIP | MIP_SEIP; + atomic_set(&env->bsip, tmp); +} + bool riscv_cpu_virt_enabled(CPURISCVState *env) { bool tmp; From patchwork Fri May 24 23:46:06 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alistair Francis X-Patchwork-Id: 10960595 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id C824413AD for ; Sat, 25 May 2019 00:11:21 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id B894221FAD for ; Sat, 25 May 2019 00:11:21 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id ABDD5287C2; Sat, 25 May 2019 00:11:21 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.0 required=2.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 78B3C21FAD for ; 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24 May 2019 16:23:20 -0700 IronPort-SDR: H5y4FZT1AzMPJPTFs9NlXdoKraJXWK/8i9bCQRqmqpDKaUU9pSBUzY4bEVHjk7pRbyTFUxq39c FNu2u7VOj7fC81GdA9Qu1JhUBwkOajDqsg9+iD2rYFqC9a4/zUAZaPakXEEiH6b5KcUqcA8KYL cJy8uw566pKtnEzyLQ1buXAO8qiDXTdkrXx4aMqDFCknhkte47x1yu4Kl3HzEzHVHHepH7DLfP MykRPGVUoz1sQvQST2EawB/SEWuEOR7Geayou3QEXJarZSeB+QyBmQldCfmiQHqjKBJoe+/izE 40Q= Received: from risc6-mainframe.sdcorp.global.sandisk.com (HELO risc6-mainframe.int.fusionio.com) ([10.196.157.140]) by uls-op-cesaip02.wdc.com with ESMTP; 24 May 2019 16:48:01 -0700 From: Alistair Francis To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Date: Fri, 24 May 2019 16:46:06 -0700 Message-Id: <8f3c0035f813d1294c77aa58238853274f631feb.1558741334.git.alistair.francis@wdc.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: References: MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 68.232.143.124 Subject: [Qemu-devel] [RFC v1 12/23] target/ricsv: Flush the TLB on virtulisation mode changes X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair23@gmail.com, palmer@sifive.com, alistair.francis@wdc.com Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP To ensure our TLB isn't out-of-date we flush it on all virt mode changes. Unlike priv mode this isn't saved in the mmu_idx as all guests share V=1. The easiest option is just to flush on all changes. Signed-off-by: Alistair Francis --- target/riscv/cpu_helper.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 0128546e6a..81f1cc83e5 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -157,6 +157,11 @@ void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable) return; } + /* Flush the TLB on all virt mode changes. */ + if (((env->virt & VIRT_MODE_MASK) >> VIRT_MODE_SHIFT) != enable) { + tlb_flush(CPU(riscv_env_get_cpu(env))); + } + env->virt &= ~VIRT_MODE_MASK; env->virt |= enable << VIRT_MODE_SHIFT; } From patchwork Fri May 24 23:46:09 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alistair Francis X-Patchwork-Id: 10960593 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id E5F4E13AD for ; Sat, 25 May 2019 00:11:20 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id D680E287C2 for ; Sat, 25 May 2019 00:11:20 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id CAF2C289BC; Sat, 25 May 2019 00:11:20 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.0 required=2.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 82D88287C2 for ; Sat, 25 May 2019 00:11:20 +0000 (UTC) Received: from localhost ([127.0.0.1]:33612 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hUKHP-0001Hk-RZ for patchwork-qemu-devel@patchwork.kernel.org; Fri, 24 May 2019 20:11:19 -0400 Received: from eggs.gnu.org ([209.51.188.92]:60399) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hUK42-0005au-AX for qemu-devel@nongnu.org; Fri, 24 May 2019 19:57:31 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hUJuw-0004Ub-Bp for qemu-devel@nongnu.org; Fri, 24 May 2019 19:48:07 -0400 Received: from esa1.hgst.iphmx.com ([68.232.141.245]:5520) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1hUJuv-0004TN-W8; Fri, 24 May 2019 19:48:06 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1558741686; x=1590277686; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=gGFuqft3Gy+jQsmp9J8ov+i4/Ieho2R14R8oFQ3Co8Y=; b=JJjCXtJUdllU8tQwR/u5zZcFDk0sZaERhGLKxtVyPDf3RiPBuGjXJqdv wAwf2oISyk7fl2yF9l4SwQKFPC4B6lsFDxYFyZKHlPdjwE1CNuV3ogdvd fSVvEY0lDCbSifbNRQNq9tPkYGKYDKsIHG61k/FMRfBcqBmLrPcz/veUM mMOznYVly02mO6CyEDdtDurEd5LsrnFkNMMXgUlCh5cweJ2pkU3AiQMJM zF+T7hx9/Rjhn4SZyiO1fhIn8ZrFMOGepKUrdL7qAAbX2JB50oxI8ydks 4VcWWEKCtN0A03/JjPEiwVOq5EhYdSvX9ysmsWsZYDDkho2AHVUkbvd+A A==; X-IronPort-AV: E=Sophos;i="5.60,508,1549900800"; d="scan'208";a="215265016" Received: from uls-op-cesaip02.wdc.com (HELO uls-op-cesaep02.wdc.com) ([199.255.45.15]) by ob1.hgst.iphmx.com with ESMTP; 25 May 2019 07:48:04 +0800 IronPort-SDR: FIZK7D33MqSuWYJOMmcc+Gf+Fx4B8kzn0tVrJgzNN6cxfGxG9+MBEezQtBC/aCraz+y+fxK8kG Zjb2dx7d0HXrJH4ooclj8pqfjh4awdTQBuh0v/O2NO4cN9wZ16eJifowUEruFI7/1E9V0cgc/z 3EXMBN2I0fAGhKko00TE/qIoHlP2Q34I7bo7ivIzSllLkI52gncGgQgILd2W/+p0eD346+ORU6 RvxS8obFhnpuVrsHuIns2taM3Pt/DfGDHHnGhEYvbw4/2j70NrvEdIoD+831og9eCPC0l4Zm8i qWsRz2jVeRoP+WC/iPV013MV Received: from uls-op-cesaip01.wdc.com ([10.248.3.36]) by uls-op-cesaep02.wdc.com with ESMTP; 24 May 2019 16:25:43 -0700 IronPort-SDR: 81Ph2PkovrGGzJ2Clj407IS1Bz6ZXeQ2fLQaR+kVh5zLkoLS3jKeCstSI40Nhrp6mS1qw4fAku Po/qH1LwowgMelUcVonZ25TA07UChdRdDuJv9C7HMLFyWoUVIblehMRoGem2OTvjdGPYUP/rVU 1pdnpp1W6OL75Zr4UPtRUWLRntSPZs4utxpI1WVxZGEuOm9wFkTn584g/JkTnE+pwH/29dKR78 OKJ7alIKzIfvZQQAefs5bcv2pC4wP5+LcCreb+hgdrlAS0FtUNLkaSutK3c94UGeakB6IviqDi Esk= Received: from risc6-mainframe.sdcorp.global.sandisk.com (HELO risc6-mainframe.int.fusionio.com) ([10.196.157.140]) by uls-op-cesaip01.wdc.com with ESMTP; 24 May 2019 16:48:04 -0700 From: Alistair Francis To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Date: Fri, 24 May 2019 16:46:09 -0700 Message-Id: X-Mailer: git-send-email 2.21.0 In-Reply-To: References: MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 68.232.141.245 Subject: [Qemu-devel] [RFC v1 13/23] target/riscv: Generate illegal instruction on WFI when V=1 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair23@gmail.com, palmer@sifive.com, alistair.francis@wdc.com Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP Signed-off-by: Alistair Francis --- target/riscv/op_helper.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index 644d0fb35f..e08bb8dd5a 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -130,9 +130,10 @@ void helper_wfi(CPURISCVState *env) { CPUState *cs = CPU(riscv_env_get_cpu(env)); - if (env->priv == PRV_S && + if ((env->priv == PRV_S && env->priv_ver >= PRIV_VERSION_1_10_0 && - get_field(env->mstatus, MSTATUS_TW)) { + get_field(env->mstatus, MSTATUS_TW)) || + riscv_cpu_virt_enabled(env)) { riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); } else { cs->halted = 1; From patchwork Fri May 24 23:46:12 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alistair Francis X-Patchwork-Id: 10960589 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 2C829933 for ; Sat, 25 May 2019 00:08:33 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 1B832288BC for ; Sat, 25 May 2019 00:08:33 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 10664289BF; Sat, 25 May 2019 00:08:33 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.0 required=2.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id B4E5B288BC for ; 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24 May 2019 16:25:46 -0700 IronPort-SDR: aAFRx7VBpsLfvI66IaERPM6iTf2F1B3Sek2FF/jA1ahodM/jQ8fl92+3+u+32UlC59J+ekfcb1 4PLpLMfbJrqjY3J5AfTnjbfmrOuI5Xz4KNtCkUOkVbJxMoyjhbiaZbroHnqLc6nLv8nFDBkTSW xcq9OEYJwKYK60KIQInJhS7Rt4X1T8eVHfafCvsSFcEEjNaPklsDxKTxb9S+lE310SEx3WkZDA fcZgqeeadg/E3Mnbv7gPKsSOyoXAoc7tCkftlU7odzVEqM1txyWcaQSZK06ljWd84j82ksVc6e e7k= Received: from risc6-mainframe.sdcorp.global.sandisk.com (HELO risc6-mainframe.int.fusionio.com) ([10.196.157.140]) by uls-op-cesaip01.wdc.com with ESMTP; 24 May 2019 16:48:07 -0700 From: Alistair Francis To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Date: Fri, 24 May 2019 16:46:12 -0700 Message-Id: <2072d4920dd97b56f5a15d8eab64d39fc78e9390.1558741334.git.alistair.francis@wdc.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: References: MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 68.232.141.245 Subject: [Qemu-devel] [RFC v1 14/23] riscv: plic: Remove unused interrupt functions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair23@gmail.com, palmer@sifive.com, alistair.francis@wdc.com Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP Signed-off-by: Alistair Francis --- hw/riscv/sifive_plic.c | 12 ------------ include/hw/riscv/sifive_plic.h | 3 --- 2 files changed, 15 deletions(-) diff --git a/hw/riscv/sifive_plic.c b/hw/riscv/sifive_plic.c index 07a032d93d..1e7e4c8d51 100644 --- a/hw/riscv/sifive_plic.c +++ b/hw/riscv/sifive_plic.c @@ -159,18 +159,6 @@ static void sifive_plic_update(SiFivePLICState *plic) } } -void sifive_plic_raise_irq(SiFivePLICState *plic, uint32_t irq) -{ - sifive_plic_set_pending(plic, irq, true); - sifive_plic_update(plic); -} - -void sifive_plic_lower_irq(SiFivePLICState *plic, uint32_t irq) -{ - sifive_plic_set_pending(plic, irq, false); - sifive_plic_update(plic); -} - static uint32_t sifive_plic_claim(SiFivePLICState *plic, uint32_t addrid) { int i, j; diff --git a/include/hw/riscv/sifive_plic.h b/include/hw/riscv/sifive_plic.h index ce8907f6aa..3b8a623919 100644 --- a/include/hw/riscv/sifive_plic.h +++ b/include/hw/riscv/sifive_plic.h @@ -69,9 +69,6 @@ typedef struct SiFivePLICState { uint32_t aperture_size; } SiFivePLICState; -void sifive_plic_raise_irq(SiFivePLICState *plic, uint32_t irq); -void sifive_plic_lower_irq(SiFivePLICState *plic, uint32_t irq); - DeviceState *sifive_plic_create(hwaddr addr, char *hart_config, uint32_t num_sources, uint32_t num_priorities, uint32_t priority_base, uint32_t pending_base, From patchwork Fri May 24 23:46:15 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alistair Francis X-Patchwork-Id: 10960581 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id BBB0816C1 for ; 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24 May 2019 16:48:10 -0700 From: Alistair Francis To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Date: Fri, 24 May 2019 16:46:15 -0700 Message-Id: X-Mailer: git-send-email 2.21.0 In-Reply-To: References: MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 68.232.141.245 Subject: [Qemu-devel] [RFC v1 15/23] riscv: plic: Always set sip.SEIP bit for HS X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair23@gmail.com, palmer@sifive.com, alistair.francis@wdc.com Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP When the PLIC generates an interrupt ensure we always set it for the SIP CSR that corresponds to the HS (V=0) register. Signed-off-by: Alistair Francis --- hw/riscv/sifive_plic.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/hw/riscv/sifive_plic.c b/hw/riscv/sifive_plic.c index 1e7e4c8d51..25da29fa3d 100644 --- a/hw/riscv/sifive_plic.c +++ b/hw/riscv/sifive_plic.c @@ -147,7 +147,17 @@ static void sifive_plic_update(SiFivePLICState *plic) riscv_cpu_update_mip(RISCV_CPU(cpu), MIP_MEIP, BOOL_TO_MASK(level)); break; case PLICMode_S: - riscv_cpu_update_mip(RISCV_CPU(cpu), MIP_SEIP, BOOL_TO_MASK(level)); + if (riscv_cpu_virt_enabled(env)) { + if (level) { + atomic_or(&env->bsip, MIP_SEIP); + g_assert(riscv_cpu_virt_enabled(env)); + } else { + atomic_and(&env->bsip, ~MIP_SEIP); + g_assert(riscv_cpu_virt_enabled(env)); + } + } else { + riscv_cpu_update_mip(RISCV_CPU(cpu), MIP_SEIP, BOOL_TO_MASK(level)); + } break; default: break; From patchwork Fri May 24 23:46:17 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alistair Francis X-Patchwork-Id: 10960575 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 93E2516C1 for ; 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24 May 2019 16:48:13 -0700 From: Alistair Francis To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Date: Fri, 24 May 2019 16:46:17 -0700 Message-Id: <5ed7686620e75fbaaacb0d4ec6c44d5ec6f2c552.1558741334.git.alistair.francis@wdc.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: References: MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 68.232.141.245 Subject: [Qemu-devel] [RFC v1 16/23] target/riscv: Add hypvervisor trap support X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair23@gmail.com, palmer@sifive.com, alistair.francis@wdc.com Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP Signed-off-by: Alistair Francis --- target/riscv/cpu_bits.h | 4 +-- target/riscv/cpu_helper.c | 71 +++++++++++++++++++++++++++++++++------ target/riscv/csr.c | 4 +-- 3 files changed, 65 insertions(+), 14 deletions(-) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 28117bdd32..8966c1bff6 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -508,8 +508,8 @@ #define RISCV_EXCP_STORE_AMO_ADDR_MIS 0x6 #define RISCV_EXCP_STORE_AMO_ACCESS_FAULT 0x7 #define RISCV_EXCP_U_ECALL 0x8 -#define RISCV_EXCP_S_ECALL 0x9 -#define RISCV_EXCP_H_ECALL 0xa +#define RISCV_EXCP_HS_ECALL 0x9 +#define RISCV_EXCP_VS_ECALL 0xa #define RISCV_EXCP_M_ECALL 0xb #define RISCV_EXCP_INST_PAGE_FAULT 0xc /* since: priv-1.10.0 */ #define RISCV_EXCP_LOAD_PAGE_FAULT 0xd /* since: priv-1.10.0 */ diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 81f1cc83e5..b7e47b97f5 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -595,6 +595,7 @@ void riscv_cpu_do_interrupt(CPUState *cs) RISCVCPU *cpu = RISCV_CPU(cs); CPURISCVState *env = &cpu->env; + target_ulong s; /* cs->exception is 32-bits wide unlike mcause which is XLEN-bits wide * so we mask off the MSB and separate into trap type and cause. @@ -604,13 +605,6 @@ void riscv_cpu_do_interrupt(CPUState *cs) target_ulong deleg = async ? env->mideleg : env->medeleg; target_ulong tval = 0; - static const int ecall_cause_map[] = { - [PRV_U] = RISCV_EXCP_U_ECALL, - [PRV_S] = RISCV_EXCP_S_ECALL, - [PRV_H] = RISCV_EXCP_H_ECALL, - [PRV_M] = RISCV_EXCP_M_ECALL - }; - if (!async) { /* set tval to badaddr for traps with address information */ switch (cause) { @@ -631,7 +625,16 @@ void riscv_cpu_do_interrupt(CPUState *cs) /* ecall is dispatched as one cause so translate based on mode */ if (cause == RISCV_EXCP_U_ECALL) { assert(env->priv <= 3); - cause = ecall_cause_map[env->priv]; + + if (env->priv == PRV_M) { + cause = RISCV_EXCP_M_ECALL; + } else if (env->priv == PRV_S && riscv_cpu_virt_enabled(env)) { + cause = RISCV_EXCP_VS_ECALL; + } else if (env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) { + cause = RISCV_EXCP_HS_ECALL; + } else if (env->priv == PRV_U) { + cause = RISCV_EXCP_U_ECALL; + } } } @@ -641,7 +644,42 @@ void riscv_cpu_do_interrupt(CPUState *cs) if (env->priv <= PRV_S && cause < TARGET_LONG_BITS && ((deleg >> cause) & 1)) { /* handle the trap in S-mode */ - target_ulong s = env->mstatus; + if (riscv_has_ext(env, RVH)) { + target_ulong hdeleg = async ? env->hideleg : env->hedeleg; + + if (riscv_cpu_virt_enabled(env) && ((hdeleg >> cause) & 1) && + !riscv_cpu_force_hs_excep_enabled(env)) { + /* Trap to VS mode */ + } else if (riscv_cpu_virt_enabled(env)) { + /* Trap into HS mode, from virt */ + riscv_cpu_swap_background_regs(env); + env->hstatus = set_field(env->hstatus, HSTATUS_SP2V, + get_field(env->hstatus, HSTATUS_SPV)); + env->hstatus = set_field(env->hstatus, HSTATUS_SP2P, + get_field(env->mstatus, SSTATUS_SPP)); + env->hstatus = set_field(env->hstatus, HSTATUS_SPV, + riscv_cpu_virt_enabled(env)); + + if (riscv_cpu_force_hs_excep_enabled(env)) { + env->hstatus = set_field(env->hstatus, HSTATUS_STL, 1); + } else { + env->hstatus = set_field(env->hstatus, HSTATUS_STL, 0); + } + + riscv_cpu_set_virt_enabled(env, VIRT_OFF); + riscv_cpu_set_force_hs_excep(env, CLEAR_HS_EXCEP); + } else { + /* Trap into HS mode */ + env->hstatus = set_field(env->hstatus, HSTATUS_SP2V, + get_field(env->hstatus, HSTATUS_SPV)); + env->hstatus = set_field(env->hstatus, HSTATUS_SP2P, + get_field(env->mstatus, SSTATUS_SPP)); + env->hstatus = set_field(env->hstatus, HSTATUS_SPV, + riscv_cpu_virt_enabled(env)); + } + } + + s = env->mstatus; s = set_field(s, MSTATUS_SPIE, env->priv_ver >= PRIV_VERSION_1_10_0 ? get_field(s, MSTATUS_SIE) : get_field(s, MSTATUS_UIE << env->priv)); s = set_field(s, MSTATUS_SPP, env->priv); @@ -655,7 +693,20 @@ void riscv_cpu_do_interrupt(CPUState *cs) riscv_cpu_set_mode(env, PRV_S); } else { /* handle the trap in M-mode */ - target_ulong s = env->mstatus; + if (riscv_has_ext(env, RVH)) { + if (riscv_cpu_virt_enabled(env)) { + riscv_cpu_swap_background_regs(env); + } + env->mstatus = set_field(env->mstatus, MSTATUS_MPV, + riscv_cpu_virt_enabled(env)); + env->mstatus = set_field(env->mstatus, MSTATUS_MTL, + riscv_cpu_force_hs_excep_enabled(env)); + + /* Trapping to M mode, virt is disabled */ + riscv_cpu_set_virt_enabled(env, VIRT_OFF); + } + + s = env->mstatus; s = set_field(s, MSTATUS_MPIE, env->priv_ver >= PRIV_VERSION_1_10_0 ? get_field(s, MSTATUS_MIE) : get_field(s, MSTATUS_UIE << env->priv)); s = set_field(s, MSTATUS_MPP, env->priv); diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 908e166426..43d9bb941d 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -239,8 +239,8 @@ static const target_ulong delegable_excps = (1ULL << (RISCV_EXCP_STORE_AMO_ADDR_MIS)) | (1ULL << (RISCV_EXCP_STORE_AMO_ACCESS_FAULT)) | (1ULL << (RISCV_EXCP_U_ECALL)) | - (1ULL << (RISCV_EXCP_S_ECALL)) | - (1ULL << (RISCV_EXCP_H_ECALL)) | + (1ULL << (RISCV_EXCP_VS_ECALL)) | + (1ULL << (RISCV_EXCP_HS_ECALL)) | (1ULL << (RISCV_EXCP_M_ECALL)) | (1ULL << (RISCV_EXCP_INST_PAGE_FAULT)) | (1ULL << (RISCV_EXCP_LOAD_PAGE_FAULT)) | From patchwork Fri May 24 23:46:20 2019 Content-Type: text/plain; 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X-Received-From: 68.232.141.245 Subject: [Qemu-devel] [RFC v1 17/23] target/riscv: Add Hypervisor trap return support X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair23@gmail.com, palmer@sifive.com, alistair.francis@wdc.com Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP Signed-off-by: Alistair Francis --- target/riscv/op_helper.c | 66 ++++++++++++++++++++++++++++++++-------- 1 file changed, 54 insertions(+), 12 deletions(-) diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index e08bb8dd5a..60dcd73fc7 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -73,6 +73,8 @@ target_ulong helper_csrrc(CPURISCVState *env, target_ulong src, target_ulong helper_sret(CPURISCVState *env, target_ulong cpu_pc_deb) { + target_ulong prev_priv, prev_virt, mstatus; + if (!(env->priv >= PRV_S)) { riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); } @@ -87,16 +89,46 @@ target_ulong helper_sret(CPURISCVState *env, target_ulong cpu_pc_deb) riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); } - target_ulong mstatus = env->mstatus; - target_ulong prev_priv = get_field(mstatus, MSTATUS_SPP); - mstatus = set_field(mstatus, - env->priv_ver >= PRIV_VERSION_1_10_0 ? - MSTATUS_SIE : MSTATUS_UIE << prev_priv, - get_field(mstatus, MSTATUS_SPIE)); - mstatus = set_field(mstatus, MSTATUS_SPIE, 0); - mstatus = set_field(mstatus, MSTATUS_SPP, PRV_U); + mstatus = env->mstatus; + + if (riscv_has_ext(env, RVH) && !riscv_cpu_virt_enabled(env)) { + /* We support Hypervisor extensions and virtulisation is disabled */ + target_ulong hstatus = env->hstatus; + + prev_priv = get_field(mstatus, MSTATUS_SPP); + prev_virt = get_field(hstatus, HSTATUS_SPV); + + hstatus = set_field(hstatus, HSTATUS_SPV, + get_field(hstatus, HSTATUS_SP2V)); + mstatus = set_field(mstatus, MSTATUS_SPP, + get_field(hstatus, HSTATUS_SP2P)); + hstatus = set_field(hstatus, HSTATUS_SP2V, 0); + hstatus = set_field(hstatus, HSTATUS_SP2P, 0); + mstatus = set_field(mstatus, SSTATUS_SIE, + get_field(mstatus, SSTATUS_SPIE)); + mstatus = set_field(mstatus, SSTATUS_SPIE, 1); + + env->mstatus = mstatus; + env->hstatus = hstatus; + + if (prev_virt == VIRT_ON) { + riscv_cpu_swap_background_regs(env); + } + + riscv_cpu_set_virt_enabled(env, prev_virt); + } else { + prev_priv = get_field(mstatus, MSTATUS_SPP); + + mstatus = set_field(mstatus, + env->priv_ver >= PRIV_VERSION_1_10_0 ? + MSTATUS_SIE : MSTATUS_UIE << prev_priv, + get_field(mstatus, MSTATUS_SPIE)); + mstatus = set_field(mstatus, MSTATUS_SPIE, 0); + mstatus = set_field(mstatus, MSTATUS_SPP, PRV_U); + env->mstatus = mstatus; + } + riscv_cpu_set_mode(env, prev_priv); - env->mstatus = mstatus; return retpc; } @@ -114,14 +146,24 @@ target_ulong helper_mret(CPURISCVState *env, target_ulong cpu_pc_deb) target_ulong mstatus = env->mstatus; target_ulong prev_priv = get_field(mstatus, MSTATUS_MPP); + target_ulong prev_virt = get_field(mstatus, MSTATUS_MPV); mstatus = set_field(mstatus, env->priv_ver >= PRIV_VERSION_1_10_0 ? MSTATUS_MIE : MSTATUS_UIE << prev_priv, get_field(mstatus, MSTATUS_MPIE)); - mstatus = set_field(mstatus, MSTATUS_MPIE, 0); - mstatus = set_field(mstatus, MSTATUS_MPP, PRV_U); - riscv_cpu_set_mode(env, prev_priv); + mstatus = set_field(mstatus, MSTATUS_MPIE, 1); + mstatus = set_field(mstatus, MSTATUS_MPP, 0); + mstatus = set_field(mstatus, MSTATUS_MPV, 0); env->mstatus = mstatus; + riscv_cpu_set_mode(env, prev_priv); + + if (riscv_has_ext(env, RVH)) { + if (prev_virt == VIRT_ON) { + riscv_cpu_swap_background_regs(env); + } + + riscv_cpu_set_virt_enabled(env, prev_virt); + } return retpc; } From patchwork Fri May 24 23:46:23 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alistair Francis X-Patchwork-Id: 10960585 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id E05A013AD for ; Sat, 25 May 2019 00:08:24 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id CF83C2888D for ; Sat, 25 May 2019 00:08:24 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id C36A3289A9; Sat, 25 May 2019 00:08:24 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.0 required=2.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id D32072888D for ; Sat, 25 May 2019 00:08:22 +0000 (UTC) Received: from localhost ([127.0.0.1]:33534 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hUKEY-0006Yp-35 for patchwork-qemu-devel@patchwork.kernel.org; Fri, 24 May 2019 20:08:22 -0400 Received: from eggs.gnu.org ([209.51.188.92]:60227) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hUK3x-0005Im-6T for qemu-devel@nongnu.org; Fri, 24 May 2019 19:57:26 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hUJv8-0004eF-O9 for qemu-devel@nongnu.org; Fri, 24 May 2019 19:48:19 -0400 Received: from esa1.hgst.iphmx.com ([68.232.141.245]:5520) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1hUJv8-0004TN-8W; Fri, 24 May 2019 19:48:18 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1558741698; x=1590277698; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=C5UgGc4V2pAKfw6v1wYMZEJGSRpC8Q7ki2tjMjGBTmM=; b=HCIMtlaggTn3+X+GxwAPn/FGyUfY+jsrVkrABtcl0gWC/k/WSWo4Qqhz uWlBQhD4FdH+gz2Zl9UPfmLg3ZhyxE7ltd5p/yEtNL5D3RGxMkGyBlf+3 eIKwNmUtRyEFI2V9IqFDw5CWWZt08vp7404CmCSpGrw7jUS4/vHTCbjYb 8FTqQ8EWiwFS6J7y6xTZ3cs724StwPWbgjQ6L2nnvUHFKX05H39MvlnWY ebU/NayfMWGQZ1J80VCeyN8SJA/+yHJNgao4ZuFkdBlt+C5MaLUsmee+C sRrFH2rpy8VuQYiBshrZ3y+QpOiyqS6CWyT2kECBFGs9fb1tJGewRM3rq A==; X-IronPort-AV: E=Sophos;i="5.60,508,1549900800"; d="scan'208";a="215265026" Received: from uls-op-cesaip02.wdc.com (HELO uls-op-cesaep02.wdc.com) ([199.255.45.15]) by ob1.hgst.iphmx.com with ESMTP; 25 May 2019 07:48:17 +0800 IronPort-SDR: 1KyMA9vfDuVoFL1cp5qW2dNdD5mjxhRbuSNo03A1OrLltZBWwrKlYT/j28L+4plKp8m2uugDvc 3gem/qgxcyC41Hlc/tS0td3oUqy9XzwusROm9DW8fqrdQd5z+2YwhdzNIhczpvs2ZPu8VNUq7B 14WPNC5VMqfoEjfjA52qbIY050L1lAVaSNqKVkmPJNMqybD8RDVeM6Ilc48KC0DeSRaylxpR7K Upkt2aCbyS4jhDiKhLenarowY71wuO6u3+bdpxQN/oGJ8XLbghQqWkk5s9hJBcS/0beBSvzK9B mSWlubxtzH2EdA63WMaiLWB6 Received: from uls-op-cesaip02.wdc.com ([10.248.3.37]) by uls-op-cesaep02.wdc.com with ESMTP; 24 May 2019 16:25:57 -0700 IronPort-SDR: NmYa43uZ6yHTlFScaKaRWilrsdDFi/yS2evywLq6hxOpsXeZVX5QGF7xNfsTJWI3BcgLGZvcnJ wKsTxASjHYSpEoFOjAZvYsVM3791UGGoNTMt9NVPfKy8fSCUN07bfPoN//OJDL+WVImqTlv3Xn FTBBVLl67Nv0zSIAq+WJTRC2vTPtPKa3kzfPdNwS9w413IbtaF3XUnOknRKRgodsEOHwU9+qGZ jSGh0r6NAos6pc2U/K3/KZdXizOXPbVPSLU0XPncN5poqm3cg20NHEbYbKNMr7/JbVq1Iskoof Fnk= Received: from risc6-mainframe.sdcorp.global.sandisk.com (HELO risc6-mainframe.int.fusionio.com) ([10.196.157.140]) by uls-op-cesaip02.wdc.com with ESMTP; 24 May 2019 16:48:17 -0700 From: Alistair Francis To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Date: Fri, 24 May 2019 16:46:23 -0700 Message-Id: <68722b887546714923b1d23cea80042f0cd0b8ba.1558741334.git.alistair.francis@wdc.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: References: MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 68.232.141.245 Subject: [Qemu-devel] [RFC v1 18/23] target/riscv: Add hfence instructions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair23@gmail.com, palmer@sifive.com, alistair.francis@wdc.com Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP Signed-off-by: Alistair Francis --- target/riscv/insn32.decode | 23 ++++++----- .../riscv/insn_trans/trans_privileged.inc.c | 40 +++++++++++++++++++ 2 files changed, 54 insertions(+), 9 deletions(-) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 6f3ab7aa52..6c79c5fd0c 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -59,20 +59,25 @@ @r2_rm ....... ..... ..... ... ..... ....... %rs1 %rm %rd @r2 ....... ..... ..... ... ..... ....... %rs1 %rd +@hfence_gvma ....... ..... ..... ... ..... ....... %rs2 %rs1 +@hfence_bvma ....... ..... ..... ... ..... ....... %rs2 %rs1 + @sfence_vma ....... ..... ..... ... ..... ....... %rs2 %rs1 @sfence_vm ....... ..... ..... ... ..... ....... %rs1 # *** Privileged Instructions *** -ecall 000000000000 00000 000 00000 1110011 -ebreak 000000000001 00000 000 00000 1110011 -uret 0000000 00010 00000 000 00000 1110011 -sret 0001000 00010 00000 000 00000 1110011 -hret 0010000 00010 00000 000 00000 1110011 -mret 0011000 00010 00000 000 00000 1110011 -wfi 0001000 00101 00000 000 00000 1110011 -sfence_vma 0001001 ..... ..... 000 00000 1110011 @sfence_vma -sfence_vm 0001000 00100 ..... 000 00000 1110011 @sfence_vm +ecall 000000000000 00000 000 00000 1110011 +ebreak 000000000001 00000 000 00000 1110011 +uret 0000000 00010 00000 000 00000 1110011 +sret 0001000 00010 00000 000 00000 1110011 +hret 0010000 00010 00000 000 00000 1110011 +mret 0011000 00010 00000 000 00000 1110011 +wfi 0001000 00101 00000 000 00000 1110011 +hfence_gvma 1010001 ..... ..... 000 00000 1110011 @hfence_gvma +hfence_bvma 0010001 ..... ..... 000 00000 1110011 @hfence_bvma +sfence_vma 0001001 ..... ..... 000 00000 1110011 @sfence_vma +sfence_vm 0001000 00100 ..... 000 00000 1110011 @sfence_vm # *** RV32I Base Instruction Set *** lui .................... ..... 0110111 @u diff --git a/target/riscv/insn_trans/trans_privileged.inc.c b/target/riscv/insn_trans/trans_privileged.inc.c index 664d6ba3f2..ac953ad30d 100644 --- a/target/riscv/insn_trans/trans_privileged.inc.c +++ b/target/riscv/insn_trans/trans_privileged.inc.c @@ -108,3 +108,43 @@ static bool trans_sfence_vm(DisasContext *ctx, arg_sfence_vm *a) #endif return false; } + +static bool trans_hfence_gvma(DisasContext *ctx, arg_sfence_vma *a) +{ +#ifndef CONFIG_USER_ONLY + if (ctx->priv_ver == PRIV_VERSION_1_10_0 && + has_ext(ctx, RVH)) { + /* Hpervisor extensions exist */ + /* + * if (env->priv == PRV_M || + * (env->priv == PRV_S && + * !riscv_cpu_virt_enabled(env) && + * get_field(ctx->mstatus_fs, MSTATUS_TVM))) { + */ + gen_helper_tlb_flush(cpu_env); + return true; + /* } */ + } +#endif + return false; +} + +static bool trans_hfence_bvma(DisasContext *ctx, arg_sfence_vma *a) +{ +#ifndef CONFIG_USER_ONLY + if (ctx->priv_ver == PRIV_VERSION_1_10_0 && + has_ext(ctx, RVH)) { + /* Hpervisor extensions exist */ + /* + * if (env->priv == PRV_M || + * (env->priv == PRV_S && + * !riscv_cpu_virt_enabled(env) && + * get_field(ctx->mstatus_fs, MSTATUS_TVM))) { + */ + gen_helper_tlb_flush(cpu_env); + return true; + /* } */ + } +#endif + return false; +} From patchwork Fri May 24 23:46:25 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alistair Francis X-Patchwork-Id: 10960579 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id ED5D21708 for ; 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24 May 2019 16:48:21 -0700 From: Alistair Francis To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Date: Fri, 24 May 2019 16:46:25 -0700 Message-Id: X-Mailer: git-send-email 2.21.0 In-Reply-To: References: MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 68.232.141.245 Subject: [Qemu-devel] [RFC v1 19/23] target/riscv: Allow specifying MMU stage X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair23@gmail.com, palmer@sifive.com, alistair.francis@wdc.com Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP Signed-off-by: Alistair Francis --- target/riscv/cpu_helper.c | 35 +++++++++++++++++++++++++++-------- 1 file changed, 27 insertions(+), 8 deletions(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index b7e47b97f5..3c963d26bc 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -261,10 +261,19 @@ void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv) * * Adapted from Spike's mmu_t::translate and mmu_t::walk * + * @env: CPURISCVState + * @physical: This will be set to the calculated physical address + * @prot: The returned protection attributes + * @addr: The virtual address to be translated + * @access_type: The type of MMU access + * @mmu_idx: Indicates current privilege level + * @first_stage: Are we in first stage translation? + * Second stage is used for hypervisor guest translation */ static int get_physical_address(CPURISCVState *env, hwaddr *physical, int *prot, target_ulong addr, - int access_type, int mmu_idx) + int access_type, int mmu_idx, + bool first_stage) { /* NOTE: the env->pc value visible here will not be * correct, but the value visible to the exception handler @@ -455,12 +464,20 @@ restart: } static void raise_mmu_exception(CPURISCVState *env, target_ulong address, - MMUAccessType access_type) + MMUAccessType access_type, bool first_stage) { CPUState *cs = CPU(riscv_env_get_cpu(env)); - int page_fault_exceptions = - (env->priv_ver >= PRIV_VERSION_1_10_0) && - get_field(env->satp, SATP_MODE) != VM_1_10_MBARE; + int page_fault_exceptions; + if (first_stage) { + page_fault_exceptions = + (env->priv_ver >= PRIV_VERSION_1_10_0) && + get_field(env->satp, SATP_MODE) != VM_1_10_MBARE; + riscv_cpu_set_force_hs_excep(env, CLEAR_HS_EXCEP); + } else { + page_fault_exceptions = + get_field(env->hgatp, HGATP_MODE) != VM_1_10_MBARE; + riscv_cpu_set_force_hs_excep(env, FORCE_HS_EXCEP); + } switch (access_type) { case MMU_INST_FETCH: cs->exception_index = page_fault_exceptions ? @@ -487,7 +504,8 @@ hwaddr riscv_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) int prot; int mmu_idx = cpu_mmu_index(&cpu->env, false); - if (get_physical_address(&cpu->env, &phys_addr, &prot, addr, 0, mmu_idx)) { + if (get_physical_address(&cpu->env, &phys_addr, &prot, addr, 0, mmu_idx, + true)) { return -1; } return phys_addr; @@ -547,7 +565,8 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, qemu_log_mask(CPU_LOG_MMU, "%s ad %" VADDR_PRIx " rw %d mmu_idx %d\n", __func__, address, access_type, mmu_idx); - ret = get_physical_address(env, &pa, &prot, address, access_type, mmu_idx); + ret = get_physical_address(env, &pa, &prot, address, access_type, mmu_idx, + true); qemu_log_mask(CPU_LOG_MMU, "%s address=%" VADDR_PRIx " ret %d physical " TARGET_FMT_plx @@ -564,7 +583,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, } else if (probe) { return false; } else { - raise_mmu_exception(env, address, access_type); + raise_mmu_exception(env, address, access_type, true); riscv_raise_exception(env, cs->exception_index, retaddr); } #else From patchwork Fri May 24 23:46:28 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alistair Francis X-Patchwork-Id: 10960571 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 9845C933 for ; Sat, 25 May 2019 00:02:02 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 87C23286F1 for ; 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24 May 2019 16:48:23 -0700 From: Alistair Francis To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Date: Fri, 24 May 2019 16:46:28 -0700 Message-Id: X-Mailer: git-send-email 2.21.0 In-Reply-To: References: MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 68.232.141.245 Subject: [Qemu-devel] [RFC v1 20/23] target/riscv: Allow specifying number of MMU stages X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair23@gmail.com, palmer@sifive.com, alistair.francis@wdc.com Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP Signed-off-by: Alistair Francis --- target/riscv/cpu_helper.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 3c963d26bc..f57e49c973 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -273,7 +273,7 @@ void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv) static int get_physical_address(CPURISCVState *env, hwaddr *physical, int *prot, target_ulong addr, int access_type, int mmu_idx, - bool first_stage) + bool first_stage, bool two_stage) { /* NOTE: the env->pc value visible here will not be * correct, but the value visible to the exception handler @@ -505,9 +505,10 @@ hwaddr riscv_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) int mmu_idx = cpu_mmu_index(&cpu->env, false); if (get_physical_address(&cpu->env, &phys_addr, &prot, addr, 0, mmu_idx, - true)) { + true, false)) { return -1; } + return phys_addr; } @@ -566,7 +567,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, __func__, address, access_type, mmu_idx); ret = get_physical_address(env, &pa, &prot, address, access_type, mmu_idx, - true); + true, false); qemu_log_mask(CPU_LOG_MMU, "%s address=%" VADDR_PRIx " ret %d physical " TARGET_FMT_plx From patchwork Fri May 24 23:46:31 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alistair Francis X-Patchwork-Id: 10960563 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id A5F0076 for ; Fri, 24 May 2019 23:58:54 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 9527728999 for ; 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24 May 2019 16:48:26 -0700 From: Alistair Francis To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Date: Fri, 24 May 2019 16:46:31 -0700 Message-Id: <566fbd2d52bae6da22dbe51c6ef1716653c4dfba.1558741334.git.alistair.francis@wdc.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: References: MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 68.232.141.245 Subject: [Qemu-devel] [RFC v1 21/23] target/riscv: Implement second stage MMU X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair23@gmail.com, palmer@sifive.com, alistair.francis@wdc.com Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP Signed-off-by: Alistair Francis --- target/riscv/cpu_helper.c | 87 +++++++++++++++++++++++++++++++++++---- 1 file changed, 78 insertions(+), 9 deletions(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index f57e49c973..387c12547b 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -280,13 +280,40 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical, * (riscv_cpu_do_interrupt) is correct */ int mode = mmu_idx; - + bool use_background = false; + + /* + * Check if we should use the background registers for the two + * stage translation. We don't need to check if we actually need + * two stage translation as that happened before this function + * was called. Background registers will be used if the guest has + * forced a two stage translation to be on (in HS or M mode). + */ if (mode == PRV_M && access_type != MMU_INST_FETCH) { if (get_field(env->mstatus, MSTATUS_MPRV)) { mode = get_field(env->mstatus, MSTATUS_MPP); + + if (riscv_has_ext(env, RVH) && + get_field(env->mstatus, MSTATUS_MPV)) { + use_background = true; + } + } + } + + if (mode == PRV_S && access_type != MMU_INST_FETCH && + riscv_has_ext(env, RVH) && !riscv_cpu_virt_enabled(env)) { + if (get_field(env->hstatus, HSTATUS_SPRV)) { + mode = get_field(env->mstatus, SSTATUS_SPP); + use_background = true; } } + if (first_stage == false) { + /* We are in stage 2 translation, this is similar to stage 1. */ + /* Stage 2 is always taken as U-mode */ + mode = PRV_U; + } + if (mode == PRV_M || !riscv_feature(env, RISCV_FEATURE_MMU)) { *physical = addr; *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; @@ -296,13 +323,30 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical, *prot = 0; target_ulong base; - int levels, ptidxbits, ptesize, vm, sum; - int mxr = get_field(env->mstatus, MSTATUS_MXR); + int levels, ptidxbits, ptesize, vm, sum, mxr, widened; + + if (first_stage == true) { + mxr = get_field(env->mstatus, MSTATUS_MXR); + } else { + mxr = get_field(env->bsstatus, MSTATUS_MXR); + } if (env->priv_ver >= PRIV_VERSION_1_10_0) { - base = get_field(env->satp, SATP_PPN) << PGSHIFT; + if (first_stage == true) { + if (use_background) { + base = get_field(env->bsatp, SATP_PPN) << PGSHIFT; + vm = get_field(env->bsatp, SATP_MODE); + } else { + base = get_field(env->satp, SATP_PPN) << PGSHIFT; + vm = get_field(env->satp, SATP_MODE); + } + widened = 0; + } else { + base = get_field(env->hgatp, HGATP_PPN) << PGSHIFT; + vm = get_field(env->hgatp, HGATP_MODE); + widened = 2; + } sum = get_field(env->mstatus, MSTATUS_SUM); - vm = get_field(env->satp, SATP_MODE); switch (vm) { case VM_1_10_SV32: levels = 2; ptidxbits = 10; ptesize = 4; break; @@ -320,6 +364,7 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical, g_assert_not_reached(); } } else { + widened = 0; base = env->sptbr << PGSHIFT; sum = !get_field(env->mstatus, MSTATUS_PUM); vm = get_field(env->mstatus, MSTATUS_VM); @@ -340,7 +385,7 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical, } CPUState *cs = CPU(riscv_env_get_cpu(env)); - int va_bits = PGSHIFT + levels * ptidxbits; + int va_bits = PGSHIFT + levels * ptidxbits + widened; target_ulong mask = (1L << (TARGET_LONG_BITS - (va_bits - 1))) - 1; target_ulong masked_msbs = (addr >> (va_bits - 1)) & mask; if (masked_msbs != 0 && masked_msbs != mask) { @@ -354,11 +399,30 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical, restart: #endif for (i = 0; i < levels; i++, ptshift -= ptidxbits) { - target_ulong idx = (addr >> (PGSHIFT + ptshift)) & + target_ulong idx; + if (i == 0) { + idx = (addr >> (PGSHIFT + ptshift)) & + ((1 << (ptidxbits + widened)) - 1); + } else { + idx = (addr >> (PGSHIFT + ptshift)) & ((1 << ptidxbits) - 1); + } /* check that physical address of PTE is legal */ - target_ulong pte_addr = base + idx * ptesize; + target_ulong pte_addr; + + if (two_stage && first_stage) { + hwaddr vbase; + + /* Do the second stage translation on the base PTE address. */ + get_physical_address(env, &vbase, prot, base, access_type, + mmu_idx, false, true); + + pte_addr = vbase + idx * ptesize; + } else { + pte_addr = base + idx * ptesize; + } + #if defined(TARGET_RISCV32) target_ulong pte = ldl_phys(cs->as, pte_addr); #elif defined(TARGET_RISCV64) @@ -444,7 +508,12 @@ restart: /* for superpage mappings, make a fake leaf PTE for the TLB's benefit. */ target_ulong vpn = addr >> PGSHIFT; - *physical = (ppn | (vpn & ((1L << ptshift) - 1))) << PGSHIFT; + if (i == 0) { + *physical = (ppn | (vpn & ((1L << (ptshift + widened)) - 1))) << + PGSHIFT; + } else { + *physical = (ppn | (vpn & ((1L << ptshift) - 1))) << PGSHIFT; + } /* set permissions on the TLB entry */ if ((pte & PTE_R) || ((pte & PTE_X) && mxr)) { From patchwork Fri May 24 23:46:33 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alistair Francis X-Patchwork-Id: 10960567 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 4D42616C1 for ; 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24 May 2019 16:48:29 -0700 From: Alistair Francis To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Date: Fri, 24 May 2019 16:46:33 -0700 Message-Id: X-Mailer: git-send-email 2.21.0 In-Reply-To: References: MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 68.232.141.245 Subject: [Qemu-devel] [RFC v1 22/23] target/riscv: Call the second stage MMU in virtualisation mode X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair23@gmail.com, palmer@sifive.com, alistair.francis@wdc.com Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP The qemu_log_mask(CPU_LOG_MMU,... calls trigger false positive checkpatch errors which are being ignored. Signed-off-by: Alistair Francis --- target/riscv/cpu_helper.c | 118 ++++++++++++++++++++++++++++++++------ 1 file changed, 99 insertions(+), 19 deletions(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 387c12547b..99091ed0fd 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -569,15 +569,23 @@ static void raise_mmu_exception(CPURISCVState *env, target_ulong address, hwaddr riscv_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) { RISCVCPU *cpu = RISCV_CPU(cs); + CPURISCVState *env = &cpu->env; hwaddr phys_addr; int prot; int mmu_idx = cpu_mmu_index(&cpu->env, false); - if (get_physical_address(&cpu->env, &phys_addr, &prot, addr, 0, mmu_idx, - true, false)) { + if (get_physical_address(env, &phys_addr, &prot, addr, 0, mmu_idx, + true, riscv_cpu_virt_enabled(env))) { return -1; } + if (riscv_cpu_virt_enabled(env)) { + if (get_physical_address(env, &phys_addr, &prot, phys_addr, + 0, mmu_idx, false, true)) { + return -1; + } + } + return phys_addr; } @@ -628,34 +636,106 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, #ifndef CONFIG_USER_ONLY RISCVCPU *cpu = RISCV_CPU(cs); CPURISCVState *env = &cpu->env; + vaddr im_address; hwaddr pa = 0; int prot; + bool m_mode_two_stage = false; + bool hs_mode_two_stage = false; int ret = TRANSLATE_FAIL; qemu_log_mask(CPU_LOG_MMU, "%s ad %" VADDR_PRIx " rw %d mmu_idx %d\n", __func__, address, access_type, mmu_idx); - ret = get_physical_address(env, &pa, &prot, address, access_type, mmu_idx, - true, false); + /* + * Determine if we are in M mode and MPRV is set or in HS mode and SPRV is + * set and we want to access a virtulisation address. + */ + if (riscv_has_ext(env, RVH)) { + m_mode_two_stage = env->priv == PRV_M && + access_type != MMU_INST_FETCH && + get_field(env->mstatus, MSTATUS_MPRV) && + get_field(env->mstatus, MSTATUS_MPV); + + hs_mode_two_stage = env->priv == PRV_S && + !riscv_cpu_virt_enabled(env) && + access_type != MMU_INST_FETCH && + get_field(env->hstatus, HSTATUS_SPRV) && + get_field(env->hstatus, HSTATUS_SPV); + } + + if (riscv_cpu_virt_enabled(env) || m_mode_two_stage || hs_mode_two_stage) { + /* Two stage lookup */ + ret = get_physical_address(env, &pa, &prot, address, access_type, + mmu_idx, true, true); - qemu_log_mask(CPU_LOG_MMU, - "%s address=%" VADDR_PRIx " ret %d physical " TARGET_FMT_plx - " prot %d\n", __func__, address, ret, pa, prot); + qemu_log_mask(CPU_LOG_MMU, + "%s 1st-stage address=%" VADDR_PRIx " ret %d physical " + TARGET_FMT_plx " prot %d\n", + __func__, address, ret, pa, prot); - if (riscv_feature(env, RISCV_FEATURE_PMP) && - !pmp_hart_has_privs(env, pa, TARGET_PAGE_SIZE, 1 << access_type)) { - ret = TRANSLATE_FAIL; - } - if (ret == TRANSLATE_SUCCESS) { - tlb_set_page(cs, address & TARGET_PAGE_MASK, pa & TARGET_PAGE_MASK, - prot, mmu_idx, TARGET_PAGE_SIZE); - return true; - } else if (probe) { - return false; + if (ret == TRANSLATE_FAIL) { + if (!probe) { + raise_mmu_exception(env, address, access_type, true); + riscv_raise_exception(env, cs->exception_index, retaddr); + } + return ret; + } + + /* Second stage lookup */ + im_address = pa; + + ret = get_physical_address(env, &pa, &prot, im_address, access_type, mmu_idx, + false, true); + + qemu_log_mask(CPU_LOG_MMU, + "%s 2nd-stage address=%" VADDR_PRIx " ret %d physical " + TARGET_FMT_plx " prot %d\n", + __func__, im_address, ret, pa, prot); + + if (riscv_feature(env, RISCV_FEATURE_PMP) && + !pmp_hart_has_privs(env, pa, TARGET_PAGE_SIZE, 1 << access_type)) { + ret = TRANSLATE_FAIL; + } + + if (ret == TRANSLATE_FAIL) { + /* + * Guest physical address translation failed, this is a HS + * level exception + */ + if (!probe) { + raise_mmu_exception(env, im_address | (address & (TARGET_PAGE_SIZE - 1)), access_type, false); + riscv_raise_exception(env, cs->exception_index, retaddr); + } + return ret; + } } else { - raise_mmu_exception(env, address, access_type, true); - riscv_raise_exception(env, cs->exception_index, retaddr); + /* Single stage lookup */ + ret = get_physical_address(env, &pa, &prot, address, access_type, + mmu_idx, true, false); + + qemu_log_mask(CPU_LOG_MMU, + "%s address=%" VADDR_PRIx " ret %d physical " + TARGET_FMT_plx " prot %d\n", + __func__, address, ret, pa, prot); + + if (riscv_feature(env, RISCV_FEATURE_PMP) && + !pmp_hart_has_privs(env, pa, TARGET_PAGE_SIZE, 1 << access_type)) { + ret = TRANSLATE_FAIL; + } + + if (ret == TRANSLATE_FAIL) { + if (!probe) { + raise_mmu_exception(env, address, access_type, true); + riscv_raise_exception(env, cs->exception_index, retaddr); + } + return ret; + } } + + tlb_set_page(cs, address & TARGET_PAGE_MASK, pa & TARGET_PAGE_MASK, + prot, mmu_idx, TARGET_PAGE_SIZE); + return true; + #else switch (access_type) { case MMU_INST_FETCH: From patchwork Fri May 24 23:46:36 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alistair Francis X-Patchwork-Id: 10960565 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 7D89776 for ; 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24 May 2019 16:48:31 -0700 From: Alistair Francis To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Date: Fri, 24 May 2019 16:46:36 -0700 Message-Id: <0c227e8cc03a2b33f67e497b94e6d8283e98d96e.1558741334.git.alistair.francis@wdc.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: References: MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 68.232.141.245 Subject: [Qemu-devel] [RFC v1 23/23] target/riscv: Allow enabling the Hypervisor extension X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair23@gmail.com, palmer@sifive.com, alistair.francis@wdc.com Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP Signed-off-by: Alistair Francis --- target/riscv/cpu.c | 4 ++++ target/riscv/cpu.h | 1 + 2 files changed, 5 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index c1495ef037..b17dfb86c6 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -436,6 +436,9 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) if (cpu->cfg.ext_u) { target_misa |= RVU; } + if (cpu->cfg.ext_h) { + target_misa |= RVH; + } set_misa(env, RVXLEN | target_misa); } @@ -472,6 +475,7 @@ static Property riscv_cpu_properties[] = { DEFINE_PROP_BOOL("c", RISCVCPU, cfg.ext_c, true), DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true), DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true), + DEFINE_PROP_BOOL("h", RISCVCPU, cfg.ext_h, false), DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec), DEFINE_PROP_STRING("user_spec", RISCVCPU, cfg.user_spec), DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true), diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 9897392ab7..d2cfc69e9a 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -259,6 +259,7 @@ typedef struct RISCVCPU { bool ext_c; bool ext_s; bool ext_u; + bool ext_h; char *priv_spec; char *user_spec;