From patchwork Wed Aug 29 07:02:56 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chunyan Zhang X-Patchwork-Id: 10579581 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id CB4E51709 for ; Wed, 29 Aug 2018 07:04:08 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id BC4222AB64 for ; Wed, 29 Aug 2018 07:04:08 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id B095F2AB82; Wed, 29 Aug 2018 07:04:08 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 5928E2AB64 for ; Wed, 29 Aug 2018 07:04:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727629AbeH2K6n (ORCPT ); Wed, 29 Aug 2018 06:58:43 -0400 Received: from mail-pl1-f196.google.com ([209.85.214.196]:37285 "EHLO mail-pl1-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727623AbeH2K6m (ORCPT ); Wed, 29 Aug 2018 06:58:42 -0400 Received: by mail-pl1-f196.google.com with SMTP id d12-v6so1893324pls.4 for ; Wed, 29 Aug 2018 00:03:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=++1fRQNMnXH0A0SYZtvAp1/7snJJJbIXHOql7gVNj04=; b=BOj+JRQH3cjH6wss3IOQ35mX1jeAxamz9/uZJmdsbxWmm8KX/Rp3UoDa1j1JhJRtmq 3NEjRJjtNz6LmV4aE689SdAkmmOZ6AUknrsB0demBYZRj3AF5mzdXvaRRaYk9dVkjhdH ExNN38rlF0LpYG3eCiIpXP/GnYUrpuIag7HeA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=++1fRQNMnXH0A0SYZtvAp1/7snJJJbIXHOql7gVNj04=; b=Eh2HVvTZMm7FDQpQVdoOgVOcqkwnb3kE/Qx6Bq03HplEyJmV5AZvPOMHRf3DVFslqs 4z2zL4s90ceT8aX1/ewjilgS04LAuNT8Zm+8K4DK9vP219t/mlklM1y10y4CpEqEl6DV vgtr3wFmG9T8r7+H504Ulq8puIzeGTKPoksWzBk+MfAYMExHgj/Y8xP0+9d7g8g++qXy 04ZeH4OCamd8Mj+48fREfDKfHIt2/i7VzEwoyw62aX/BuhcvjA0hYE3Pj+367Dhz9plm JJkdY7wtDq/6hC1+PwfuwfqAnbKqm2eQ2t1d4pK2rI/cMe87do+JrPADgV/N5zYNoOAj Hj5Q== X-Gm-Message-State: APzg51CP/kFjbApc+78Ih+yT3nBveWfmBTeXWVbbrSqvasDjof0Kviog Jrfh4hUD8kv+rDHVdfu3vnlYow== X-Google-Smtp-Source: ANB0VdYfwop77x7SvQssysqKAm1fS3YxqyDxo4rrsvM/3Mc1e09RyFk0HbhXniSmJycGnccSk8uoUg== X-Received: by 2002:a17:902:1ab:: with SMTP id b40-v6mr4825100plb.55.1535526197764; Wed, 29 Aug 2018 00:03:17 -0700 (PDT) Received: from ubt.spreadtrum.com ([117.18.48.102]) by smtp.gmail.com with ESMTPSA id d81-v6sm4317342pfj.122.2018.08.29.00.03.13 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 29 Aug 2018 00:03:16 -0700 (PDT) From: Chunyan Zhang To: Ulf Hansson , Adrian Hunter Cc: linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, Orson Zhai , Baolin Wang , Billows Wu , Jason Wu , Chunyan Zhang , Chunyan Zhang Subject: [PATCH V7 1/9] mmc: sdhci: Add version V4 definition Date: Wed, 29 Aug 2018 15:02:56 +0800 Message-Id: <1535526184-32718-2-git-send-email-zhang.chunyan@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1535526184-32718-1-git-send-email-zhang.chunyan@linaro.org> References: <1535526184-32718-1-git-send-email-zhang.chunyan@linaro.org> Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Added definitions for v400, v410, v420. Signed-off-by: Chunyan Zhang Acked-by: Adrian Hunter --- drivers/mmc/host/sdhci.c | 2 +- drivers/mmc/host/sdhci.h | 3 +++ 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c index 97e4efa..01bf88c 100644 --- a/drivers/mmc/host/sdhci.c +++ b/drivers/mmc/host/sdhci.c @@ -3508,7 +3508,7 @@ int sdhci_setup_host(struct sdhci_host *host) override_timeout_clk = host->timeout_clk; - if (host->version > SDHCI_SPEC_300) { + if (host->version > SDHCI_SPEC_420) { pr_err("%s: Unknown controller version (%d). You may experience problems.\n", mmc_hostname(mmc), host->version); } diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h index 732d82f..dbd48a8 100644 --- a/drivers/mmc/host/sdhci.h +++ b/drivers/mmc/host/sdhci.h @@ -270,6 +270,9 @@ #define SDHCI_SPEC_100 0 #define SDHCI_SPEC_200 1 #define SDHCI_SPEC_300 2 +#define SDHCI_SPEC_400 3 +#define SDHCI_SPEC_410 4 +#define SDHCI_SPEC_420 5 /* * End of controller registers. From patchwork Wed Aug 29 07:02:57 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chunyan Zhang X-Patchwork-Id: 10579565 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 8C323139B for ; Wed, 29 Aug 2018 07:03:24 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 7DCCD2AB4F for ; Wed, 29 Aug 2018 07:03:24 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 719462AB64; Wed, 29 Aug 2018 07:03:24 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 10B7F2AB4F for ; Wed, 29 Aug 2018 07:03:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727621AbeH2K6r (ORCPT ); Wed, 29 Aug 2018 06:58:47 -0400 Received: from mail-pf1-f194.google.com ([209.85.210.194]:44730 "EHLO mail-pf1-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727542AbeH2K6r (ORCPT ); Wed, 29 Aug 2018 06:58:47 -0400 Received: by mail-pf1-f194.google.com with SMTP id k21-v6so1840819pff.11 for ; Wed, 29 Aug 2018 00:03:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=0bL6uBRbs/l+78y2aEPGUN9m7CQDwNO1TiU4HYYkWDc=; b=XSEqzSedKXNLYfE5NpsZk4ZukWRCrcCS8Ptgchl3HwUEfTonVcJNiNjDWVXt4mgVqi cll3t+kMR2kfe6ca+IbbVwjBT4EsS7MDXCt1ist+6p9CSMRlnhTDJZUBiZLH1SpkM4No y0LjozQ914oQxRUvlpMEaQbvb2vkrf9mxnxlw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=0bL6uBRbs/l+78y2aEPGUN9m7CQDwNO1TiU4HYYkWDc=; b=Sb9kWYKwRoFsKW0Pdj0SclaIO7424dUigPQXYZi+HEh8JrQJyWsrsjjhktseKUNGHg IYwlBKrRVQB+7Egkp/Sypruxfl/o+uV4U9hY7SMiImnQVL1svz3wkBlapAKDzmld9V0q tA1kDiA7/Or4ciNZpwaEtE1bQverMkIl+/Adj3Az4LwyL35Yl+ioE/oqu2hsDimRxK6X 4o/9tJdKlslknrGQwFSjlcP1z04IYR8KF2bISDLiJQcEN9jAdBv5uUqBuPH+U84Oe2pa XYAM/C6X4EWWt3lhDdppyzw5N4X5AFBL2GEzxOXiuSkwD3+DNEgVO2QPkvoW7VT01D+X Mc/Q== X-Gm-Message-State: APzg51A6hDAjSXAXLOnDMs1mz6166QLk0SdIlBxvMwDE4n1BDmrcDjjx sClZSZtnixcMpfUmet3jGpUoqA== X-Google-Smtp-Source: ANB0Vdar+ysLTvqIFGE6vci4pfzo/6AyL4gO2MXrB2GJWyRz+FatCWhwIpwpMoe0sQnJyG86WPWwyw== X-Received: by 2002:a62:174a:: with SMTP id 71-v6mr4718133pfx.217.1535526201978; Wed, 29 Aug 2018 00:03:21 -0700 (PDT) Received: from ubt.spreadtrum.com ([117.18.48.102]) by smtp.gmail.com with ESMTPSA id d81-v6sm4317342pfj.122.2018.08.29.00.03.18 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 29 Aug 2018 00:03:21 -0700 (PDT) From: Chunyan Zhang To: Ulf Hansson , Adrian Hunter Cc: linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, Orson Zhai , Baolin Wang , Billows Wu , Jason Wu , Chunyan Zhang , Chunyan Zhang Subject: [PATCH V7 2/9] mmc: sdhci: Add sd host v4 mode Date: Wed, 29 Aug 2018 15:02:57 +0800 Message-Id: <1535526184-32718-3-git-send-email-zhang.chunyan@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1535526184-32718-1-git-send-email-zhang.chunyan@linaro.org> References: <1535526184-32718-1-git-send-email-zhang.chunyan@linaro.org> Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP For SD host controller version 4.00 or later ones, there're two modes of implementation - Version 3.00 compatible mode or Version 4 mode. This patch introduced an interface to enable v4 mode. Signed-off-by: Chunyan Zhang Acked-by: Adrian Hunter --- drivers/mmc/host/sdhci.c | 29 +++++++++++++++++++++++++++++ drivers/mmc/host/sdhci.h | 3 +++ 2 files changed, 32 insertions(+) diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c index 01bf88c..0c61105 100644 --- a/drivers/mmc/host/sdhci.c +++ b/drivers/mmc/host/sdhci.c @@ -123,6 +123,29 @@ EXPORT_SYMBOL_GPL(sdhci_dumpregs); * * \*****************************************************************************/ +static void sdhci_do_enable_v4_mode(struct sdhci_host *host) +{ + u16 ctrl2; + + ctrl2 = sdhci_readb(host, SDHCI_HOST_CONTROL2); + if (ctrl2 & SDHCI_CTRL_V4_MODE) + return; + + ctrl2 |= SDHCI_CTRL_V4_MODE; + sdhci_writeb(host, ctrl2, SDHCI_HOST_CONTROL); +} + +/* + * This can be called before sdhci_add_host() by Vendor's host controller + * driver to enable v4 mode if supported. + */ +void sdhci_enable_v4_mode(struct sdhci_host *host) +{ + host->v4_mode = true; + sdhci_do_enable_v4_mode(host); +} +EXPORT_SYMBOL_GPL(sdhci_enable_v4_mode); + static inline bool sdhci_data_line_cmd(struct mmc_command *cmd) { return cmd->data || cmd->flags & MMC_RSP_BUSY; @@ -252,6 +275,9 @@ static void sdhci_init(struct sdhci_host *host, int soft) else sdhci_do_reset(host, SDHCI_RESET_ALL); + if (host->v4_mode) + sdhci_do_enable_v4_mode(host); + sdhci_set_default_irqs(host); host->cqe_on = false; @@ -3378,6 +3404,9 @@ void __sdhci_read_caps(struct sdhci_host *host, u16 *ver, u32 *caps, u32 *caps1) sdhci_do_reset(host, SDHCI_RESET_ALL); + if (host->v4_mode) + sdhci_do_enable_v4_mode(host); + of_property_read_u64(mmc_dev(host->mmc)->of_node, "sdhci-caps-mask", &dt_caps_mask); of_property_read_u64(mmc_dev(host->mmc)->of_node, diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h index dbd48a8..61611e3 100644 --- a/drivers/mmc/host/sdhci.h +++ b/drivers/mmc/host/sdhci.h @@ -184,6 +184,7 @@ #define SDHCI_CTRL_DRV_TYPE_D 0x0030 #define SDHCI_CTRL_EXEC_TUNING 0x0040 #define SDHCI_CTRL_TUNED_CLK 0x0080 +#define SDHCI_CTRL_V4_MODE 0x1000 #define SDHCI_CTRL_PRESET_VAL_ENABLE 0x8000 #define SDHCI_CAPABILITIES 0x40 @@ -504,6 +505,7 @@ struct sdhci_host { bool preset_enabled; /* Preset is enabled */ bool pending_reset; /* Cmd/data reset is pending */ bool irq_wake_enabled; /* IRQ wakeup is enabled */ + bool v4_mode; /* Host Version 4 Enable */ struct mmc_request *mrqs_done[SDHCI_MAX_MRQS]; /* Requests done */ struct mmc_command *cmd; /* Current command */ @@ -752,6 +754,7 @@ bool sdhci_cqe_irq(struct sdhci_host *host, u32 intmask, int *cmd_error, int *data_error); void sdhci_dumpregs(struct sdhci_host *host); +void sdhci_enable_v4_mode(struct sdhci_host *host); void sdhci_start_tuning(struct sdhci_host *host); void sdhci_end_tuning(struct sdhci_host *host); From patchwork Wed Aug 29 07:02:58 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chunyan Zhang X-Patchwork-Id: 10579579 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 5FBD61805 for ; Wed, 29 Aug 2018 07:04:07 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 509902AB6C for ; Wed, 29 Aug 2018 07:04:07 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 44C8D2ABC1; Wed, 29 Aug 2018 07:04:07 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id D5BF12AB6C for ; Wed, 29 Aug 2018 07:04:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727677AbeH2K6w (ORCPT ); Wed, 29 Aug 2018 06:58:52 -0400 Received: from mail-pf1-f195.google.com ([209.85.210.195]:41799 "EHLO mail-pf1-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727676AbeH2K6v (ORCPT ); Wed, 29 Aug 2018 06:58:51 -0400 Received: by mail-pf1-f195.google.com with SMTP id h79-v6so1850648pfk.8 for ; Wed, 29 Aug 2018 00:03:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=BASbtQme+9NYFc4kTckiwE+4eWZRxL4aqBbLe9Llj1Q=; b=bnWksmN6GQj35dKzO4xh6PQHDeTHjXqRX/50rR0UJsPqMDLeO6PJ8Y3I8b484TM3i9 /oobJYzs2wrpgQl+XdL82G6I4HKhf2nhTwYEWtMza29xB7v54kMbwGUmLwG6+mCQ6X3d +JrJD3xSTr9McuDvh6oHF8wdznp0iTc7o0zuc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=BASbtQme+9NYFc4kTckiwE+4eWZRxL4aqBbLe9Llj1Q=; b=aoG+lDy48j+DDu+514/9nefwmn0z4g43XL1OcMPrWVASTXmJgHlkm60W5IH3J23o8e TrF8+rMEMTZUOtg7YMfoqpsv6bbCcFsL4RrqyXggiPUXKUcU48nEa+7bIRmpxnQWtsxO 01Nbxzq0xN1oaXNl3FCZB5RpcHiiSWyuwWA7P5VTDYfewHZH02tBN8K9Ylq9eRDNU4xI ej+bEmfCk2rZA3PMEZWeE4V8QOa2SWxoDediZ1xUL+YyL2dtPaeQq7DrcA6LTrXSUNd5 nsO9uAyBm2qaw/2a0FoiGpS+APoVAO9r3umKjru/MtHRvOPst+viMWiYGr8pR7jhxJl6 EN0A== X-Gm-Message-State: APzg51Bug3XLBwA3YsLkwEEc6xoM855i4zXS2fOiYkLVdtrxhkS1WZeD ImE2GukFcaQdcfiLPODlUxY7sg== X-Google-Smtp-Source: ANB0VdapLOnzBLMKH/431ZdVn3ej3fh6U0Bxr9zGARMNkcigjM9RmytYnb5hwkCqRcIfCdHZbcECXQ== X-Received: by 2002:a63:444d:: with SMTP id t13-v6mr4541487pgk.102.1535526206262; Wed, 29 Aug 2018 00:03:26 -0700 (PDT) Received: from ubt.spreadtrum.com ([117.18.48.102]) by smtp.gmail.com with ESMTPSA id d81-v6sm4317342pfj.122.2018.08.29.00.03.22 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 29 Aug 2018 00:03:25 -0700 (PDT) From: Chunyan Zhang To: Ulf Hansson , Adrian Hunter Cc: linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, Orson Zhai , Baolin Wang , Billows Wu , Jason Wu , Chunyan Zhang , Chunyan Zhang Subject: [PATCH V7 3/9] mmc: sdhci: Change SDMA address register for v4 mode Date: Wed, 29 Aug 2018 15:02:58 +0800 Message-Id: <1535526184-32718-4-git-send-email-zhang.chunyan@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1535526184-32718-1-git-send-email-zhang.chunyan@linaro.org> References: <1535526184-32718-1-git-send-email-zhang.chunyan@linaro.org> Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP According to the SD host controller specification version 4.10, when Host Version 4 is enabled, SDMA uses ADMA System Address register (05Fh-058h) instead of using SDMA System Address register to support both 32-bit and 64-bit addressing. Signed-off-by: Chunyan Zhang Acked-by: Adrian Hunter --- drivers/mmc/host/sdhci.c | 30 ++++++++++++++++++++---------- 1 file changed, 20 insertions(+), 10 deletions(-) diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c index 0c61105..6fb70da 100644 --- a/drivers/mmc/host/sdhci.c +++ b/drivers/mmc/host/sdhci.c @@ -727,7 +727,7 @@ static void sdhci_adma_table_post(struct sdhci_host *host, } } -static u32 sdhci_sdma_address(struct sdhci_host *host) +static dma_addr_t sdhci_sdma_address(struct sdhci_host *host) { if (host->bounce_buffer) return host->bounce_addr; @@ -735,6 +735,17 @@ static u32 sdhci_sdma_address(struct sdhci_host *host) return sg_dma_address(host->data->sg); } +static void sdhci_set_sdma_addr(struct sdhci_host *host, dma_addr_t addr) +{ + if (host->v4_mode) { + sdhci_writel(host, addr, SDHCI_ADMA_ADDRESS); + if (host->flags & SDHCI_USE_64_BIT_DMA) + sdhci_writel(host, (u64)addr >> 32, SDHCI_ADMA_ADDRESS_HI); + } else { + sdhci_writel(host, addr, SDHCI_DMA_ADDRESS); + } +} + static unsigned int sdhci_target_timeout(struct sdhci_host *host, struct mmc_command *cmd, struct mmc_data *data) @@ -994,8 +1005,7 @@ static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd) SDHCI_ADMA_ADDRESS_HI); } else { WARN_ON(sg_cnt != 1); - sdhci_writel(host, sdhci_sdma_address(host), - SDHCI_DMA_ADDRESS); + sdhci_set_sdma_addr(host, sdhci_sdma_address(host)); } } @@ -2830,7 +2840,7 @@ static void sdhci_data_irq(struct sdhci_host *host, u32 intmask) * some controllers are faulty, don't trust them. */ if (intmask & SDHCI_INT_DMA_END) { - u32 dmastart, dmanow; + dma_addr_t dmastart, dmanow; dmastart = sdhci_sdma_address(host); dmanow = dmastart + host->data->bytes_xfered; @@ -2838,12 +2848,12 @@ static void sdhci_data_irq(struct sdhci_host *host, u32 intmask) * Force update to the next DMA block boundary. */ dmanow = (dmanow & - ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) + + ~((dma_addr_t)SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) + SDHCI_DEFAULT_BOUNDARY_SIZE; host->data->bytes_xfered = dmanow - dmastart; - DBG("DMA base 0x%08x, transferred 0x%06x bytes, next 0x%08x\n", - dmastart, host->data->bytes_xfered, dmanow); - sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS); + DBG("DMA base %pad, transferred 0x%06x bytes, next %pad\n", + &dmastart, host->data->bytes_xfered, &dmanow); + sdhci_set_sdma_addr(host, dmanow); } if (intmask & SDHCI_INT_DATA_END) { @@ -3590,8 +3600,8 @@ int sdhci_setup_host(struct sdhci_host *host) } } - /* SDMA does not support 64-bit DMA */ - if (host->flags & SDHCI_USE_64_BIT_DMA) + /* SDMA does not support 64-bit DMA if v4 mode not set */ + if ((host->flags & SDHCI_USE_64_BIT_DMA) && !host->v4_mode) host->flags &= ~SDHCI_USE_SDMA; if (host->flags & SDHCI_USE_ADMA) { From patchwork Wed Aug 29 07:02:59 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chunyan Zhang X-Patchwork-Id: 10579577 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 50682139B for ; Wed, 29 Aug 2018 07:04:07 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 3FC412AB64 for ; Wed, 29 Aug 2018 07:04:07 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 3412A2ABC2; Wed, 29 Aug 2018 07:04:07 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 988A42AB64 for ; Wed, 29 Aug 2018 07:04:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727456AbeH2K7a (ORCPT ); Wed, 29 Aug 2018 06:59:30 -0400 Received: from mail-pl1-f194.google.com ([209.85.214.194]:38020 "EHLO mail-pl1-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727575AbeH2K64 (ORCPT ); Wed, 29 Aug 2018 06:58:56 -0400 Received: by mail-pl1-f194.google.com with SMTP id u11-v6so1888655plq.5 for ; Wed, 29 Aug 2018 00:03:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=c/eV9ZN7dNN0gTb1HotdKJUB+PKAX41PZSlC9GVsCR4=; b=iGDms1bGEXHVyC9Lz1Sq6+1gpZzMe7gRddF7OC5SiZxFn0I6odf01I53tcgHGUoYAr FGCEIHaBbBx9WvaAmiDSZAh2yA0gcHdq1kxOcPhvLEIcWgbJpXVxj0CbJ+SQpvnhUZMR h14i/JmOVODpA7RWBlp8Br/W1vdl635OZ/Cag= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=c/eV9ZN7dNN0gTb1HotdKJUB+PKAX41PZSlC9GVsCR4=; b=kbCah+X301HtMSVxvzK3on4jRej7w/0Uf9MJ/a7fd3LqmlA4GzRQgYRLI/FdV9jQPH 6W+Lm+BIFSh8ghp1uSov3Ahjqopf2zPmWEevLli1zNhG1Q9NV6ZasHoJWDpS4+R9snhS HI/lorXrzof3mmsThb0XpES9zWPwhG0ZhZANgNka5ftymhRlb1HmKZCPI8QJ0M1FZGDU Vvpp3yAsg+r2H0i35LvtiOShzvPlJVvX9A4RJL3ipcpJD44InXuLs9DsOh7md+2szoKn xbJj6Yz+xD4TNwHyBKbo+WNw/evjYHRr3wZw8ghIkRcC1/lMbTo+9onzGNjjuTtA008q kgaQ== X-Gm-Message-State: APzg51AYzXklM9T1ydT4bXEbYJ8ZCv1XY2IQHccnzmIOaL6fnbw7pk4u 4AzmtSZbkDHa1psBN3J396IxJw== X-Google-Smtp-Source: ANB0VdayDGUFWhXeMt02HOw11tTEfYXRYVUB4L8wBliJJchqIa9Vk1vFs2miREtzhYeMNl+dvnp5/A== X-Received: by 2002:a17:902:4401:: with SMTP id k1-v6mr4562523pld.97.1535526210900; Wed, 29 Aug 2018 00:03:30 -0700 (PDT) Received: from ubt.spreadtrum.com ([117.18.48.102]) by smtp.gmail.com with ESMTPSA id d81-v6sm4317342pfj.122.2018.08.29.00.03.26 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 29 Aug 2018 00:03:30 -0700 (PDT) From: Chunyan Zhang To: Ulf Hansson , Adrian Hunter Cc: linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, Orson Zhai , Baolin Wang , Billows Wu , Jason Wu , Chunyan Zhang , Chunyan Zhang Subject: [PATCH V7 4/9] mmc: sdhci: Add ADMA2 64-bit addressing support for V4 mode Date: Wed, 29 Aug 2018 15:02:59 +0800 Message-Id: <1535526184-32718-5-git-send-email-zhang.chunyan@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1535526184-32718-1-git-send-email-zhang.chunyan@linaro.org> References: <1535526184-32718-1-git-send-email-zhang.chunyan@linaro.org> Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP ADMA2 64-bit addressing support is divided into V3 mode and V4 mode. So there are two kinds of descriptors for ADMA2 64-bit addressing i.e. 96-bit Descriptor for V3 mode, and 128-bit Descriptor for V4 mode. 128-bit Descriptor is aligned to 8-byte. For V4 mode, ADMA2 64-bit addressing is enabled via Host Control 2 register. Signed-off-by: Chunyan Zhang Acked-by: Adrian Hunter --- drivers/mmc/host/sdhci.c | 92 +++++++++++++++++++++++++++++++++++------------- drivers/mmc/host/sdhci.h | 12 +++++-- 2 files changed, 78 insertions(+), 26 deletions(-) diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c index 6fb70da..17345b6 100644 --- a/drivers/mmc/host/sdhci.c +++ b/drivers/mmc/host/sdhci.c @@ -266,6 +266,52 @@ static void sdhci_set_default_irqs(struct sdhci_host *host) sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); } +static void sdhci_config_dma(struct sdhci_host *host) +{ + u8 ctrl; + u16 ctrl2; + + if (host->version < SDHCI_SPEC_200) + return; + + ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); + + /* + * Always adjust the DMA selection as some controllers + * (e.g. JMicron) can't do PIO properly when the selection + * is ADMA. + */ + ctrl &= ~SDHCI_CTRL_DMA_MASK; + if (!(host->flags & SDHCI_REQ_USE_DMA)) + goto out; + + /* Note if DMA Select is zero then SDMA is selected */ + if (host->flags & SDHCI_USE_ADMA) + ctrl |= SDHCI_CTRL_ADMA32; + + if (host->flags & SDHCI_USE_64_BIT_DMA) { + /* + * If v4 mode, all supported DMA can be 64-bit addressing if + * controller supports 64-bit system address, otherwise only + * ADMA can support 64-bit addressing. + */ + if (host->v4_mode) { + ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); + ctrl2 |= SDHCI_CTRL_64BIT_ADDR; + sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2); + } else if (host->flags & SDHCI_USE_ADMA) { + /* + * Don't need to undo SDHCI_CTRL_ADMA32 in order to + * set SDHCI_CTRL_ADMA64. + */ + ctrl |= SDHCI_CTRL_ADMA64; + } + } + +out: + sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); +} + static void sdhci_init(struct sdhci_host *host, int soft) { struct mmc_host *mmc = host->mmc; @@ -913,7 +959,6 @@ static void sdhci_set_timeout(struct sdhci_host *host, struct mmc_command *cmd) static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd) { - u8 ctrl; struct mmc_data *data = cmd->data; host->data_timeout = 0; @@ -1009,25 +1054,7 @@ static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd) } } - /* - * Always adjust the DMA selection as some controllers - * (e.g. JMicron) can't do PIO properly when the selection - * is ADMA. - */ - if (host->version >= SDHCI_SPEC_200) { - ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); - ctrl &= ~SDHCI_CTRL_DMA_MASK; - if ((host->flags & SDHCI_REQ_USE_DMA) && - (host->flags & SDHCI_USE_ADMA)) { - if (host->flags & SDHCI_USE_64_BIT_DMA) - ctrl |= SDHCI_CTRL_ADMA64; - else - ctrl |= SDHCI_CTRL_ADMA32; - } else { - ctrl |= SDHCI_CTRL_SDMA; - } - sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); - } + sdhci_config_dma(host); if (!(host->flags & SDHCI_REQ_USE_DMA)) { int flags; @@ -3511,6 +3538,19 @@ static int sdhci_allocate_bounce_buffer(struct sdhci_host *host) return 0; } +static inline bool sdhci_can_64bit_dma(struct sdhci_host *host) +{ + /* + * According to SD Host Controller spec v4.10, bit[27] added from + * version 4.10 in Capabilities Register is used as 64-bit System + * Address support for V4 mode. + */ + if (host->version >= SDHCI_SPEC_410 && host->v4_mode) + return host->caps & SDHCI_CAN_64BIT_V4; + + return host->caps & SDHCI_CAN_64BIT; +} + int sdhci_setup_host(struct sdhci_host *host) { struct mmc_host *mmc; @@ -3582,7 +3622,7 @@ int sdhci_setup_host(struct sdhci_host *host) * SDHCI_QUIRK2_BROKEN_64_BIT_DMA must be left to the drivers to * implement. */ - if (host->caps & SDHCI_CAN_64BIT) + if (sdhci_can_64bit_dma(host)) host->flags |= SDHCI_USE_64_BIT_DMA; if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) { @@ -3616,8 +3656,8 @@ int sdhci_setup_host(struct sdhci_host *host) */ if (host->flags & SDHCI_USE_64_BIT_DMA) { host->adma_table_sz = (SDHCI_MAX_SEGS * 2 + 1) * - SDHCI_ADMA2_64_DESC_SZ; - host->desc_sz = SDHCI_ADMA2_64_DESC_SZ; + SDHCI_ADMA2_64_DESC_SZ(host); + host->desc_sz = SDHCI_ADMA2_64_DESC_SZ(host); } else { host->adma_table_sz = (SDHCI_MAX_SEGS * 2 + 1) * SDHCI_ADMA2_32_DESC_SZ; @@ -3625,7 +3665,11 @@ int sdhci_setup_host(struct sdhci_host *host) } host->align_buffer_sz = SDHCI_MAX_SEGS * SDHCI_ADMA2_ALIGN; - buf = dma_alloc_coherent(mmc_dev(mmc), host->align_buffer_sz + + /* + * Use zalloc to zero the reserved high 32-bits of 128-bit + * descriptors so that they never need to be written. + */ + buf = dma_zalloc_coherent(mmc_dev(mmc), host->align_buffer_sz + host->adma_table_sz, &dma, GFP_KERNEL); if (!buf) { pr_warn("%s: Unable to allocate ADMA buffers - falling back to standard DMA\n", diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h index 61611e3..c5cc513 100644 --- a/drivers/mmc/host/sdhci.h +++ b/drivers/mmc/host/sdhci.h @@ -185,6 +185,7 @@ #define SDHCI_CTRL_EXEC_TUNING 0x0040 #define SDHCI_CTRL_TUNED_CLK 0x0080 #define SDHCI_CTRL_V4_MODE 0x1000 +#define SDHCI_CTRL_64BIT_ADDR 0x2000 #define SDHCI_CTRL_PRESET_VAL_ENABLE 0x8000 #define SDHCI_CAPABILITIES 0x40 @@ -205,6 +206,7 @@ #define SDHCI_CAN_VDD_330 0x01000000 #define SDHCI_CAN_VDD_300 0x02000000 #define SDHCI_CAN_VDD_180 0x04000000 +#define SDHCI_CAN_64BIT_V4 0x08000000 #define SDHCI_CAN_64BIT 0x10000000 #define SDHCI_SUPPORT_SDR50 0x00000001 @@ -309,8 +311,14 @@ struct sdhci_adma2_32_desc { */ #define SDHCI_ADMA2_DESC_ALIGN 8 -/* ADMA2 64-bit DMA descriptor size */ -#define SDHCI_ADMA2_64_DESC_SZ 12 +/* + * ADMA2 64-bit DMA descriptor size + * According to SD Host Controller spec v4.10, there are two kinds of + * descriptors for 64-bit addressing mode: 96-bit Descriptor and 128-bit + * Descriptor, if Host Version 4 Enable is set in the Host Control 2 + * register, 128-bit Descriptor will be selected. + */ +#define SDHCI_ADMA2_64_DESC_SZ(host) ((host)->v4_mode ? 16 : 12) /* * ADMA2 64-bit descriptor. Note 12-byte descriptor can't always be 8-byte From patchwork Wed Aug 29 07:03:00 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chunyan Zhang X-Patchwork-Id: 10579573 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 13E841709 for ; Wed, 29 Aug 2018 07:04:06 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 04F292AB82 for ; Wed, 29 Aug 2018 07:04:06 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id ECF282ABC1; Wed, 29 Aug 2018 07:04:05 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 7D12D2AB6C for ; Wed, 29 Aug 2018 07:04:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727392AbeH2K7B (ORCPT ); Wed, 29 Aug 2018 06:59:01 -0400 Received: from mail-pl1-f196.google.com ([209.85.214.196]:38029 "EHLO mail-pl1-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726858AbeH2K7B (ORCPT ); Wed, 29 Aug 2018 06:59:01 -0400 Received: by mail-pl1-f196.google.com with SMTP id u11-v6so1888743plq.5 for ; Wed, 29 Aug 2018 00:03:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=gVnMBXKc4i1JKgy6ffbRwQOZ0ThpKQAJZ1YKfPm++hw=; b=ZgS7aX3Gd161MtYIFxe4+J6bndokBsbo5aXCfXNj3pxipKi+TVYcErEWiGn27HJGHL UWVYIe2mMiv4As65G44FqFrne5ummVTBxIV0F+IQ0LUUVXUVOi6kTX0Bpo8aLatbXUaY f526m9PouwRhPGgltyy115t1Q9tRqkrsiwdBg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=gVnMBXKc4i1JKgy6ffbRwQOZ0ThpKQAJZ1YKfPm++hw=; b=s3zas39fMI2Dr3asPlaTYqHudE4vrJnW8TEKXAdaMFPlbS6Mr33FgAK1TkkgCACZZ+ wvmMmd5LxgbXvK/EDIPgCqstttMAFZ9YeFdiMwXG8yh/OjqeBIa8MWwuKozexTE+Wr+9 h70ecOVqt5rxhbBgA5OWlJ9E1Hl5To4IwBnowgk+UPh1rBC0D45f9Gk2d1IEYimrZEL0 KN7MbziH1FdJSOalzBxWewLv3LlO0EbZ4A363621h4bHg1A4JkMTy3J9HmXA9+RRjhVt WV6L7f1A+qXPyzOXwHkTy9pFLI3WVnzCcLxxC+LTtvxOZxVEYwIdtl/Vp0W7DexOizzU cHDw== X-Gm-Message-State: APzg51B8IN9Q239Kne+ou6auP1elmqssrR3M64bJIVuUoO0FpoEGykh5 dOM/PxqqR3NthbAksczG4ex93Q== X-Google-Smtp-Source: ANB0VdYbGWA74Z8v2IKITWrbHgu4J5amSQZUqvpBvoSQL5Yg9YyRcsKJaX+vwYhSI7PJ7kURqFcV7g== X-Received: by 2002:a17:902:850c:: with SMTP id bj12-v6mr4823484plb.330.1535526216022; Wed, 29 Aug 2018 00:03:36 -0700 (PDT) Received: from ubt.spreadtrum.com ([117.18.48.102]) by smtp.gmail.com with ESMTPSA id d81-v6sm4317342pfj.122.2018.08.29.00.03.31 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 29 Aug 2018 00:03:35 -0700 (PDT) From: Chunyan Zhang To: Ulf Hansson , Adrian Hunter Cc: linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, Orson Zhai , Baolin Wang , Billows Wu , Jason Wu , Chunyan Zhang , Chunyan Zhang Subject: [PATCH V7 5/9] mmc: sdhci: Add 32-bit block count support for v4 mode Date: Wed, 29 Aug 2018 15:03:00 +0800 Message-Id: <1535526184-32718-6-git-send-email-zhang.chunyan@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1535526184-32718-1-git-send-email-zhang.chunyan@linaro.org> References: <1535526184-32718-1-git-send-email-zhang.chunyan@linaro.org> Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Host Controller Version 4.10 re-defines SDMA System Address register as 32-bit Block Count for v4 mode, and SDMA uses ADMA System Address register (05Fh-058h) instead if v4 mode is enabled. Also when using 32-bit block count, 16-bit block count register need to be set to zero. Since using 32-bit Block Count would cause problems for auto-cmd23, it can be chosen via host->quirk2. Signed-off-by: Chunyan Zhang Acked-by: Adrian Hunter --- drivers/mmc/host/sdhci.c | 14 +++++++++++++- drivers/mmc/host/sdhci.h | 8 ++++++++ 2 files changed, 21 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c index 17345b6..604bf4c 100644 --- a/drivers/mmc/host/sdhci.c +++ b/drivers/mmc/host/sdhci.c @@ -1073,7 +1073,19 @@ static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd) /* Set the DMA boundary value and block size */ sdhci_writew(host, SDHCI_MAKE_BLKSZ(host->sdma_boundary, data->blksz), SDHCI_BLOCK_SIZE); - sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT); + + /* + * For Version 4.10 onwards, if v4 mode is enabled, 32-bit Block Count + * can be supported, in that case 16-bit block count register must be 0. + */ + if (host->version >= SDHCI_SPEC_410 && host->v4_mode && + (host->quirks2 & SDHCI_QUIRK2_USE_32BIT_BLK_CNT)) { + if (sdhci_readw(host, SDHCI_BLOCK_COUNT)) + sdhci_writew(host, 0, SDHCI_BLOCK_COUNT); + sdhci_writew(host, data->blocks, SDHCI_32BIT_BLK_CNT); + } else { + sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT); + } } static inline bool sdhci_auto_cmd12(struct sdhci_host *host, diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h index c5cc513..f7a1079 100644 --- a/drivers/mmc/host/sdhci.h +++ b/drivers/mmc/host/sdhci.h @@ -28,6 +28,7 @@ #define SDHCI_DMA_ADDRESS 0x00 #define SDHCI_ARGUMENT2 SDHCI_DMA_ADDRESS +#define SDHCI_32BIT_BLK_CNT SDHCI_DMA_ADDRESS #define SDHCI_BLOCK_SIZE 0x04 #define SDHCI_MAKE_BLKSZ(dma, blksz) (((dma & 0x7) << 12) | (blksz & 0xFFF)) @@ -462,6 +463,13 @@ struct sdhci_host { * obtainable timeout. */ #define SDHCI_QUIRK2_DISABLE_HW_TIMEOUT (1<<17) +/* + * 32-bit block count may not support eMMC where upper bits of CMD23 are used + * for other purposes. Consequently we support 16-bit block count by default. + * Otherwise, SDHCI_QUIRK2_USE_32BIT_BLK_CNT can be selected to use 32-bit + * block count. + */ +#define SDHCI_QUIRK2_USE_32BIT_BLK_CNT (1<<18) int irq; /* Device IRQ */ void __iomem *ioaddr; /* Mapped address */ From patchwork Wed Aug 29 07:03:01 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chunyan Zhang X-Patchwork-Id: 10579575 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 279BA1805 for ; Wed, 29 Aug 2018 07:04:06 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 18B682AB64 for ; Wed, 29 Aug 2018 07:04:06 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 0D14D2ABDD; Wed, 29 Aug 2018 07:04:06 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id EC2A82AB64 for ; Wed, 29 Aug 2018 07:04:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727558AbeH2K7G (ORCPT ); Wed, 29 Aug 2018 06:59:06 -0400 Received: from mail-pg1-f195.google.com ([209.85.215.195]:33113 "EHLO mail-pg1-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727560AbeH2K7F (ORCPT ); Wed, 29 Aug 2018 06:59:05 -0400 Received: by mail-pg1-f195.google.com with SMTP id y3-v6so698105pgv.0 for ; Wed, 29 Aug 2018 00:03:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=9gO45GPUCiWNoJSPPW5yykw6lOn1on3+rP/v8SuzWGk=; b=QBFWRQX0gaMKEq94OiPVi2I1NokcHktXgosg718cMFPkhord4M7chknNgxq8A2jmQj x06VfYu0EJETEi2z/cDBCJCJ0siqFU0S5OPRdYA9iXvj1SgN9zgcWt3HBSVW8vWLILlz 2OvFYmmAM+K2bS4ZEIoUgPzpEeGwH0MVRT/tI= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=9gO45GPUCiWNoJSPPW5yykw6lOn1on3+rP/v8SuzWGk=; b=mArkso4Dq/yOfCcNJ1go4w9GRfXx+3H1FA8b7xkA5Z9Wp6RQfcM5BfjTuXZokAe9lY FqlgUgX/roAAHSH1BiBMU/987vhf91gPAX4imUOs7Mk4lUV//ldphwQf1sAPRiucDB+5 UglPoA8p3cAgKUp/Vza9UDGSCYP721zrLOxEZjGrnhqYECLmpy/jUXNhwv4f4Agg4P2h gVZO7GNtXtKKpNxFwVHU9BNS7WIA5CDuG85AX2/s4c8U2D3J0HsU8DatewYz4EO7QlIp iVRAg1uy1UXgkib9ikcT3hFF2EL01q6GcExkJYjHKH0VHHdC9yKHDxg0UUr+uN9MtKyU NuSQ== X-Gm-Message-State: APzg51ACvEP1Qz5gWwdtl05KSYjfzMyzofqBlpOo3qaMKBD5UdfjbhVq Z6TTVKhqgucZghoeJFcWbz5cVg== X-Google-Smtp-Source: ANB0Vdbc4wwz0uzRwiVT7NbKw1p/EJqLtGX1ATiEULmbHmrh+hKWJdGAzxncAeeB5pSr061df78yow== X-Received: by 2002:a65:5189:: with SMTP id h9-v6mr4598889pgq.13.1535526220465; Wed, 29 Aug 2018 00:03:40 -0700 (PDT) Received: from ubt.spreadtrum.com ([117.18.48.102]) by smtp.gmail.com with ESMTPSA id d81-v6sm4317342pfj.122.2018.08.29.00.03.36 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 29 Aug 2018 00:03:39 -0700 (PDT) From: Chunyan Zhang To: Ulf Hansson , Adrian Hunter Cc: linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, Orson Zhai , Baolin Wang , Billows Wu , Jason Wu , Chunyan Zhang , Chunyan Zhang Subject: [PATCH V7 6/9] mmc: sdhci: Add Auto CMD Auto Select support Date: Wed, 29 Aug 2018 15:03:01 +0800 Message-Id: <1535526184-32718-7-git-send-email-zhang.chunyan@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1535526184-32718-1-git-send-email-zhang.chunyan@linaro.org> References: <1535526184-32718-1-git-send-email-zhang.chunyan@linaro.org> Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP As SD Host Controller Specification v4.10 documents: Host Controller Version 4.10 defines this "Auto CMD Auto Select" mode. Selection of Auto CMD depends on setting of CMD23 Enable in the Host Control 2 register which indicates whether card supports CMD23. If CMD23 Enable =1, Auto CMD23 is used and if CMD23 Enable =0, Auto CMD12 is used. In case of Version 4.10 or later, use of Auto CMD Auto Select is recommended rather than use of Auto CMD12 Enable or Auto CMD23 Enable. This patch add this new mode support. Signed-off-by: Chunyan Zhang Acked-by: Adrian Hunter --- drivers/mmc/host/sdhci.c | 49 ++++++++++++++++++++++++++++++++++++++---------- drivers/mmc/host/sdhci.h | 2 ++ 2 files changed, 41 insertions(+), 10 deletions(-) diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c index 604bf4c..62d843ac90 100644 --- a/drivers/mmc/host/sdhci.c +++ b/drivers/mmc/host/sdhci.c @@ -1095,6 +1095,43 @@ static inline bool sdhci_auto_cmd12(struct sdhci_host *host, !mrq->cap_cmd_during_tfr; } +static inline void sdhci_auto_cmd_select(struct sdhci_host *host, + struct mmc_command *cmd, + u16 *mode) +{ + bool use_cmd12 = sdhci_auto_cmd12(host, cmd->mrq) && + (cmd->opcode != SD_IO_RW_EXTENDED); + bool use_cmd23 = cmd->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23); + u16 ctrl2; + + /* + * In case of Version 4.10 or later, use of 'Auto CMD Auto + * Select' is recommended rather than use of 'Auto CMD12 + * Enable' or 'Auto CMD23 Enable'. + */ + if (host->version >= SDHCI_SPEC_410 && (use_cmd12 || use_cmd23)) { + *mode |= SDHCI_TRNS_AUTO_SEL; + + ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); + if (use_cmd23) + ctrl2 |= SDHCI_CMD23_ENABLE; + else + ctrl2 &= ~SDHCI_CMD23_ENABLE; + sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2); + + return; + } + + /* + * If we are sending CMD23, CMD12 never gets sent + * on successful completion (so no Auto-CMD12). + */ + if (use_cmd12) + *mode |= SDHCI_TRNS_AUTO_CMD12; + else if (use_cmd23) + *mode |= SDHCI_TRNS_AUTO_CMD23; +} + static void sdhci_set_transfer_mode(struct sdhci_host *host, struct mmc_command *cmd) { @@ -1123,17 +1160,9 @@ static void sdhci_set_transfer_mode(struct sdhci_host *host, if (mmc_op_multi(cmd->opcode) || data->blocks > 1) { mode = SDHCI_TRNS_BLK_CNT_EN | SDHCI_TRNS_MULTI; - /* - * If we are sending CMD23, CMD12 never gets sent - * on successful completion (so no Auto-CMD12). - */ - if (sdhci_auto_cmd12(host, cmd->mrq) && - (cmd->opcode != SD_IO_RW_EXTENDED)) - mode |= SDHCI_TRNS_AUTO_CMD12; - else if (cmd->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) { - mode |= SDHCI_TRNS_AUTO_CMD23; + sdhci_auto_cmd_select(host, cmd, &mode); + if (cmd->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) sdhci_writel(host, cmd->mrq->sbc->arg, SDHCI_ARGUMENT2); - } } if (data->flags & MMC_DATA_READ) diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h index f7a1079..4a19ff8 100644 --- a/drivers/mmc/host/sdhci.h +++ b/drivers/mmc/host/sdhci.h @@ -42,6 +42,7 @@ #define SDHCI_TRNS_BLK_CNT_EN 0x02 #define SDHCI_TRNS_AUTO_CMD12 0x04 #define SDHCI_TRNS_AUTO_CMD23 0x08 +#define SDHCI_TRNS_AUTO_SEL 0x0C #define SDHCI_TRNS_READ 0x10 #define SDHCI_TRNS_MULTI 0x20 @@ -185,6 +186,7 @@ #define SDHCI_CTRL_DRV_TYPE_D 0x0030 #define SDHCI_CTRL_EXEC_TUNING 0x0040 #define SDHCI_CTRL_TUNED_CLK 0x0080 +#define SDHCI_CMD23_ENABLE 0x0800 #define SDHCI_CTRL_V4_MODE 0x1000 #define SDHCI_CTRL_64BIT_ADDR 0x2000 #define SDHCI_CTRL_PRESET_VAL_ENABLE 0x8000 From patchwork Wed Aug 29 07:03:02 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chunyan Zhang X-Patchwork-Id: 10579567 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 0D492139B for ; Wed, 29 Aug 2018 07:03:52 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id F238E2AB5F for ; Wed, 29 Aug 2018 07:03:51 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id E69042AB6C; Wed, 29 Aug 2018 07:03:51 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 92A5A2AB5F for ; Wed, 29 Aug 2018 07:03:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727788AbeH2K7K (ORCPT ); Wed, 29 Aug 2018 06:59:10 -0400 Received: from mail-pl1-f195.google.com ([209.85.214.195]:34112 "EHLO mail-pl1-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727172AbeH2K7J (ORCPT ); Wed, 29 Aug 2018 06:59:09 -0400 Received: by mail-pl1-f195.google.com with SMTP id f6-v6so1899381plo.1 for ; Wed, 29 Aug 2018 00:03:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=F6JNjnqOBxraoAmJ2G9nQq3A9aaEWZWPodCkmFELEA4=; b=FTt8+uiIDtMNr76i4SHHbEdmo3x0fQckM4/6nQz3cKegXczL/kS8xRQ86loF+ym1uP 3Fpd5LHKwS30oEPpmqKE/5WBxvTynx6qm7zdYVXJzSnMnivIcq/YIMSSdvCqnFxpwflb ohKMYLCNY5PjsqLIsr49T3uTBongbaNEe/jJg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=F6JNjnqOBxraoAmJ2G9nQq3A9aaEWZWPodCkmFELEA4=; b=gTJAdtn6b5/GSHnnKd1C1H3uS0gVhkCdGKx4mLKWNedtdX1QD9FL1SfSP9/WwUv72D fFDjTb7pKlMr42xNj+SZq7wVnG/yPArYAZccAL824FfQiLW4H3jRgnCQKIkmJM54S9RN g3Ns9jFcgobL7UQQ6lbtJZ1Tfx/eQQGSJX78lBWXQl1+0qFm8eQusZ7kTGFYKAj67k6a pbOyL5mE5+wq/AIkLwnymSqnGuiLZbIbMd8y9kIrjHwDnoajUgSRKr9ecNeYkKh6tD7e 7ZLSUlUtfwieG60TAU+Gz+R1X1DI//US+yfQpKO8c/OCL9PWIdAx/jjOm+BAbgAcVatR eNtQ== X-Gm-Message-State: APzg51AyBXgW0U/XwW5ShXQrq8ZLRQIMymhIOlq+UMzn6rjhc9rIX29X rXZk352xGoVqU17itmRdNBn0uQ== X-Google-Smtp-Source: ANB0Vdb9jhj0ILPiroZ4dZvMX4HK1fY7gO+RlY8olSezD7WgLyIVb3OxW7/irkjFgdX7242wF/scqA== X-Received: by 2002:a17:902:a987:: with SMTP id bh7-v6mr4834081plb.182.1535526224623; Wed, 29 Aug 2018 00:03:44 -0700 (PDT) Received: from ubt.spreadtrum.com ([117.18.48.102]) by smtp.gmail.com with ESMTPSA id d81-v6sm4317342pfj.122.2018.08.29.00.03.40 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 29 Aug 2018 00:03:43 -0700 (PDT) From: Chunyan Zhang To: Ulf Hansson , Adrian Hunter Cc: linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, Orson Zhai , Baolin Wang , Billows Wu , Jason Wu , Chunyan Zhang , Chunyan Zhang Subject: [PATCH V7 7/9] mmc: sdhci: SDMA may use Auto-CMD23 in v4 mode Date: Wed, 29 Aug 2018 15:03:02 +0800 Message-Id: <1535526184-32718-8-git-send-email-zhang.chunyan@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1535526184-32718-1-git-send-email-zhang.chunyan@linaro.org> References: <1535526184-32718-1-git-send-email-zhang.chunyan@linaro.org> Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP When Host Version 4 Enable is set to 1, SDMA uses ADMA System Address register (05Fh-058h) instead of using register (000h-004h) to indicate its system address of data location. The register (000h-004h) is re-assigned to 32-bit Block Count and Auto CMD23 argument, so then SDMA may use Auto CMD23. Signed-off-by: Chunyan Zhang --- drivers/mmc/host/sdhci.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c index 62d843ac90..ac92e0f 100644 --- a/drivers/mmc/host/sdhci.c +++ b/drivers/mmc/host/sdhci.c @@ -3834,10 +3834,14 @@ int sdhci_setup_host(struct sdhci_host *host) if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12) host->flags |= SDHCI_AUTO_CMD12; - /* Auto-CMD23 stuff only works in ADMA or PIO. */ + /* + * For v3 mode, Auto-CMD23 stuff only works in ADMA or PIO; + * For v4 mode, SDMA may use Auto-CMD23 as well. + */ if ((host->version >= SDHCI_SPEC_300) && ((host->flags & SDHCI_USE_ADMA) || - !(host->flags & SDHCI_USE_SDMA)) && + (!host->v4_mode && !(host->flags & SDHCI_USE_SDMA)) || + (host->v4_mode && (host->flags & SDHCI_USE_SDMA))) && !(host->quirks2 & SDHCI_QUIRK2_ACMD23_BROKEN)) { host->flags |= SDHCI_AUTO_CMD23; DBG("Auto-CMD23 available\n"); From patchwork Wed Aug 29 07:03:03 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chunyan Zhang X-Patchwork-Id: 10579571 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id ADE3D139B for ; Wed, 29 Aug 2018 07:04:04 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 9BC662AB64 for ; Wed, 29 Aug 2018 07:04:04 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 8F3E12AB82; Wed, 29 Aug 2018 07:04:04 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 768402AB64 for ; Wed, 29 Aug 2018 07:04:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727484AbeH2K7Q (ORCPT ); Wed, 29 Aug 2018 06:59:16 -0400 Received: from mail-pf1-f193.google.com ([209.85.210.193]:36687 "EHLO mail-pf1-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727544AbeH2K7P (ORCPT ); Wed, 29 Aug 2018 06:59:15 -0400 Received: by mail-pf1-f193.google.com with SMTP id b11-v6so1864959pfo.3 for ; Wed, 29 Aug 2018 00:03:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=EOMZ+0K209Ld8iUvEB262q4DzLp3hVOASvPvbcCcg2M=; b=JUqpZI61TEon5sfgOcZNnaAZXcYm0PEL3aOemvMnN6FR5HYF/TXQuOhczmHF/bFTrS zssrxO5GF5MefrC2mZ/XfjgL87Bhb2z24urqAcHBKzlrGNMiLJR7MUGrNtad7JAaEpA2 doOln/nrKkAC4EcRiI0G0zCAuTiFihET3GDcU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=EOMZ+0K209Ld8iUvEB262q4DzLp3hVOASvPvbcCcg2M=; b=sOHaKvE4cH2HYm7p7cJCXev5l9wYjhAXynMS4qiLhkE7jWWWhq3yrFEjarxPQMa2T5 qQXmmdhTYD3m55qyw94v8HXwLXoM64XX7262J0I+qnDDzm+h2SxHlle9zjq/1U8fwvwX sm3Dtmnxj+qABmQnPMcj+p5GmbNFgRr5Hx3UMgdrOtHtwvGCG5DfoBdR6LmgcUJ8Bt0r WTPj2LF/1XkXDH3sucV3XuS8KFo+7doKfX2SHBsR1zrGy4ncveLjJ2sFuNrhRfxLUgYN UJkiM1rJS+dBWyMRSSvutEvmYeQ19P6fY+C5p2D0vKG59Y+zsIwkFU/Fum5k993tNexy 9v7A== X-Gm-Message-State: APzg51AdoZG618nfDUn72DQyP6Yh6tSONiXJotr7rh0vdZnQ+hY3mgnW o7kOpp297yzqE9rUop9u+gAd/g== X-Google-Smtp-Source: ANB0VdbTHh5S2zVDmqtGqixbDNTMeGLoUByjgWLAQ9Gc2UU0dLvIMXUjaXKvABiaBqGsAcq8gtLTrA== X-Received: by 2002:a62:760a:: with SMTP id r10-v6mr4677067pfc.207.1535526230129; Wed, 29 Aug 2018 00:03:50 -0700 (PDT) Received: from ubt.spreadtrum.com ([117.18.48.102]) by smtp.gmail.com with ESMTPSA id d81-v6sm4317342pfj.122.2018.08.29.00.03.44 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 29 Aug 2018 00:03:49 -0700 (PDT) From: Chunyan Zhang To: Ulf Hansson , Adrian Hunter Cc: linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, Orson Zhai , Baolin Wang , Billows Wu , Jason Wu , Chunyan Zhang , Chunyan Zhang Subject: [PATCH V7 8/9] mmc: sdhci-sprd: Add Spreadtrum's initial host controller Date: Wed, 29 Aug 2018 15:03:03 +0800 Message-Id: <1535526184-32718-9-git-send-email-zhang.chunyan@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1535526184-32718-1-git-send-email-zhang.chunyan@linaro.org> References: <1535526184-32718-1-git-send-email-zhang.chunyan@linaro.org> Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Chunyan Zhang This patch adds the initial support of Secure Digital Host Controller Interface compliant controller found in some latest Spreadtrum chipsets. This patch has been tested on the version of SPRD-R11 controller. R11 is a variant based on SD v4.0 specification. With this driver, R11 mmc can be initialized, can be mounted, read and written. Original-by: Billows Wu Signed-off-by: Chunyan Zhang --- drivers/mmc/host/Kconfig | 13 ++ drivers/mmc/host/Makefile | 1 + drivers/mmc/host/sdhci-sprd.c | 498 ++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 512 insertions(+) create mode 100644 drivers/mmc/host/sdhci-sprd.c diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig index d09feb6..cf984f0 100644 --- a/drivers/mmc/host/Kconfig +++ b/drivers/mmc/host/Kconfig @@ -593,6 +593,19 @@ config MMC_SDRICOH_CS To compile this driver as a module, choose M here: the module will be called sdricoh_cs. +config MMC_SDHCI_SPRD + tristate "Spreadtrum SDIO host Controller" + depends on ARCH_SPRD + depends on MMC_SDHCI_PLTFM + select MMC_SDHCI_IO_ACCESSORS + help + This selects the SDIO Host Controller in Spreadtrum + SoCs, this driver supports R11(IP version: R11P0). + + If you have a controller with this interface, say Y or M here. + + If unsure, say N. + config MMC_TMIO_CORE tristate diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile index a835d1a..5363d06 100644 --- a/drivers/mmc/host/Makefile +++ b/drivers/mmc/host/Makefile @@ -92,6 +92,7 @@ obj-$(CONFIG_MMC_SDHCI_ST) += sdhci-st.o obj-$(CONFIG_MMC_SDHCI_MICROCHIP_PIC32) += sdhci-pic32.o obj-$(CONFIG_MMC_SDHCI_BRCMSTB) += sdhci-brcmstb.o obj-$(CONFIG_MMC_SDHCI_OMAP) += sdhci-omap.o +obj-$(CONFIG_MMC_SDHCI_SPRD) += sdhci-sprd.o obj-$(CONFIG_MMC_CQHCI) += cqhci.o ifeq ($(CONFIG_CB710_DEBUG),y) diff --git a/drivers/mmc/host/sdhci-sprd.c b/drivers/mmc/host/sdhci-sprd.c new file mode 100644 index 0000000..decd8cd --- /dev/null +++ b/drivers/mmc/host/sdhci-sprd.c @@ -0,0 +1,498 @@ +// SPDX-License-Identifier: GPL-2.0 +// +// Secure Digital Host Controller +// +// Copyright (C) 2018 Spreadtrum, Inc. +// Author: Chunyan Zhang + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "sdhci-pltfm.h" + +/* SDHCI_ARGUMENT2 register high 16bit */ +#define SDHCI_SPRD_ARG2_STUFF GENMASK(31, 16) + +#define SDHCI_SPRD_REG_32_DLL_DLY_OFFSET 0x208 +#define SDHCIBSPRD_IT_WR_DLY_INV BIT(5) +#define SDHCI_SPRD_BIT_CMD_DLY_INV BIT(13) +#define SDHCI_SPRD_BIT_POSRD_DLY_INV BIT(21) +#define SDHCI_SPRD_BIT_NEGRD_DLY_INV BIT(29) + +#define SDHCI_SPRD_REG_32_BUSY_POSI 0x250 +#define SDHCI_SPRD_BIT_OUTR_CLK_AUTO_EN BIT(25) +#define SDHCI_SPRD_BIT_INNR_CLK_AUTO_EN BIT(24) + +#define SDHCI_SPRD_REG_DEBOUNCE 0x28C +#define SDHCI_SPRD_BIT_DLL_BAK BIT(0) +#define SDHCI_SPRD_BIT_DLL_VAL BIT(1) + +#define SDHCI_SPRD_INT_SIGNAL_MASK 0x1B7F410B + +/* SDHCI_HOST_CONTROL2 */ +#define SDHCI_SPRD_CTRL_HS200 0x0005 +#define SDHCI_SPRD_CTRL_HS400 0x0006 + +/* + * According to the standard specification, BIT(3) of SDHCI_SOFTWARE_RESET is + * reserved, and only used on Spreadtrum's design, the hardware cannot work + * if this bit is cleared. + * 1 : normal work + * 0 : hardware reset + */ +#define SDHCI_HW_RESET_CARD BIT(3) + +#define SDHCI_SPRD_MAX_CUR 0xFFFFFF +#define SDHCI_SPRD_CLK_MAX_DIV 1023 + +#define SDHCI_SPRD_CLK_DEF_RATE 26000000 + +struct sdhci_sprd_host { + u32 version; + struct clk *clk_sdio; + struct clk *clk_enable; + u32 base_rate; + int flags; /* backup of host attribute */ +}; + +#define TO_SPRD_HOST(host) sdhci_pltfm_priv(sdhci_priv(host)) + +static void sdhci_sprd_init_config(struct sdhci_host *host) +{ + u16 val; + + /* set dll backup mode */ + val = sdhci_readl(host, SDHCI_SPRD_REG_DEBOUNCE); + val |= SDHCI_SPRD_BIT_DLL_BAK | SDHCI_SPRD_BIT_DLL_VAL; + sdhci_writel(host, val, SDHCI_SPRD_REG_DEBOUNCE); +} + +static inline u32 sdhci_sprd_readl(struct sdhci_host *host, int reg) +{ + if (unlikely(reg == SDHCI_MAX_CURRENT)) + return SDHCI_SPRD_MAX_CUR; + + return readl_relaxed(host->ioaddr + reg); +} + +static inline void sdhci_sprd_writel(struct sdhci_host *host, u32 val, int reg) +{ + /* SDHCI_MAX_CURRENT is reserved on Spreadtrum's platform */ + if (unlikely(reg == SDHCI_MAX_CURRENT)) + return; + + if (unlikely(reg == SDHCI_SIGNAL_ENABLE || reg == SDHCI_INT_ENABLE)) + val = val & SDHCI_SPRD_INT_SIGNAL_MASK; + + writel_relaxed(val, host->ioaddr + reg); +} + +static inline void sdhci_sprd_writew(struct sdhci_host *host, u16 val, int reg) +{ + /* SDHCI_BLOCK_COUNT is Read Only on Spreadtrum's platform */ + if (unlikely(reg == SDHCI_BLOCK_COUNT)) + return; + + writew_relaxed(val, host->ioaddr + reg); +} + +static inline void sdhci_sprd_writeb(struct sdhci_host *host, u8 val, int reg) +{ + /* + * Since BIT(3) of SDHCI_SOFTWARE_RESET is reserved according to the + * standard specification, sdhci_reset() write this register directly + * without checking other reserved bits, that will clear BIT(3) which + * is defined as hardware reset on Spreadtrum's platform and clearing + * it by mistake will lead the card not work. So here we need to work + * around it. + */ + if (unlikely(reg == SDHCI_SOFTWARE_RESET)) { + if (readb_relaxed(host->ioaddr + reg) & SDHCI_HW_RESET_CARD) + val |= SDHCI_HW_RESET_CARD; + } + + writeb_relaxed(val, host->ioaddr + reg); +} + +static inline void sdhci_sprd_sd_clk_off(struct sdhci_host *host) +{ + u16 ctrl = sdhci_readw(host, SDHCI_CLOCK_CONTROL); + + ctrl &= ~SDHCI_CLOCK_CARD_EN; + sdhci_writew(host, ctrl, SDHCI_CLOCK_CONTROL); +} + +static inline void +sdhci_sprd_set_dll_invert(struct sdhci_host *host, u32 mask, bool en) +{ + u32 dll_dly_offset; + + dll_dly_offset = sdhci_readl(host, SDHCI_SPRD_REG_32_DLL_DLY_OFFSET); + if (en) + dll_dly_offset |= mask; + else + dll_dly_offset &= ~mask; + sdhci_writel(host, dll_dly_offset, SDHCI_SPRD_REG_32_DLL_DLY_OFFSET); +} + +static inline u32 sdhci_sprd_calc_div(u32 base_clk, u32 clk) +{ + u32 div; + + /* select 2x clock source */ + if (base_clk <= clk * 2) + return 0; + + div = (u32) (base_clk / (clk * 2)); + + if ((base_clk / div) > (clk * 2)) + div++; + + if (div > SDHCI_SPRD_CLK_MAX_DIV) + div = SDHCI_SPRD_CLK_MAX_DIV; + + if (div % 2) + div = (div + 1) / 2; + else + div = div / 2; + + return div; +} + +static inline void _sdhci_sprd_set_clock(struct sdhci_host *host, + unsigned int clk) +{ + struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host); + u32 div, val, mask; + + div = sdhci_sprd_calc_div(sprd_host->base_rate, clk); + + clk |= ((div & 0x300) >> 2) | ((div & 0xFF) << 8); + sdhci_enable_clk(host, clk); + + /* enable auto gate sdhc_enable_auto_gate */ + val = sdhci_readl(host, SDHCI_SPRD_REG_32_BUSY_POSI); + mask = SDHCI_SPRD_BIT_OUTR_CLK_AUTO_EN | + SDHCI_SPRD_BIT_INNR_CLK_AUTO_EN; + if (mask != (val & mask)) { + val |= mask; + sdhci_writel(host, val, SDHCI_SPRD_REG_32_BUSY_POSI); + } +} + +static void sdhci_sprd_set_clock(struct sdhci_host *host, unsigned int clock) +{ + bool en = false; + + if (clock == 0) { + sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL); + } else if (clock != host->clock) { + sdhci_sprd_sd_clk_off(host); + _sdhci_sprd_set_clock(host, clock); + + if (clock <= 400000) + en = true; + sdhci_sprd_set_dll_invert(host, SDHCI_SPRD_BIT_CMD_DLY_INV | + SDHCI_SPRD_BIT_POSRD_DLY_INV, en); + } else { + _sdhci_sprd_set_clock(host, clock); + } +} + +static unsigned int sdhci_sprd_get_max_clock(struct sdhci_host *host) +{ + struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host); + + return clk_round_rate(sprd_host->clk_sdio, ULONG_MAX); +} + +static unsigned int sdhci_sprd_get_min_clock(struct sdhci_host *host) +{ + return 400000; +} + +static void sdhci_sprd_set_uhs_signaling(struct sdhci_host *host, + unsigned int timing) +{ + u16 ctrl_2; + + if (timing == host->timing) + return; + + ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); + /* Select Bus Speed Mode for host */ + ctrl_2 &= ~SDHCI_CTRL_UHS_MASK; + switch (timing) { + case MMC_TIMING_UHS_SDR12: + ctrl_2 |= SDHCI_CTRL_UHS_SDR12; + break; + case MMC_TIMING_MMC_HS: + case MMC_TIMING_SD_HS: + case MMC_TIMING_UHS_SDR25: + ctrl_2 |= SDHCI_CTRL_UHS_SDR25; + break; + case MMC_TIMING_UHS_SDR50: + ctrl_2 |= SDHCI_CTRL_UHS_SDR50; + break; + case MMC_TIMING_UHS_SDR104: + ctrl_2 |= SDHCI_CTRL_UHS_SDR104; + break; + case MMC_TIMING_UHS_DDR50: + case MMC_TIMING_MMC_DDR52: + ctrl_2 |= SDHCI_CTRL_UHS_DDR50; + break; + case MMC_TIMING_MMC_HS200: + ctrl_2 |= SDHCI_SPRD_CTRL_HS200; + break; + case MMC_TIMING_MMC_HS400: + ctrl_2 |= SDHCI_SPRD_CTRL_HS400; + break; + default: + break; + } + + sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); +} + +static void sdhci_sprd_hw_reset(struct sdhci_host *host) +{ + int val; + + /* + * Note: don't use sdhci_writeb() API here since it is redirected to + * sdhci_sprd_writeb() in which we have a workaround for + * SDHCI_SOFTWARE_RESET which would make bit SDHCI_HW_RESET_CARD can + * not be cleared. + */ + val = readb_relaxed(host->ioaddr + SDHCI_SOFTWARE_RESET); + val &= ~SDHCI_HW_RESET_CARD; + writeb_relaxed(val, host->ioaddr + SDHCI_SOFTWARE_RESET); + /* wait for 10 us */ + usleep_range(10, 20); + + val |= SDHCI_HW_RESET_CARD; + writeb_relaxed(val, host->ioaddr + SDHCI_SOFTWARE_RESET); + usleep_range(300, 500); +} + +static struct sdhci_ops sdhci_sprd_ops = { + .read_l = sdhci_sprd_readl, + .write_l = sdhci_sprd_writel, + .write_b = sdhci_sprd_writeb, + .set_clock = sdhci_sprd_set_clock, + .get_max_clock = sdhci_sprd_get_max_clock, + .get_min_clock = sdhci_sprd_get_min_clock, + .set_bus_width = sdhci_set_bus_width, + .reset = sdhci_reset, + .set_uhs_signaling = sdhci_sprd_set_uhs_signaling, + .hw_reset = sdhci_sprd_hw_reset, +}; + +static void sdhci_sprd_request(struct mmc_host *mmc, struct mmc_request *mrq) +{ + struct sdhci_host *host = mmc_priv(mmc); + struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host); + + host->flags = sprd_host->flags; + + /* + * From version 4.10 onward, ARGUMENT2 register is also as 32-bit + * block count register which doesn't support stuff bits of + * CMD23 argument on Spreadtrum's sd host controller. + */ + if (host->version >= SDHCI_SPEC_410 && + mrq->sbc && (mrq->sbc->arg & SDHCI_SPRD_ARG2_STUFF) && + (host->flags & SDHCI_AUTO_CMD23)) + host->flags &= ~SDHCI_AUTO_CMD23; + + sdhci_request(mmc, mrq); +} + +static const struct sdhci_pltfm_data sdhci_sprd_pdata = { + .quirks = SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK, + .quirks2 = SDHCI_QUIRK2_BROKEN_HS200 | + SDHCI_QUIRK2_USE_32BIT_BLK_CNT, + .ops = &sdhci_sprd_ops, +}; + +static int sdhci_sprd_probe(struct platform_device *pdev) +{ + struct sdhci_host *host; + struct sdhci_sprd_host *sprd_host; + struct clk *clk; + int ret = 0; + + host = sdhci_pltfm_init(pdev, &sdhci_sprd_pdata, sizeof(*sprd_host)); + if (IS_ERR(host)) + return PTR_ERR(host); + + host->dma_mask = DMA_BIT_MASK(64); + pdev->dev.dma_mask = &host->dma_mask; + host->mmc_host_ops.request = sdhci_sprd_request; + + host->mmc->caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED | + MMC_CAP_ERASE | MMC_CAP_CMD23; + ret = mmc_of_parse(host->mmc); + if (ret) + goto pltfm_free; + + sprd_host = TO_SPRD_HOST(host); + + clk = devm_clk_get(&pdev->dev, "sdio"); + if (IS_ERR(clk)) { + ret = PTR_ERR(clk); + goto pltfm_free; + } + sprd_host->clk_sdio = clk; + sprd_host->base_rate = clk_get_rate(sprd_host->clk_sdio); + if (!sprd_host->base_rate) + sprd_host->base_rate = SDHCI_SPRD_CLK_DEF_RATE; + + clk = devm_clk_get(&pdev->dev, "enable"); + if (IS_ERR(clk)) { + ret = PTR_ERR(clk); + goto pltfm_free; + } + sprd_host->clk_enable = clk; + + ret = clk_prepare_enable(sprd_host->clk_sdio); + if (ret) + goto pltfm_free; + + clk_prepare_enable(sprd_host->clk_enable); + if (ret) + goto clk_disable; + + sdhci_sprd_init_config(host); + host->version = sdhci_readw(host, SDHCI_HOST_VERSION); + sprd_host->version = ((host->version & SDHCI_VENDOR_VER_MASK) >> + SDHCI_VENDOR_VER_SHIFT); + + pm_runtime_get_noresume(&pdev->dev); + pm_runtime_set_active(&pdev->dev); + pm_runtime_enable(&pdev->dev); + pm_runtime_set_autosuspend_delay(&pdev->dev, 50); + pm_runtime_use_autosuspend(&pdev->dev); + pm_suspend_ignore_children(&pdev->dev, 1); + + sdhci_enable_v4_mode(host); + + ret = sdhci_setup_host(host); + if (ret) + goto pm_runtime_disable; + + sprd_host->flags = host->flags; + + ret = __sdhci_add_host(host); + if (ret) + goto err_cleanup_host; + + pm_runtime_mark_last_busy(&pdev->dev); + pm_runtime_put_autosuspend(&pdev->dev); + + return 0; + +err_cleanup_host: + sdhci_cleanup_host(host); + +pm_runtime_disable: + pm_runtime_disable(&pdev->dev); + pm_runtime_set_suspended(&pdev->dev); + + clk_disable_unprepare(sprd_host->clk_enable); + +clk_disable: + clk_disable_unprepare(sprd_host->clk_sdio); + +pltfm_free: + sdhci_pltfm_free(pdev); + return ret; +} + +static int sdhci_sprd_remove(struct platform_device *pdev) +{ + struct sdhci_host *host = platform_get_drvdata(pdev); + struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host); + struct mmc_host *mmc = host->mmc; + + mmc_remove_host(mmc); + clk_disable_unprepare(sprd_host->clk_sdio); + clk_disable_unprepare(sprd_host->clk_enable); + + mmc_free_host(mmc); + + return 0; +} + +static const struct of_device_id sdhci_sprd_of_match[] = { + { .compatible = "sprd,sdhci-r11", }, + { } +}; +MODULE_DEVICE_TABLE(of, sdhci_sprd_of_match); + +#ifdef CONFIG_PM +static int sdhci_sprd_runtime_suspend(struct device *dev) +{ + struct sdhci_host *host = dev_get_drvdata(dev); + struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host); + + sdhci_runtime_suspend_host(host); + + clk_disable_unprepare(sprd_host->clk_sdio); + clk_disable_unprepare(sprd_host->clk_enable); + + return 0; +} + +static int sdhci_sprd_runtime_resume(struct device *dev) +{ + struct sdhci_host *host = dev_get_drvdata(dev); + struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host); + int ret; + + ret = clk_prepare_enable(sprd_host->clk_enable); + if (ret) + return ret; + + ret = clk_prepare_enable(sprd_host->clk_sdio); + if (ret) { + clk_disable_unprepare(sprd_host->clk_enable); + return ret; + } + + sdhci_runtime_resume_host(host); + + return 0; +} +#endif + +static const struct dev_pm_ops sdhci_sprd_pm_ops = { + SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, + pm_runtime_force_resume) + SET_RUNTIME_PM_OPS(sdhci_sprd_runtime_suspend, + sdhci_sprd_runtime_resume, NULL) +}; + +static struct platform_driver sdhci_sprd_driver = { + .probe = sdhci_sprd_probe, + .remove = sdhci_sprd_remove, + .driver = { + .name = "sdhci_sprd_r11", + .of_match_table = of_match_ptr(sdhci_sprd_of_match), + .pm = &sdhci_sprd_pm_ops, + }, +}; +module_platform_driver(sdhci_sprd_driver); + +MODULE_DESCRIPTION("Spreadtrum sdio host controller r11 driver"); +MODULE_LICENSE("GPL v2"); +MODULE_ALIAS("platform:sdhci-sprd-r11"); From patchwork Wed Aug 29 07:03:04 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chunyan Zhang X-Patchwork-Id: 10579569 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id A0B7A1709 for ; Wed, 29 Aug 2018 07:04:02 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 920862AB64 for ; Wed, 29 Aug 2018 07:04:02 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 860E52AB82; Wed, 29 Aug 2018 07:04:02 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id C926F2AB64 for ; Wed, 29 Aug 2018 07:04:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727406AbeH2K7Y (ORCPT ); Wed, 29 Aug 2018 06:59:24 -0400 Received: from mail-pl1-f193.google.com ([209.85.214.193]:34120 "EHLO mail-pl1-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727590AbeH2K7T (ORCPT ); Wed, 29 Aug 2018 06:59:19 -0400 Received: by mail-pl1-f193.google.com with SMTP id f6-v6so1899547plo.1 for ; Wed, 29 Aug 2018 00:03:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=/RXtHte8bNFCXLz2sWlB+/MjHMcewoMGpsLw3S8KcCM=; b=Jr7z9XrhU3HrcPk/AT/DjDvnFFmTvleGb0H/furxCuBSYyZzL7uKeWtLUYar+F4IIm Wrt2u60UvZF4n/jHJcSF2kmPpVoRuvu+KpbmsZeWZoPnrxTfLHtVhelmeOLNp4to8NNb 2scOigqUNNicqcWV8Z83dAFah/7kyxkvoRmRg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=/RXtHte8bNFCXLz2sWlB+/MjHMcewoMGpsLw3S8KcCM=; b=UXoDNMFZIfXTw5tpQx87YABXzv4NUBILHb6OYMtg6za6DxsldBTrV10ojird2MNwaO xPU6jwzB7sVFtT0CqyhAllua2nLwTb184jnDa/8/jVUNvuXuxoJTpo5gVxh31B4GtzHq +j1VdHtcEBwW17OkNdtmq+OIvanXgdiVbyt/Q6bekC/e4zWdUETNxqjTEvhd+v7XIqS6 Aycxzu9oEyDUiSHPyoYP9TZZagXYMIG4zTSzqKcGB4m0vQ3RDKDDOCghk60j675EOXyS GNJsxr1Nf+C9HLwtRWlpUfW9B8iS8+S4EXxHse8yoOR60jHrNSPzsxvpbXSznO6bJ2qK 6IvA== X-Gm-Message-State: APzg51CIaSEW9vmt39FExUS+//izeZrNelHSZDG3QoLN0Orkf9kAdo6D ZA5Sc/klVtsZR95CsAZt5oDAzA== X-Google-Smtp-Source: ANB0Vdbdr+A5Bk/wBR5YVlkydZGX5vZd5YV2BsgEn4+LYzTHFAcGw8UH+2ipxrOBmL7mQktLBiZ7Wg== X-Received: by 2002:a17:902:7203:: with SMTP id ba3-v6mr4757417plb.179.1535526234254; Wed, 29 Aug 2018 00:03:54 -0700 (PDT) Received: from ubt.spreadtrum.com ([117.18.48.102]) by smtp.gmail.com with ESMTPSA id d81-v6sm4317342pfj.122.2018.08.29.00.03.50 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 29 Aug 2018 00:03:53 -0700 (PDT) From: Chunyan Zhang To: Ulf Hansson , Adrian Hunter Cc: linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, Orson Zhai , Baolin Wang , Billows Wu , Jason Wu , Chunyan Zhang , Chunyan Zhang Subject: [PATCH V7 9/9] dt-bindings: sdhci-sprd: Add bindings for the sdhci-sprd controller Date: Wed, 29 Aug 2018 15:03:04 +0800 Message-Id: <1535526184-32718-10-git-send-email-zhang.chunyan@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1535526184-32718-1-git-send-email-zhang.chunyan@linaro.org> References: <1535526184-32718-1-git-send-email-zhang.chunyan@linaro.org> Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Chunyan Zhang This patch adds the device-tree binding documentation for Spreadtrum SDHCI driver. Signed-off-by: Chunyan Zhang --- .../devicetree/bindings/mmc/sdhci-sprd.txt | 41 ++++++++++++++++++++++ 1 file changed, 41 insertions(+) create mode 100644 Documentation/devicetree/bindings/mmc/sdhci-sprd.txt diff --git a/Documentation/devicetree/bindings/mmc/sdhci-sprd.txt b/Documentation/devicetree/bindings/mmc/sdhci-sprd.txt new file mode 100644 index 0000000..45c9978 --- /dev/null +++ b/Documentation/devicetree/bindings/mmc/sdhci-sprd.txt @@ -0,0 +1,41 @@ +* Spreadtrum SDHCI controller (sdhci-sprd) + +The Secure Digital (SD) Host controller on Spreadtrum SoCs provides an interface +for MMC, SD and SDIO types of cards. + +This file documents differences between the core properties in mmc.txt +and the properties used by the sdhci-sprd driver. + +Required properties: +- compatible: Should contain "sprd,sdhci-r11". +- reg: physical base address of the controller and length. +- interrupts: Interrupts used by the SDHCI controller. +- clocks: Should contain phandle for the clock feeding the SDHCI controller +- clock-names: Should contain the following: + "sdio" - SDIO source clock (required) + "enable" - gate clock which used for enabling/disabling the device (required) + +Optional properties: +- assigned-clocks: the same with "sdio" clock +- assigned-clock-parents: the default parent of "sdio" clock + +Examples: + +sdio0: sdio@20600000 { + compatible = "sprd,sdhci-r11"; + reg = <0 0x20600000 0 0x1000>; + interrupts = ; + + clock-names = "sdio", "enable"; + clocks = <&ap_clk CLK_EMMC_2X>, + <&apahb_gate CLK_EMMC_EB>; + assigned-clocks = <&ap_clk CLK_EMMC_2X>; + assigned-clock-parents = <&rpll CLK_RPLL_390M>; + + bus-width = <8>; + non-removable; + no-sdio; + no-sd; + cap-mmc-hw-reset; + status = "okay"; +};