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[217.76.161.89]) by smtp.gmail.com with ESMTPSA id l190sm10186301wml.16.2019.06.02.01.05.03 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Sun, 02 Jun 2019 01:05:04 -0700 (PDT) From: Paul Walmsley To: linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org Subject: [PATCH v3 1/5] arch: riscv: add support for building DTB files from DT source data Date: Sun, 2 Jun 2019 01:04:56 -0700 Message-Id: <20190602080500.31700-2-paul.walmsley@sifive.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190602080500.31700-1-paul.walmsley@sifive.com> References: <20190602080500.31700-1-paul.walmsley@sifive.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190602_010506_171589_12A2C448 X-CRM114-Status: UNSURE ( 8.85 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Paul Walmsley , Palmer Dabbelt , Albert Ou Sender: "linux-riscv" Errors-To: linux-riscv-bounces+patchwork-linux-riscv=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Similar to ARM64, add support for building DTB files from DT source data for RISC-V boards. This patch starts with the infrastructure needed for SiFive boards. Boards from other vendors would add support here in a similar form. Signed-off-by: Paul Walmsley Signed-off-by: Paul Walmsley Cc: Palmer Dabbelt Cc: Albert Ou --- arch/riscv/boot/dts/Makefile | 2 ++ 1 file changed, 2 insertions(+) create mode 100644 arch/riscv/boot/dts/Makefile diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile new file mode 100644 index 000000000000..dcc3ada78455 --- /dev/null +++ b/arch/riscv/boot/dts/Makefile @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0 +subdir-y += sifive From patchwork Sun Jun 2 08:04:57 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paul Walmsley X-Patchwork-Id: 10971665 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 6CDB11515 for ; Sun, 2 Jun 2019 08:05:19 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 6075D287BD for ; Sun, 2 Jun 2019 08:05:19 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 52969288A0; Sun, 2 Jun 2019 08:05:19 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id E0A3F287BD for ; Sun, 2 Jun 2019 08:05:18 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=nAL5rZ0wP586L/h2IxtRzCi8rOi2H4zwKjNZoSCASM0=; b=Q7G1m75thNlIgx +HpmaP98mqfmPvZeLbPmdw8BQ13itNjvjT1Gie81TcEZNNdMILs/pXJoynHHZ4+87qHgCEag5hgXy 8RxXUi79FbPY1uPEuDMKOxGHc8HpQ505wqWrm8vKEZS6RLpJ4oRd1Qw9e4TuRPQd7XLJII9o+raDI mz5gMfBSrb1U7fMggWYQyNijv2kipwHksPKErD2pwkHGmrkxHmjee4dq7EX0VmfnHKauWHXWey9Sx ST7IBID3Gs9IC25dCYdP6m9im7QC1vbrYMGwHx2TJ6fvMFprRuq4sAABtHa2cwK/DUz/xeW5we0pn s6YwaGX0/cGMYCuaggIg==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1hXLUR-00058r-5D; Sun, 02 Jun 2019 08:05:15 +0000 Received: from mail-wr1-x443.google.com ([2a00:1450:4864:20::443]) by bombadil.infradead.org with esmtps (Exim 4.90_1 #2 (Red Hat Linux)) id 1hXLUJ-0004Mh-VT for linux-riscv@lists.infradead.org; Sun, 02 Jun 2019 08:05:13 +0000 Received: by mail-wr1-x443.google.com with SMTP id p11so4360256wre.7 for ; Sun, 02 Jun 2019 01:05:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=19JHlpBM08NaaoHMsfAWuVL8kWvPtpcvA1ACdpeOftw=; b=VCdfTsHhwzCR9YhzLBuLeD/dMl6Knig2Qrr/Lpl2mzOsirlbvU1qW+irHX7isYh0D9 61JGiq+jQWtwbNdIx//Skzk3QztjQOK3IJdl4hnFMlFxKKXdMqNt880RYGiwa04PbPyf wx3kh+5yoUnvomaQdj8RDE2wqlLmjjLg2jqJqIMjP7QfgvrSR+E2DoxHSo9r9MueQc9E LRO/J843GZGz9QAhACybdilvcL3oSrZGjOp08ChuTXgK/6lR+biQbXan2NoItoUcZiwO yPtH39dTYbSnzcmvYnCzWy9kl5NLCNDrVcvmY0JCVGL4bisWtinY7qslXDqIe6+neqxC 7ofw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=19JHlpBM08NaaoHMsfAWuVL8kWvPtpcvA1ACdpeOftw=; b=nG7aPslNp393/wLdSlUAY+6uJAnbk0wzN9Fm9Dz07jT9CN56UoZazhUatBlSEIz1G/ lFL56O/dj0cc1CooRzFodxpxauchleQoIX0ojXJa6astq8CtTIMruP2lrxyA7O6VWUvm oFbezK9IOxCSqYrcDq2pYeDwLGXHgF15B8l/OdkcGlXp/CzvvLkwIQwfkXmsT5KH5gUn GAG37QACczvPlXCYOvoEBAx6ydbFqkEsURdEvjiDmnbZqQIccxq3RKTTYMO250nr/cs7 jCFrkws7mWX0EEcOM0IP8+TUVoK9Z/DfDZ+ercHWKTE0fqgt8lwmRFhfbgNNS+OMXhvC nqmA== X-Gm-Message-State: APjAAAU6ehYjKU0SwPCb/cVfKw4umpNvyFX/jEF4BtDEIVs1NWY4BXZD qgXCT2ywyBPOS1+leZD5RhKjrRtOKe0= X-Google-Smtp-Source: APXvYqwE8EuKMBl8b7yhXkwj4vtsenrRLz2TFZwMuxn258Kx08W0WGwnpfz+wP7SL38hHnLQqp7PqA== X-Received: by 2002:adf:ea4a:: with SMTP id j10mr360935wrn.114.1559462706355; Sun, 02 Jun 2019 01:05:06 -0700 (PDT) Received: from viisi.fritz.box (217-76-161-89.static.highway.a1.net. [217.76.161.89]) by smtp.gmail.com with ESMTPSA id l190sm10186301wml.16.2019.06.02.01.05.04 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Sun, 02 Jun 2019 01:05:05 -0700 (PDT) From: Paul Walmsley To: linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org Subject: [PATCH v3 2/5] dt-bindings: riscv: sifive: add YAML documentation for the SiFive FU540 Date: Sun, 2 Jun 2019 01:04:57 -0700 Message-Id: <20190602080500.31700-3-paul.walmsley@sifive.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190602080500.31700-1-paul.walmsley@sifive.com> References: <20190602080500.31700-1-paul.walmsley@sifive.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190602_010508_087747_51AEF538 X-CRM114-Status: GOOD ( 11.22 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , devicetree@vger.kernel.org, Paul Walmsley , Albert Ou , Palmer Dabbelt , Rob Herring Sender: "linux-riscv" Errors-To: linux-riscv-bounces+patchwork-linux-riscv=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Add YAML DT binding documentation for the SiFive FU540 SoC. This SoC is documented at: https://static.dev.sifive.com/FU540-C000-v1.0.pdf Passes dt-doc-validate, as of yaml-bindings commit 4c79d42e9216. This second version incorporates review feedback from Rob Herring . Signed-off-by: Paul Walmsley Signed-off-by: Paul Walmsley Cc: Rob Herring Cc: Mark Rutland Cc: Palmer Dabbelt Cc: Albert Ou Cc: devicetree@vger.kernel.org Cc: linux-riscv@lists.infradead.org Cc: linux-kernel@vger.kernel.org Reviewed-by: Rob Herring --- .../devicetree/bindings/riscv/sifive.yaml | 25 +++++++++++++++++++ MAINTAINERS | 9 +++++++ 2 files changed, 34 insertions(+) create mode 100644 Documentation/devicetree/bindings/riscv/sifive.yaml diff --git a/Documentation/devicetree/bindings/riscv/sifive.yaml b/Documentation/devicetree/bindings/riscv/sifive.yaml new file mode 100644 index 000000000000..ce7ca191789e --- /dev/null +++ b/Documentation/devicetree/bindings/riscv/sifive.yaml @@ -0,0 +1,25 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/riscv/sifive.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: SiFive SoC-based boards + +maintainers: + - Paul Walmsley + - Palmer Dabbelt + +description: + SiFive SoC-based boards + +properties: + $nodename: + const: '/' + compatible: + items: + - enum: + - sifive,freedom-unleashed-a00 + - const: sifive,fu540-c000 + - const: sifive,fu540 +... diff --git a/MAINTAINERS b/MAINTAINERS index 5cfbea4ce575..8a64051cf5fc 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -14322,6 +14322,15 @@ S: Supported K: sifive N: sifive +SIFIVE FU540 SYSTEM-ON-CHIP +M: Paul Walmsley +M: Palmer Dabbelt +L: linux-riscv@lists.infradead.org +T: git git://git.kernel.org/pub/scm/linux/kernel/git/pjw/sifive.git +S: Supported +K: fu540 +N: fu540 + SILEAD TOUCHSCREEN DRIVER M: Hans de Goede L: linux-input@vger.kernel.org From patchwork Sun Jun 2 08:04:58 2019 Content-Type: text/plain; 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[217.76.161.89]) by smtp.gmail.com with ESMTPSA id l190sm10186301wml.16.2019.06.02.01.05.06 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Sun, 02 Jun 2019 01:05:07 -0700 (PDT) From: Paul Walmsley To: linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org Subject: [PATCH v3 3/5] dt-bindings: riscv: convert cpu binding to json-schema Date: Sun, 2 Jun 2019 01:04:58 -0700 Message-Id: <20190602080500.31700-4-paul.walmsley@sifive.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190602080500.31700-1-paul.walmsley@sifive.com> References: <20190602080500.31700-1-paul.walmsley@sifive.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190602_010510_178521_C879F070 X-CRM114-Status: GOOD ( 15.24 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , Lorenzo Pieralisi , Paul Walmsley , Rob Herring , devicetree@vger.kernel.org Sender: "linux-riscv" Errors-To: linux-riscv-bounces+patchwork-linux-riscv=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP At Rob's request, we're starting to migrate our DT binding documentation to json-schema YAML format. Start by converting our cpu binding documentation. While doing so, document more properties and nodes. This includes adding binding documentation support for the E51 and U54 CPU cores ("harts") that are present on this SoC. These cores are described in: https://static.dev.sifive.com/FU540-C000-v1.0.pdf This cpus.yaml file is intended to be a starting point and to evolve over time. It passes dt-doc-validate as of the yaml-bindings commit 4c79d42e9216. This patch was originally based on the ARM json-schema binding documentation as added by commit 672951cbd1b7 ("dt-bindings: arm: Convert cpu binding to json-schema"). Signed-off-by: Paul Walmsley Signed-off-by: Paul Walmsley Cc: Rob Herring Cc: Mark Rutland Cc: Lorenzo Pieralisi Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: linux-riscv@lists.infradead.org --- .../devicetree/bindings/riscv/cpus.yaml | 168 ++++++++++++++++++ 1 file changed, 168 insertions(+) create mode 100644 Documentation/devicetree/bindings/riscv/cpus.yaml diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml new file mode 100644 index 000000000000..6e8d55d9d4e1 --- /dev/null +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml @@ -0,0 +1,168 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/riscv/cpus.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: RISC-V bindings for 'cpus' DT nodes + +maintainers: + - Paul Walmsley + - Palmer Dabbelt + +allOf: + - $ref: /schemas/cpus.yaml# + +properties: + $nodename: + const: cpus + description: Container of cpu nodes + + '#address-cells': + const: 1 + description: | + A single unsigned 32-bit integer uniquely identifies each RISC-V + hart in a system. (See the "reg" node under the "cpu" node, + below). + + '#size-cells': + const: 0 + +patternProperties: + '^cpu@[0-9a-f]+$': + properties: + compatible: + type: array + items: + - enum: + - sifive,rocket0 + - sifive,e5 + - sifive,e51 + - sifive,u54-mc + - sifive,u54 + - sifive,u5 + - const: riscv + description: + Identifies that the hart uses the RISC-V instruction set + and identifies the type of the hart. + + mmu-type: + allOf: + - $ref: "/schemas/types.yaml#/definitions/string" + - enum: + - riscv,sv32 + - riscv,sv39 + - riscv,sv48 + description: + Identifies the MMU address translation mode used on this + hart. These values originate from the RISC-V Privileged + Specification document, available from + https://riscv.org/specifications/ + + riscv,isa: + allOf: + - $ref: "/schemas/types.yaml#/definitions/string" + - enum: + - rv64imac + - rv64imafdc + description: + Identifies the specific RISC-V instruction set architecture + supported by the hart. These are documented in the RISC-V + User-Level ISA document, available from + https://riscv.org/specifications/ + + timebase-frequency: + type: integer + minimum: 1 + description: + Specifies the clock frequency of the system timer in Hz. + This value is common to all harts on a single system image. + + interrupt-controller: + type: object + description: Describes the CPU's local interrupt controller + + properties: + '#interrupt-cells': + const: 1 + + compatible: + const: riscv,cpu-intc + + interrupt-controller: true + + required: + - '#interrupt-cells' + - compatible + - interrupt-controller + + required: + - riscv,isa + - timebase-frequency + - interrupt-controller + +examples: + - | + // Example 1: SiFive Freedom U540G Development Kit + cpus { + #address-cells = <1>; + #size-cells = <0>; + timebase-frequency = <1000000>; + cpu@0 { + clock-frequency = <0>; + compatible = "sifive,rocket0", "riscv"; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <128>; + i-cache-size = <16384>; + reg = <0>; + riscv,isa = "rv64imac"; + cpu_intc0: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu@1 { + clock-frequency = <0>; + compatible = "sifive,rocket0", "riscv"; + d-cache-block-size = <64>; + d-cache-sets = <64>; + d-cache-size = <32768>; + d-tlb-sets = <1>; + d-tlb-size = <32>; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <64>; + i-cache-size = <32768>; + i-tlb-sets = <1>; + i-tlb-size = <32>; + mmu-type = "riscv,sv39"; + reg = <1>; + riscv,isa = "rv64imafdc"; + tlb-split; + cpu_intc1: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + }; + + - | + // Example 2: Spike ISA Simulator with 1 Hart + cpus { + cpu@0 { + device_type = "cpu"; + reg = <0>; + compatible = "riscv"; + riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv48"; + interrupt-controller { + #interrupt-cells = <1>; + interrupt-controller; + compatible = "riscv,cpu-intc"; + }; + }; + }; +... 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[217.76.161.89]) by smtp.gmail.com with ESMTPSA id l190sm10186301wml.16.2019.06.02.01.05.08 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Sun, 02 Jun 2019 01:05:09 -0700 (PDT) From: Paul Walmsley To: linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org Subject: [PATCH v3 4/5] riscv: dts: add initial support for the SiFive FU540-C000 SoC Date: Sun, 2 Jun 2019 01:04:59 -0700 Message-Id: <20190602080500.31700-5-paul.walmsley@sifive.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190602080500.31700-1-paul.walmsley@sifive.com> References: <20190602080500.31700-1-paul.walmsley@sifive.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190602_010511_816699_34582E2A X-CRM114-Status: GOOD ( 13.76 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , devicetree@vger.kernel.org, Paul Walmsley , Albert Ou , Palmer Dabbelt , Rob Herring , ShihPo Hung Sender: "linux-riscv" Errors-To: linux-riscv-bounces+patchwork-linux-riscv=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Add initial support for the SiFive FU540-C000 SoC. This is a 28nm SoC based around the SiFive U54-MC core complex and a TileLink interconnect. This file is expected to grow as more device drivers are added to the kernel. This patch includes a fix to the QSPI memory map due to a documentation bug, found by ShihPo Hung , adds entries for the I2C controller, and merges all DT changes that formerly were made dynamically by the riscv-pk BBL proxy kernel. Signed-off-by: Paul Walmsley Signed-off-by: Paul Walmsley Cc: Rob Herring Cc: Mark Rutland Cc: Palmer Dabbelt Cc: Albert Ou Cc: ShihPo Hung Cc: devicetree@vger.kernel.org Cc: linux-riscv@lists.infradead.org Cc: linux-kernel@vger.kernel.org Tested-by: Loys Ollivier --- arch/riscv/boot/dts/sifive/fu540-c000.dtsi | 215 +++++++++++++++++++++ 1 file changed, 215 insertions(+) create mode 100644 arch/riscv/boot/dts/sifive/fu540-c000.dtsi diff --git a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi new file mode 100644 index 000000000000..3c06ee4b2b29 --- /dev/null +++ b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi @@ -0,0 +1,215 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* Copyright (c) 2018-2019 SiFive, Inc */ + +/dts-v1/; + +#include + +/ { + #address-cells = <2>; + #size-cells = <2>; + compatible = "sifive,fu540-c000", "sifive,fu540"; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + }; + + chosen { + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + timebase-frequency = <1000000>; + cpu0: cpu@0 { + compatible = "sifive,e51", "sifive,rocket0", "riscv"; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <128>; + i-cache-size = <16384>; + reg = <0>; + riscv,isa = "rv64imac"; + status = "disabled"; + cpu0_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu1: cpu@1 { + compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; + d-cache-block-size = <64>; + d-cache-sets = <64>; + d-cache-size = <32768>; + d-tlb-sets = <1>; + d-tlb-size = <32>; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <64>; + i-cache-size = <32768>; + i-tlb-sets = <1>; + i-tlb-size = <32>; + mmu-type = "riscv,sv39"; + reg = <1>; + riscv,isa = "rv64imafdc"; + tlb-split; + cpu1_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu2: cpu@2 { + clock-frequency = <0>; + compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; + d-cache-block-size = <64>; + d-cache-sets = <64>; + d-cache-size = <32768>; + d-tlb-sets = <1>; + d-tlb-size = <32>; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <64>; + i-cache-size = <32768>; + i-tlb-sets = <1>; + i-tlb-size = <32>; + mmu-type = "riscv,sv39"; + reg = <2>; + riscv,isa = "rv64imafdc"; + tlb-split; + cpu2_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu3: cpu@3 { + clock-frequency = <0>; + compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; + d-cache-block-size = <64>; + d-cache-sets = <64>; + d-cache-size = <32768>; + d-tlb-sets = <1>; + d-tlb-size = <32>; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <64>; + i-cache-size = <32768>; + i-tlb-sets = <1>; + i-tlb-size = <32>; + mmu-type = "riscv,sv39"; + reg = <3>; + riscv,isa = "rv64imafdc"; + tlb-split; + cpu3_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu4: cpu@4 { + clock-frequency = <0>; + compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; + d-cache-block-size = <64>; + d-cache-sets = <64>; + d-cache-size = <32768>; + d-tlb-sets = <1>; + d-tlb-size = <32>; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <64>; + i-cache-size = <32768>; + i-tlb-sets = <1>; + i-tlb-size = <32>; + mmu-type = "riscv,sv39"; + reg = <4>; + riscv,isa = "rv64imafdc"; + tlb-split; + cpu4_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + }; + soc { + #address-cells = <2>; + #size-cells = <2>; + compatible = "sifive,fu540-c000", "sifive,fu540", "simple-bus"; + ranges; + plic0: interrupt-controller@c000000 { + #interrupt-cells = <1>; + compatible = "sifive,plic-1.0.0"; + reg = <0x0 0xc000000 0x0 0x4000000>; + riscv,ndev = <53>; + interrupt-controller; + interrupts-extended = < + &cpu0_intc 0xffffffff + &cpu1_intc 0xffffffff &cpu1_intc 9 + &cpu2_intc 0xffffffff &cpu2_intc 9 + &cpu3_intc 0xffffffff &cpu3_intc 9 + &cpu4_intc 0xffffffff &cpu4_intc 9>; + }; + prci: clock-controller@10000000 { + compatible = "sifive,fu540-c000-prci"; + reg = <0x0 0x10000000 0x0 0x1000>; + clocks = <&hfclk>, <&rtcclk>; + #clock-cells = <1>; + }; + uart0: serial@10010000 { + compatible = "sifive,fu540-c000-uart", "sifive,uart0"; + reg = <0x0 0x10010000 0x0 0x1000>; + interrupt-parent = <&plic0>; + interrupts = <4>; + clocks = <&prci PRCI_CLK_TLCLK>; + }; + uart1: serial@10011000 { + compatible = "sifive,fu540-c000-uart", "sifive,uart0"; + reg = <0x0 0x10011000 0x0 0x1000>; + interrupt-parent = <&plic0>; + interrupts = <5>; + clocks = <&prci PRCI_CLK_TLCLK>; + }; + i2c0: i2c@10030000 { + compatible = "sifive,fu540-c000-i2c", "sifive,i2c0"; + reg = <0x0 0x10030000 0x0 0x1000>; + interrupt-parent = <&plic0>; + interrupts = <50>; + clocks = <&prci PRCI_CLK_TLCLK>; + reg-shift = <2>; + reg-io-width = <1>; + #address-cells = <1>; + #size-cells = <0>; + }; + qspi0: spi@10040000 { + compatible = "sifive,fu540-c000-spi", "sifive,spi0"; + reg = <0x0 0x10040000 0x0 0x1000 + 0x0 0x20000000 0x0 0x10000000>; + interrupt-parent = <&plic0>; + interrupts = <51>; + clocks = <&prci PRCI_CLK_TLCLK>; + #address-cells = <1>; + #size-cells = <0>; + }; + qspi1: spi@10041000 { + compatible = "sifive,fu540-c000-spi", "sifive,spi0"; + reg = <0x0 0x10041000 0x0 0x1000 + 0x0 0x30000000 0x0 0x10000000>; + interrupt-parent = <&plic0>; + interrupts = <52>; + clocks = <&prci PRCI_CLK_TLCLK>; + #address-cells = <1>; + #size-cells = <0>; + }; + qspi2: spi@10050000 { + compatible = "sifive,fu540-c000-spi", "sifive,spi0"; + reg = <0x0 0x10050000 0x0 0x1000>; + interrupt-parent = <&plic0>; + interrupts = <6>; + clocks = <&prci PRCI_CLK_TLCLK>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; +}; From patchwork Sun Jun 2 08:05:00 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paul Walmsley X-Patchwork-Id: 10971669 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 6B03D1398 for ; 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[217.76.161.89]) by smtp.gmail.com with ESMTPSA id l190sm10186301wml.16.2019.06.02.01.05.09 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Sun, 02 Jun 2019 01:05:11 -0700 (PDT) From: Paul Walmsley To: linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org Subject: [PATCH v3 5/5] riscv: dts: add initial board data for the SiFive HiFive Unleashed Date: Sun, 2 Jun 2019 01:05:00 -0700 Message-Id: <20190602080500.31700-6-paul.walmsley@sifive.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190602080500.31700-1-paul.walmsley@sifive.com> References: <20190602080500.31700-1-paul.walmsley@sifive.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190602_010513_061409_53095801 X-CRM114-Status: GOOD ( 12.53 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , devicetree@vger.kernel.org, Paul Walmsley , Albert Ou , Palmer Dabbelt , Rob Herring Sender: "linux-riscv" Errors-To: linux-riscv-bounces+patchwork-linux-riscv=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Add initial board data for the SiFive HiFive Unleashed A00. Currently the data populated in this DT file describes the board DRAM configuration and the external clock sources that supply the PRCI. This third version incorporates changes based on more comments from Rob Herring . Signed-off-by: Paul Walmsley Signed-off-by: Paul Walmsley Cc: Rob Herring Cc: Mark Rutland Cc: Palmer Dabbelt Cc: Albert Ou Cc: devicetree@vger.kernel.org Cc: linux-riscv@lists.infradead.org Cc: linux-kernel@vger.kernel.org Tested-by: Loys Ollivier --- arch/riscv/boot/dts/sifive/Makefile | 2 + .../boot/dts/sifive/hifive-unleashed-a00.dts | 67 +++++++++++++++++++ 2 files changed, 69 insertions(+) create mode 100644 arch/riscv/boot/dts/sifive/Makefile create mode 100644 arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts diff --git a/arch/riscv/boot/dts/sifive/Makefile b/arch/riscv/boot/dts/sifive/Makefile new file mode 100644 index 000000000000..baaeef9efdcb --- /dev/null +++ b/arch/riscv/boot/dts/sifive/Makefile @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-y += hifive-unleashed-a00.dtb diff --git a/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts b/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts new file mode 100644 index 000000000000..1de4ea1577d5 --- /dev/null +++ b/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts @@ -0,0 +1,67 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* Copyright (c) 2018-2019 SiFive, Inc */ + +/dts-v1/; + +#include "fu540-c000.dtsi" + +/* Clock frequency (in Hz) of the PCB crystal for rtcclk */ +#define RTCCLK_FREQ 1000000 + +/ { + #address-cells = <2>; + #size-cells = <2>; + model = "SiFive HiFive Unleashed A00"; + compatible = "sifive,hifive-unleashed-a00", "sifive,fu540-c000"; + + chosen { + }; + + cpus { + timebase-frequency = ; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x0 0x80000000 0x2 0x00000000>; + }; + + soc { + }; + + hfclk: hfclk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <33333333>; + clock-output-names = "hfclk"; + }; + + rtcclk: rtcclk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = ; + clock-output-names = "rtcclk"; + }; +}; + +&qspi0 { + flash@0 { + compatible = "issi,is25wp256", "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <50000000>; + m25p,fast-read; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + }; +}; + +&qspi2 { + status = "okay"; + mmc@0 { + compatible = "mmc-spi-slot"; + reg = <0>; + spi-max-frequency = <20000000>; + voltage-ranges = <3300 3300>; + disable-wp; + }; +};