From patchwork Mon Jun 3 10:36:01 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Yoshihiro Shimoda X-Patchwork-Id: 10972723 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 54EC776 for ; Mon, 3 Jun 2019 10:41:02 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 4623128691 for ; Mon, 3 Jun 2019 10:41:02 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 39B70288AC; Mon, 3 Jun 2019 10:41:02 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 62B9028691 for ; Mon, 3 Jun 2019 10:41:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726710AbfFCKlA (ORCPT ); Mon, 3 Jun 2019 06:41:00 -0400 Received: from relmlor1.renesas.com ([210.160.252.171]:7357 "EHLO relmlie5.idc.renesas.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1726520AbfFCKlA (ORCPT ); Mon, 3 Jun 2019 06:41:00 -0400 X-IronPort-AV: E=Sophos;i="5.60,546,1549897200"; d="scan'208";a="17684991" Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie5.idc.renesas.com with ESMTP; 03 Jun 2019 19:40:57 +0900 Received: from localhost.localdomain (unknown [10.166.17.210]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 6A8E7424C191; Mon, 3 Jun 2019 19:40:57 +0900 (JST) From: Yoshihiro Shimoda To: wim@linux-watchdog.org, linux@roeck-us.net Cc: linux-watchdog@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Yoshihiro Shimoda Subject: [PATCH v2] watchdog: renesas_wdt: Add a few cycles delay Date: Mon, 3 Jun 2019 19:36:01 +0900 Message-Id: <1559558161-31244-1-git-send-email-yoshihiro.shimoda.uh@renesas.com> X-Mailer: git-send-email 2.7.4 Sender: linux-watchdog-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-watchdog@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP According to the hardware manual of R-Car Gen2 and Gen3, software should wait a few RLCK cycles as following: - Delay 2 cycles before setting watchdog counter. - Delay 3 cycles before disabling module clock. So, this patch adds such delays. Signed-off-by: Yoshihiro Shimoda Reviewed-by: Geert Uytterhoeven Reviewed-by: Wolfram Sang Reviewed-by: Niklas Söderlund --- Changes from v1 (https://patchwork.kernel.org/patch/10972641/): - Change formula to improve accuracy. - Add Geert-san's Reviewed-by. drivers/watchdog/renesas_wdt.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/drivers/watchdog/renesas_wdt.c b/drivers/watchdog/renesas_wdt.c index 565dbc1..525a1fe 100644 --- a/drivers/watchdog/renesas_wdt.c +++ b/drivers/watchdog/renesas_wdt.c @@ -7,6 +7,7 @@ */ #include #include +#include #include #include #include @@ -70,6 +71,15 @@ static int rwdt_init_timeout(struct watchdog_device *wdev) return 0; } +static void rwdt_wait(struct rwdt_priv *priv, unsigned int cycles) +{ + unsigned long delays; + + delays = DIV_ROUND_UP(cycles * 1000000, priv->clk_rate); + + usleep_range(delays, 2 * delays); +} + static int rwdt_start(struct watchdog_device *wdev) { struct rwdt_priv *priv = watchdog_get_drvdata(wdev); @@ -80,6 +90,8 @@ static int rwdt_start(struct watchdog_device *wdev) /* Stop the timer before we modify any register */ val = readb_relaxed(priv->base + RWTCSRA) & ~RWTCSRA_TME; rwdt_write(priv, val, RWTCSRA); + /* Delay 2 cycles before setting watchdog counter */ + rwdt_wait(priv, 2); rwdt_init_timeout(wdev); rwdt_write(priv, priv->cks, RWTCSRA); @@ -98,6 +110,8 @@ static int rwdt_stop(struct watchdog_device *wdev) struct rwdt_priv *priv = watchdog_get_drvdata(wdev); rwdt_write(priv, priv->cks, RWTCSRA); + /* Delay 3 cycles before disabling module clock */ + rwdt_wait(priv, 3); pm_runtime_put(wdev->parent); return 0;