From patchwork Wed Jun 5 21:57:33 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aditya Swarup X-Patchwork-Id: 10977945 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 110546C5 for ; Wed, 5 Jun 2019 22:02:06 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 0361C27F8E for ; Wed, 5 Jun 2019 22:02:06 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id EC12428A6F; Wed, 5 Jun 2019 22:02:05 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 99FC227F8E for ; Wed, 5 Jun 2019 22:02:05 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 02656892C9; Wed, 5 Jun 2019 22:02:05 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by gabe.freedesktop.org (Postfix) with ESMTPS id 3FBC2892C9 for ; Wed, 5 Jun 2019 22:02:04 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga107.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 05 Jun 2019 15:02:03 -0700 X-ExtLoop1: 1 Received: from aswarup-desk.jf.intel.com ([10.54.75.32]) by orsmga002.jf.intel.com with ESMTP; 05 Jun 2019 15:02:03 -0700 From: Aditya Swarup To: intel-gfx@lists.freedesktop.org Date: Wed, 5 Jun 2019 14:57:33 -0700 Message-Id: <20190605215733.10227-1-aditya.swarup@intel.com> X-Mailer: git-send-email 2.17.1 Subject: [Intel-gfx] [PATCH] drm/i915/icl: Enable SSC for ICL using panel_use_ssc X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jani Nikula , Lucas De Marchi MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP To enable SSC for DPLL, we need to set the bit DPLL_CFGCR0_SSC_ENABLE_ICL while configuring cfgcr0 register. This bit should be set only when we are enabling SSC using kernel mod parameter panel_use_ssc. Also, moving intel_panel_use_ssc() declaration to intel_drv.h. Signed-off-by: Aditya Swarup Cc: Lucas De Marchi Cc: Clinton Taylor Cc: Jani Nikula --- drivers/gpu/drm/i915/intel_display.c | 8 -------- drivers/gpu/drm/i915/intel_dpll_mgr.c | 4 ++++ drivers/gpu/drm/i915/intel_drv.h | 8 ++++++++ 3 files changed, 12 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 012ad08f38c3..34c82a17ab1b 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -7377,14 +7377,6 @@ intel_link_compute_m_n(u16 bits_per_pixel, int nlanes, constant_n); } -static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv) -{ - if (i915_modparams.panel_use_ssc >= 0) - return i915_modparams.panel_use_ssc != 0; - return dev_priv->vbt.lvds_use_ssc - && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE); -} - static u32 pnv_dpll_compute_fp(struct dpll *dpll) { return (1 << dpll->n) << 16 | dpll->m2; diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c index 897d93537414..6c460fb81d6a 100644 --- a/drivers/gpu/drm/i915/intel_dpll_mgr.c +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c @@ -2527,6 +2527,10 @@ static bool icl_calc_dpll_state(struct intel_crtc_state *crtc_state, cfgcr0 = DPLL_CFGCR0_DCO_FRACTION(pll_params.dco_fraction) | pll_params.dco_integer; + if (intel_panel_use_ssc(dev_priv)) { + cfgcr0 |= DPLL_CFGCR0_SSC_ENABLE_ICL; + } + cfgcr1 = DPLL_CFGCR1_QDIV_RATIO(pll_params.qdiv_ratio) | DPLL_CFGCR1_QDIV_MODE(pll_params.qdiv_mode) | DPLL_CFGCR1_KDIV(pll_params.kdiv) | diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index 270f5bb43d9b..e9af27e841b3 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -1497,6 +1497,14 @@ intel_wait_for_vblank(struct drm_i915_private *dev_priv, enum pipe pipe) { drm_wait_one_vblank(&dev_priv->drm, pipe); } +static inline bool +intel_panel_use_ssc(struct drm_i915_private *dev_priv) +{ + if (i915_modparams.panel_use_ssc >= 0) + return i915_modparams.panel_use_ssc != 0; + return dev_priv->vbt.lvds_use_ssc + && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE); +} static inline void intel_wait_for_vblank_if_active(struct drm_i915_private *dev_priv, int pipe) {