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Thu, 6 Jun 2019 03:45:56 -0700 Received: from saturn.ad.analog.com (10.48.65.129) by NWD2HUBCAS7.ad.analog.com (10.64.69.107) with Microsoft SMTP Server id 14.3.408.0; Thu, 6 Jun 2019 06:45:56 -0400 From: Alexandru Ardelean To: CC: Alexandru Ardelean Subject: [PATCH 1/4] dmaengine: virt-dma: store result on dma descriptor Date: Thu, 6 Jun 2019 13:45:47 +0300 Message-ID: <20190606104550.32336-1-alexandru.ardelean@analog.com> X-Mailer: git-send-email 2.20.1 MIME-Version: 1.0 X-ADIRoutedOnPrem: True X-EOPAttributedMessage: 0 X-MS-Office365-Filtering-HT: Tenant X-Forefront-Antispam-Report: CIP:137.71.25.57;IPV:NLI;CTRY:US;EFV:NLI;SFV:NSPM;SFS:(10009020)(376002)(346002)(396003)(39860400002)(136003)(2980300002)(199004)(189003)(106002)(8936002)(316002)(8676002)(36756003)(77096007)(26005)(1076003)(246002)(50466002)(50226002)(126002)(14444005)(356004)(6666004)(48376002)(47776003)(6916009)(7696005)(51416003)(2906002)(336012)(7636002)(5660300002)(2870700001)(4326008)(426003)(186003)(486006)(2351001)(2616005)(476003)(44832011)(70586007)(70206006)(305945005)(478600001)(86362001)(107886003);DIR:OUT;SFP:1101;SCL:1;SRVR:SN2PR03MB2270;H:nwd2mta2.analog.com;FPR:;SPF:Pass;LANG:en;PTR:nwd2mail11.analog.com;A:1;MX:1; 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Signed-off-by: Alexandru Ardelean --- drivers/dma/virt-dma.c | 4 ++-- drivers/dma/virt-dma.h | 4 ++++ 2 files changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/dma/virt-dma.c b/drivers/dma/virt-dma.c index 88ad8ed2a8d6..bf560a20c8a8 100644 --- a/drivers/dma/virt-dma.c +++ b/drivers/dma/virt-dma.c @@ -101,7 +101,7 @@ static void vchan_complete(unsigned long arg) } spin_unlock_irq(&vc->lock); - dmaengine_desc_callback_invoke(&cb, NULL); + dmaengine_desc_callback_invoke(&cb, &vd->tx_result); list_for_each_entry_safe(vd, _vd, &head, node) { dmaengine_desc_get_callback(&vd->tx, &cb); @@ -109,7 +109,7 @@ static void vchan_complete(unsigned long arg) list_del(&vd->node); vchan_vdesc_fini(vd); - dmaengine_desc_callback_invoke(&cb, NULL); + dmaengine_desc_callback_invoke(&cb, &vd->tx_result); } } diff --git a/drivers/dma/virt-dma.h b/drivers/dma/virt-dma.h index b09b75ab0751..eb767c583b7e 100644 --- a/drivers/dma/virt-dma.h +++ b/drivers/dma/virt-dma.h @@ -17,6 +17,7 @@ struct virt_dma_desc { struct dma_async_tx_descriptor tx; + struct dmaengine_result tx_result; /* protected by vc.lock */ struct list_head node; }; @@ -65,6 +66,9 @@ static inline struct dma_async_tx_descriptor *vchan_tx_prep(struct virt_dma_chan vd->tx.tx_submit = vchan_tx_submit; vd->tx.desc_free = vchan_tx_desc_free; + vd->tx_result.result = DMA_TRANS_NOERROR; + vd->tx_result.residue = 0; + spin_lock_irqsave(&vc->lock, flags); list_add_tail(&vd->node, &vc->desc_allocated); spin_unlock_irqrestore(&vc->lock, flags); From patchwork Thu Jun 6 10:45:48 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexandru Ardelean X-Patchwork-Id: 10979213 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 19EDE2D47 for ; Thu, 6 Jun 2019 10:46:04 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 08941201A4 for ; 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vger.kernel.org; dkim=none (message not signed) header.d=none;vger.kernel.org; dmarc=bestguesspass action=none header.from=analog.com; Received-SPF: Pass (protection.outlook.com: domain of analog.com designates 137.71.25.57 as permitted sender) receiver=protection.outlook.com; client-ip=137.71.25.57; helo=nwd2mta2.analog.com; Received: from nwd2mta2.analog.com (137.71.25.57) by SN1NAM02FT012.mail.protection.outlook.com (10.152.72.95) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.20.1965.12 via Frontend Transport; Thu, 6 Jun 2019 10:45:57 +0000 Received: from NWD2HUBCAS7.ad.analog.com (nwd2hubcas7.ad.analog.com [10.64.69.107]) by nwd2mta2.analog.com (8.13.8/8.13.8) with ESMTP id x56Ajvb3013752 (version=TLSv1/SSLv3 cipher=AES256-SHA bits=256 verify=OK) for ; Thu, 6 Jun 2019 03:45:57 -0700 Received: from saturn.ad.analog.com (10.48.65.129) by NWD2HUBCAS7.ad.analog.com (10.64.69.107) with Microsoft SMTP Server id 14.3.408.0; Thu, 6 Jun 2019 06:45:57 -0400 From: Alexandru Ardelean To: CC: Alexandru Ardelean Subject: [PATCH 2/4] dmaengine: axi-dmac: populate residue info for completed xfers Date: Thu, 6 Jun 2019 13:45:48 +0300 Message-ID: <20190606104550.32336-2-alexandru.ardelean@analog.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190606104550.32336-1-alexandru.ardelean@analog.com> References: <20190606104550.32336-1-alexandru.ardelean@analog.com> MIME-Version: 1.0 X-ADIRoutedOnPrem: True X-EOPAttributedMessage: 0 X-MS-Office365-Filtering-HT: Tenant X-Forefront-Antispam-Report: CIP:137.71.25.57;IPV:NLI;CTRY:US;EFV:NLI;SFV:NSPM;SFS:(10009020)(396003)(136003)(346002)(39860400002)(376002)(2980300002)(199004)(189003)(316002)(50466002)(2870700001)(426003)(106002)(126002)(246002)(51416003)(48376002)(8676002)(6916009)(1076003)(86362001)(5660300002)(36756003)(77096007)(6666004)(7636002)(14444005)(76176011)(70586007)(11346002)(44832011)(70206006)(186003)(2616005)(476003)(446003)(486006)(305945005)(7696005)(8936002)(50226002)(478600001)(107886003)(2906002)(4326008)(356004)(47776003)(2351001)(26005)(336012);DIR:OUT;SFP:1101;SCL:1;SRVR:BL2PR03MB548;H:nwd2mta2.analog.com;FPR:;SPF:Pass;LANG:en;PTR:nwd2mail11.analog.com;A:1;MX:1; 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This change implements computing DMA residue information for transfers, based on that reported information. The way this is done, is to dequeue the partial transfers from the FIFO of partial transfers, store the partial length to the correct segment & descriptor, and compute the residue before submitting the DMA cookie to the DMA framework. Signed-off-by: Alexandru Ardelean --- drivers/dma/dma-axi-dmac.c | 99 +++++++++++++++++++++++++++++++++++++- 1 file changed, 98 insertions(+), 1 deletion(-) diff --git a/drivers/dma/dma-axi-dmac.c b/drivers/dma/dma-axi-dmac.c index d5e29bbc3d43..e0702697e2b3 100644 --- a/drivers/dma/dma-axi-dmac.c +++ b/drivers/dma/dma-axi-dmac.c @@ -64,6 +64,8 @@ #define AXI_DMAC_REG_STATUS 0x430 #define AXI_DMAC_REG_CURRENT_SRC_ADDR 0x434 #define AXI_DMAC_REG_CURRENT_DEST_ADDR 0x438 +#define AXI_DMAC_REG_PARTIAL_XFER_LEN 0x44c +#define AXI_DMAC_REG_PARTIAL_XFER_ID 0x450 #define AXI_DMAC_CTRL_ENABLE BIT(0) #define AXI_DMAC_CTRL_PAUSE BIT(1) @@ -73,6 +75,9 @@ #define AXI_DMAC_FLAG_CYCLIC BIT(0) #define AXI_DMAC_FLAG_LAST BIT(1) +#define AXI_DMAC_FLAG_PARTIAL_REPORT BIT(2) + +#define AXI_DMAC_FLAG_PARTIAL_XFER_DONE BIT(31) /* The maximum ID allocated by the hardware is 31 */ #define AXI_DMAC_SG_UNUSED 32U @@ -85,6 +90,7 @@ struct axi_dmac_sg { unsigned int dest_stride; unsigned int src_stride; unsigned int id; + unsigned int partial_len; bool schedule_when_free; }; @@ -114,6 +120,7 @@ struct axi_dmac_chan { unsigned int address_align_mask; unsigned int length_align_mask; + bool hw_partial_xfer; bool hw_cyclic; bool hw_2d; }; @@ -245,6 +252,9 @@ static void axi_dmac_start_transfer(struct axi_dmac_chan *chan) desc->num_sgs == 1) flags |= AXI_DMAC_FLAG_CYCLIC; + if (chan->hw_partial_xfer) + flags |= AXI_DMAC_FLAG_PARTIAL_REPORT; + axi_dmac_write(dmac, AXI_DMAC_REG_X_LENGTH, sg->x_len - 1); axi_dmac_write(dmac, AXI_DMAC_REG_Y_LENGTH, sg->y_len - 1); axi_dmac_write(dmac, AXI_DMAC_REG_FLAGS, flags); @@ -257,6 +267,82 @@ static struct axi_dmac_desc *axi_dmac_active_desc(struct axi_dmac_chan *chan) struct axi_dmac_desc, vdesc.node); } +static inline unsigned int axi_dmac_total_sg_bytes(struct axi_dmac_chan *chan, + struct axi_dmac_sg *sg) +{ + if (chan->hw_2d) + return sg->x_len * sg->y_len; + else + return sg->x_len; +} + +static void axi_dmac_dequeue_partial_xfers(struct axi_dmac_chan *chan) +{ + struct axi_dmac *dmac = chan_to_axi_dmac(chan); + struct axi_dmac_desc *desc; + struct axi_dmac_sg *sg; + u32 xfer_done, len, id, i; + bool found_sg; + + do { + len = axi_dmac_read(dmac, AXI_DMAC_REG_PARTIAL_XFER_LEN); + id = axi_dmac_read(dmac, AXI_DMAC_REG_PARTIAL_XFER_ID); + + found_sg = false; + list_for_each_entry(desc, &chan->active_descs, vdesc.node) { + for (i = 0; i < desc->num_sgs; i++) { + sg = &desc->sg[i]; + if (sg->id == AXI_DMAC_SG_UNUSED) + continue; + if (sg->id == id) { + sg->partial_len = len; + found_sg = true; + break; + } + } + if (found_sg) + break; + } + + if (found_sg) { + dev_dbg(dmac->dma_dev.dev, + "Found partial segment id=%u, len=%u\n", + id, len); + } else { + dev_warn(dmac->dma_dev.dev, + "Not found partial segment id=%u, len=%u\n", + id, len); + } + + /* Check if we have any more partial transfers */ + xfer_done = axi_dmac_read(dmac, AXI_DMAC_REG_TRANSFER_DONE); + xfer_done = !(xfer_done & AXI_DMAC_FLAG_PARTIAL_XFER_DONE); + + } while (!xfer_done); +} + +static void axi_dmac_compute_residue(struct axi_dmac_chan *chan, + struct axi_dmac_desc *active) +{ + struct dmaengine_result *rslt = &active->vdesc.tx_result; + unsigned int start = active->num_completed - 1; + struct axi_dmac_sg *sg; + unsigned int i, total; + + rslt->result = DMA_TRANS_NOERROR; + rslt->residue = 0; + + /* + * We get here if the last completed segment is partial, which + * means we can compute the residue from that segment onwards + */ + for (i = start; i < active->num_sgs; i++) { + sg = &active->sg[i]; + total = axi_dmac_total_sg_bytes(chan, sg); + rslt->residue += (total - sg->partial_len); + } +} + static bool axi_dmac_transfer_done(struct axi_dmac_chan *chan, unsigned int completed_transfers) { @@ -268,6 +354,10 @@ static bool axi_dmac_transfer_done(struct axi_dmac_chan *chan, if (!active) return false; + if (chan->hw_partial_xfer && + (completed_transfers & AXI_DMAC_FLAG_PARTIAL_XFER_DONE)) + axi_dmac_dequeue_partial_xfers(chan); + do { sg = &active->sg[active->num_completed]; if (sg->id == AXI_DMAC_SG_UNUSED) /* Not yet submitted */ @@ -281,10 +371,14 @@ static bool axi_dmac_transfer_done(struct axi_dmac_chan *chan, start_next = true; } + if (sg->partial_len) + axi_dmac_compute_residue(chan, active); + if (active->cyclic) vchan_cyclic_callback(&active->vdesc); - if (active->num_completed == active->num_sgs) { + if (active->num_completed == active->num_sgs || + sg->partial_len) { if (active->cyclic) { active->num_completed = 0; /* wrap around */ } else { @@ -675,6 +769,9 @@ static int axi_dmac_detect_caps(struct axi_dmac *dmac) return -ENODEV; } + if (version >= ADI_AXI_PCORE_VER(4, 2, 'a')) + chan->hw_partial_xfer = true; + if (version >= ADI_AXI_PCORE_VER(4, 1, 'a')) { axi_dmac_write(dmac, AXI_DMAC_REG_X_LENGTH, 0x00); chan->length_align_mask = From patchwork Thu Jun 6 10:45:49 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexandru Ardelean X-Patchwork-Id: 10979209 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id F23AD6C5 for ; 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Thu, 6 Jun 2019 06:45:58 -0400 From: Alexandru Ardelean To: CC: Alexandru Ardelean Subject: [PATCH 3/4] dmaengine: axi-dmac: terminate early DMA transfers after a partial one Date: Thu, 6 Jun 2019 13:45:49 +0300 Message-ID: <20190606104550.32336-3-alexandru.ardelean@analog.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190606104550.32336-1-alexandru.ardelean@analog.com> References: <20190606104550.32336-1-alexandru.ardelean@analog.com> MIME-Version: 1.0 X-ADIRoutedOnPrem: True X-EOPAttributedMessage: 0 X-MS-Office365-Filtering-HT: Tenant X-Forefront-Antispam-Report: CIP:137.71.25.57;IPV:NLI;CTRY:US;EFV:NLI;SFV:NSPM;SFS:(10009020)(346002)(376002)(136003)(39850400004)(396003)(2980300002)(189003)(199004)(106002)(44832011)(11346002)(2870700001)(305945005)(36756003)(2906002)(478600001)(486006)(356004)(8936002)(77096007)(6666004)(2616005)(336012)(476003)(26005)(186003)(426003)(246002)(47776003)(70206006)(2351001)(6916009)(7636002)(86362001)(126002)(4326008)(316002)(70586007)(14444005)(107886003)(50226002)(446003)(8676002)(5660300002)(76176011)(50466002)(1076003)(51416003)(48376002)(7696005);DIR:OUT;SFP:1101;SCL:1;SRVR:BLUPR03MB552;H:nwd2mta2.analog.com;FPR:;SPF:Pass;LANG:en;PTR:nwd2mail11.analog.com;MX:1;A:1; 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This change implements this by adding a new flag on the AXI DMAC descriptor. This flags is set to true, if there was a partial transfer in a previously completed segment. When that flag is true, the TLAST flag is added to the to the submitted segment, signaling the controller to stop receiving more segments. Signed-off-by: Alexandru Ardelean --- drivers/dma/dma-axi-dmac.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/dma/dma-axi-dmac.c b/drivers/dma/dma-axi-dmac.c index e0702697e2b3..3b418d545c7a 100644 --- a/drivers/dma/dma-axi-dmac.c +++ b/drivers/dma/dma-axi-dmac.c @@ -97,6 +97,7 @@ struct axi_dmac_sg { struct axi_dmac_desc { struct virt_dma_desc vdesc; bool cyclic; + bool have_partial_xfer; unsigned int num_submitted; unsigned int num_completed; @@ -221,7 +222,8 @@ static void axi_dmac_start_transfer(struct axi_dmac_chan *chan) } desc->num_submitted++; - if (desc->num_submitted == desc->num_sgs) { + if (desc->num_submitted == desc->num_sgs || + desc->have_partial_xfer) { if (desc->cyclic) desc->num_submitted = 0; /* Start again */ else @@ -295,6 +297,7 @@ static void axi_dmac_dequeue_partial_xfers(struct axi_dmac_chan *chan) if (sg->id == AXI_DMAC_SG_UNUSED) continue; if (sg->id == id) { + desc->have_partial_xfer = true; sg->partial_len = len; found_sg = true; break; From patchwork Thu Jun 6 10:45:50 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexandru Ardelean X-Patchwork-Id: 10979211 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id CFE9F6C5 for ; Thu, 6 Jun 2019 10:46:03 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id BF551201A4 for ; Thu, 6 Jun 2019 10:46:03 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id B19CF28843; Thu, 6 Jun 2019 10:46:03 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 3EC1C287AD for ; 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Thu, 6 Jun 2019 03:45:59 -0700 Received: from saturn.ad.analog.com (10.48.65.129) by NWD2HUBCAS7.ad.analog.com (10.64.69.107) with Microsoft SMTP Server id 14.3.408.0; Thu, 6 Jun 2019 06:45:59 -0400 From: Alexandru Ardelean To: CC: Alexandru Ardelean Subject: [PATCH 4/4] dmaengine: axi-dmac: add regmap support Date: Thu, 6 Jun 2019 13:45:50 +0300 Message-ID: <20190606104550.32336-4-alexandru.ardelean@analog.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190606104550.32336-1-alexandru.ardelean@analog.com> References: <20190606104550.32336-1-alexandru.ardelean@analog.com> MIME-Version: 1.0 X-ADIRoutedOnPrem: True X-EOPAttributedMessage: 0 X-MS-Office365-Filtering-HT: Tenant X-Forefront-Antispam-Report: CIP:137.71.25.57;IPV:NLI;CTRY:US;EFV:NLI;SFV:NSPM;SFS:(10009020)(346002)(396003)(136003)(39850400004)(376002)(2980300002)(199004)(189003)(107886003)(106002)(50466002)(1076003)(305945005)(7636002)(2906002)(4326008)(246002)(50226002)(6306002)(8676002)(8936002)(356004)(6666004)(48376002)(316002)(2870700001)(5660300002)(6916009)(336012)(426003)(51416003)(7696005)(966005)(478600001)(14444005)(36756003)(2351001)(77096007)(486006)(186003)(446003)(11346002)(126002)(26005)(47776003)(86362001)(76176011)(70206006)(2616005)(70586007)(476003)(44832011);DIR:OUT;SFP:1101;SCL:1;SRVR:DM5PR03MB3130;H:nwd2mta2.analog.com;FPR:;SPF:Pass;LANG:en;PTR:nwd2mail11.analog.com;A:1;MX:1; X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 21a27c51-291d-4e91-e811-08d6ea6c29db X-Microsoft-Antispam: BCL:0;PCL:0;RULEID:(2390118)(7020095)(4652040)(8989299)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(5600148)(711020)(4605104)(4709080)(1401327)(2017052603328);SRVR:DM5PR03MB3130; X-MS-TrafficTypeDiagnostic: DM5PR03MB3130: X-MS-Exchange-PUrlCount: 1 X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:7219; X-Forefront-PRVS: 00603B7EEF X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam-Message-Info: C2TyvMEd7aFqHuOmnBdkahyTyI8+Xu8vfhPRCwpGrN85/W+qhcMHsil0Bs6L4KcNystF7gtdgW33Euovatty7ts/1ceQcMpNHiRlheSNt9hs4ZfKGNexdX52e/GFFP1Mhnwr2gI19e0AtHSZItip39mgyMN/NzcZTyb4LoGR2RHmwrYfomIQvf/Hkb7lLekKZZdwOT91N188pDUu6RxjrW9RG8g0EQUErDSkRp38m7nnOjGP5agphDq6a8S4pJF/Xlz/4cW+vg9SeUrNv/D2TOOyh3ypTirlyohyIXYTXUpIYxFpcG6J3bRa2XIoqxIrjaGYQoxxuqo3FGI8XkFwfNa73YjshDPM1jie9ES/YedAl/9XIae6sTm6282ak2wyXa0WA4ZWF1MI/zCsQDINC2fBE29bsfBdRmgKUCM+QaU= X-OriginatorOrg: analog.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Jun 2019 10:45:59.6917 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 21a27c51-291d-4e91-e811-08d6ea6c29db X-MS-Exchange-CrossTenant-Id: eaa689b4-8f87-40e0-9c6f-7228de4d754a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=eaa689b4-8f87-40e0-9c6f-7228de4d754a;Ip=[137.71.25.57];Helo=[nwd2mta2.analog.com] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR03MB3130 Sender: dmaengine-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: dmaengine@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The registers for AXI DMAC are detailed at: https://wiki.analog.com/resources/fpga/docs/axi_dmac#register_map This change adds regmap support for these registers, in case some wants to have a more direct access to them via this interface. Signed-off-by: Alexandru Ardelean --- drivers/dma/Kconfig | 1 + drivers/dma/dma-axi-dmac.c | 41 ++++++++++++++++++++++++++++++++++++++ 2 files changed, 42 insertions(+) diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig index eaf78f4e07ce..ae631c6e8bc5 100644 --- a/drivers/dma/Kconfig +++ b/drivers/dma/Kconfig @@ -102,6 +102,7 @@ config AXI_DMAC depends on MICROBLAZE || NIOS2 || ARCH_ZYNQ || ARCH_ZYNQMP || ARCH_SOCFPGA || COMPILE_TEST select DMA_ENGINE select DMA_VIRTUAL_CHANNELS + select REGMAP_MMIO help Enable support for the Analog Devices AXI-DMAC peripheral. This DMA controller is often used in Analog Device's reference designs for FPGA diff --git a/drivers/dma/dma-axi-dmac.c b/drivers/dma/dma-axi-dmac.c index 3b418d545c7a..a35b76f08dfa 100644 --- a/drivers/dma/dma-axi-dmac.c +++ b/drivers/dma/dma-axi-dmac.c @@ -19,6 +19,7 @@ #include #include #include +#include #include #include @@ -679,6 +680,44 @@ static void axi_dmac_desc_free(struct virt_dma_desc *vdesc) kfree(container_of(vdesc, struct axi_dmac_desc, vdesc)); } +static bool axi_dmac_regmap_rdwr(struct device *dev, unsigned int reg) +{ + switch (reg) { + case AXI_DMAC_REG_IRQ_MASK: + case AXI_DMAC_REG_IRQ_SOURCE: + case AXI_DMAC_REG_IRQ_PENDING: + case AXI_DMAC_REG_CTRL: + case AXI_DMAC_REG_TRANSFER_ID: + case AXI_DMAC_REG_START_TRANSFER: + case AXI_DMAC_REG_FLAGS: + case AXI_DMAC_REG_DEST_ADDRESS: + case AXI_DMAC_REG_SRC_ADDRESS: + case AXI_DMAC_REG_X_LENGTH: + case AXI_DMAC_REG_Y_LENGTH: + case AXI_DMAC_REG_DEST_STRIDE: + case AXI_DMAC_REG_SRC_STRIDE: + case AXI_DMAC_REG_TRANSFER_DONE: + case AXI_DMAC_REG_ACTIVE_TRANSFER_ID : + case AXI_DMAC_REG_STATUS: + case AXI_DMAC_REG_CURRENT_SRC_ADDR: + case AXI_DMAC_REG_CURRENT_DEST_ADDR: + case AXI_DMAC_REG_PARTIAL_XFER_LEN: + case AXI_DMAC_REG_PARTIAL_XFER_ID: + return true; + default: + return false; + } +} + +static const struct regmap_config axi_dmac_regmap_config = { + .reg_bits = 32, + .val_bits = 32, + .reg_stride = 4, + .max_register = AXI_DMAC_REG_PARTIAL_XFER_ID, + .readable_reg = axi_dmac_regmap_rdwr, + .writeable_reg = axi_dmac_regmap_rdwr, +}; + /* * The configuration stored in the devicetree matches the configuration * parameters of the peripheral instance and allows the driver to know which @@ -883,6 +922,8 @@ static int axi_dmac_probe(struct platform_device *pdev) platform_set_drvdata(pdev, dmac); + devm_regmap_init_mmio(&pdev->dev, dmac->base, &axi_dmac_regmap_config); + return 0; err_unregister_of: