From patchwork Thu Jun 6 21:52:10 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniele Ceraolo Spurio X-Patchwork-Id: 10980497 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 8B0E414B6 for ; Thu, 6 Jun 2019 21:52:44 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 79EBA28AD7 for ; Thu, 6 Jun 2019 21:52:44 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 6DF5128ADA; Thu, 6 Jun 2019 21:52:44 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id CC01928AD7 for ; Thu, 6 Jun 2019 21:52:43 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 3526B899BC; Thu, 6 Jun 2019 21:52:43 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by gabe.freedesktop.org (Postfix) with ESMTPS id 2481D899BC for ; Thu, 6 Jun 2019 21:52:42 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga105.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 06 Jun 2019 14:52:42 -0700 X-ExtLoop1: 1 Received: from dceraolo-linux.fm.intel.com ([10.1.27.145]) by orsmga002.jf.intel.com with ESMTP; 06 Jun 2019 14:52:41 -0700 From: Daniele Ceraolo Spurio To: intel-gfx@lists.freedesktop.org Date: Thu, 6 Jun 2019 14:52:10 -0700 Message-Id: <20190606215218.34486-2-daniele.ceraolospurio@intel.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190606215218.34486-1-daniele.ceraolospurio@intel.com> References: <20190606215218.34486-1-daniele.ceraolospurio@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [RFC 1/8] drm/i915: use vfuncs for reg_read/write_fw_domains X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP Instead of going through the if-else chain every time, let's save the function in the uncore structure. Note that the new functions are purposely not used from the reg read/write functions to keep the inlining there. While at it, use the new macro to call the old ones to clean the code a bit. Signed-off-by: Daniele Ceraolo Spurio --- drivers/gpu/drm/i915/intel_uncore.c | 172 ++++++++----------- drivers/gpu/drm/i915/intel_uncore.h | 5 + drivers/gpu/drm/i915/selftests/mock_uncore.c | 4 +- 3 files changed, 75 insertions(+), 106 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c index f78668123f02..c3be79c4957b 100644 --- a/drivers/gpu/drm/i915/intel_uncore.c +++ b/drivers/gpu/drm/i915/intel_uncore.c @@ -901,6 +901,12 @@ static bool is_gen##x##_shadowed(u32 offset) \ __is_genX_shadowed(8) __is_genX_shadowed(11) +static enum forcewake_domains +gen6_reg_write_fw_domains(struct intel_uncore *uncore, i915_reg_t reg) +{ + return FORCEWAKE_RENDER; +} + #define __gen8_reg_write_fw_domains(uncore, offset) \ ({ \ enum forcewake_domains __fwd; \ @@ -1145,26 +1151,23 @@ func##_read##x(struct intel_uncore *uncore, i915_reg_t reg, bool trace) { \ val = __raw_uncore_read##x(uncore, reg); \ GEN6_READ_FOOTER; \ } -#define __gen6_read(x) __gen_read(gen6, x) -#define __fwtable_read(x) __gen_read(fwtable, x) -#define __gen11_fwtable_read(x) __gen_read(gen11_fwtable, x) - -__gen11_fwtable_read(8) -__gen11_fwtable_read(16) -__gen11_fwtable_read(32) -__gen11_fwtable_read(64) -__fwtable_read(8) -__fwtable_read(16) -__fwtable_read(32) -__fwtable_read(64) -__gen6_read(8) -__gen6_read(16) -__gen6_read(32) -__gen6_read(64) - -#undef __gen11_fwtable_read -#undef __fwtable_read -#undef __gen6_read + +#define __gen_reg_read_funcs(func) \ +static enum forcewake_domains \ +func##_reg_read_fw_domains(struct intel_uncore *uncore, i915_reg_t reg) { \ + return __##func##_reg_read_fw_domains(uncore, i915_mmio_reg_offset(reg)); \ +} \ +\ +__gen_read(func, 8) \ +__gen_read(func, 16) \ +__gen_read(func, 32) \ +__gen_read(func, 64) + +__gen_reg_read_funcs(gen11_fwtable); +__gen_reg_read_funcs(fwtable); +__gen_reg_read_funcs(gen6); + +#undef __gen_reg_read_funcs #undef GEN6_READ_FOOTER #undef GEN6_READ_HEADER @@ -1225,6 +1228,9 @@ gen6_write##x(struct intel_uncore *uncore, i915_reg_t reg, u##x val, bool trace) __raw_uncore_write##x(uncore, reg, val); \ GEN6_WRITE_FOOTER; \ } +__gen6_write(8) +__gen6_write(16) +__gen6_write(32) #define __gen_write(func, x) \ static void \ @@ -1237,38 +1243,33 @@ func##_write##x(struct intel_uncore *uncore, i915_reg_t reg, u##x val, bool trac __raw_uncore_write##x(uncore, reg, val); \ GEN6_WRITE_FOOTER; \ } -#define __gen8_write(x) __gen_write(gen8, x) -#define __fwtable_write(x) __gen_write(fwtable, x) -#define __gen11_fwtable_write(x) __gen_write(gen11_fwtable, x) - -__gen11_fwtable_write(8) -__gen11_fwtable_write(16) -__gen11_fwtable_write(32) -__fwtable_write(8) -__fwtable_write(16) -__fwtable_write(32) -__gen8_write(8) -__gen8_write(16) -__gen8_write(32) -__gen6_write(8) -__gen6_write(16) -__gen6_write(32) -#undef __gen11_fwtable_write -#undef __fwtable_write -#undef __gen8_write -#undef __gen6_write +#define __gen_reg_write_funcs(func) \ +static enum forcewake_domains \ +func##_reg_write_fw_domains(struct intel_uncore *uncore, i915_reg_t reg) { \ + return __##func##_reg_write_fw_domains(uncore, i915_mmio_reg_offset(reg)); \ +} \ +\ +__gen_write(func, 8) \ +__gen_write(func, 16) \ +__gen_write(func, 32) + +__gen_reg_write_funcs(gen11_fwtable); +__gen_reg_write_funcs(fwtable); +__gen_reg_write_funcs(gen8); + +#undef __gen_reg_write_funcs #undef GEN6_WRITE_FOOTER #undef GEN6_WRITE_HEADER -#define ASSIGN_WRITE_MMIO_VFUNCS(uncore, x) \ +#define ASSIGN_WRITE_MMIO_VFUNCS_NO_FW(uncore, x) \ do { \ (uncore)->funcs.mmio_writeb = x##_write8; \ (uncore)->funcs.mmio_writew = x##_write16; \ (uncore)->funcs.mmio_writel = x##_write32; \ } while (0) -#define ASSIGN_READ_MMIO_VFUNCS(uncore, x) \ +#define ASSIGN_READ_MMIO_VFUNCS_NO_FW(uncore, x) \ do { \ (uncore)->funcs.mmio_readb = x##_read8; \ (uncore)->funcs.mmio_readw = x##_read16; \ @@ -1276,6 +1277,17 @@ do { \ (uncore)->funcs.mmio_readq = x##_read64; \ } while (0) +#define ASSIGN_WRITE_MMIO_VFUNCS(uncore, x) \ +do { \ + ASSIGN_WRITE_MMIO_VFUNCS_NO_FW((uncore), x); \ + (uncore)->funcs.write_fw_domains = x##_reg_write_fw_domains; \ +} while (0) + +#define ASSIGN_READ_MMIO_VFUNCS(uncore, x) \ +do { \ + ASSIGN_READ_MMIO_VFUNCS_NO_FW(uncore, x); \ + (uncore)->funcs.read_fw_domains = x##_reg_read_fw_domains; \ +} while (0) static void fw_domain_init(struct intel_uncore *uncore, enum forcewake_domain_id domain_id, @@ -1559,11 +1571,11 @@ int intel_uncore_init_mmio(struct intel_uncore *uncore) if (!intel_uncore_has_forcewake(uncore)) { if (IS_GEN(i915, 5)) { - ASSIGN_WRITE_MMIO_VFUNCS(uncore, gen5); - ASSIGN_READ_MMIO_VFUNCS(uncore, gen5); + ASSIGN_WRITE_MMIO_VFUNCS_NO_FW(uncore, gen5); + ASSIGN_READ_MMIO_VFUNCS_NO_FW(uncore, gen5); } else { - ASSIGN_WRITE_MMIO_VFUNCS(uncore, gen2); - ASSIGN_READ_MMIO_VFUNCS(uncore, gen2); + ASSIGN_WRITE_MMIO_VFUNCS_NO_FW(uncore, gen2); + ASSIGN_READ_MMIO_VFUNCS_NO_FW(uncore, gen2); } } else if (IS_GEN_RANGE(i915, 6, 7)) { ASSIGN_WRITE_MMIO_VFUNCS(uncore, gen6); @@ -1594,6 +1606,12 @@ int intel_uncore_init_mmio(struct intel_uncore *uncore) ASSIGN_READ_MMIO_VFUNCS(uncore, gen11_fwtable); } + /* make sure fw funcs are set if and only if we have fw*/ + GEM_BUG_ON(intel_uncore_has_forcewake(uncore) != !!uncore->funcs.force_wake_get); + GEM_BUG_ON(intel_uncore_has_forcewake(uncore) != !!uncore->funcs.force_wake_put); + GEM_BUG_ON(intel_uncore_has_forcewake(uncore) != !!uncore->funcs.read_fw_domains); + GEM_BUG_ON(intel_uncore_has_forcewake(uncore) != !!uncore->funcs.write_fw_domains); + if (HAS_FPGA_DBG_UNCLAIMED(i915)) uncore->flags |= UNCORE_HAS_FPGA_DBG_UNCLAIMED; @@ -1866,62 +1884,6 @@ intel_uncore_arm_unclaimed_mmio_detection(struct intel_uncore *uncore) return ret; } -static enum forcewake_domains -intel_uncore_forcewake_for_read(struct intel_uncore *uncore, - i915_reg_t reg) -{ - struct drm_i915_private *i915 = uncore_to_i915(uncore); - u32 offset = i915_mmio_reg_offset(reg); - enum forcewake_domains fw_domains; - - if (INTEL_GEN(i915) >= 11) { - fw_domains = __gen11_fwtable_reg_read_fw_domains(uncore, offset); - } else if (HAS_FWTABLE(i915)) { - fw_domains = __fwtable_reg_read_fw_domains(uncore, offset); - } else if (INTEL_GEN(i915) >= 6) { - fw_domains = __gen6_reg_read_fw_domains(uncore, offset); - } else { - /* on devices with FW we expect to hit one of the above cases */ - if (intel_uncore_has_forcewake(uncore)) - MISSING_CASE(INTEL_GEN(i915)); - - fw_domains = 0; - } - - WARN_ON(fw_domains & ~uncore->fw_domains); - - return fw_domains; -} - -static enum forcewake_domains -intel_uncore_forcewake_for_write(struct intel_uncore *uncore, - i915_reg_t reg) -{ - struct drm_i915_private *i915 = uncore_to_i915(uncore); - u32 offset = i915_mmio_reg_offset(reg); - enum forcewake_domains fw_domains; - - if (INTEL_GEN(i915) >= 11) { - fw_domains = __gen11_fwtable_reg_write_fw_domains(uncore, offset); - } else if (HAS_FWTABLE(i915) && !IS_VALLEYVIEW(i915)) { - fw_domains = __fwtable_reg_write_fw_domains(uncore, offset); - } else if (IS_GEN(i915, 8)) { - fw_domains = __gen8_reg_write_fw_domains(uncore, offset); - } else if (IS_GEN_RANGE(i915, 6, 7)) { - fw_domains = FORCEWAKE_RENDER; - } else { - /* on devices with FW we expect to hit one of the above cases */ - if (intel_uncore_has_forcewake(uncore)) - MISSING_CASE(INTEL_GEN(i915)); - - fw_domains = 0; - } - - WARN_ON(fw_domains & ~uncore->fw_domains); - - return fw_domains; -} - /** * intel_uncore_forcewake_for_reg - which forcewake domains are needed to access * a register @@ -1948,10 +1910,12 @@ intel_uncore_forcewake_for_reg(struct intel_uncore *uncore, return 0; if (op & FW_REG_READ) - fw_domains = intel_uncore_forcewake_for_read(uncore, reg); + fw_domains = uncore->funcs.read_fw_domains(uncore, reg); if (op & FW_REG_WRITE) - fw_domains |= intel_uncore_forcewake_for_write(uncore, reg); + fw_domains |= uncore->funcs.write_fw_domains(uncore, reg); + + WARN_ON(fw_domains & ~uncore->fw_domains); return fw_domains; } diff --git a/drivers/gpu/drm/i915/intel_uncore.h b/drivers/gpu/drm/i915/intel_uncore.h index d6af3de70121..72ef8b262930 100644 --- a/drivers/gpu/drm/i915/intel_uncore.h +++ b/drivers/gpu/drm/i915/intel_uncore.h @@ -70,6 +70,11 @@ struct intel_uncore_funcs { void (*force_wake_put)(struct intel_uncore *uncore, enum forcewake_domains domains); + enum forcewake_domains (*read_fw_domains)(struct intel_uncore *uncore, + i915_reg_t r); + enum forcewake_domains (*write_fw_domains)(struct intel_uncore *uncore, + i915_reg_t r); + u8 (*mmio_readb)(struct intel_uncore *uncore, i915_reg_t r, bool trace); u16 (*mmio_readw)(struct intel_uncore *uncore, diff --git a/drivers/gpu/drm/i915/selftests/mock_uncore.c b/drivers/gpu/drm/i915/selftests/mock_uncore.c index ff8999c63a12..343017215463 100644 --- a/drivers/gpu/drm/i915/selftests/mock_uncore.c +++ b/drivers/gpu/drm/i915/selftests/mock_uncore.c @@ -41,6 +41,6 @@ __nop_read(64) void mock_uncore_init(struct intel_uncore *uncore) { - ASSIGN_WRITE_MMIO_VFUNCS(uncore, nop); - ASSIGN_READ_MMIO_VFUNCS(uncore, nop); + ASSIGN_WRITE_MMIO_VFUNCS_NO_FW(uncore, nop); + ASSIGN_READ_MMIO_VFUNCS_NO_FW(uncore, nop); } From patchwork Thu Jun 6 21:52:11 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniele Ceraolo Spurio X-Patchwork-Id: 10980499 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 8184F14B6 for ; Thu, 6 Jun 2019 21:52:46 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 7095728AD7 for ; Thu, 6 Jun 2019 21:52:46 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 64A5828ADA; Thu, 6 Jun 2019 21:52:46 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 0F76F28AD7 for ; Thu, 6 Jun 2019 21:52:45 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 58A82899C4; Thu, 6 Jun 2019 21:52:45 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by gabe.freedesktop.org (Postfix) with ESMTPS id 35C97899BE for ; Thu, 6 Jun 2019 21:52:44 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga105.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 06 Jun 2019 14:52:44 -0700 X-ExtLoop1: 1 Received: from dceraolo-linux.fm.intel.com ([10.1.27.145]) by orsmga002.jf.intel.com with ESMTP; 06 Jun 2019 14:52:43 -0700 From: Daniele Ceraolo Spurio To: intel-gfx@lists.freedesktop.org Date: Thu, 6 Jun 2019 14:52:11 -0700 Message-Id: <20190606215218.34486-3-daniele.ceraolospurio@intel.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190606215218.34486-1-daniele.ceraolospurio@intel.com> References: <20190606215218.34486-1-daniele.ceraolospurio@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [RFC 2/8] drm/i915: kill uncore_sanitize X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP uncore_sanitize performs no action on the uncore structure and just calls intel_sanitize_gt_powersave, so we can just call the latter directly. Signed-off-by: Daniele Ceraolo Spurio Reviewed-by: Jani Nikula --- drivers/gpu/drm/i915/i915_drv.c | 12 ++++++++++-- drivers/gpu/drm/i915/intel_uncore.c | 9 --------- drivers/gpu/drm/i915/intel_uncore.h | 1 - 3 files changed, 10 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index 1af6751e1b36..05ee328e3f66 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -1622,7 +1622,8 @@ static int i915_driver_init_hw(struct drm_i915_private *dev_priv) pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY, PM_QOS_DEFAULT_VALUE); - intel_uncore_sanitize(dev_priv); + /* BIOS often leaves RC6 enabled, but disable it for hw init */ + intel_sanitize_gt_powersave(dev_priv); intel_gt_init_workarounds(dev_priv); i915_gem_load_init_fences(dev_priv); @@ -1915,6 +1916,9 @@ int i915_driver_load(struct pci_dev *pdev, const struct pci_device_id *ent) out_cleanup_hw: i915_driver_cleanup_hw(dev_priv); i915_ggtt_cleanup_hw(dev_priv); + + /* Paranoia: make sure we have disabled everything before we exit. */ + intel_sanitize_gt_powersave(dev_priv); out_cleanup_mmio: i915_driver_cleanup_mmio(dev_priv); out_runtime_pm_put: @@ -1984,6 +1988,10 @@ static void i915_driver_release(struct drm_device *dev) i915_gem_fini(dev_priv); i915_ggtt_cleanup_hw(dev_priv); + + /* Paranoia: make sure we have disabled everything before we exit. */ + intel_sanitize_gt_powersave(dev_priv); + i915_driver_cleanup_mmio(dev_priv); enable_rpm_wakeref_asserts(dev_priv); @@ -2349,7 +2357,7 @@ static int i915_drm_resume_early(struct drm_device *dev) hsw_disable_pc8(dev_priv); } - intel_uncore_sanitize(dev_priv); + intel_sanitize_gt_powersave(dev_priv); intel_power_domains_resume(dev_priv); diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c index c3be79c4957b..ef7eed9237a0 100644 --- a/drivers/gpu/drm/i915/intel_uncore.c +++ b/drivers/gpu/drm/i915/intel_uncore.c @@ -537,12 +537,6 @@ void intel_uncore_runtime_resume(struct intel_uncore *uncore) iosf_mbi_register_pmic_bus_access_notifier(&uncore->pmic_bus_access_nb); } -void intel_uncore_sanitize(struct drm_i915_private *dev_priv) -{ - /* BIOS often leaves RC6 enabled, but disable it for hw init */ - intel_sanitize_gt_powersave(dev_priv); -} - static void __intel_uncore_forcewake_get(struct intel_uncore *uncore, enum forcewake_domains fw_domains) { @@ -1664,9 +1658,6 @@ void intel_uncore_prune_mmio_domains(struct intel_uncore *uncore) void intel_uncore_fini_mmio(struct intel_uncore *uncore) { - /* Paranoia: make sure we have disabled everything before we exit. */ - intel_uncore_sanitize(uncore_to_i915(uncore)); - iosf_mbi_punit_acquire(); iosf_mbi_unregister_pmic_bus_access_notifier_unlocked( &uncore->pmic_bus_access_nb); diff --git a/drivers/gpu/drm/i915/intel_uncore.h b/drivers/gpu/drm/i915/intel_uncore.h index 72ef8b262930..bf06b6b16892 100644 --- a/drivers/gpu/drm/i915/intel_uncore.h +++ b/drivers/gpu/drm/i915/intel_uncore.h @@ -182,7 +182,6 @@ intel_uncore_has_fifo(const struct intel_uncore *uncore) return uncore->flags & UNCORE_HAS_FIFO; } -void intel_uncore_sanitize(struct drm_i915_private *dev_priv); void intel_uncore_init_early(struct intel_uncore *uncore); int intel_uncore_init_mmio(struct intel_uncore *uncore); void intel_uncore_prune_mmio_domains(struct intel_uncore *uncore); From patchwork Thu Jun 6 21:52:12 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniele Ceraolo Spurio X-Patchwork-Id: 10980501 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 18B6314C0 for ; Thu, 6 Jun 2019 21:52:48 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 069B228AD7 for ; Thu, 6 Jun 2019 21:52:48 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id EE6B128ADA; Thu, 6 Jun 2019 21:52:47 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 44DA728AD7 for ; Thu, 6 Jun 2019 21:52:47 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 870F5899BE; Thu, 6 Jun 2019 21:52:46 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by gabe.freedesktop.org (Postfix) with ESMTPS id 2ECC2899BE for ; Thu, 6 Jun 2019 21:52:45 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga105.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 06 Jun 2019 14:52:45 -0700 X-ExtLoop1: 1 Received: from dceraolo-linux.fm.intel.com ([10.1.27.145]) by orsmga002.jf.intel.com with ESMTP; 06 Jun 2019 14:52:44 -0700 From: Daniele Ceraolo Spurio To: intel-gfx@lists.freedesktop.org Date: Thu, 6 Jun 2019 14:52:12 -0700 Message-Id: <20190606215218.34486-4-daniele.ceraolospurio@intel.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190606215218.34486-1-daniele.ceraolospurio@intel.com> References: <20190606215218.34486-1-daniele.ceraolospurio@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [RFC 3/8] drm/i915: dynamically allocate forcewake domains X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP In an upcoming patch we will introduce a display uncore with no forcewake domains, so let's avoid wasting memory and be ready to allocate only what we need. Signed-off-by: Daniele Ceraolo Spurio --- drivers/gpu/drm/i915/intel_uncore.c | 141 +++++++++++++++++----------- drivers/gpu/drm/i915/intel_uncore.h | 13 +-- 2 files changed, 92 insertions(+), 62 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c index ef7eed9237a0..30650e6e2f54 100644 --- a/drivers/gpu/drm/i915/intel_uncore.c +++ b/drivers/gpu/drm/i915/intel_uncore.c @@ -344,7 +344,7 @@ intel_uncore_fw_release_timer(struct hrtimer *timer) { struct intel_uncore_forcewake_domain *domain = container_of(timer, struct intel_uncore_forcewake_domain, timer); - struct intel_uncore *uncore = forcewake_domain_to_uncore(domain); + struct intel_uncore *uncore = domain->uncore; unsigned long irqflags; assert_rpm_device_not_suspended(uncore->rpm); @@ -1283,23 +1283,24 @@ do { \ (uncore)->funcs.read_fw_domains = x##_reg_read_fw_domains; \ } while (0) -static void fw_domain_init(struct intel_uncore *uncore, +static int fw_domain_init(struct intel_uncore *uncore, enum forcewake_domain_id domain_id, i915_reg_t reg_set, i915_reg_t reg_ack) { struct intel_uncore_forcewake_domain *d; - if (WARN_ON(domain_id >= FW_DOMAIN_ID_COUNT)) - return; - - d = &uncore->fw_domain[domain_id]; + GEM_BUG_ON(domain_id >= FW_DOMAIN_ID_COUNT); + GEM_BUG_ON(uncore->fw_domain[domain_id]); - WARN_ON(d->wake_count); + d = kzalloc(sizeof(*d), GFP_KERNEL); + if (!d) + return -ENOMEM; WARN_ON(!i915_mmio_reg_valid(reg_set)); WARN_ON(!i915_mmio_reg_valid(reg_ack)); + d->uncore = uncore; d->wake_count = 0; d->reg_set = uncore->regs + i915_mmio_reg_offset(reg_set); d->reg_ack = uncore->regs + i915_mmio_reg_offset(reg_ack); @@ -1325,6 +1326,10 @@ static void fw_domain_init(struct intel_uncore *uncore, uncore->fw_domains |= BIT(domain_id); fw_domain_reset(d); + + uncore->fw_domain[domain_id] = d; + + return 0; } static void fw_domain_fini(struct intel_uncore *uncore, @@ -1332,78 +1337,93 @@ static void fw_domain_fini(struct intel_uncore *uncore, { struct intel_uncore_forcewake_domain *d; - if (WARN_ON(domain_id >= FW_DOMAIN_ID_COUNT)) - return; + GEM_BUG_ON(domain_id >= FW_DOMAIN_ID_COUNT); - d = &uncore->fw_domain[domain_id]; + d = fetch_and_zero(&uncore->fw_domain[domain_id]); + uncore->fw_domains &= ~BIT(domain_id); - WARN_ON(d->wake_count); - WARN_ON(hrtimer_cancel(&d->timer)); - memset(d, 0, sizeof(*d)); + if (d) { + WARN_ON(d->wake_count); + WARN_ON(hrtimer_cancel(&d->timer)); + kfree(d); + } +} - uncore->fw_domains &= ~BIT(domain_id); +static void intel_uncore_fw_domains_fini(struct intel_uncore *uncore) +{ + struct intel_uncore_forcewake_domain *d; + int tmp; + + for_each_fw_domain(d, uncore, tmp) + fw_domain_fini(uncore, d->id); } -static void intel_uncore_fw_domains_init(struct intel_uncore *uncore) +static int intel_uncore_fw_domains_init(struct intel_uncore *uncore) { struct drm_i915_private *i915 = uncore_to_i915(uncore); + int ret; + +#define __fw_domain_init(id, set, ack) \ + ret = fw_domain_init(uncore, id, set, ack); \ + if (ret) \ + goto out_clean; if (!intel_uncore_has_forcewake(uncore)) - return; + return 0; if (INTEL_GEN(i915) >= 11) { int i; - uncore->funcs.force_wake_get = - fw_domains_get_with_fallback; + uncore->funcs.force_wake_get = fw_domains_get_with_fallback; uncore->funcs.force_wake_put = fw_domains_put; - fw_domain_init(uncore, FW_DOMAIN_ID_RENDER, - FORCEWAKE_RENDER_GEN9, - FORCEWAKE_ACK_RENDER_GEN9); - fw_domain_init(uncore, FW_DOMAIN_ID_BLITTER, - FORCEWAKE_BLITTER_GEN9, - FORCEWAKE_ACK_BLITTER_GEN9); + __fw_domain_init(FW_DOMAIN_ID_RENDER, + FORCEWAKE_RENDER_GEN9, + FORCEWAKE_ACK_RENDER_GEN9); + __fw_domain_init(FW_DOMAIN_ID_BLITTER, + FORCEWAKE_BLITTER_GEN9, + FORCEWAKE_ACK_BLITTER_GEN9); + for (i = 0; i < I915_MAX_VCS; i++) { if (!HAS_ENGINE(i915, _VCS(i))) continue; - fw_domain_init(uncore, FW_DOMAIN_ID_MEDIA_VDBOX0 + i, - FORCEWAKE_MEDIA_VDBOX_GEN11(i), - FORCEWAKE_ACK_MEDIA_VDBOX_GEN11(i)); + __fw_domain_init(FW_DOMAIN_ID_MEDIA_VDBOX0 + i, + FORCEWAKE_MEDIA_VDBOX_GEN11(i), + FORCEWAKE_ACK_MEDIA_VDBOX_GEN11(i)); } for (i = 0; i < I915_MAX_VECS; i++) { if (!HAS_ENGINE(i915, _VECS(i))) continue; - fw_domain_init(uncore, FW_DOMAIN_ID_MEDIA_VEBOX0 + i, - FORCEWAKE_MEDIA_VEBOX_GEN11(i), - FORCEWAKE_ACK_MEDIA_VEBOX_GEN11(i)); + __fw_domain_init(FW_DOMAIN_ID_MEDIA_VEBOX0 + i, + FORCEWAKE_MEDIA_VEBOX_GEN11(i), + FORCEWAKE_ACK_MEDIA_VEBOX_GEN11(i)); } } else if (IS_GEN_RANGE(i915, 9, 10)) { - uncore->funcs.force_wake_get = - fw_domains_get_with_fallback; + uncore->funcs.force_wake_get = fw_domains_get_with_fallback; uncore->funcs.force_wake_put = fw_domains_put; - fw_domain_init(uncore, FW_DOMAIN_ID_RENDER, - FORCEWAKE_RENDER_GEN9, - FORCEWAKE_ACK_RENDER_GEN9); - fw_domain_init(uncore, FW_DOMAIN_ID_BLITTER, - FORCEWAKE_BLITTER_GEN9, - FORCEWAKE_ACK_BLITTER_GEN9); - fw_domain_init(uncore, FW_DOMAIN_ID_MEDIA, - FORCEWAKE_MEDIA_GEN9, FORCEWAKE_ACK_MEDIA_GEN9); + __fw_domain_init(FW_DOMAIN_ID_RENDER, + FORCEWAKE_RENDER_GEN9, + FORCEWAKE_ACK_RENDER_GEN9); + __fw_domain_init(FW_DOMAIN_ID_BLITTER, + FORCEWAKE_BLITTER_GEN9, + FORCEWAKE_ACK_BLITTER_GEN9); + __fw_domain_init(FW_DOMAIN_ID_MEDIA, + FORCEWAKE_MEDIA_GEN9, + FORCEWAKE_ACK_MEDIA_GEN9); } else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) { uncore->funcs.force_wake_get = fw_domains_get; uncore->funcs.force_wake_put = fw_domains_put; - fw_domain_init(uncore, FW_DOMAIN_ID_RENDER, - FORCEWAKE_VLV, FORCEWAKE_ACK_VLV); - fw_domain_init(uncore, FW_DOMAIN_ID_MEDIA, - FORCEWAKE_MEDIA_VLV, FORCEWAKE_ACK_MEDIA_VLV); + __fw_domain_init(FW_DOMAIN_ID_RENDER, + FORCEWAKE_VLV, FORCEWAKE_ACK_VLV); + __fw_domain_init(FW_DOMAIN_ID_MEDIA, + FORCEWAKE_MEDIA_VLV, FORCEWAKE_ACK_MEDIA_VLV); } else if (IS_HASWELL(i915) || IS_BROADWELL(i915)) { uncore->funcs.force_wake_get = fw_domains_get_with_thread_status; uncore->funcs.force_wake_put = fw_domains_put; - fw_domain_init(uncore, FW_DOMAIN_ID_RENDER, - FORCEWAKE_MT, FORCEWAKE_ACK_HSW); + __fw_domain_init(FW_DOMAIN_ID_RENDER, + FORCEWAKE_MT, FORCEWAKE_ACK_HSW); } else if (IS_IVYBRIDGE(i915)) { u32 ecobus; @@ -1430,8 +1450,8 @@ static void intel_uncore_fw_domains_init(struct intel_uncore *uncore) __raw_uncore_write32(uncore, FORCEWAKE, 0); __raw_posting_read(uncore, ECOBUS); - fw_domain_init(uncore, FW_DOMAIN_ID_RENDER, - FORCEWAKE_MT, FORCEWAKE_MT_ACK); + __fw_domain_init(FW_DOMAIN_ID_RENDER, + FORCEWAKE_MT, FORCEWAKE_MT_ACK); spin_lock_irq(&uncore->lock); fw_domains_get_with_thread_status(uncore, FORCEWAKE_RENDER); @@ -1442,19 +1462,28 @@ static void intel_uncore_fw_domains_init(struct intel_uncore *uncore) if (!(ecobus & FORCEWAKE_MT_ENABLE)) { DRM_INFO("No MT forcewake available on Ivybridge, this can result in issues\n"); DRM_INFO("when using vblank-synced partial screen updates.\n"); - fw_domain_init(uncore, FW_DOMAIN_ID_RENDER, - FORCEWAKE, FORCEWAKE_ACK); + __fw_domain_init(FW_DOMAIN_ID_RENDER, + FORCEWAKE, FORCEWAKE_ACK); } } else if (IS_GEN(i915, 6)) { uncore->funcs.force_wake_get = fw_domains_get_with_thread_status; uncore->funcs.force_wake_put = fw_domains_put; - fw_domain_init(uncore, FW_DOMAIN_ID_RENDER, - FORCEWAKE, FORCEWAKE_ACK); + __fw_domain_init(FW_DOMAIN_ID_RENDER, + FORCEWAKE, FORCEWAKE_ACK); } +#undef __fw_domain_init + /* All future platforms are expected to require complex power gating */ WARN_ON(uncore->fw_domains == 0); + + return 0; + +out_clean: + intel_uncore_fw_domains_fini(uncore); + return ret; + } #define ASSIGN_FW_DOMAINS_TABLE(uncore, d) \ @@ -1554,7 +1583,12 @@ int intel_uncore_init_mmio(struct intel_uncore *uncore) if (INTEL_GEN(i915) > 5 && !intel_vgpu_active(i915)) uncore->flags |= UNCORE_HAS_FORCEWAKE; - intel_uncore_fw_domains_init(uncore); + ret = intel_uncore_fw_domains_init(uncore); + if (ret) { + uncore_mmio_cleanup(uncore); + return ret; + } + __intel_uncore_early_sanitize(uncore, 0); uncore->unclaimed_mmio_check = 1; @@ -1662,6 +1696,7 @@ void intel_uncore_fini_mmio(struct intel_uncore *uncore) iosf_mbi_unregister_pmic_bus_access_notifier_unlocked( &uncore->pmic_bus_access_nb); intel_uncore_forcewake_reset(uncore); + intel_uncore_fw_domains_fini(uncore); iosf_mbi_punit_release(); uncore_mmio_cleanup(uncore); } diff --git a/drivers/gpu/drm/i915/intel_uncore.h b/drivers/gpu/drm/i915/intel_uncore.h index bf06b6b16892..2bb80962e7c5 100644 --- a/drivers/gpu/drm/i915/intel_uncore.h +++ b/drivers/gpu/drm/i915/intel_uncore.h @@ -125,6 +125,7 @@ struct intel_uncore { enum forcewake_domains fw_domains_saved; /* user domains saved for S3 */ struct intel_uncore_forcewake_domain { + struct intel_uncore *uncore; enum forcewake_domain_id id; enum forcewake_domains mask; unsigned int wake_count; @@ -132,7 +133,7 @@ struct intel_uncore { struct hrtimer timer; u32 __iomem *reg_set; u32 __iomem *reg_ack; - } fw_domain[FW_DOMAIN_ID_COUNT]; + } *fw_domain[FW_DOMAIN_ID_COUNT]; struct { unsigned int count; @@ -146,18 +147,12 @@ struct intel_uncore { /* Iterate over initialised fw domains */ #define for_each_fw_domain_masked(domain__, mask__, uncore__, tmp__) \ - for (tmp__ = (mask__); \ - tmp__ ? (domain__ = &(uncore__)->fw_domain[__mask_next_bit(tmp__)]), 1 : 0;) + for (tmp__ = (mask__); tmp__ ;) \ + for_each_if(domain__ = (uncore__)->fw_domain[__mask_next_bit(tmp__)]) #define for_each_fw_domain(domain__, uncore__, tmp__) \ for_each_fw_domain_masked(domain__, (uncore__)->fw_domains, uncore__, tmp__) -static inline struct intel_uncore * -forcewake_domain_to_uncore(const struct intel_uncore_forcewake_domain *d) -{ - return container_of(d, struct intel_uncore, fw_domain[d->id]); -} - static inline bool intel_uncore_has_forcewake(const struct intel_uncore *uncore) { From patchwork Thu Jun 6 21:52:13 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniele Ceraolo Spurio X-Patchwork-Id: 10980505 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id CEFFD14B6 for ; Thu, 6 Jun 2019 21:52:49 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id BE76128AD7 for ; Thu, 6 Jun 2019 21:52:49 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id B30CD28ADA; Thu, 6 Jun 2019 21:52:49 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 5CABD28AD7 for ; Thu, 6 Jun 2019 21:52:49 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id E52AE899D6; Thu, 6 Jun 2019 21:52:47 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by gabe.freedesktop.org (Postfix) with ESMTPS id E3CEC899D4 for ; Thu, 6 Jun 2019 21:52:45 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga105.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 06 Jun 2019 14:52:45 -0700 X-ExtLoop1: 1 Received: from dceraolo-linux.fm.intel.com ([10.1.27.145]) by orsmga002.jf.intel.com with ESMTP; 06 Jun 2019 14:52:45 -0700 From: Daniele Ceraolo Spurio To: intel-gfx@lists.freedesktop.org Date: Thu, 6 Jun 2019 14:52:13 -0700 Message-Id: <20190606215218.34486-5-daniele.ceraolospurio@intel.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190606215218.34486-1-daniele.ceraolospurio@intel.com> References: <20190606215218.34486-1-daniele.ceraolospurio@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [RFC 4/8] drm/i915: explicitly prune forcewake domain X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP When we know which engines we're fusing off we can immediately remove the corresponding forcewake domain, no need to go though the masks again. Signed-off-by: Daniele Ceraolo Spurio --- drivers/gpu/drm/i915/i915_drv.c | 2 -- drivers/gpu/drm/i915/intel_device_info.c | 4 +++ drivers/gpu/drm/i915/intel_uncore.c | 32 ++++-------------------- drivers/gpu/drm/i915/intel_uncore.h | 3 ++- 4 files changed, 11 insertions(+), 30 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index 05ee328e3f66..9094736af5da 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -995,8 +995,6 @@ static int i915_driver_init_mmio(struct drm_i915_private *dev_priv) intel_device_info_init_mmio(dev_priv); - intel_uncore_prune_mmio_domains(&dev_priv->uncore); - intel_uc_init_mmio(dev_priv); ret = intel_engines_init_mmio(dev_priv); diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c index 97f742530fa1..48d159d9e42a 100644 --- a/drivers/gpu/drm/i915/intel_device_info.c +++ b/drivers/gpu/drm/i915/intel_device_info.c @@ -1027,6 +1027,8 @@ void intel_device_info_init_mmio(struct drm_i915_private *dev_priv) if (!(BIT(i) & vdbox_mask)) { info->engine_mask &= ~BIT(_VCS(i)); + intel_uncore_fw_domain_prune(&dev_priv->uncore, + FW_DOMAIN_ID_MEDIA_VDBOX0 + i); DRM_DEBUG_DRIVER("vcs%u fused off\n", i); continue; } @@ -1048,6 +1050,8 @@ void intel_device_info_init_mmio(struct drm_i915_private *dev_priv) if (!(BIT(i) & vebox_mask)) { info->engine_mask &= ~BIT(_VECS(i)); + intel_uncore_fw_domain_prune(&dev_priv->uncore, + FW_DOMAIN_ID_MEDIA_VEBOX0 + i); DRM_DEBUG_DRIVER("vecs%u fused off\n", i); } } diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c index 30650e6e2f54..7ebea00207a6 100644 --- a/drivers/gpu/drm/i915/intel_uncore.c +++ b/drivers/gpu/drm/i915/intel_uncore.c @@ -1659,35 +1659,13 @@ int intel_uncore_init_mmio(struct intel_uncore *uncore) * the forcewake domains. Prune them, to make sure they only reference existing * engines. */ -void intel_uncore_prune_mmio_domains(struct intel_uncore *uncore) +void intel_uncore_fw_domain_prune(struct intel_uncore *uncore, + enum forcewake_domain_id domain_id) { - struct drm_i915_private *i915 = uncore_to_i915(uncore); - - if (INTEL_GEN(i915) >= 11) { - enum forcewake_domains fw_domains = uncore->fw_domains; - enum forcewake_domain_id domain_id; - int i; - - for (i = 0; i < I915_MAX_VCS; i++) { - domain_id = FW_DOMAIN_ID_MEDIA_VDBOX0 + i; - - if (HAS_ENGINE(i915, _VCS(i))) - continue; - - if (fw_domains & BIT(domain_id)) - fw_domain_fini(uncore, domain_id); - } - - for (i = 0; i < I915_MAX_VECS; i++) { - domain_id = FW_DOMAIN_ID_MEDIA_VEBOX0 + i; - - if (HAS_ENGINE(i915, _VECS(i))) - continue; + if (WARN_ON(!(uncore->fw_domains & BIT(domain_id)))) + return; - if (fw_domains & BIT(domain_id)) - fw_domain_fini(uncore, domain_id); - } - } + fw_domain_fini(uncore, domain_id); } void intel_uncore_fini_mmio(struct intel_uncore *uncore) diff --git a/drivers/gpu/drm/i915/intel_uncore.h b/drivers/gpu/drm/i915/intel_uncore.h index 2bb80962e7c5..b2de47da053f 100644 --- a/drivers/gpu/drm/i915/intel_uncore.h +++ b/drivers/gpu/drm/i915/intel_uncore.h @@ -179,7 +179,8 @@ intel_uncore_has_fifo(const struct intel_uncore *uncore) void intel_uncore_init_early(struct intel_uncore *uncore); int intel_uncore_init_mmio(struct intel_uncore *uncore); -void intel_uncore_prune_mmio_domains(struct intel_uncore *uncore); +void intel_uncore_fw_domain_prune(struct intel_uncore *uncore, + enum forcewake_domain_id domain_id); bool intel_uncore_unclaimed_mmio(struct intel_uncore *uncore); bool intel_uncore_arm_unclaimed_mmio_detection(struct intel_uncore *uncore); void intel_uncore_fini_mmio(struct intel_uncore *uncore); From patchwork Thu Jun 6 21:52:14 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniele Ceraolo Spurio X-Patchwork-Id: 10980503 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id F010F14C0 for ; Thu, 6 Jun 2019 21:52:48 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id E023528AD7 for ; Thu, 6 Jun 2019 21:52:48 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id D4B8B28ADA; Thu, 6 Jun 2019 21:52:48 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 4394A28AD7 for ; Thu, 6 Jun 2019 21:52:48 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 55A31899D5; Thu, 6 Jun 2019 21:52:47 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by gabe.freedesktop.org (Postfix) with ESMTPS id B6762899D4 for ; Thu, 6 Jun 2019 21:52:46 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga105.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 06 Jun 2019 14:52:46 -0700 X-ExtLoop1: 1 Received: from dceraolo-linux.fm.intel.com ([10.1.27.145]) by orsmga002.jf.intel.com with ESMTP; 06 Jun 2019 14:52:46 -0700 From: Daniele Ceraolo Spurio To: intel-gfx@lists.freedesktop.org Date: Thu, 6 Jun 2019 14:52:14 -0700 Message-Id: <20190606215218.34486-6-daniele.ceraolospurio@intel.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190606215218.34486-1-daniele.ceraolospurio@intel.com> References: <20190606215218.34486-1-daniele.ceraolospurio@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [RFC 5/8] drm/i915: split out uncore_mmio_debug X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP Multiple uncore structures will share the debug infrastructure, so move it to a common place and add extra locking around it. Signed-off-by: Daniele Ceraolo Spurio --- drivers/gpu/drm/i915/i915_drv.c | 1 + drivers/gpu/drm/i915/i915_drv.h | 1 + drivers/gpu/drm/i915/intel_uncore.c | 66 ++++++++++++++++++++--------- drivers/gpu/drm/i915/intel_uncore.h | 10 ++++- 4 files changed, 58 insertions(+), 20 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index 9094736af5da..8fdd668eb7c7 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -897,6 +897,7 @@ static int i915_driver_init_early(struct drm_i915_private *dev_priv) spin_lock_init(&dev_priv->irq_lock); spin_lock_init(&dev_priv->gpu_error.lock); + spin_lock_init(&dev_priv->mmio_debug.lock); mutex_init(&dev_priv->backlight_lock); mutex_init(&dev_priv->sb_lock); diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index a0539b837df5..5522132a2ad2 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1398,6 +1398,7 @@ struct drm_i915_private { resource_size_t stolen_usable_size; /* Total size minus reserved ranges */ struct intel_uncore uncore; + struct intel_uncore_mmio_debug mmio_debug; struct i915_virtual_gpu vgpu; diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c index 7ebea00207a6..8e42476ea4a7 100644 --- a/drivers/gpu/drm/i915/intel_uncore.c +++ b/drivers/gpu/drm/i915/intel_uncore.c @@ -34,6 +34,13 @@ #define __raw_posting_read(...) ((void)__raw_uncore_read32(__VA_ARGS__)) +void +intel_uncore_mmio_debug_init_early(struct intel_uncore_mmio_debug *mmio_debug) +{ + spin_lock_init(&mmio_debug->lock); + mmio_debug->unclaimed_mmio_check = 1; +} + static const char * const forcewake_domain_names[] = { "render", "blitter", @@ -473,6 +480,8 @@ check_for_unclaimed_mmio(struct intel_uncore *uncore) { bool ret = false; + lockdep_assert_held(&uncore->debug->lock); + if (intel_uncore_has_fpga_dbg_unclaimed(uncore)) ret |= fpga_check_for_unclaimed_mmio(uncore); @@ -489,7 +498,7 @@ static void __intel_uncore_early_sanitize(struct intel_uncore *uncore, unsigned int restore_forcewake) { /* clear out unclaimed reg detection bit */ - if (check_for_unclaimed_mmio(uncore)) + if (intel_uncore_unclaimed_mmio(uncore)) DRM_DEBUG("unclaimed mmio detected on uncore init, clearing\n"); /* WaDisableShadowRegForCpd:chv */ @@ -595,18 +604,20 @@ void intel_uncore_forcewake_get(struct intel_uncore *uncore, void intel_uncore_forcewake_user_get(struct intel_uncore *uncore) { spin_lock_irq(&uncore->lock); + spin_lock_irq(&uncore->debug->lock); if (!uncore->user_forcewake.count++) { intel_uncore_forcewake_get__locked(uncore, FORCEWAKE_ALL); /* Save and disable mmio debugging for the user bypass */ uncore->user_forcewake.saved_mmio_check = - uncore->unclaimed_mmio_check; + uncore->debug->unclaimed_mmio_check; uncore->user_forcewake.saved_mmio_debug = i915_modparams.mmio_debug; - uncore->unclaimed_mmio_check = 0; + uncore->debug->unclaimed_mmio_check = 0; i915_modparams.mmio_debug = 0; } + spin_unlock_irq(&uncore->debug->lock); spin_unlock_irq(&uncore->lock); } @@ -620,18 +631,20 @@ void intel_uncore_forcewake_user_get(struct intel_uncore *uncore) void intel_uncore_forcewake_user_put(struct intel_uncore *uncore) { spin_lock_irq(&uncore->lock); + spin_lock_irq(&uncore->debug->lock); if (!--uncore->user_forcewake.count) { - if (intel_uncore_unclaimed_mmio(uncore)) + if (check_for_unclaimed_mmio(uncore)) dev_info(uncore_to_i915(uncore)->drm.dev, "Invalid mmio detected during user access\n"); - uncore->unclaimed_mmio_check = + uncore->debug->unclaimed_mmio_check = uncore->user_forcewake.saved_mmio_check; i915_modparams.mmio_debug = uncore->user_forcewake.saved_mmio_debug; intel_uncore_forcewake_put__locked(uncore, FORCEWAKE_ALL); } + spin_unlock_irq(&uncore->debug->lock); spin_unlock_irq(&uncore->lock); } @@ -1044,12 +1057,19 @@ static inline void unclaimed_reg_debug(struct intel_uncore *uncore, const i915_reg_t reg, const bool read, - const bool before) + const bool before, + unsigned long *irqflags) { if (likely(!i915_modparams.mmio_debug)) return; + if (before) + spin_lock_irqsave(&uncore->debug->lock, *irqflags); + __unclaimed_reg_debug(uncore, reg, read, before); + + if (!before) + spin_unlock_irqrestore(&uncore->debug->lock, *irqflags); } #define GEN2_READ_HEADER(x) \ @@ -1095,13 +1115,14 @@ __gen2_read(64) #define GEN6_READ_HEADER(x) \ u32 offset = i915_mmio_reg_offset(reg); \ unsigned long irqflags; \ + unsigned long debug_irqflags; \ u##x val = 0; \ __assert_rpm_wakelock_held(uncore->rpm); \ spin_lock_irqsave(&uncore->lock, irqflags); \ - unclaimed_reg_debug(uncore, reg, true, true) + unclaimed_reg_debug(uncore, reg, true, true, &debug_irqflags) #define GEN6_READ_FOOTER \ - unclaimed_reg_debug(uncore, reg, true, false); \ + unclaimed_reg_debug(uncore, reg, true, false, &debug_irqflags); \ spin_unlock_irqrestore(&uncore->lock, irqflags); \ trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \ return val @@ -1204,13 +1225,14 @@ __gen2_write(32) #define GEN6_WRITE_HEADER \ u32 offset = i915_mmio_reg_offset(reg); \ unsigned long irqflags; \ + unsigned long debug_irqflags; \ trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \ __assert_rpm_wakelock_held(uncore->rpm); \ spin_lock_irqsave(&uncore->lock, irqflags); \ - unclaimed_reg_debug(uncore, reg, false, true) + unclaimed_reg_debug(uncore, reg, false, true, &debug_irqflags) #define GEN6_WRITE_FOOTER \ - unclaimed_reg_debug(uncore, reg, false, false); \ + unclaimed_reg_debug(uncore, reg, false, false, &debug_irqflags); \ spin_unlock_irqrestore(&uncore->lock, irqflags) #define __gen6_write(x) \ @@ -1574,6 +1596,9 @@ int intel_uncore_init_mmio(struct intel_uncore *uncore) struct drm_i915_private *i915 = uncore_to_i915(uncore); int ret; + uncore->rpm = &i915->runtime_pm; + uncore->debug = &i915->mmio_debug; + ret = uncore_mmio_setup(uncore); if (ret) return ret; @@ -1591,12 +1616,9 @@ int intel_uncore_init_mmio(struct intel_uncore *uncore) __intel_uncore_early_sanitize(uncore, 0); - uncore->unclaimed_mmio_check = 1; uncore->pmic_bus_access_nb.notifier_call = i915_pmic_bus_access_notifier; - uncore->rpm = &i915->runtime_pm; - if (!intel_uncore_has_forcewake(uncore)) { if (IS_GEN(i915, 5)) { ASSIGN_WRITE_MMIO_VFUNCS_NO_FW(uncore, gen5); @@ -1858,7 +1880,13 @@ int __intel_wait_for_register(struct intel_uncore *uncore, bool intel_uncore_unclaimed_mmio(struct intel_uncore *uncore) { - return check_for_unclaimed_mmio(uncore); + bool ret; + + spin_lock_irq(&uncore->debug->lock); + ret = check_for_unclaimed_mmio(uncore); + spin_unlock_irq(&uncore->debug->lock); + + return ret; } bool @@ -1866,24 +1894,24 @@ intel_uncore_arm_unclaimed_mmio_detection(struct intel_uncore *uncore) { bool ret = false; - spin_lock_irq(&uncore->lock); + spin_lock_irq(&uncore->debug->lock); - if (unlikely(uncore->unclaimed_mmio_check <= 0)) + if (unlikely(uncore->debug->unclaimed_mmio_check <= 0)) goto out; - if (unlikely(intel_uncore_unclaimed_mmio(uncore))) { + if (unlikely(check_for_unclaimed_mmio(uncore))) { if (!i915_modparams.mmio_debug) { DRM_DEBUG("Unclaimed register detected, " "enabling oneshot unclaimed register reporting. " "Please use i915.mmio_debug=N for more information.\n"); i915_modparams.mmio_debug++; } - uncore->unclaimed_mmio_check--; + uncore->debug->unclaimed_mmio_check--; ret = true; } out: - spin_unlock_irq(&uncore->lock); + spin_unlock_irq(&uncore->debug->lock); return ret; } diff --git a/drivers/gpu/drm/i915/intel_uncore.h b/drivers/gpu/drm/i915/intel_uncore.h index b2de47da053f..53c1a334e2ae 100644 --- a/drivers/gpu/drm/i915/intel_uncore.h +++ b/drivers/gpu/drm/i915/intel_uncore.h @@ -36,6 +36,11 @@ struct drm_i915_private; struct i915_runtime_pm; struct intel_uncore; +struct intel_uncore_mmio_debug { + spinlock_t lock; /** lock is also taken in irq contexts. */ + int unclaimed_mmio_check; +}; + enum forcewake_domain_id { FW_DOMAIN_ID_RENDER = 0, FW_DOMAIN_ID_BLITTER, @@ -142,7 +147,7 @@ struct intel_uncore { int saved_mmio_debug; } user_forcewake; - int unclaimed_mmio_check; + struct intel_uncore_mmio_debug *debug; }; /* Iterate over initialised fw domains */ @@ -177,6 +182,9 @@ intel_uncore_has_fifo(const struct intel_uncore *uncore) return uncore->flags & UNCORE_HAS_FIFO; } +void +intel_uncore_mmio_debug_init_early(struct intel_uncore_mmio_debug *mmio_debug); + void intel_uncore_init_early(struct intel_uncore *uncore); int intel_uncore_init_mmio(struct intel_uncore *uncore); void intel_uncore_fw_domain_prune(struct intel_uncore *uncore, From patchwork Thu Jun 6 21:52:15 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniele Ceraolo Spurio X-Patchwork-Id: 10980509 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id DD32414C0 for ; Thu, 6 Jun 2019 21:52:51 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id CB5C428AD7 for ; Thu, 6 Jun 2019 21:52:51 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id BFC6B28ADA; Thu, 6 Jun 2019 21:52:51 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 38E4F28AD7 for ; Thu, 6 Jun 2019 21:52:51 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 93289899D4; Thu, 6 Jun 2019 21:52:50 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by gabe.freedesktop.org (Postfix) with ESMTPS id 809CE899D4 for ; Thu, 6 Jun 2019 21:52:47 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga105.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 06 Jun 2019 14:52:47 -0700 X-ExtLoop1: 1 Received: from dceraolo-linux.fm.intel.com ([10.1.27.145]) by orsmga002.jf.intel.com with ESMTP; 06 Jun 2019 14:52:47 -0700 From: Daniele Ceraolo Spurio To: intel-gfx@lists.freedesktop.org Date: Thu, 6 Jun 2019 14:52:15 -0700 Message-Id: <20190606215218.34486-7-daniele.ceraolospurio@intel.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190606215218.34486-1-daniele.ceraolospurio@intel.com> References: <20190606215218.34486-1-daniele.ceraolospurio@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [RFC 6/8] drm/i915: drop forcewake_user_get/put X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP Now that we've split out the mmio_debug, we can manipulate that independently from the debugfs and just call the normal forcewake get/put functions. Signed-off-by: Daniele Ceraolo Spurio --- drivers/gpu/drm/i915/i915_debugfs.c | 19 +++++-- drivers/gpu/drm/i915/i915_drv.c | 2 +- drivers/gpu/drm/i915/i915_drv.h | 1 + drivers/gpu/drm/i915/intel_uncore.c | 80 +++++++++-------------------- drivers/gpu/drm/i915/intel_uncore.h | 14 ++--- 5 files changed, 45 insertions(+), 71 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index f212241a2758..7e69829008e6 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -1391,7 +1391,7 @@ static int i915_forcewake_domains(struct seq_file *m, void *data) unsigned int tmp; seq_printf(m, "user.bypass_count = %u\n", - uncore->user_forcewake.count); + atomic_read(&i915->user_forcewake_count)); for_each_fw_domain(fw_domain, uncore, tmp) seq_printf(m, "%s.wake_count = %u\n", @@ -4219,7 +4219,11 @@ static int i915_forcewake_open(struct inode *inode, struct file *file) return 0; file->private_data = (void *)(uintptr_t)intel_runtime_pm_get(i915); - intel_uncore_forcewake_user_get(&i915->uncore); + + if (atomic_inc_return(&i915->user_forcewake_count) == 1) { + intel_uncore_forcewake_get(&i915->uncore, FORCEWAKE_ALL); + intel_uncore_mmio_debug_suspend(&i915->mmio_debug); + } return 0; } @@ -4231,9 +4235,14 @@ static int i915_forcewake_release(struct inode *inode, struct file *file) if (INTEL_GEN(i915) < 6) return 0; - intel_uncore_forcewake_user_put(&i915->uncore); - intel_runtime_pm_put(i915, - (intel_wakeref_t)(uintptr_t)file->private_data); + if (atomic_dec_and_test(&i915->user_forcewake_count)) { + if (intel_uncore_unclaimed_mmio(&i915->uncore)) + dev_info(i915->drm.dev, + "Invalid mmio detected during user access\n"); + + intel_uncore_mmio_debug_resume(&i915->mmio_debug); + intel_uncore_forcewake_put(&i915->uncore, FORCEWAKE_ALL); + } return 0; } diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index 8fdd668eb7c7..024f270f6f00 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -2187,7 +2187,7 @@ static int i915_drm_suspend_late(struct drm_device *dev, bool hibernation) out: enable_rpm_wakeref_asserts(dev_priv); - if (!dev_priv->uncore.user_forcewake.count) + if (!atomic_read(&dev_priv->user_forcewake_count)) intel_runtime_pm_cleanup(dev_priv); return ret; diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 5522132a2ad2..dc6b3e4af575 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1399,6 +1399,7 @@ struct drm_i915_private { struct intel_uncore uncore; struct intel_uncore_mmio_debug mmio_debug; + atomic_t user_forcewake_count; struct i915_virtual_gpu vgpu; diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c index 8e42476ea4a7..c460426b0562 100644 --- a/drivers/gpu/drm/i915/intel_uncore.c +++ b/drivers/gpu/drm/i915/intel_uncore.c @@ -41,6 +41,28 @@ intel_uncore_mmio_debug_init_early(struct intel_uncore_mmio_debug *mmio_debug) mmio_debug->unclaimed_mmio_check = 1; } +/* Save and disable mmio debugging for the user bypass */ +void intel_uncore_mmio_debug_suspend(struct intel_uncore_mmio_debug *mmio_debug) +{ + spin_lock_irq(&mmio_debug->lock); + if (!mmio_debug->suspended) { + mmio_debug->saved_mmio_check = mmio_debug->unclaimed_mmio_check; + mmio_debug->unclaimed_mmio_check = 0; + mmio_debug->suspended = true; + } + spin_unlock_irq(&mmio_debug->lock); +} + +void intel_uncore_mmio_debug_resume(struct intel_uncore_mmio_debug *mmio_debug) +{ + spin_lock_irq(&mmio_debug->lock); + if (mmio_debug->suspended) { + mmio_debug->unclaimed_mmio_check = mmio_debug->saved_mmio_check; + mmio_debug->suspended = false; + } + spin_unlock_irq(&mmio_debug->lock); +} + static const char * const forcewake_domain_names[] = { "render", "blitter", @@ -482,6 +504,9 @@ check_for_unclaimed_mmio(struct intel_uncore *uncore) lockdep_assert_held(&uncore->debug->lock); + if (uncore->debug->suspended) + return false; + if (intel_uncore_has_fpga_dbg_unclaimed(uncore)) ret |= fpga_check_for_unclaimed_mmio(uncore); @@ -593,61 +618,6 @@ void intel_uncore_forcewake_get(struct intel_uncore *uncore, spin_unlock_irqrestore(&uncore->lock, irqflags); } -/** - * intel_uncore_forcewake_user_get - claim forcewake on behalf of userspace - * @uncore: the intel_uncore structure - * - * This function is a wrapper around intel_uncore_forcewake_get() to acquire - * the GT powerwell and in the process disable our debugging for the - * duration of userspace's bypass. - */ -void intel_uncore_forcewake_user_get(struct intel_uncore *uncore) -{ - spin_lock_irq(&uncore->lock); - spin_lock_irq(&uncore->debug->lock); - if (!uncore->user_forcewake.count++) { - intel_uncore_forcewake_get__locked(uncore, FORCEWAKE_ALL); - - /* Save and disable mmio debugging for the user bypass */ - uncore->user_forcewake.saved_mmio_check = - uncore->debug->unclaimed_mmio_check; - uncore->user_forcewake.saved_mmio_debug = - i915_modparams.mmio_debug; - - uncore->debug->unclaimed_mmio_check = 0; - i915_modparams.mmio_debug = 0; - } - spin_unlock_irq(&uncore->debug->lock); - spin_unlock_irq(&uncore->lock); -} - -/** - * intel_uncore_forcewake_user_put - release forcewake on behalf of userspace - * @uncore: the intel_uncore structure - * - * This function complements intel_uncore_forcewake_user_get() and releases - * the GT powerwell taken on behalf of the userspace bypass. - */ -void intel_uncore_forcewake_user_put(struct intel_uncore *uncore) -{ - spin_lock_irq(&uncore->lock); - spin_lock_irq(&uncore->debug->lock); - if (!--uncore->user_forcewake.count) { - if (check_for_unclaimed_mmio(uncore)) - dev_info(uncore_to_i915(uncore)->drm.dev, - "Invalid mmio detected during user access\n"); - - uncore->debug->unclaimed_mmio_check = - uncore->user_forcewake.saved_mmio_check; - i915_modparams.mmio_debug = - uncore->user_forcewake.saved_mmio_debug; - - intel_uncore_forcewake_put__locked(uncore, FORCEWAKE_ALL); - } - spin_unlock_irq(&uncore->debug->lock); - spin_unlock_irq(&uncore->lock); -} - /** * intel_uncore_forcewake_get__locked - grab forcewake domain references * @uncore: the intel_uncore structure diff --git a/drivers/gpu/drm/i915/intel_uncore.h b/drivers/gpu/drm/i915/intel_uncore.h index 53c1a334e2ae..1de1e8505124 100644 --- a/drivers/gpu/drm/i915/intel_uncore.h +++ b/drivers/gpu/drm/i915/intel_uncore.h @@ -39,6 +39,8 @@ struct intel_uncore; struct intel_uncore_mmio_debug { spinlock_t lock; /** lock is also taken in irq contexts. */ int unclaimed_mmio_check; + int saved_mmio_check; + bool suspended; }; enum forcewake_domain_id { @@ -140,13 +142,6 @@ struct intel_uncore { u32 __iomem *reg_ack; } *fw_domain[FW_DOMAIN_ID_COUNT]; - struct { - unsigned int count; - - int saved_mmio_check; - int saved_mmio_debug; - } user_forcewake; - struct intel_uncore_mmio_debug *debug; }; @@ -184,6 +179,8 @@ intel_uncore_has_fifo(const struct intel_uncore *uncore) void intel_uncore_mmio_debug_init_early(struct intel_uncore_mmio_debug *mmio_debug); +void intel_uncore_mmio_debug_suspend(struct intel_uncore_mmio_debug *mmio_debug); +void intel_uncore_mmio_debug_resume(struct intel_uncore_mmio_debug *mmio_debug); void intel_uncore_init_early(struct intel_uncore *uncore); int intel_uncore_init_mmio(struct intel_uncore *uncore); @@ -219,9 +216,6 @@ void intel_uncore_forcewake_get__locked(struct intel_uncore *uncore, void intel_uncore_forcewake_put__locked(struct intel_uncore *uncore, enum forcewake_domains domains); -void intel_uncore_forcewake_user_get(struct intel_uncore *uncore); -void intel_uncore_forcewake_user_put(struct intel_uncore *uncore); - int __intel_wait_for_register(struct intel_uncore *uncore, i915_reg_t reg, u32 mask, From patchwork Thu Jun 6 21:52:16 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniele Ceraolo Spurio X-Patchwork-Id: 10980507 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id CFCC514C0 for ; Thu, 6 Jun 2019 21:52:50 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id BF71328AD7 for ; Thu, 6 Jun 2019 21:52:50 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id B3C0F28ADA; Thu, 6 Jun 2019 21:52:50 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 3818228AD7 for ; Thu, 6 Jun 2019 21:52:50 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 6CC03899DC; Thu, 6 Jun 2019 21:52:49 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by gabe.freedesktop.org (Postfix) with ESMTPS id 5AEEC899D4 for ; Thu, 6 Jun 2019 21:52:48 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga105.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 06 Jun 2019 14:52:48 -0700 X-ExtLoop1: 1 Received: from dceraolo-linux.fm.intel.com ([10.1.27.145]) by orsmga002.jf.intel.com with ESMTP; 06 Jun 2019 14:52:48 -0700 From: Daniele Ceraolo Spurio To: intel-gfx@lists.freedesktop.org Date: Thu, 6 Jun 2019 14:52:16 -0700 Message-Id: <20190606215218.34486-8-daniele.ceraolospurio@intel.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190606215218.34486-1-daniele.ceraolospurio@intel.com> References: <20190606215218.34486-1-daniele.ceraolospurio@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [RFC 7/8] drm/i915: introduce display_uncore X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP A forcewake-less uncore to be used to decouple GT accesses from display ones to avoid serializing them when there is no need. All the uncore suspend/resume functions are forcewake-related, so no need to call them for display_uncore. Signed-off-by: Daniele Ceraolo Spurio --- drivers/gpu/drm/i915/i915_drv.c | 14 +++++++++++--- drivers/gpu/drm/i915/i915_drv.h | 6 +++++- drivers/gpu/drm/i915/intel_uncore.c | 23 +++++++++++++++++------ drivers/gpu/drm/i915/intel_uncore.h | 9 ++++++++- 4 files changed, 41 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index 024f270f6f00..635024cad005 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -893,7 +893,8 @@ static int i915_driver_init_early(struct drm_i915_private *dev_priv) intel_device_info_subplatform_init(dev_priv); - intel_uncore_init_early(&dev_priv->uncore); + intel_uncore_init_early(&dev_priv->uncore, 0); + intel_uncore_init_early(&dev_priv->de_uncore, UNCORE_IS_DISPLAY); spin_lock_init(&dev_priv->irq_lock); spin_lock_init(&dev_priv->gpu_error.lock); @@ -991,6 +992,10 @@ static int i915_driver_init_mmio(struct drm_i915_private *dev_priv) if (ret < 0) goto err_bridge; + ret = intel_uncore_init_mmio(&dev_priv->de_uncore); + if (ret < 0) + goto err_uncore; + /* Try to make sure MCHBAR is enabled before poking at it */ intel_setup_mchbar(dev_priv); @@ -1000,14 +1005,16 @@ static int i915_driver_init_mmio(struct drm_i915_private *dev_priv) ret = intel_engines_init_mmio(dev_priv); if (ret) - goto err_uncore; + goto err_mchbar; i915_gem_init_mmio(dev_priv); return 0; -err_uncore: +err_mchbar: intel_teardown_mchbar(dev_priv); + intel_uncore_fini_mmio(&dev_priv->de_uncore); +err_uncore: intel_uncore_fini_mmio(&dev_priv->uncore); err_bridge: pci_dev_put(dev_priv->bridge_dev); @@ -1022,6 +1029,7 @@ static int i915_driver_init_mmio(struct drm_i915_private *dev_priv) static void i915_driver_cleanup_mmio(struct drm_i915_private *dev_priv) { intel_teardown_mchbar(dev_priv); + intel_uncore_fini_mmio(&dev_priv->de_uncore); intel_uncore_fini_mmio(&dev_priv->uncore); pci_dev_put(dev_priv->bridge_dev); } diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index dc6b3e4af575..87dcc7addc53 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1398,6 +1398,7 @@ struct drm_i915_private { resource_size_t stolen_usable_size; /* Total size minus reserved ranges */ struct intel_uncore uncore; + struct intel_uncore de_uncore; struct intel_uncore_mmio_debug mmio_debug; atomic_t user_forcewake_count; @@ -2013,7 +2014,10 @@ static inline struct drm_i915_private *huc_to_i915(struct intel_huc *huc) static inline struct drm_i915_private *uncore_to_i915(struct intel_uncore *uncore) { - return container_of(uncore, struct drm_i915_private, uncore); + if (intel_uncore_is_display(uncore)) + return container_of(uncore, struct drm_i915_private, de_uncore); + else + return container_of(uncore, struct drm_i915_private, uncore); } /* Simple iterator over all initialised engines */ diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c index c460426b0562..64479a746f56 100644 --- a/drivers/gpu/drm/i915/intel_uncore.c +++ b/drivers/gpu/drm/i915/intel_uncore.c @@ -549,6 +549,9 @@ static void __intel_uncore_early_sanitize(struct intel_uncore *uncore, void intel_uncore_suspend(struct intel_uncore *uncore) { + if (!intel_uncore_is_display(uncore)) + return; + iosf_mbi_punit_acquire(); iosf_mbi_unregister_pmic_bus_access_notifier_unlocked( &uncore->pmic_bus_access_nb); @@ -560,6 +563,9 @@ void intel_uncore_resume_early(struct intel_uncore *uncore) { unsigned int restore_forcewake; + if (!intel_uncore_is_display(uncore)) + return; + restore_forcewake = fetch_and_zero(&uncore->fw_domains_saved); __intel_uncore_early_sanitize(uncore, restore_forcewake); @@ -568,6 +574,9 @@ void intel_uncore_resume_early(struct intel_uncore *uncore) void intel_uncore_runtime_resume(struct intel_uncore *uncore) { + if (!intel_uncore_is_display(uncore)) + return; + iosf_mbi_register_pmic_bus_access_notifier(&uncore->pmic_bus_access_nb); } @@ -1556,9 +1565,10 @@ static void uncore_mmio_cleanup(struct intel_uncore *uncore) pci_iounmap(pdev, uncore->regs); } -void intel_uncore_init_early(struct intel_uncore *uncore) +void intel_uncore_init_early(struct intel_uncore *uncore, u32 flags) { spin_lock_init(&uncore->lock); + uncore->flags = flags; } int intel_uncore_init_mmio(struct intel_uncore *uncore) @@ -1575,7 +1585,8 @@ int intel_uncore_init_mmio(struct intel_uncore *uncore) i915_check_vgpu(i915); - if (INTEL_GEN(i915) > 5 && !intel_vgpu_active(i915)) + if (INTEL_GEN(i915) > 5 && !intel_vgpu_active(i915) && + !intel_uncore_is_display(uncore)) uncore->flags |= UNCORE_HAS_FORCEWAKE; ret = intel_uncore_fw_domains_init(uncore); @@ -1586,9 +1597,6 @@ int intel_uncore_init_mmio(struct intel_uncore *uncore) __intel_uncore_early_sanitize(uncore, 0); - uncore->pmic_bus_access_nb.notifier_call = - i915_pmic_bus_access_notifier; - if (!intel_uncore_has_forcewake(uncore)) { if (IS_GEN(i915, 5)) { ASSIGN_WRITE_MMIO_VFUNCS_NO_FW(uncore, gen5); @@ -1641,7 +1649,10 @@ int intel_uncore_init_mmio(struct intel_uncore *uncore) if (IS_GEN_RANGE(i915, 6, 7)) uncore->flags |= UNCORE_HAS_FIFO; - iosf_mbi_register_pmic_bus_access_notifier(&uncore->pmic_bus_access_nb); + if (intel_uncore_has_forcewake(uncore)) { + uncore->pmic_bus_access_nb.notifier_call = i915_pmic_bus_access_notifier; + iosf_mbi_register_pmic_bus_access_notifier(&uncore->pmic_bus_access_nb); + } return 0; } diff --git a/drivers/gpu/drm/i915/intel_uncore.h b/drivers/gpu/drm/i915/intel_uncore.h index 1de1e8505124..07e79cb6c756 100644 --- a/drivers/gpu/drm/i915/intel_uncore.h +++ b/drivers/gpu/drm/i915/intel_uncore.h @@ -118,6 +118,7 @@ struct intel_uncore { #define UNCORE_HAS_FPGA_DBG_UNCLAIMED BIT(1) #define UNCORE_HAS_DBG_UNCLAIMED BIT(2) #define UNCORE_HAS_FIFO BIT(3) +#define UNCORE_IS_DISPLAY BIT(4) const struct intel_forcewake_range *fw_domains_table; unsigned int fw_domains_table_entries; @@ -177,12 +178,18 @@ intel_uncore_has_fifo(const struct intel_uncore *uncore) return uncore->flags & UNCORE_HAS_FIFO; } +static inline bool +intel_uncore_is_display(const struct intel_uncore *uncore) +{ + return uncore->flags & UNCORE_IS_DISPLAY; +} + void intel_uncore_mmio_debug_init_early(struct intel_uncore_mmio_debug *mmio_debug); void intel_uncore_mmio_debug_suspend(struct intel_uncore_mmio_debug *mmio_debug); void intel_uncore_mmio_debug_resume(struct intel_uncore_mmio_debug *mmio_debug); -void intel_uncore_init_early(struct intel_uncore *uncore); +void intel_uncore_init_early(struct intel_uncore *uncore, u32 flags); int intel_uncore_init_mmio(struct intel_uncore *uncore); void intel_uncore_fw_domain_prune(struct intel_uncore *uncore, enum forcewake_domain_id domain_id); From patchwork Thu Jun 6 21:52:17 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniele Ceraolo Spurio X-Patchwork-Id: 10980511 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id DE19714B6 for ; Thu, 6 Jun 2019 21:52:54 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id CAE3328AD7 for ; Thu, 6 Jun 2019 21:52:54 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id BEB5C28ADA; Thu, 6 Jun 2019 21:52:54 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 4945D28AD7 for ; Thu, 6 Jun 2019 21:52:53 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id A09EE899E8; Thu, 6 Jun 2019 21:52:52 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by gabe.freedesktop.org (Postfix) with ESMTPS id 6A44A899D4 for ; Thu, 6 Jun 2019 21:52:49 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga105.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 06 Jun 2019 14:52:49 -0700 X-ExtLoop1: 1 Received: from dceraolo-linux.fm.intel.com ([10.1.27.145]) by orsmga002.jf.intel.com with ESMTP; 06 Jun 2019 14:52:49 -0700 From: Daniele Ceraolo Spurio To: intel-gfx@lists.freedesktop.org Date: Thu, 6 Jun 2019 14:52:17 -0700 Message-Id: <20190606215218.34486-9-daniele.ceraolospurio@intel.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190606215218.34486-1-daniele.ceraolospurio@intel.com> References: <20190606215218.34486-1-daniele.ceraolospurio@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [RFC 8/8] drm/i915: move intel_hdmi to de_uncore X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP As an example of usage of the new structure Signed-off-by: Daniele Ceraolo Spurio --- drivers/gpu/drm/i915/intel_hdmi.c | 275 ++++++++++++++++-------------- 1 file changed, 151 insertions(+), 124 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c index 097bfa504ece..2d0a551a4c0b 100644 --- a/drivers/gpu/drm/i915/intel_hdmi.c +++ b/drivers/gpu/drm/i915/intel_hdmi.c @@ -72,7 +72,8 @@ assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi) enabled_bits = HAS_DDI(dev_priv) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE; - WARN(I915_READ(intel_hdmi->hdmi_reg) & enabled_bits, + WARN(intel_uncore_read(&dev_priv->de_uncore, intel_hdmi->hdmi_reg) & + enabled_bits, "HDMI port enabled, expecting disabled\n"); } @@ -80,7 +81,8 @@ static void assert_hdmi_transcoder_func_disabled(struct drm_i915_private *dev_priv, enum transcoder cpu_transcoder) { - WARN(I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)) & + WARN(intel_uncore_read(&dev_priv->de_uncore, + TRANS_DDI_FUNC_CTL(cpu_transcoder)) & TRANS_DDI_FUNC_ENABLE, "HDMI transcoder function enabled, expecting disabled\n"); } @@ -208,7 +210,8 @@ static void g4x_write_infoframe(struct intel_encoder *encoder, { const u32 *data = frame; struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); - u32 val = I915_READ(VIDEO_DIP_CTL); + struct intel_uncore *uncore = &dev_priv->de_uncore; + u32 val = intel_uncore_read(uncore, VIDEO_DIP_CTL); int i; WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); @@ -218,22 +221,22 @@ static void g4x_write_infoframe(struct intel_encoder *encoder, val &= ~g4x_infoframe_enable(type); - I915_WRITE(VIDEO_DIP_CTL, val); + intel_uncore_write(uncore, VIDEO_DIP_CTL, val); for (i = 0; i < len; i += 4) { - I915_WRITE(VIDEO_DIP_DATA, *data); + intel_uncore_write(uncore, VIDEO_DIP_DATA, *data); data++; } /* Write every possible data byte to force correct ECC calculation. */ for (; i < VIDEO_DIP_DATA_SIZE; i += 4) - I915_WRITE(VIDEO_DIP_DATA, 0); + intel_uncore_write(uncore, VIDEO_DIP_DATA, 0); val |= g4x_infoframe_enable(type); val &= ~VIDEO_DIP_FREQ_MASK; val |= VIDEO_DIP_FREQ_VSYNC; - I915_WRITE(VIDEO_DIP_CTL, val); - POSTING_READ(VIDEO_DIP_CTL); + intel_uncore_write(uncore, VIDEO_DIP_CTL, val); + intel_uncore_posting_read(uncore, VIDEO_DIP_CTL); } static void g4x_read_infoframe(struct intel_encoder *encoder, @@ -242,25 +245,26 @@ static void g4x_read_infoframe(struct intel_encoder *encoder, void *frame, ssize_t len) { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); + struct intel_uncore *uncore = &dev_priv->de_uncore; u32 val, *data = frame; int i; - val = I915_READ(VIDEO_DIP_CTL); + val = intel_uncore_read(uncore, VIDEO_DIP_CTL); val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ val |= g4x_infoframe_index(type); - I915_WRITE(VIDEO_DIP_CTL, val); + intel_uncore_write(uncore, VIDEO_DIP_CTL, val); for (i = 0; i < len; i += 4) - *data++ = I915_READ(VIDEO_DIP_DATA); + *data++ = intel_uncore_read(uncore, VIDEO_DIP_DATA); } static u32 g4x_infoframes_enabled(struct intel_encoder *encoder, const struct intel_crtc_state *pipe_config) { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); - u32 val = I915_READ(VIDEO_DIP_CTL); + u32 val = intel_uncore_read(&dev_priv->de_uncore, VIDEO_DIP_CTL); if ((val & VIDEO_DIP_ENABLE) == 0) return 0; @@ -279,9 +283,10 @@ static void ibx_write_infoframe(struct intel_encoder *encoder, { const u32 *data = frame; struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); + struct intel_uncore *uncore = &dev_priv->de_uncore; struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe); - u32 val = I915_READ(reg); + u32 val = intel_uncore_read(uncore, reg); int i; WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); @@ -291,22 +296,22 @@ static void ibx_write_infoframe(struct intel_encoder *encoder, val &= ~g4x_infoframe_enable(type); - I915_WRITE(reg, val); + intel_uncore_write(uncore, reg, val); for (i = 0; i < len; i += 4) { - I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data); + intel_uncore_write(uncore, TVIDEO_DIP_DATA(intel_crtc->pipe), *data); data++; } /* Write every possible data byte to force correct ECC calculation. */ for (; i < VIDEO_DIP_DATA_SIZE; i += 4) - I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0); + intel_uncore_write(uncore, TVIDEO_DIP_DATA(intel_crtc->pipe), 0); val |= g4x_infoframe_enable(type); val &= ~VIDEO_DIP_FREQ_MASK; val |= VIDEO_DIP_FREQ_VSYNC; - I915_WRITE(reg, val); - POSTING_READ(reg); + intel_uncore_write(uncore, reg, val); + intel_uncore_posting_read(uncore, reg); } static void ibx_read_infoframe(struct intel_encoder *encoder, @@ -315,19 +320,20 @@ static void ibx_read_infoframe(struct intel_encoder *encoder, void *frame, ssize_t len) { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); + struct intel_uncore *uncore = &dev_priv->de_uncore; struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); u32 val, *data = frame; int i; - val = I915_READ(TVIDEO_DIP_CTL(crtc->pipe)); + val = intel_uncore_read(uncore, TVIDEO_DIP_CTL(crtc->pipe)); val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ val |= g4x_infoframe_index(type); - I915_WRITE(TVIDEO_DIP_CTL(crtc->pipe), val); + intel_uncore_write(uncore, TVIDEO_DIP_CTL(crtc->pipe), val); for (i = 0; i < len; i += 4) - *data++ = I915_READ(TVIDEO_DIP_DATA(crtc->pipe)); + *data++ = intel_uncore_read(uncore, TVIDEO_DIP_DATA(crtc->pipe)); } static u32 ibx_infoframes_enabled(struct intel_encoder *encoder, @@ -336,7 +342,7 @@ static u32 ibx_infoframes_enabled(struct intel_encoder *encoder, struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe; i915_reg_t reg = TVIDEO_DIP_CTL(pipe); - u32 val = I915_READ(reg); + u32 val = intel_uncore_read(&dev_priv->de_uncore, reg); if ((val & VIDEO_DIP_ENABLE) == 0) return 0; @@ -356,9 +362,10 @@ static void cpt_write_infoframe(struct intel_encoder *encoder, { const u32 *data = frame; struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); + struct intel_uncore *uncore = &dev_priv->de_uncore; struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe); - u32 val = I915_READ(reg); + u32 val = intel_uncore_read(uncore, reg); int i; WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); @@ -371,22 +378,22 @@ static void cpt_write_infoframe(struct intel_encoder *encoder, if (type != HDMI_INFOFRAME_TYPE_AVI) val &= ~g4x_infoframe_enable(type); - I915_WRITE(reg, val); + intel_uncore_write(uncore, reg, val); for (i = 0; i < len; i += 4) { - I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data); + intel_uncore_write(uncore, TVIDEO_DIP_DATA(intel_crtc->pipe), *data); data++; } /* Write every possible data byte to force correct ECC calculation. */ for (; i < VIDEO_DIP_DATA_SIZE; i += 4) - I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0); + intel_uncore_write(uncore, TVIDEO_DIP_DATA(intel_crtc->pipe), 0); val |= g4x_infoframe_enable(type); val &= ~VIDEO_DIP_FREQ_MASK; val |= VIDEO_DIP_FREQ_VSYNC; - I915_WRITE(reg, val); - POSTING_READ(reg); + intel_uncore_write(uncore, reg, val); + intel_uncore_posting_read(uncore, reg); } static void cpt_read_infoframe(struct intel_encoder *encoder, @@ -395,19 +402,20 @@ static void cpt_read_infoframe(struct intel_encoder *encoder, void *frame, ssize_t len) { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); + struct intel_uncore *uncore = &dev_priv->de_uncore; struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); u32 val, *data = frame; int i; - val = I915_READ(TVIDEO_DIP_CTL(crtc->pipe)); + val = intel_uncore_read(uncore, TVIDEO_DIP_CTL(crtc->pipe)); val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ val |= g4x_infoframe_index(type); - I915_WRITE(TVIDEO_DIP_CTL(crtc->pipe), val); + intel_uncore_write(uncore, TVIDEO_DIP_CTL(crtc->pipe), val); for (i = 0; i < len; i += 4) - *data++ = I915_READ(TVIDEO_DIP_DATA(crtc->pipe)); + *data++ = intel_uncore_read(uncore, TVIDEO_DIP_DATA(crtc->pipe)); } static u32 cpt_infoframes_enabled(struct intel_encoder *encoder, @@ -415,7 +423,7 @@ static u32 cpt_infoframes_enabled(struct intel_encoder *encoder, { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe; - u32 val = I915_READ(TVIDEO_DIP_CTL(pipe)); + u32 val = intel_uncore_read(&dev_priv->de_uncore, TVIDEO_DIP_CTL(pipe)); if ((val & VIDEO_DIP_ENABLE) == 0) return 0; @@ -432,9 +440,10 @@ static void vlv_write_infoframe(struct intel_encoder *encoder, { const u32 *data = frame; struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); + struct intel_uncore *uncore = &dev_priv->de_uncore; struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); i915_reg_t reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe); - u32 val = I915_READ(reg); + u32 val = intel_uncore_read(uncore, reg); int i; WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); @@ -444,22 +453,22 @@ static void vlv_write_infoframe(struct intel_encoder *encoder, val &= ~g4x_infoframe_enable(type); - I915_WRITE(reg, val); + intel_uncore_write(uncore, reg, val); for (i = 0; i < len; i += 4) { - I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data); + intel_uncore_write(uncore, VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data); data++; } /* Write every possible data byte to force correct ECC calculation. */ for (; i < VIDEO_DIP_DATA_SIZE; i += 4) - I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), 0); + intel_uncore_write(uncore, VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), 0); val |= g4x_infoframe_enable(type); val &= ~VIDEO_DIP_FREQ_MASK; val |= VIDEO_DIP_FREQ_VSYNC; - I915_WRITE(reg, val); - POSTING_READ(reg); + intel_uncore_write(uncore, reg, val); + intel_uncore_posting_read(uncore, reg); } static void vlv_read_infoframe(struct intel_encoder *encoder, @@ -468,19 +477,20 @@ static void vlv_read_infoframe(struct intel_encoder *encoder, void *frame, ssize_t len) { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); + struct intel_uncore *uncore = &dev_priv->de_uncore; struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); u32 val, *data = frame; int i; - val = I915_READ(VLV_TVIDEO_DIP_CTL(crtc->pipe)); + val = intel_uncore_read(uncore, VLV_TVIDEO_DIP_CTL(crtc->pipe)); val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ val |= g4x_infoframe_index(type); - I915_WRITE(VLV_TVIDEO_DIP_CTL(crtc->pipe), val); + intel_uncore_write(uncore, VLV_TVIDEO_DIP_CTL(crtc->pipe), val); for (i = 0; i < len; i += 4) - *data++ = I915_READ(VLV_TVIDEO_DIP_DATA(crtc->pipe)); + *data++ = intel_uncore_read(uncore, VLV_TVIDEO_DIP_DATA(crtc->pipe)); } static u32 vlv_infoframes_enabled(struct intel_encoder *encoder, @@ -488,7 +498,7 @@ static u32 vlv_infoframes_enabled(struct intel_encoder *encoder, { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe; - u32 val = I915_READ(VLV_TVIDEO_DIP_CTL(pipe)); + u32 val = intel_uncore_read(&dev_priv->de_uncore, VLV_TVIDEO_DIP_CTL(pipe)); if ((val & VIDEO_DIP_ENABLE) == 0) return 0; @@ -508,30 +518,33 @@ static void hsw_write_infoframe(struct intel_encoder *encoder, { const u32 *data = frame; struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); + struct intel_uncore *uncore = &dev_priv->de_uncore; enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; i915_reg_t ctl_reg = HSW_TVIDEO_DIP_CTL(cpu_transcoder); int data_size; int i; - u32 val = I915_READ(ctl_reg); + u32 val = intel_uncore_read(uncore, ctl_reg); data_size = hsw_dip_data_size(type); val &= ~hsw_infoframe_enable(type); - I915_WRITE(ctl_reg, val); + intel_uncore_write(uncore, ctl_reg, val); for (i = 0; i < len; i += 4) { - I915_WRITE(hsw_dip_data_reg(dev_priv, cpu_transcoder, - type, i >> 2), *data); + intel_uncore_write(uncore, + hsw_dip_data_reg(dev_priv, cpu_transcoder, + type, i >> 2), *data); data++; } /* Write every possible data byte to force correct ECC calculation. */ for (; i < data_size; i += 4) - I915_WRITE(hsw_dip_data_reg(dev_priv, cpu_transcoder, - type, i >> 2), 0); + intel_uncore_write(uncore, hsw_dip_data_reg(dev_priv, + cpu_transcoder, + type, i >> 2), 0); val |= hsw_infoframe_enable(type); - I915_WRITE(ctl_reg, val); - POSTING_READ(ctl_reg); + intel_uncore_write(uncore, ctl_reg, val); + intel_uncore_posting_read(uncore, ctl_reg); } static void hsw_read_infoframe(struct intel_encoder *encoder, @@ -540,22 +553,26 @@ static void hsw_read_infoframe(struct intel_encoder *encoder, void *frame, ssize_t len) { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); + struct intel_uncore *uncore = &dev_priv->de_uncore; enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; u32 val, *data = frame; int i; - val = I915_READ(HSW_TVIDEO_DIP_CTL(cpu_transcoder)); + val = intel_uncore_read(uncore, HSW_TVIDEO_DIP_CTL(cpu_transcoder)); for (i = 0; i < len; i += 4) - *data++ = I915_READ(hsw_dip_data_reg(dev_priv, cpu_transcoder, - type, i >> 2)); + *data++ = intel_uncore_read(uncore, + hsw_dip_data_reg(dev_priv, + cpu_transcoder, + type, i >> 2)); } static u32 hsw_infoframes_enabled(struct intel_encoder *encoder, const struct intel_crtc_state *pipe_config) { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); - u32 val = I915_READ(HSW_TVIDEO_DIP_CTL(pipe_config->cpu_transcoder)); + u32 val = intel_uncore_read(&dev_priv->de_uncore, + HSW_TVIDEO_DIP_CTL(pipe_config->cpu_transcoder)); u32 mask; mask = (VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW | @@ -838,10 +855,11 @@ static void g4x_set_infoframes(struct intel_encoder *encoder, const struct drm_connector_state *conn_state) { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); + struct intel_uncore *uncore = &dev_priv->de_uncore; struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base); struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi; i915_reg_t reg = VIDEO_DIP_CTL; - u32 val = I915_READ(reg); + u32 val = intel_uncore_read(uncore, reg); u32 port = VIDEO_DIP_PORT(encoder->port); assert_hdmi_port_disabled(intel_hdmi); @@ -867,8 +885,8 @@ static void g4x_set_infoframes(struct intel_encoder *encoder, } val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD); - I915_WRITE(reg, val); - POSTING_READ(reg); + intel_uncore_write(uncore, reg, val); + intel_uncore_posting_read(uncore, reg); return; } @@ -886,8 +904,8 @@ static void g4x_set_infoframes(struct intel_encoder *encoder, val &= ~(VIDEO_DIP_ENABLE_AVI | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD); - I915_WRITE(reg, val); - POSTING_READ(reg); + intel_uncore_write(uncore, reg, val); + intel_uncore_posting_read(uncore, reg); intel_write_infoframe(encoder, crtc_state, HDMI_INFOFRAME_TYPE_AVI, @@ -964,7 +982,7 @@ static bool intel_hdmi_set_gcp_infoframe(struct intel_encoder *encoder, else return false; - I915_WRITE(reg, crtc_state->infoframes.gcp); + intel_uncore_write(&dev_priv->de_uncore, reg, crtc_state->infoframes.gcp); return true; } @@ -989,7 +1007,7 @@ void intel_hdmi_read_gcp_infoframe(struct intel_encoder *encoder, else return; - crtc_state->infoframes.gcp = I915_READ(reg); + crtc_state->infoframes.gcp = intel_uncore_read(&dev_priv->de_uncore, reg); } static void intel_hdmi_compute_gcp_infoframe(struct intel_encoder *encoder, @@ -1020,11 +1038,12 @@ static void ibx_set_infoframes(struct intel_encoder *encoder, const struct drm_connector_state *conn_state) { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); + struct intel_uncore *uncore = &dev_priv->de_uncore; struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base); struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi; i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe); - u32 val = I915_READ(reg); + u32 val = intel_uncore_read(uncore, reg); u32 port = VIDEO_DIP_PORT(encoder->port); assert_hdmi_port_disabled(intel_hdmi); @@ -1038,8 +1057,8 @@ static void ibx_set_infoframes(struct intel_encoder *encoder, val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); - I915_WRITE(reg, val); - POSTING_READ(reg); + intel_uncore_write(uncore, reg, val); + intel_uncore_posting_read(uncore, reg); return; } @@ -1059,8 +1078,8 @@ static void ibx_set_infoframes(struct intel_encoder *encoder, if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state)) val |= VIDEO_DIP_ENABLE_GCP; - I915_WRITE(reg, val); - POSTING_READ(reg); + intel_uncore_write(uncore, reg, val); + intel_uncore_posting_read(uncore, reg); intel_write_infoframe(encoder, crtc_state, HDMI_INFOFRAME_TYPE_AVI, @@ -1079,10 +1098,11 @@ static void cpt_set_infoframes(struct intel_encoder *encoder, const struct drm_connector_state *conn_state) { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); + struct intel_uncore *uncore = &dev_priv->de_uncore; struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe); - u32 val = I915_READ(reg); + u32 val = intel_uncore_read(uncore, reg); assert_hdmi_port_disabled(intel_hdmi); @@ -1095,8 +1115,8 @@ static void cpt_set_infoframes(struct intel_encoder *encoder, val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); - I915_WRITE(reg, val); - POSTING_READ(reg); + intel_uncore_write(uncore, reg, val); + intel_uncore_posting_read(uncore, reg); return; } @@ -1108,8 +1128,8 @@ static void cpt_set_infoframes(struct intel_encoder *encoder, if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state)) val |= VIDEO_DIP_ENABLE_GCP; - I915_WRITE(reg, val); - POSTING_READ(reg); + intel_uncore_write(uncore, reg, val); + intel_uncore_posting_read(uncore, reg); intel_write_infoframe(encoder, crtc_state, HDMI_INFOFRAME_TYPE_AVI, @@ -1128,10 +1148,11 @@ static void vlv_set_infoframes(struct intel_encoder *encoder, const struct drm_connector_state *conn_state) { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); + struct intel_uncore *uncore = &dev_priv->de_uncore; struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); i915_reg_t reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe); - u32 val = I915_READ(reg); + u32 val = intel_uncore_read(uncore, reg); u32 port = VIDEO_DIP_PORT(encoder->port); assert_hdmi_port_disabled(intel_hdmi); @@ -1145,8 +1166,8 @@ static void vlv_set_infoframes(struct intel_encoder *encoder, val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); - I915_WRITE(reg, val); - POSTING_READ(reg); + intel_uncore_write(uncore, reg, val); + intel_uncore_posting_read(uncore, reg); return; } @@ -1166,8 +1187,8 @@ static void vlv_set_infoframes(struct intel_encoder *encoder, if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state)) val |= VIDEO_DIP_ENABLE_GCP; - I915_WRITE(reg, val); - POSTING_READ(reg); + intel_uncore_write(uncore, reg, val); + intel_uncore_posting_read(uncore, reg); intel_write_infoframe(encoder, crtc_state, HDMI_INFOFRAME_TYPE_AVI, @@ -1186,8 +1207,9 @@ static void hsw_set_infoframes(struct intel_encoder *encoder, const struct drm_connector_state *conn_state) { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); + struct intel_uncore *uncore = &dev_priv->de_uncore; i915_reg_t reg = HSW_TVIDEO_DIP_CTL(crtc_state->cpu_transcoder); - u32 val = I915_READ(reg); + u32 val = intel_uncore_read(uncore, reg); assert_hdmi_transcoder_func_disabled(dev_priv, crtc_state->cpu_transcoder); @@ -1198,16 +1220,16 @@ static void hsw_set_infoframes(struct intel_encoder *encoder, VIDEO_DIP_ENABLE_DRM_GLK); if (!enable) { - I915_WRITE(reg, val); - POSTING_READ(reg); + intel_uncore_write(uncore, reg, val); + intel_uncore_posting_read(uncore, reg); return; } if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state)) val |= VIDEO_DIP_ENABLE_GCP_HSW; - I915_WRITE(reg, val); - POSTING_READ(reg); + intel_uncore_write(uncore, reg, val); + intel_uncore_posting_read(uncore, reg); intel_write_infoframe(encoder, crtc_state, HDMI_INFOFRAME_TYPE_AVI, @@ -1437,7 +1459,8 @@ static int kbl_repositioning_enc_en_signal(struct intel_connector *connector) int ret; for (;;) { - scanline = I915_READ(PIPEDSL(intel_crtc->pipe)); + scanline = intel_uncore_read(&dev_priv->de_uncore, + PIPEDSL(intel_crtc->pipe)); if (scanline > 100 && scanline < 200) break; usleep_range(25, 50); @@ -1491,6 +1514,7 @@ bool intel_hdmi_hdcp_check_link(struct intel_digital_port *intel_dig_port) { struct drm_i915_private *dev_priv = intel_dig_port->base.base.dev->dev_private; + struct intel_uncore *uncore = &dev_priv->de_uncore; enum port port = intel_dig_port->base.port; int ret; union { @@ -1502,13 +1526,13 @@ bool intel_hdmi_hdcp_check_link(struct intel_digital_port *intel_dig_port) if (ret) return false; - I915_WRITE(PORT_HDCP_RPRIME(port), ri.reg); + intel_uncore_write(uncore, PORT_HDCP_RPRIME(port), ri.reg); /* Wait for Ri prime match */ - if (wait_for(I915_READ(PORT_HDCP_STATUS(port)) & + if (wait_for(intel_uncore_read(uncore, PORT_HDCP_STATUS(port)) & (HDCP_STATUS_RI_MATCH | HDCP_STATUS_ENC), 1)) { DRM_ERROR("Ri' mismatch detected, link check failed (%x)\n", - I915_READ(PORT_HDCP_STATUS(port))); + intel_uncore_read(uncore, PORT_HDCP_STATUS(port))); return false; } return true; @@ -1751,8 +1775,8 @@ static void intel_hdmi_prepare(struct intel_encoder *encoder, else hdmi_val |= SDVO_PIPE_SEL(crtc->pipe); - I915_WRITE(intel_hdmi->hdmi_reg, hdmi_val); - POSTING_READ(intel_hdmi->hdmi_reg); + intel_uncore_write(&dev_priv->de_uncore, intel_hdmi->hdmi_reg, hdmi_val); + intel_uncore_posting_read(&dev_priv->de_uncore, intel_hdmi->hdmi_reg); } static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder, @@ -1786,7 +1810,7 @@ static void intel_hdmi_get_config(struct intel_encoder *encoder, pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI); - tmp = I915_READ(intel_hdmi->hdmi_reg); + tmp = intel_uncore_read(&dev_priv->de_uncore, intel_hdmi->hdmi_reg); if (tmp & SDVO_HSYNC_ACTIVE_HIGH) flags |= DRM_MODE_FLAG_PHSYNC; @@ -1862,14 +1886,14 @@ static void g4x_enable_hdmi(struct intel_encoder *encoder, struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); u32 temp; - temp = I915_READ(intel_hdmi->hdmi_reg); + temp = intel_uncore_read(&dev_priv->de_uncore, intel_hdmi->hdmi_reg); temp |= SDVO_ENABLE; if (pipe_config->has_audio) temp |= SDVO_AUDIO_ENABLE; - I915_WRITE(intel_hdmi->hdmi_reg, temp); - POSTING_READ(intel_hdmi->hdmi_reg); + intel_uncore_write(&dev_priv->de_uncore, intel_hdmi->hdmi_reg, temp); + intel_uncore_posting_read(&dev_priv->de_uncore, intel_hdmi->hdmi_reg); if (pipe_config->has_audio) intel_enable_hdmi_audio(encoder, pipe_config, conn_state); @@ -1881,10 +1905,11 @@ static void ibx_enable_hdmi(struct intel_encoder *encoder, { struct drm_device *dev = encoder->base.dev; struct drm_i915_private *dev_priv = to_i915(dev); + struct intel_uncore *uncore = &dev_priv->de_uncore; struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); u32 temp; - temp = I915_READ(intel_hdmi->hdmi_reg); + temp = intel_uncore_read(uncore, intel_hdmi->hdmi_reg); temp |= SDVO_ENABLE; if (pipe_config->has_audio) @@ -1894,10 +1919,10 @@ static void ibx_enable_hdmi(struct intel_encoder *encoder, * HW workaround, need to write this twice for issue * that may result in first write getting masked. */ - I915_WRITE(intel_hdmi->hdmi_reg, temp); - POSTING_READ(intel_hdmi->hdmi_reg); - I915_WRITE(intel_hdmi->hdmi_reg, temp); - POSTING_READ(intel_hdmi->hdmi_reg); + intel_uncore_write(uncore, intel_hdmi->hdmi_reg, temp); + intel_uncore_posting_read(uncore, intel_hdmi->hdmi_reg); + intel_uncore_write(uncore, intel_hdmi->hdmi_reg, temp); + intel_uncore_posting_read(uncore, intel_hdmi->hdmi_reg); /* * HW workaround, need to toggle enable bit off and on @@ -1908,17 +1933,18 @@ static void ibx_enable_hdmi(struct intel_encoder *encoder, */ if (pipe_config->pipe_bpp > 24 && pipe_config->pixel_multiplier > 1) { - I915_WRITE(intel_hdmi->hdmi_reg, temp & ~SDVO_ENABLE); - POSTING_READ(intel_hdmi->hdmi_reg); + intel_uncore_write(uncore, intel_hdmi->hdmi_reg, + temp & ~SDVO_ENABLE); + intel_uncore_posting_read(uncore, intel_hdmi->hdmi_reg); /* * HW workaround, need to write this twice for issue * that may result in first write getting masked. */ - I915_WRITE(intel_hdmi->hdmi_reg, temp); - POSTING_READ(intel_hdmi->hdmi_reg); - I915_WRITE(intel_hdmi->hdmi_reg, temp); - POSTING_READ(intel_hdmi->hdmi_reg); + intel_uncore_write(uncore, intel_hdmi->hdmi_reg, temp); + intel_uncore_posting_read(uncore, intel_hdmi->hdmi_reg); + intel_uncore_write(uncore, intel_hdmi->hdmi_reg, temp); + intel_uncore_posting_read(uncore, intel_hdmi->hdmi_reg); } if (pipe_config->has_audio) @@ -1931,12 +1957,13 @@ static void cpt_enable_hdmi(struct intel_encoder *encoder, { struct drm_device *dev = encoder->base.dev; struct drm_i915_private *dev_priv = to_i915(dev); + struct intel_uncore *uncore = &dev_priv->de_uncore; struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc); struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); enum pipe pipe = crtc->pipe; u32 temp; - temp = I915_READ(intel_hdmi->hdmi_reg); + temp = intel_uncore_read(uncore, intel_hdmi->hdmi_reg); temp |= SDVO_ENABLE; if (pipe_config->has_audio) @@ -1953,27 +1980,25 @@ static void cpt_enable_hdmi(struct intel_encoder *encoder, */ if (pipe_config->pipe_bpp > 24) { - I915_WRITE(TRANS_CHICKEN1(pipe), - I915_READ(TRANS_CHICKEN1(pipe)) | - TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE); + intel_uncore_rmw(uncore, TRANS_CHICKEN1(pipe), + 0, TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE); temp &= ~SDVO_COLOR_FORMAT_MASK; temp |= SDVO_COLOR_FORMAT_8bpc; } - I915_WRITE(intel_hdmi->hdmi_reg, temp); - POSTING_READ(intel_hdmi->hdmi_reg); + intel_uncore_write(uncore, intel_hdmi->hdmi_reg, temp); + intel_uncore_posting_read(uncore, intel_hdmi->hdmi_reg); if (pipe_config->pipe_bpp > 24) { temp &= ~SDVO_COLOR_FORMAT_MASK; temp |= HDMI_COLOR_FORMAT_12bpc; - I915_WRITE(intel_hdmi->hdmi_reg, temp); - POSTING_READ(intel_hdmi->hdmi_reg); + intel_uncore_write(uncore, intel_hdmi->hdmi_reg, temp); + intel_uncore_posting_read(uncore, intel_hdmi->hdmi_reg); - I915_WRITE(TRANS_CHICKEN1(pipe), - I915_READ(TRANS_CHICKEN1(pipe)) & - ~TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE); + intel_uncore_rmw(uncore, TRANS_CHICKEN1(pipe), + TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE, 0); } if (pipe_config->has_audio) @@ -1992,17 +2017,18 @@ static void intel_disable_hdmi(struct intel_encoder *encoder, { struct drm_device *dev = encoder->base.dev; struct drm_i915_private *dev_priv = to_i915(dev); + struct intel_uncore *uncore = &dev_priv->de_uncore; struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); struct intel_digital_port *intel_dig_port = hdmi_to_dig_port(intel_hdmi); struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc); u32 temp; - temp = I915_READ(intel_hdmi->hdmi_reg); + temp = intel_uncore_read(uncore, intel_hdmi->hdmi_reg); temp &= ~(SDVO_ENABLE | SDVO_AUDIO_ENABLE); - I915_WRITE(intel_hdmi->hdmi_reg, temp); - POSTING_READ(intel_hdmi->hdmi_reg); + intel_uncore_write(uncore, intel_hdmi->hdmi_reg, temp); + intel_uncore_posting_read(uncore, intel_hdmi->hdmi_reg); /* * HW workaround for IBX, we need to move the port @@ -2023,14 +2049,14 @@ static void intel_disable_hdmi(struct intel_encoder *encoder, * HW workaround, need to write this twice for issue * that may result in first write getting masked. */ - I915_WRITE(intel_hdmi->hdmi_reg, temp); - POSTING_READ(intel_hdmi->hdmi_reg); - I915_WRITE(intel_hdmi->hdmi_reg, temp); - POSTING_READ(intel_hdmi->hdmi_reg); + intel_uncore_write(uncore, intel_hdmi->hdmi_reg, temp); + intel_uncore_posting_read(uncore, intel_hdmi->hdmi_reg); + intel_uncore_write(uncore, intel_hdmi->hdmi_reg, temp); + intel_uncore_posting_read(uncore, intel_hdmi->hdmi_reg); temp &= ~SDVO_ENABLE; - I915_WRITE(intel_hdmi->hdmi_reg, temp); - POSTING_READ(intel_hdmi->hdmi_reg); + intel_uncore_write(uncore, intel_hdmi->hdmi_reg, temp); + intel_uncore_posting_read(uncore, intel_hdmi->hdmi_reg); intel_wait_for_vblank_if_active(dev_priv, PIPE_A); intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true); @@ -3109,8 +3135,9 @@ void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port, * generated on the port when a cable is not attached. */ if (IS_G45(dev_priv)) { - u32 temp = I915_READ(PEG_BAND_GAP_DATA); - I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd); + u32 temp = intel_uncore_read(&dev_priv->de_uncore, PEG_BAND_GAP_DATA); + intel_uncore_write(&dev_priv->de_uncore, PEG_BAND_GAP_DATA, + (temp & ~0xf) | 0xd); } intel_hdmi->cec_notifier = cec_notifier_get_conn(dev->dev,