From patchwork Sat Jun 8 20:48:04 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Petr Cvek X-Patchwork-Id: 10983417 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 35E2914B6 for ; Sat, 8 Jun 2019 20:48:42 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 2002228A44 for ; Sat, 8 Jun 2019 20:48:42 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 13F9328B26; Sat, 8 Jun 2019 20:48:42 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FROM,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 86A4528AD3 for ; Sat, 8 Jun 2019 20:48:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727406AbfFHUsl (ORCPT ); Sat, 8 Jun 2019 16:48:41 -0400 Received: from mail-wm1-f67.google.com ([209.85.128.67]:56149 "EHLO mail-wm1-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727364AbfFHUsl (ORCPT ); Sat, 8 Jun 2019 16:48:41 -0400 Received: by mail-wm1-f67.google.com with SMTP id a15so5105705wmj.5 for ; Sat, 08 Jun 2019 13:48:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=UtD9LqGAYakgNOjMfkfswsTmJIWlE3YoJFMFCxDn+fg=; b=LDyQTtv5EX1Jn09YLEnjGaoibpxNYmVNs/c6Or9AmgA5psWHn25QarpfOu70U057TW /WmeEQbB34fTdxXVibQuU7mNbx6W8bFpf7GmXRBr3LwCeLkwvcPULSgYQVg7M6h9vaZ7 upk0Y/8WPgi3TCRwZ/H/qAacNisisuIc+QWr1Bc5wUU7WqWMdoPiuch3g0MpUH/zYPF1 FmwOGrug8CMSrn1PLZiFq5WzofHAlMdD9JBrO9Qu/Q5UiE4mZZjS6oNl/RSV2CUBJGG6 LiG3oBQfnPoM642DFemNgBaTDkHUrFOv2mFmeLg294GU8N+4eexVk2lgUEFdOxhHbUrl sTMQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=UtD9LqGAYakgNOjMfkfswsTmJIWlE3YoJFMFCxDn+fg=; b=W44tbHjqPyBkuHZ5/u/lkRkvFDfMPXT/MK+3WCRa1ralhY3Kls/BwPjRIFBr6b6wvV wK6MpA7ERrRKR0PdG6fLNJXHuD2FHSUvbaeewrhQJDxhBIYs66VKDJvGozGtMeIhF8EW 6Tmq+tV7OlZoVi3OkjF7uOUMU1dAklTUeiOO2ehJadulzwFwaahexfIMQpzBrAQMHokh kPpfdSPd8U9OvBIVrlxPlJkE0O+fhnaA0mF7ErvXqmqhRfHeounIml7/7AKb1cj634ok QPgqM3xyV57Nfh5jWKVgeRRzDMCSL0xr37FPZAM+v0wN00A1TCy5gAJfSouQ3/mRAeuF lOaA== X-Gm-Message-State: APjAAAU1/tsKL0nggQ6Pa2k3KWGThV0IMqFJQucLQPdJhAOiAh0qpXnN RFLI++G91VTKmT9LMuT4UKg= X-Google-Smtp-Source: APXvYqxA4kIf6JyrcOnsgnkTGYhGsoMyGre6NzWlKmmX+BmpB1xJ+k/RiPFrNwwsEkKRMXiCtCJ6Mw== X-Received: by 2002:a1c:c8:: with SMTP id 191mr8109727wma.6.1560026919473; Sat, 08 Jun 2019 13:48:39 -0700 (PDT) Received: from kontron.lan (2001-1ae9-0ff1-f191-359a-8d64-e90a-f663.ip6.tmcz.cz. [2001:1ae9:ff1:f191:359a:8d64:e90a:f663]) by smtp.gmail.com with ESMTPSA id f204sm4986394wme.18.2019.06.08.13.48.38 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Sat, 08 Jun 2019 13:48:39 -0700 (PDT) From: petrcvekcz@gmail.com X-Google-Original-From: petrcvekcz.gmail.com To: hauke@hauke-m.de, john@phrozen.org Cc: Petr Cvek , linux-mips@vger.kernel.org, openwrt-devel@lists.openwrt.org, pakahmar@hotmail.com Subject: [PATCH v1 1/7] MIPS: lantiq: Move macro directly to iomem function Date: Sat, 8 Jun 2019 22:48:04 +0200 Message-Id: X-Mailer: git-send-email 2.21.0 In-Reply-To: References: MIME-Version: 1.0 Sender: linux-mips-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Petr Cvek Using the variable as a temporary holder for the macro of the register offset value is not necessary. Move it directly to the IOMEM read/write call. Signed-off-by: Petr Cvek --- arch/mips/lantiq/irq.c | 18 ++++++++---------- 1 file changed, 8 insertions(+), 10 deletions(-) diff --git a/arch/mips/lantiq/irq.c b/arch/mips/lantiq/irq.c index 6549499eb202..fb3e1cc2cf6b 100644 --- a/arch/mips/lantiq/irq.c +++ b/arch/mips/lantiq/irq.c @@ -77,44 +77,42 @@ int ltq_eiu_get_irq(int exin) void ltq_disable_irq(struct irq_data *d) { - u32 ier = LTQ_ICU_IM0_IER; int offset = d->hwirq - MIPS_CPU_IRQ_CASCADE; int im = offset / INT_NUM_IM_OFFSET; offset %= INT_NUM_IM_OFFSET; - ltq_icu_w32(im, ltq_icu_r32(im, ier) & ~BIT(offset), ier); + ltq_icu_w32(im, ltq_icu_r32(im, LTQ_ICU_IM0_IER) & ~BIT(offset), + LTQ_ICU_IM0_IER); } void ltq_mask_and_ack_irq(struct irq_data *d) { - u32 ier = LTQ_ICU_IM0_IER; - u32 isr = LTQ_ICU_IM0_ISR; int offset = d->hwirq - MIPS_CPU_IRQ_CASCADE; int im = offset / INT_NUM_IM_OFFSET; offset %= INT_NUM_IM_OFFSET; - ltq_icu_w32(im, ltq_icu_r32(im, ier) & ~BIT(offset), ier); - ltq_icu_w32(im, BIT(offset), isr); + ltq_icu_w32(im, ltq_icu_r32(im, LTQ_ICU_IM0_IER) & ~BIT(offset), + LTQ_ICU_IM0_IER); + ltq_icu_w32(im, BIT(offset), LTQ_ICU_IM0_ISR); } static void ltq_ack_irq(struct irq_data *d) { - u32 isr = LTQ_ICU_IM0_ISR; int offset = d->hwirq - MIPS_CPU_IRQ_CASCADE; int im = offset / INT_NUM_IM_OFFSET; offset %= INT_NUM_IM_OFFSET; - ltq_icu_w32(im, BIT(offset), isr); + ltq_icu_w32(im, BIT(offset), LTQ_ICU_IM0_ISR); } void ltq_enable_irq(struct irq_data *d) { - u32 ier = LTQ_ICU_IM0_IER; int offset = d->hwirq - MIPS_CPU_IRQ_CASCADE; int im = offset / INT_NUM_IM_OFFSET; offset %= INT_NUM_IM_OFFSET; - ltq_icu_w32(im, ltq_icu_r32(im, ier) | BIT(offset), ier); + ltq_icu_w32(im, ltq_icu_r32(im, LTQ_ICU_IM0_IER) | BIT(offset), + LTQ_ICU_IM0_IER); } static int ltq_eiu_settype(struct irq_data *d, unsigned int type) From patchwork Sat Jun 8 20:48:05 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Petr Cvek X-Patchwork-Id: 10983419 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id A9D9814B6 for ; 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[2001:1ae9:ff1:f191:359a:8d64:e90a:f663]) by smtp.gmail.com with ESMTPSA id f204sm4986394wme.18.2019.06.08.13.48.42 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Sat, 08 Jun 2019 13:48:42 -0700 (PDT) From: petrcvekcz@gmail.com X-Google-Original-From: petrcvekcz.gmail.com To: hauke@hauke-m.de, john@phrozen.org Cc: Petr Cvek , linux-mips@vger.kernel.org, openwrt-devel@lists.openwrt.org, pakahmar@hotmail.com Subject: [PATCH v1 2/7] MIPS: lantiq: Change variables to the same type as the source Date: Sat, 8 Jun 2019 22:48:05 +0200 Message-Id: <799e71c36228ff077087e2b4545a5e5275e53729.1560024463.git.petrcvekcz@gmail.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: References: MIME-Version: 1.0 Sender: linux-mips-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Petr Cvek A structure irq_data, irq_desc_get_irq() and irq_linear_revmap() use a different type than defined in the lantiq ICU driver, which is using signed integers. The substracted result should never be negative nor is tested for that situation. Change it to unsigned. Signed-off-by: Petr Cvek --- arch/mips/lantiq/irq.c | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/arch/mips/lantiq/irq.c b/arch/mips/lantiq/irq.c index fb3e1cc2cf6b..ef946eb41439 100644 --- a/arch/mips/lantiq/irq.c +++ b/arch/mips/lantiq/irq.c @@ -77,8 +77,8 @@ int ltq_eiu_get_irq(int exin) void ltq_disable_irq(struct irq_data *d) { - int offset = d->hwirq - MIPS_CPU_IRQ_CASCADE; - int im = offset / INT_NUM_IM_OFFSET; + unsigned long offset = d->hwirq - MIPS_CPU_IRQ_CASCADE; + unsigned long im = offset / INT_NUM_IM_OFFSET; offset %= INT_NUM_IM_OFFSET; ltq_icu_w32(im, ltq_icu_r32(im, LTQ_ICU_IM0_IER) & ~BIT(offset), @@ -87,8 +87,8 @@ void ltq_disable_irq(struct irq_data *d) void ltq_mask_and_ack_irq(struct irq_data *d) { - int offset = d->hwirq - MIPS_CPU_IRQ_CASCADE; - int im = offset / INT_NUM_IM_OFFSET; + unsigned long offset = d->hwirq - MIPS_CPU_IRQ_CASCADE; + unsigned long im = offset / INT_NUM_IM_OFFSET; offset %= INT_NUM_IM_OFFSET; ltq_icu_w32(im, ltq_icu_r32(im, LTQ_ICU_IM0_IER) & ~BIT(offset), @@ -98,8 +98,8 @@ void ltq_mask_and_ack_irq(struct irq_data *d) static void ltq_ack_irq(struct irq_data *d) { - int offset = d->hwirq - MIPS_CPU_IRQ_CASCADE; - int im = offset / INT_NUM_IM_OFFSET; + unsigned long offset = d->hwirq - MIPS_CPU_IRQ_CASCADE; + unsigned long im = offset / INT_NUM_IM_OFFSET; offset %= INT_NUM_IM_OFFSET; ltq_icu_w32(im, BIT(offset), LTQ_ICU_IM0_ISR); @@ -107,8 +107,8 @@ static void ltq_ack_irq(struct irq_data *d) void ltq_enable_irq(struct irq_data *d) { - int offset = d->hwirq - MIPS_CPU_IRQ_CASCADE; - int im = offset / INT_NUM_IM_OFFSET; + unsigned long offset = d->hwirq - MIPS_CPU_IRQ_CASCADE; + unsigned long im = offset / INT_NUM_IM_OFFSET; offset %= INT_NUM_IM_OFFSET; ltq_icu_w32(im, ltq_icu_r32(im, LTQ_ICU_IM0_IER) | BIT(offset), @@ -224,9 +224,9 @@ static struct irq_chip ltq_eiu_type = { static void ltq_hw_irq_handler(struct irq_desc *desc) { - int module = irq_desc_get_irq(desc) - 2; + unsigned int module = irq_desc_get_irq(desc) - 2; u32 irq; - int hwirq; + irq_hw_number_t hwirq; irq = ltq_icu_r32(module, LTQ_ICU_IM0_IOSR); if (irq == 0) From patchwork Sat Jun 8 20:48:06 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Petr Cvek X-Patchwork-Id: 10983421 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 3F4F676 for ; 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[2001:1ae9:ff1:f191:359a:8d64:e90a:f663]) by smtp.gmail.com with ESMTPSA id f204sm4986394wme.18.2019.06.08.13.48.44 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Sat, 08 Jun 2019 13:48:44 -0700 (PDT) From: petrcvekcz@gmail.com X-Google-Original-From: petrcvekcz.gmail.com To: hauke@hauke-m.de, john@phrozen.org Cc: Petr Cvek , linux-mips@vger.kernel.org, openwrt-devel@lists.openwrt.org, pakahmar@hotmail.com Subject: [PATCH v1 3/7] MIPS: lantiq: Fix attributes of of_device_id structure Date: Sat, 8 Jun 2019 22:48:06 +0200 Message-Id: X-Mailer: git-send-email 2.21.0 In-Reply-To: References: MIME-Version: 1.0 Sender: linux-mips-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Petr Cvek According to the checkpatch the driver structure of_device_id requires to be const and with attribute __initconst. Change it accordingly. Signed-off-by: Petr Cvek --- arch/mips/lantiq/irq.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/mips/lantiq/irq.c b/arch/mips/lantiq/irq.c index ef946eb41439..2df5d37d0a7b 100644 --- a/arch/mips/lantiq/irq.c +++ b/arch/mips/lantiq/irq.c @@ -347,7 +347,7 @@ unsigned int get_c0_compare_int(void) return CP0_LEGACY_COMPARE_IRQ; } -static struct of_device_id __initdata of_irq_ids[] = { +static const struct of_device_id of_irq_ids[] __initconst = { { .compatible = "lantiq,icu", .data = icu_of_init }, {}, }; From patchwork Sat Jun 8 20:48:07 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Petr Cvek X-Patchwork-Id: 10983423 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 7B92D76 for ; Sat, 8 Jun 2019 20:48:50 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 6783C28A44 for ; Sat, 8 Jun 2019 20:48:50 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 5C0F228B26; Sat, 8 Jun 2019 20:48:50 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FROM,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 1737528A44 for ; Sat, 8 Jun 2019 20:48:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727372AbfFHUsu (ORCPT ); Sat, 8 Jun 2019 16:48:50 -0400 Received: from mail-wr1-f65.google.com ([209.85.221.65]:42383 "EHLO mail-wr1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727364AbfFHUst (ORCPT ); Sat, 8 Jun 2019 16:48:49 -0400 Received: by mail-wr1-f65.google.com with SMTP id x17so5395389wrl.9 for ; Sat, 08 Jun 2019 13:48:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=acjgtnfZM5+ljClU7KhpnoMYZUUlOHiWM5nNWs1Eo98=; b=hNfcyjqhuvXJAtaFSSotaRfOcxQ1ZnU9e1QriFcxjibGRhteg9Ucr9TtUqdmKmJX3P S2jW21TiOwDeMcNUxt3BWv/uj6t+NzlUfjSzbjMRr1317ye6mBEyvIMxLXYC4j6CSM01 4LGHE06ttI7Wu+mCdmn7QJR+Vj6/M+tlu8FL9qogBYUBwDKXEZsKRanh1mtPFiuCO7FN QCTMKakHQWIzn5OeVEcpiMDCXgt/Gr9Scbka9erWngAdZHzVs0fyuY5+w07MAckUfBzc nywWVENiEslnTrsBEIxE/PmQM8lQyrFT4yIfbdlKusAJxyTnlPbmzeWknLQ3jwvUEdEL OCwQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=acjgtnfZM5+ljClU7KhpnoMYZUUlOHiWM5nNWs1Eo98=; b=AhvdakGN/lynYd7iPsw+CEYTNArD4WlucWWsVRO0nhioPau+VLC8fgDTbagGZHMJQ6 7qNH0d6IqzuFO2AX+Ovkzt2vltgfLgR6I4ywqV2qofGcN2BxfMohup+Um/1HQ0Mr3xyn gJJAbU1xxKzVdt4maP49RhF4Z1rGzDTBMyGXmzfmV4SO9IkXO3r61xMtWGMqRMx4zgXc nghDG9sZU5j8omagShcAk6fGPVxumCsbdIrzu+301O/gw9w/h+hUfB1v5a2Gyor4iUSp u/FlbTbJN0Q+uMnRdhMz7K+KM21wQQFVHwy2IcyWglfYmZZGMFwTJDErcDTVkPL9QiYh gA0Q== X-Gm-Message-State: APjAAAV6+gKyJB2rZ6c3gW+wp8lLkshMhY6eeGIX1tBgytFMJ8KLy/AJ QQsQ4TECt9s9lpVrYe/gCok= X-Google-Smtp-Source: APXvYqzcB1B6B8BjfG4zuebkHlw6A/0J7EtIAvsIyA0gCg26GTnBSXxxa7/TM7FMVVg5P1sFeQveUQ== X-Received: by 2002:adf:b447:: with SMTP id v7mr3710307wrd.208.1560026928461; Sat, 08 Jun 2019 13:48:48 -0700 (PDT) Received: from kontron.lan (2001-1ae9-0ff1-f191-359a-8d64-e90a-f663.ip6.tmcz.cz. [2001:1ae9:ff1:f191:359a:8d64:e90a:f663]) by smtp.gmail.com with ESMTPSA id f204sm4986394wme.18.2019.06.08.13.48.47 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Sat, 08 Jun 2019 13:48:48 -0700 (PDT) From: petrcvekcz@gmail.com X-Google-Original-From: petrcvekcz.gmail.com To: hauke@hauke-m.de, john@phrozen.org Cc: Petr Cvek , linux-mips@vger.kernel.org, openwrt-devel@lists.openwrt.org, pakahmar@hotmail.com Subject: [PATCH v1 4/7] MIPS: lantiq: Remove unused macros Date: Sat, 8 Jun 2019 22:48:07 +0200 Message-Id: <1ebc11c9588ddf0afcec336b35b50751fe1e89f8.1560024463.git.petrcvekcz@gmail.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: References: MIME-Version: 1.0 Sender: linux-mips-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Petr Cvek The last use of both macros was in 4.11. Signed-off-by: Petr Cvek --- arch/mips/lantiq/irq.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/arch/mips/lantiq/irq.c b/arch/mips/lantiq/irq.c index 2df5d37d0a7b..21ccd580f8f5 100644 --- a/arch/mips/lantiq/irq.c +++ b/arch/mips/lantiq/irq.c @@ -54,10 +54,6 @@ #define ltq_eiu_w32(x, y) ltq_w32((x), ltq_eiu_membase + (y)) #define ltq_eiu_r32(x) ltq_r32(ltq_eiu_membase + (x)) -/* our 2 ipi interrupts for VSMP */ -#define MIPS_CPU_IPI_RESCHED_IRQ 0 -#define MIPS_CPU_IPI_CALL_IRQ 1 - /* we have a cascade of 8 irqs */ #define MIPS_CPU_IRQ_CASCADE 8 From patchwork Sat Jun 8 20:48:08 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Petr Cvek X-Patchwork-Id: 10983425 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 9000A14B6 for ; Sat, 8 Jun 2019 20:48:52 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 7D44728A44 for ; Sat, 8 Jun 2019 20:48:52 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 7188C28B26; Sat, 8 Jun 2019 20:48:52 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FROM,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 1FFA228A44 for ; Sat, 8 Jun 2019 20:48:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727424AbfFHUsw (ORCPT ); Sat, 8 Jun 2019 16:48:52 -0400 Received: from mail-wr1-f68.google.com ([209.85.221.68]:44630 "EHLO mail-wr1-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727364AbfFHUsv (ORCPT ); Sat, 8 Jun 2019 16:48:51 -0400 Received: by mail-wr1-f68.google.com with SMTP id b17so5395037wrq.11 for ; Sat, 08 Jun 2019 13:48:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Nds0LhX8tAhIs/UmD34qgTUz4OBaMwTfQsiXTSUrrtY=; b=FckPL98ZyAAlP2fwiYD5PrZvh+RJJ+ExMIDDKpihDG8xUqewTzo6zY1DoGYJQlzChp KvJrC/F+dgybfJVdqrqgkpJC5xjrlzf1hqE+uEqZuGPT2S9LRZv8M/lWxDEZ8kGv+IbV TX24I3pOic7Nhv8ErCJvo39ygYmRB/VkrzJxrGYeAR39lvf9aUzRsWXjZFlifoWCaGtA aK35GcJh5yqMQKf2WE4JbLv2BAp+nPeL55x60MkYyuWvhXi+twYG18zXPi84eRMOKUOa UyZx8vyqqyoMMGkTD6gf4Fym5o5UUfk0roSOUhWBqVfnwLDcgLH84msBXuq7YxRlz4xL B8wg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Nds0LhX8tAhIs/UmD34qgTUz4OBaMwTfQsiXTSUrrtY=; b=QMdaikgelkoqCsM6OqDzV+2RqEw/9DxPeHJMpPEpmvnbywKy23mCu0CYKVLuWf6cbV Byx4BAb/9zd94bjkGncQ7F2pO3HjrZsJrYQA2d0oI8+UYcV/Mid7CAFbXWCtXLi94c4o 1lpCfH/ClLlLfH+xC24tM01/7sEjlMNawo99NyDSeiNPchKLeUoykQrD9vEKtBWgJNX1 NrkLUqGFO3LW1N9kfMZJvggtIaOnvGN2Ri2Sm0+wEkJpnCF2Ul4zfCTxVxu1lD1rVntH SCEyN+SXbwG/bdzd+dwmfsMTNNHU+1F/VClOoR5tXA3f8TFrXUUaqeFysEX0dyPVuHIS Hf3Q== X-Gm-Message-State: APjAAAXvCqqhSE0SnvquYemfvWJ0gH5fNetrNivquiDWuyFGk5xNqVbL E1seG9LZRHH/SdsacQL40ns= X-Google-Smtp-Source: APXvYqxyiqmModKRNJa2gzhqx+MmQaWTzNO58qfJV3yUsY08DwvAS+YcLp6B+FnDI4NsSoEnA58qKw== X-Received: by 2002:adf:ecca:: with SMTP id s10mr22013347wro.168.1560026930311; Sat, 08 Jun 2019 13:48:50 -0700 (PDT) Received: from kontron.lan (2001-1ae9-0ff1-f191-359a-8d64-e90a-f663.ip6.tmcz.cz. [2001:1ae9:ff1:f191:359a:8d64:e90a:f663]) by smtp.gmail.com with ESMTPSA id f204sm4986394wme.18.2019.06.08.13.48.49 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Sat, 08 Jun 2019 13:48:49 -0700 (PDT) From: petrcvekcz@gmail.com X-Google-Original-From: petrcvekcz.gmail.com To: hauke@hauke-m.de, john@phrozen.org Cc: Petr Cvek , linux-mips@vger.kernel.org, openwrt-devel@lists.openwrt.org, pakahmar@hotmail.com Subject: [PATCH v1 5/7] MIPS: lantiq: Fix bitfield masking Date: Sat, 8 Jun 2019 22:48:08 +0200 Message-Id: <478abd4c3d8073e6a20de2eedf22d982b79f2a4d.1560024463.git.petrcvekcz@gmail.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: References: MIME-Version: 1.0 Sender: linux-mips-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Petr Cvek The modification of EXIN register doesn't clean the bitfield before the writing of a new value. After a few modifications the bitfield would accumulate only '1's. Signed-off-by: Petr Cvek --- arch/mips/lantiq/irq.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/mips/lantiq/irq.c b/arch/mips/lantiq/irq.c index 21ccd580f8f5..35d7c5f6d159 100644 --- a/arch/mips/lantiq/irq.c +++ b/arch/mips/lantiq/irq.c @@ -150,8 +150,9 @@ static int ltq_eiu_settype(struct irq_data *d, unsigned int type) if (edge) irq_set_handler(d->hwirq, handle_edge_irq); - ltq_eiu_w32(ltq_eiu_r32(LTQ_EIU_EXIN_C) | - (val << (i * 4)), LTQ_EIU_EXIN_C); + ltq_eiu_w32((ltq_eiu_r32(LTQ_EIU_EXIN_C) & + (~(7 << (i * 4)))) | (val << (i * 4)), + LTQ_EIU_EXIN_C); } } From patchwork Sat Jun 8 20:48:09 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Petr Cvek X-Patchwork-Id: 10983427 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 7575C14B6 for ; Sat, 8 Jun 2019 20:48:55 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 62A4F28A44 for ; Sat, 8 Jun 2019 20:48:55 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 56F0F28B26; Sat, 8 Jun 2019 20:48:55 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FROM,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id E74A528A44 for ; Sat, 8 Jun 2019 20:48:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727444AbfFHUsy (ORCPT ); Sat, 8 Jun 2019 16:48:54 -0400 Received: from mail-wr1-f66.google.com ([209.85.221.66]:42387 "EHLO mail-wr1-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727364AbfFHUsy (ORCPT ); Sat, 8 Jun 2019 16:48:54 -0400 Received: by mail-wr1-f66.google.com with SMTP id x17so5395464wrl.9 for ; Sat, 08 Jun 2019 13:48:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=NDkhvgtD/o0cYL0eRaqTRxOMPTqLlZ8l9oete6cnkdg=; b=b2sWoyvyFLmxT+oY88f/Ny6QzzIZROW+5Dum6y6X09IhNYT1UCGdaeKVWbXOP3Ictk GTdSNc0olhc/TPrc70GdlcH2HBJXi/TW3kNfHU4JpHBpX8qliroBFb3Hl+Cj+5B+trH7 pXeQ5PxfozheKWnYSa5jWVgDaaMmmXk3qSEfdCNE8USw1BtFoGHSCEfAnF4Tlwei7AzO u5hH5GzHSJIpJGexKvTMWkivrhuZF2l6df0N+NvnTA24O/I2f/T8kijcnMvkHPf0Xlw9 IafA6VDydYvrBYBx7SOf5Xf93IhPctIrl7SEH121rs7Cb3dSGmvBcX6ZbrR6TXLXgvsi H7yA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=NDkhvgtD/o0cYL0eRaqTRxOMPTqLlZ8l9oete6cnkdg=; b=pfCk2JvZ5yHbl7dHcLMnO16w43BNnY/3Z04qL69Vn+M6aq9vxCV1o2CW15r4DRNJE/ Zno44bewb84fzZXzqyMlOErRqH7KST8jCCyefkRxwAE8Fh8lZInf7JshdMlr9/H6qtOo CPbLZHqP12m58IugVbhYcw6m3Ves8r9lgLh3lcLTSOLuI6GqtigzguFJvxpzEdVyBA+2 YFl5W1atpoTncCzV2ojEYSxB+u+47f6G+aECQ351N/paGqAQ5g/TEJCPnBx5Q5D2b/GJ g1JtS3Y0UnYMLHU46ZiHnZu08dILWD+njtTSTr9I23/7bbYzn005Uw6T3mS0bDmI5WiS KY/w== X-Gm-Message-State: APjAAAWFs/6mZAy7jSNV+vXqllj3g71PSAEN3sCFXjdexuqm81196WZS ysBYvnXE/uOC9frr1oY2Nnk= X-Google-Smtp-Source: APXvYqxrllq2YXhlFbcTSCsE5eJWOW2xflbeXjr/f27HPYjPDsi8g6gG0ubMjJ9KX8tqQneExDtxOA== X-Received: by 2002:adf:ef09:: with SMTP id e9mr24636275wro.79.1560026932396; Sat, 08 Jun 2019 13:48:52 -0700 (PDT) Received: from kontron.lan (2001-1ae9-0ff1-f191-359a-8d64-e90a-f663.ip6.tmcz.cz. [2001:1ae9:ff1:f191:359a:8d64:e90a:f663]) by smtp.gmail.com with ESMTPSA id f204sm4986394wme.18.2019.06.08.13.48.51 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Sat, 08 Jun 2019 13:48:52 -0700 (PDT) From: petrcvekcz@gmail.com X-Google-Original-From: petrcvekcz.gmail.com To: hauke@hauke-m.de, john@phrozen.org Cc: Petr Cvek , linux-mips@vger.kernel.org, openwrt-devel@lists.openwrt.org, pakahmar@hotmail.com Subject: [PATCH v1 6/7] MIPS: lantiq: Shorten register names, remove unused macros Date: Sat, 8 Jun 2019 22:48:09 +0200 Message-Id: <430d6780b19250426ad4aa32f8382d62fe7e7dd0.1560024463.git.petrcvekcz@gmail.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: References: MIME-Version: 1.0 Sender: linux-mips-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Petr Cvek The macros LTQ_ICU_IM1_ISR and LTQ_ICU_OFFSET seems to be unused, remove them. Allong with that, remove _IM0 substring from the macro names. The IM (interrupt module) is already defined in IOMEM access and IM0 would be misleading. Signed-off-by: Petr Cvek --- arch/mips/lantiq/irq.c | 34 ++++++++++++++++------------------ 1 file changed, 16 insertions(+), 18 deletions(-) diff --git a/arch/mips/lantiq/irq.c b/arch/mips/lantiq/irq.c index 35d7c5f6d159..b9ca20ff07d5 100644 --- a/arch/mips/lantiq/irq.c +++ b/arch/mips/lantiq/irq.c @@ -22,13 +22,11 @@ #include /* register definitions - internal irqs */ -#define LTQ_ICU_IM0_ISR 0x0000 -#define LTQ_ICU_IM0_IER 0x0008 -#define LTQ_ICU_IM0_IOSR 0x0010 -#define LTQ_ICU_IM0_IRSR 0x0018 -#define LTQ_ICU_IM0_IMR 0x0020 -#define LTQ_ICU_IM1_ISR 0x0028 -#define LTQ_ICU_OFFSET (LTQ_ICU_IM1_ISR - LTQ_ICU_IM0_ISR) +#define LTQ_ICU_ISR 0x0000 +#define LTQ_ICU_IER 0x0008 +#define LTQ_ICU_IOSR 0x0010 +#define LTQ_ICU_IRSR 0x0018 +#define LTQ_ICU_IMR 0x0020 /* register definitions - external irqs */ #define LTQ_EIU_EXIN_C 0x0000 @@ -77,8 +75,8 @@ void ltq_disable_irq(struct irq_data *d) unsigned long im = offset / INT_NUM_IM_OFFSET; offset %= INT_NUM_IM_OFFSET; - ltq_icu_w32(im, ltq_icu_r32(im, LTQ_ICU_IM0_IER) & ~BIT(offset), - LTQ_ICU_IM0_IER); + ltq_icu_w32(im, ltq_icu_r32(im, LTQ_ICU_IER) & ~BIT(offset), + LTQ_ICU_IER); } void ltq_mask_and_ack_irq(struct irq_data *d) @@ -87,9 +85,9 @@ void ltq_mask_and_ack_irq(struct irq_data *d) unsigned long im = offset / INT_NUM_IM_OFFSET; offset %= INT_NUM_IM_OFFSET; - ltq_icu_w32(im, ltq_icu_r32(im, LTQ_ICU_IM0_IER) & ~BIT(offset), - LTQ_ICU_IM0_IER); - ltq_icu_w32(im, BIT(offset), LTQ_ICU_IM0_ISR); + ltq_icu_w32(im, ltq_icu_r32(im, LTQ_ICU_IER) & ~BIT(offset), + LTQ_ICU_IER); + ltq_icu_w32(im, BIT(offset), LTQ_ICU_ISR); } static void ltq_ack_irq(struct irq_data *d) @@ -98,7 +96,7 @@ static void ltq_ack_irq(struct irq_data *d) unsigned long im = offset / INT_NUM_IM_OFFSET; offset %= INT_NUM_IM_OFFSET; - ltq_icu_w32(im, BIT(offset), LTQ_ICU_IM0_ISR); + ltq_icu_w32(im, BIT(offset), LTQ_ICU_ISR); } void ltq_enable_irq(struct irq_data *d) @@ -107,8 +105,8 @@ void ltq_enable_irq(struct irq_data *d) unsigned long im = offset / INT_NUM_IM_OFFSET; offset %= INT_NUM_IM_OFFSET; - ltq_icu_w32(im, ltq_icu_r32(im, LTQ_ICU_IM0_IER) | BIT(offset), - LTQ_ICU_IM0_IER); + ltq_icu_w32(im, ltq_icu_r32(im, LTQ_ICU_IER) | BIT(offset), + LTQ_ICU_IER); } static int ltq_eiu_settype(struct irq_data *d, unsigned int type) @@ -225,7 +223,7 @@ static void ltq_hw_irq_handler(struct irq_desc *desc) u32 irq; irq_hw_number_t hwirq; - irq = ltq_icu_r32(module, LTQ_ICU_IM0_IOSR); + irq = ltq_icu_r32(module, LTQ_ICU_IOSR); if (irq == 0) return; @@ -288,9 +286,9 @@ int __init icu_of_init(struct device_node *node, struct device_node *parent) /* turn off all irqs by default */ for (i = 0; i < MAX_IM; i++) { /* make sure all irqs are turned off by default */ - ltq_icu_w32(i, 0, LTQ_ICU_IM0_IER); + ltq_icu_w32(i, 0, LTQ_ICU_IER); /* clear all possibly pending interrupts */ - ltq_icu_w32(i, ~0, LTQ_ICU_IM0_ISR); + ltq_icu_w32(i, ~0, LTQ_ICU_ISR); } mips_cpu_irq_init(); From patchwork Sat Jun 8 20:48:10 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Petr Cvek X-Patchwork-Id: 10983429 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 82F2576 for ; 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[2001:1ae9:ff1:f191:359a:8d64:e90a:f663]) by smtp.gmail.com with ESMTPSA id f204sm4986394wme.18.2019.06.08.13.48.54 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Sat, 08 Jun 2019 13:48:54 -0700 (PDT) From: petrcvekcz@gmail.com X-Google-Original-From: petrcvekcz.gmail.com To: hauke@hauke-m.de, john@phrozen.org Cc: Petr Cvek , linux-mips@vger.kernel.org, openwrt-devel@lists.openwrt.org, pakahmar@hotmail.com Subject: [PATCH v1 7/7] MIPS: lantiq: Add SMP support for lantiq interrupt controller Date: Sat, 8 Jun 2019 22:48:10 +0200 Message-Id: <07892acc26ae73c6567254a28faac7a723cedbc3.1560024463.git.petrcvekcz@gmail.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: References: MIME-Version: 1.0 Sender: linux-mips-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Petr Cvek Some lantiq devices have two ICU controllers. Both are respectively routed to the individual VPEs. The patch adds the support for the second ICU. The patch changes a register definition of the driver. Instead of an individual IM, the whole ICU is defined. This will only affects openwrt patched kernel (vanilla doesn't have additional .dts files). Also spinlocks has been added, both cores can RMW different bitfields in the same register. Added affinity set function. The new VPE cpumask will take into the action at the irq enable. The driver can rotate the preset VPEs affinity cpumask. Either by an automatic cycling or just by using the first VPE from the affinity cpumask. This can be switched by macro AUTO_AFFINITY_ROTATION. The automatic rotation can be switched off from userspace by limiting the IRQ to only one VPE. The rotation was taken from MIPS loongson64's ht_irqdispatch(). The functionality was tested on 4.14 openwrt kernel and TP-W9980B modem. Signed-off-by: Petr Cvek --- arch/mips/lantiq/irq.c | 155 ++++++++++++++++++++++++++++++++++------- 1 file changed, 131 insertions(+), 24 deletions(-) diff --git a/arch/mips/lantiq/irq.c b/arch/mips/lantiq/irq.c index b9ca20ff07d5..0cdb7e88bfe5 100644 --- a/arch/mips/lantiq/irq.c +++ b/arch/mips/lantiq/irq.c @@ -21,6 +21,15 @@ #include #include +/* + * If defined, every IRQ enable call will switch the interrupt to + * the other VPE. You can limit used VPEs from the userspace. + * + * If not defined, only the first configured VPE from the userspace + * will be used. + */ +#define AUTO_AFFINITY_ROTATION + /* register definitions - internal irqs */ #define LTQ_ICU_ISR 0x0000 #define LTQ_ICU_IER 0x0008 @@ -46,8 +55,11 @@ */ #define LTQ_ICU_EBU_IRQ 22 -#define ltq_icu_w32(m, x, y) ltq_w32((x), ltq_icu_membase[m] + (y)) -#define ltq_icu_r32(m, x) ltq_r32(ltq_icu_membase[m] + (x)) +#define ltq_icu_w32(vpe, m, x, y) \ + ltq_w32((x), ltq_icu_membase[vpe] + m*0x28 + (y)) + +#define ltq_icu_r32(vpe, m, x) \ + ltq_r32(ltq_icu_membase[vpe] + m*0x28 + (x)) #define ltq_eiu_w32(x, y) ltq_w32((x), ltq_eiu_membase + (y)) #define ltq_eiu_r32(x) ltq_r32(ltq_eiu_membase + (x)) @@ -55,11 +67,15 @@ /* we have a cascade of 8 irqs */ #define MIPS_CPU_IRQ_CASCADE 8 +#define MAX_VPES 2 + static int exin_avail; static u32 ltq_eiu_irq[MAX_EIU]; -static void __iomem *ltq_icu_membase[MAX_IM]; +static void __iomem *ltq_icu_membase[MAX_VPES]; static void __iomem *ltq_eiu_membase; static struct irq_domain *ltq_domain; +static DEFINE_SPINLOCK(ltq_eiu_lock); +static DEFINE_RAW_SPINLOCK(ltq_icu_lock); static int ltq_perfcount_irq; int ltq_eiu_get_irq(int exin) @@ -73,45 +89,98 @@ void ltq_disable_irq(struct irq_data *d) { unsigned long offset = d->hwirq - MIPS_CPU_IRQ_CASCADE; unsigned long im = offset / INT_NUM_IM_OFFSET; + unsigned long flags; + int vpe; offset %= INT_NUM_IM_OFFSET; - ltq_icu_w32(im, ltq_icu_r32(im, LTQ_ICU_IER) & ~BIT(offset), - LTQ_ICU_IER); + + raw_spin_lock_irqsave(<q_icu_lock, flags); + for_each_present_cpu(vpe) { + ltq_icu_w32(vpe, im, + ltq_icu_r32(vpe, im, LTQ_ICU_IER) & ~BIT(offset), + LTQ_ICU_IER); + } + raw_spin_unlock_irqrestore(<q_icu_lock, flags); } void ltq_mask_and_ack_irq(struct irq_data *d) { unsigned long offset = d->hwirq - MIPS_CPU_IRQ_CASCADE; unsigned long im = offset / INT_NUM_IM_OFFSET; + unsigned long flags; + int vpe; offset %= INT_NUM_IM_OFFSET; - ltq_icu_w32(im, ltq_icu_r32(im, LTQ_ICU_IER) & ~BIT(offset), - LTQ_ICU_IER); - ltq_icu_w32(im, BIT(offset), LTQ_ICU_ISR); + + raw_spin_lock_irqsave(<q_icu_lock, flags); + for_each_present_cpu(vpe) { + ltq_icu_w32(vpe, im, + ltq_icu_r32(vpe, im, LTQ_ICU_IER) & ~BIT(offset), + LTQ_ICU_IER); + ltq_icu_w32(vpe, im, BIT(offset), LTQ_ICU_ISR); + } + raw_spin_unlock_irqrestore(<q_icu_lock, flags); } static void ltq_ack_irq(struct irq_data *d) { unsigned long offset = d->hwirq - MIPS_CPU_IRQ_CASCADE; unsigned long im = offset / INT_NUM_IM_OFFSET; + unsigned long flags; + int vpe; offset %= INT_NUM_IM_OFFSET; - ltq_icu_w32(im, BIT(offset), LTQ_ICU_ISR); + + raw_spin_lock_irqsave(<q_icu_lock, flags); + for_each_present_cpu(vpe) { + ltq_icu_w32(vpe, im, BIT(offset), LTQ_ICU_ISR); + } + raw_spin_unlock_irqrestore(<q_icu_lock, flags); } void ltq_enable_irq(struct irq_data *d) { unsigned long offset = d->hwirq - MIPS_CPU_IRQ_CASCADE; unsigned long im = offset / INT_NUM_IM_OFFSET; + unsigned long flags; + int vpe; offset %= INT_NUM_IM_OFFSET; - ltq_icu_w32(im, ltq_icu_r32(im, LTQ_ICU_IER) | BIT(offset), + +#if defined(AUTO_AFFINITY_ROTATION) + vpe = cpumask_next(smp_processor_id(), + irq_data_get_effective_affinity_mask(d)); + + /* + * There is a theoretical race condition if affinity gets changed + * meanwhile, but it would only caused a wrong VPE to be used until + * the next IRQ enable. Also the SoC has only 2 VPEs which fits + * the single u32. You can move spinlock before first mask readout + * and add it to ltq_icu_irq_set_affinity. + */ + + if (vpe >= nr_cpu_ids) + vpe = cpumask_first(irq_data_get_effective_affinity_mask(d)); +#else + vpe = cpumask_first(irq_data_get_effective_affinity_mask(d)); +#endif + + /* This shouldn't be even possible, maybe during CPU hotplug spam */ + if (unlikely(vpe >= nr_cpu_ids)) + vpe = smp_processor_id(); + + raw_spin_lock_irqsave(<q_icu_lock, flags); + + ltq_icu_w32(vpe, im, ltq_icu_r32(vpe, im, LTQ_ICU_IER) | BIT(offset), LTQ_ICU_IER); + + raw_spin_unlock_irqrestore(<q_icu_lock, flags); } static int ltq_eiu_settype(struct irq_data *d, unsigned int type) { int i; + unsigned long flags; for (i = 0; i < exin_avail; i++) { if (d->hwirq == ltq_eiu_irq[i]) { @@ -148,9 +217,11 @@ static int ltq_eiu_settype(struct irq_data *d, unsigned int type) if (edge) irq_set_handler(d->hwirq, handle_edge_irq); + spin_lock_irqsave(<q_eiu_lock, flags); ltq_eiu_w32((ltq_eiu_r32(LTQ_EIU_EXIN_C) & (~(7 << (i * 4)))) | (val << (i * 4)), LTQ_EIU_EXIN_C); + spin_unlock_irqrestore(<q_eiu_lock, flags); } } @@ -194,6 +265,21 @@ static void ltq_shutdown_eiu_irq(struct irq_data *d) } } +#if defined(CONFIG_SMP) +static int ltq_icu_irq_set_affinity(struct irq_data *d, + const struct cpumask *cpumask, bool force) +{ + struct cpumask tmask; + + if (!cpumask_and(&tmask, cpumask, cpu_online_mask)) + return -EINVAL; + + irq_data_update_effective_affinity(d, &tmask); + + return IRQ_SET_MASK_OK; +} +#endif + static struct irq_chip ltq_irq_type = { .name = "icu", .irq_enable = ltq_enable_irq, @@ -202,6 +288,9 @@ static struct irq_chip ltq_irq_type = { .irq_ack = ltq_ack_irq, .irq_mask = ltq_disable_irq, .irq_mask_ack = ltq_mask_and_ack_irq, +#if defined(CONFIG_SMP) + .irq_set_affinity = ltq_icu_irq_set_affinity, +#endif }; static struct irq_chip ltq_eiu_type = { @@ -215,6 +304,9 @@ static struct irq_chip ltq_eiu_type = { .irq_mask = ltq_disable_irq, .irq_mask_ack = ltq_mask_and_ack_irq, .irq_set_type = ltq_eiu_settype, +#if defined(CONFIG_SMP) + .irq_set_affinity = ltq_icu_irq_set_affinity, +#endif }; static void ltq_hw_irq_handler(struct irq_desc *desc) @@ -222,8 +314,9 @@ static void ltq_hw_irq_handler(struct irq_desc *desc) unsigned int module = irq_desc_get_irq(desc) - 2; u32 irq; irq_hw_number_t hwirq; + int vpe = smp_processor_id(); - irq = ltq_icu_r32(module, LTQ_ICU_IOSR); + irq = ltq_icu_r32(vpe, module, LTQ_ICU_IOSR); if (irq == 0) return; @@ -244,6 +337,7 @@ static void ltq_hw_irq_handler(struct irq_desc *desc) static int icu_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw) { struct irq_chip *chip = <q_irq_type; + struct irq_data *data; int i; if (hw < MIPS_CPU_IRQ_CASCADE) @@ -253,6 +347,10 @@ static int icu_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw) if (hw == ltq_eiu_irq[i]) chip = <q_eiu_type; + data = irq_get_irq_data(irq); + + irq_data_update_effective_affinity(data, cpumask_of(0)); + irq_set_chip_and_handler(irq, chip, handle_level_irq); return 0; @@ -267,28 +365,37 @@ int __init icu_of_init(struct device_node *node, struct device_node *parent) { struct device_node *eiu_node; struct resource res; - int i, ret; + int i, ret, vpe; - for (i = 0; i < MAX_IM; i++) { - if (of_address_to_resource(node, i, &res)) - panic("Failed to get icu memory range"); + /* load register regions of available ICUs */ + for_each_possible_cpu(vpe) { + if (of_address_to_resource(node, vpe, &res)) + panic("Failed to get icu%i memory range", vpe); if (!request_mem_region(res.start, resource_size(&res), res.name)) - pr_err("Failed to request icu memory"); + pr_err("Failed to request icu%i memory\n", vpe); - ltq_icu_membase[i] = ioremap_nocache(res.start, + ltq_icu_membase[vpe] = ioremap_nocache(res.start, resource_size(&res)); - if (!ltq_icu_membase[i]) - panic("Failed to remap icu memory"); + + if (!ltq_icu_membase[vpe]) + panic("Failed to remap icu%i memory", vpe); } /* turn off all irqs by default */ - for (i = 0; i < MAX_IM; i++) { - /* make sure all irqs are turned off by default */ - ltq_icu_w32(i, 0, LTQ_ICU_IER); - /* clear all possibly pending interrupts */ - ltq_icu_w32(i, ~0, LTQ_ICU_ISR); + for_each_possible_cpu(vpe) { + for (i = 0; i < MAX_IM; i++) { + /* make sure all irqs are turned off by default */ + ltq_icu_w32(vpe, i, 0, LTQ_ICU_IER); + + /* clear all possibly pending interrupts */ + ltq_icu_w32(vpe, i, ~0, LTQ_ICU_ISR); + ltq_icu_w32(vpe, i, ~0, LTQ_ICU_IMR); + + /* clear resend */ + ltq_icu_w32(vpe, i, 0, LTQ_ICU_IRSR); + } } mips_cpu_irq_init();