From patchwork Mon Jun 10 22:16:05 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christoph Hellwig X-Patchwork-Id: 10985545 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 256E81850 for ; Mon, 10 Jun 2019 22:16:32 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 1506D27861 for ; Mon, 10 Jun 2019 22:16:32 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 08F1C28409; Mon, 10 Jun 2019 22:16:32 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.7 required=2.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,MAILING_LIST_MULTI,RCVD_IN_DNSWL_NONE autolearn=ham version=3.3.1 Received: from kanga.kvack.org (kanga.kvack.org [205.233.56.17]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id A36C427861 for ; Mon, 10 Jun 2019 22:16:31 +0000 (UTC) Received: by kanga.kvack.org (Postfix) id 828276B026C; Mon, 10 Jun 2019 18:16:29 -0400 (EDT) Delivered-To: linux-mm-outgoing@kvack.org Received: by kanga.kvack.org (Postfix, from userid 40) id 7B0D36B026D; Mon, 10 Jun 2019 18:16:29 -0400 (EDT) X-Original-To: int-list-linux-mm@kvack.org X-Delivered-To: int-list-linux-mm@kvack.org Received: by kanga.kvack.org (Postfix, from userid 63042) id 5DBD56B026E; Mon, 10 Jun 2019 18:16:29 -0400 (EDT) X-Original-To: linux-mm@kvack.org X-Delivered-To: linux-mm@kvack.org Received: from mail-pl1-f200.google.com (mail-pl1-f200.google.com [209.85.214.200]) by kanga.kvack.org (Postfix) with ESMTP id 256826B026C for ; Mon, 10 Jun 2019 18:16:29 -0400 (EDT) Received: by mail-pl1-f200.google.com with SMTP id q2so6505237plr.19 for ; Mon, 10 Jun 2019 15:16:29 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:dkim-signature:from:to:cc:subject:date :message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=6gDH99Hzm+WVYiHprOTPdFzvuur8Lwudibupx/7wlxI=; b=JKUlco0uESJOknprmWqCK84mq6ouiNJ7MxmoELioyU59XI5LhQHJrT3jY9eHhc4AE3 rMY+qQv5WKG0RxYZ0jUglw3Lbn+z7j7Eh3MRPFey1ncIB2eNNCnfIIYCMVwEvzBl4w+Q wBviHc5uDBmouTziPJ9vBOKdkWtScI0owehyJk/uWuQRShrutLjjo7QkGIXMNWNn9jhl Sk8B1ac5eCVnvzoX+zVJsWdcI9st4gKb3wrShFoR0DwAdWf4Ju8soETYDz0uphFo+P+j RnueR20aaeVR4T6adI4X1LnO2lqHhwnp5/BUyScxpNpLkTh6Y6AMOQu3ciBB8fgAsmYV rYHw== X-Gm-Message-State: APjAAAU9yKZlNdXkQiHolRZjpK3iOtOwA/YMbheSANabzHSFhYL7uF4d zrXdSu9+xC4dWfYLHnDCiddGQ14zmJAqAJ50J3pEz4QgXD/WqArPCKGo4TUGzKV7ya8NrDzFYBq FIpCS3b0BlZQfUNwjKsgrcP0Xia/2ZMMqTAvE0EFhY1CNLgh2k//UTPd5MSi8qpw= X-Received: by 2002:a65:41c5:: with SMTP id b5mr18047729pgq.128.1560204988678; Mon, 10 Jun 2019 15:16:28 -0700 (PDT) X-Google-Smtp-Source: APXvYqxg5HgZHumF5GQwFHzY3acGosmiW29sZND0Voj7IQ5BV7lIAbuXIchPG1c+SLDCgx+TM1pH X-Received: by 2002:a65:41c5:: with SMTP id b5mr18047686pgq.128.1560204987964; Mon, 10 Jun 2019 15:16:27 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1560204987; cv=none; d=google.com; s=arc-20160816; b=DWvRp+y5xKyMcun6PW18y+h+VW20I/wrH2jYOclx7YVDJxvYo/ftbPN6HGf6mIMmXb vtWVonrmoUzn6Y+Da/fIcS2Mg1hLzK3QrvYInfrYzyRWc9XXBWevOsVox30znx73Zg7E iTrdiqwNrx0dRlDVY0pB49AhUi/BqJ2FLHcAg6PH6pAit51ZlaQWogS22Y7d/s5VC3e9 LWgK0ze+cIvUm4u2t86VFWj8fNLm7E686foyGZV3DvFKyO54OLc0MhDEB8pe29c+cFTF jng/UVESs+8yXwZZnrDuySgCW1i7FKIHtZ90pRsJa7M2u6nkmNgLxsSGeD9GmwCQG+0M 6K2w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=6gDH99Hzm+WVYiHprOTPdFzvuur8Lwudibupx/7wlxI=; b=uCpjgMopCNj3klJeG2XDaIgqS7UWld4GdTLOeHD1uXr4Tg4Je4lScPhe6AldBa/2vp hTmGX+K/uUJNrNUdtdnYmDN7K5ezmAi+VlpqRJNk5wf474AjBdo8QhbWaCPQigxwius5 bGjdM/NY1KFEO5ge9Rh4tZBeDEmpEqxIjYvlFWGGa8yXLyHtN+R+f9nnWNibYmudr9AT iFyGJxNZPb/psk7snCR8rbhig0ggWvCtjreSj7vhoz1fBolErvEuTY85KXNWsn+gO0LO G9GZANb1U7P7VMB9DWXFFrKfitS6Y27RJseF/RL1X/Sf57qdINL8RdWf/mZypiVbGIh6 WKqg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@infradead.org header.s=bombadil.20170209 header.b=scYXVmWf; spf=pass (google.com: best guess record for domain of batv+ba9daad91d8a220a3b0a+5769+infradead.org+hch@bombadil.srs.infradead.org designates 2607:7c80:54:e::133 as permitted sender) smtp.mailfrom=BATV+ba9daad91d8a220a3b0a+5769+infradead.org+hch@bombadil.srs.infradead.org Received: from bombadil.infradead.org (bombadil.infradead.org. [2607:7c80:54:e::133]) by mx.google.com with ESMTPS id t6si614716pjb.25.2019.06.10.15.16.27 for (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Mon, 10 Jun 2019 15:16:27 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of batv+ba9daad91d8a220a3b0a+5769+infradead.org+hch@bombadil.srs.infradead.org designates 2607:7c80:54:e::133 as permitted sender) client-ip=2607:7c80:54:e::133; Authentication-Results: mx.google.com; dkim=pass header.i=@infradead.org header.s=bombadil.20170209 header.b=scYXVmWf; spf=pass (google.com: best guess record for domain of batv+ba9daad91d8a220a3b0a+5769+infradead.org+hch@bombadil.srs.infradead.org designates 2607:7c80:54:e::133 as permitted sender) smtp.mailfrom=BATV+ba9daad91d8a220a3b0a+5769+infradead.org+hch@bombadil.srs.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=infradead.org; s=bombadil.20170209; h=Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From:Sender :Reply-To:Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From :Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Id:List-Help: List-Unsubscribe:List-Subscribe:List-Post:List-Owner:List-Archive; bh=6gDH99Hzm+WVYiHprOTPdFzvuur8Lwudibupx/7wlxI=; b=scYXVmWfCxMGuKvy+KYTDnjGoC rFeiHHz9ioI6lu9ROaFN8rv/PSxcZimXs1aLGEBVVnPMx2hulWbZUZNr5/Brsww2Nd1FiLPn3g1r8 lhPWU9/3Rf1xyGqPRohCDykL6Bnrl/Mf0k95KU12Z3byjITtPTYxi7EivgWeTroAOG+lF7GioAT+X LK/z1c4rgvBRp71OC3i/3ukzGiw9fXh1CFpWoyoyfzn9NJOywgZT+bx9efDKVYDGt+inbNVikvaM1 GQeC0G4kfqsjmud6V3Fi0uF/2tATq7LzhJK8X8VqDCkll68xiK1uXo3heJHbBsNx4laQghCgdLo9p uenkkJPw==; Received: from 089144193064.atnat0002.highway.a1.net ([89.144.193.64] helo=localhost) by bombadil.infradead.org with esmtpsa (Exim 4.92 #3 (Red Hat Linux)) id 1haSaY-0002kY-B7; Mon, 10 Jun 2019 22:16:26 +0000 From: Christoph Hellwig To: Palmer Dabbelt Cc: Damien Le Moal , linux-riscv@lists.infradead.org, uclinux-dev@uclinux.org, linux-mm@kvack.org, linux-kernel@vger.kernel.org Subject: [PATCH 01/17] mm: provide a print_vma_addr stub for !CONFIG_MMU Date: Tue, 11 Jun 2019 00:16:05 +0200 Message-Id: <20190610221621.10938-2-hch@lst.de> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190610221621.10938-1-hch@lst.de> References: <20190610221621.10938-1-hch@lst.de> MIME-Version: 1.0 X-SRS-Rewrite: SMTP reverse-path rewritten from by bombadil.infradead.org. See http://www.infradead.org/rpr.html X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: X-Virus-Scanned: ClamAV using ClamSMTP Signed-off-by: Christoph Hellwig Reviewed-by: Vladimir Murzin --- include/linux/mm.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/include/linux/mm.h b/include/linux/mm.h index dd0b5f4e1e45..69843ee0c5f8 100644 --- a/include/linux/mm.h +++ b/include/linux/mm.h @@ -2756,7 +2756,13 @@ extern int randomize_va_space; #endif const char * arch_vma_name(struct vm_area_struct *vma); +#ifdef CONFIG_MMU void print_vma_addr(char *prefix, unsigned long rip); +#else +static inline void print_vma_addr(char *prefix, unsigned long rip) +{ +} +#endif void *sparse_buffer_alloc(unsigned long size); struct page *sparse_mem_map_populate(unsigned long pnum, int nid, From patchwork Mon Jun 10 22:16:06 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christoph Hellwig X-Patchwork-Id: 10985547 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 416F41398 for ; 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[2607:7c80:54:e::133]) by mx.google.com with ESMTPS id w36si11182905pgl.540.2019.06.10.15.16.30 for (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Mon, 10 Jun 2019 15:16:30 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of batv+ba9daad91d8a220a3b0a+5769+infradead.org+hch@bombadil.srs.infradead.org designates 2607:7c80:54:e::133 as permitted sender) client-ip=2607:7c80:54:e::133; Authentication-Results: mx.google.com; dkim=pass header.i=@infradead.org header.s=bombadil.20170209 header.b=WoT5qfZO; spf=pass (google.com: best guess record for domain of batv+ba9daad91d8a220a3b0a+5769+infradead.org+hch@bombadil.srs.infradead.org designates 2607:7c80:54:e::133 as permitted sender) smtp.mailfrom=BATV+ba9daad91d8a220a3b0a+5769+infradead.org+hch@bombadil.srs.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=infradead.org; s=bombadil.20170209; h=Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From:Sender :Reply-To:Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From :Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Id:List-Help: List-Unsubscribe:List-Subscribe:List-Post:List-Owner:List-Archive; bh=uHFTnl4vUjrNVYTFv2dDUy+7np+VKavI9He7Ga2MW2s=; b=WoT5qfZOaCdlI5cjodJO96MTUa 0x0FTUYOBpRsHYygY/XLRcYru1xwfiTUOH/aiIMRbNiEB0rWP1GO4Xk2gH/26HqDQe+j2Ybm6u/Rv hupkRFH69Ysbq0FC3igQAwsbpJU618sqwSYdNRkyNM58whYGLdOuZJih7LYrSSzsRQCkMlyedKmp1 ApZeHTypJnTEPZDUphxKWpF2bD7O6bBM0bMcDdsTblUbbiQq7uHikPzv7wXg0izoJxUurD2y92zv1 LM0WfD9mxU80dyyv93OBxyEnVWpfoleq8QXyRkJoWLd4bGvAAP2qR00MhSEMk9xXdbgybODC2RYFM ypkZtJVA==; Received: from 089144193064.atnat0002.highway.a1.net ([89.144.193.64] helo=localhost) by bombadil.infradead.org with esmtpsa (Exim 4.92 #3 (Red Hat Linux)) id 1haSaa-0002mM-Ql; Mon, 10 Jun 2019 22:16:29 +0000 From: Christoph Hellwig To: Palmer Dabbelt Cc: Damien Le Moal , linux-riscv@lists.infradead.org, uclinux-dev@uclinux.org, linux-mm@kvack.org, linux-kernel@vger.kernel.org Subject: [PATCH 02/17] mm: stub out all of swapops.h for !CONFIG_MMU Date: Tue, 11 Jun 2019 00:16:06 +0200 Message-Id: <20190610221621.10938-3-hch@lst.de> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190610221621.10938-1-hch@lst.de> References: <20190610221621.10938-1-hch@lst.de> MIME-Version: 1.0 X-SRS-Rewrite: SMTP reverse-path rewritten from by bombadil.infradead.org. See http://www.infradead.org/rpr.html X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: X-Virus-Scanned: ClamAV using ClamSMTP The whole header file deals with swap entries and PTEs, none of which can exist for nommu builds. Signed-off-by: Christoph Hellwig --- include/linux/swapops.h | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/include/linux/swapops.h b/include/linux/swapops.h index 4d961668e5fc..b02922556846 100644 --- a/include/linux/swapops.h +++ b/include/linux/swapops.h @@ -6,6 +6,8 @@ #include #include +#ifdef CONFIG_MMU + /* * swapcache pages are stored in the swapper_space radix tree. We want to * get good packing density in that tree, so the index should be dense in @@ -50,13 +52,11 @@ static inline pgoff_t swp_offset(swp_entry_t entry) return entry.val & SWP_OFFSET_MASK; } -#ifdef CONFIG_MMU /* check whether a pte points to a swap entry */ static inline int is_swap_pte(pte_t pte) { return !pte_none(pte) && !pte_present(pte); } -#endif /* * Convert the arch-dependent pte representation of a swp_entry_t into an @@ -375,4 +375,5 @@ static inline int non_swap_entry(swp_entry_t entry) } #endif +#endif /* CONFIG_MMU */ #endif /* _LINUX_SWAPOPS_H */ From patchwork Mon Jun 10 22:16:07 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christoph Hellwig X-Patchwork-Id: 10985551 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 3F4B81515 for ; Mon, 10 Jun 2019 22:16:37 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 2F11A27861 for ; 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[2607:7c80:54:e::133]) by mx.google.com with ESMTPS id i18si10381703pfd.64.2019.06.10.15.16.33 for (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Mon, 10 Jun 2019 15:16:33 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of batv+ba9daad91d8a220a3b0a+5769+infradead.org+hch@bombadil.srs.infradead.org designates 2607:7c80:54:e::133 as permitted sender) client-ip=2607:7c80:54:e::133; Authentication-Results: mx.google.com; dkim=pass header.i=@infradead.org header.s=bombadil.20170209 header.b=oiEyUrF9; spf=pass (google.com: best guess record for domain of batv+ba9daad91d8a220a3b0a+5769+infradead.org+hch@bombadil.srs.infradead.org designates 2607:7c80:54:e::133 as permitted sender) smtp.mailfrom=BATV+ba9daad91d8a220a3b0a+5769+infradead.org+hch@bombadil.srs.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=infradead.org; s=bombadil.20170209; h=Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From:Sender :Reply-To:Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From :Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Id:List-Help: List-Unsubscribe:List-Subscribe:List-Post:List-Owner:List-Archive; bh=C4SI1FY60nHM9WI3SinoYDutxba0iN08JIEwzLdROHQ=; b=oiEyUrF9IL6rgPxNWJeKLxV3Vy A8cdnaU0V5jZiFy3sqNuhMbp91le0IAXzEcVclX9d5PaW1wff2o6pTA2bVm2UN/onTrJQeQHryhSB nnUPnH7xpOvpXmaxOwDz5rOGqBMRMR9NOBhqyJ7XBHdXPfiNQ7Mrhp+9f29lQk9Y2BTdGyyJaPI6q TVeAWffkUc/loManhERDhHXfQFG0B8mzkFQcnNPbAmCYplm8rVef85/v60iq+c5KwdSp2mrl3onW7 9J84YrKSW1WBeNpq/YL/fl/gqcugODpbtY3JYypgfqN8/G4+0fyb15o3i+3K2HQTTcFQgDpiCsyvL jnUhjrDQ==; Received: from 089144193064.atnat0002.highway.a1.net ([89.144.193.64] helo=localhost) by bombadil.infradead.org with esmtpsa (Exim 4.92 #3 (Red Hat Linux)) id 1haSad-0002pA-7n; Mon, 10 Jun 2019 22:16:31 +0000 From: Christoph Hellwig To: Palmer Dabbelt Cc: Damien Le Moal , linux-riscv@lists.infradead.org, uclinux-dev@uclinux.org, linux-mm@kvack.org, linux-kernel@vger.kernel.org Subject: [PATCH 03/17] mm/nommu: fix the MAP_UNINITIALIZED flag Date: Tue, 11 Jun 2019 00:16:07 +0200 Message-Id: <20190610221621.10938-4-hch@lst.de> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190610221621.10938-1-hch@lst.de> References: <20190610221621.10938-1-hch@lst.de> MIME-Version: 1.0 X-SRS-Rewrite: SMTP reverse-path rewritten from by bombadil.infradead.org. See http://www.infradead.org/rpr.html X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: X-Virus-Scanned: ClamAV using ClamSMTP We can't expose UAPI symbols differently based on CONFIG_ symbols, as userspace won't have them available. Instead always define the flag, but only repsect it based on the config option. Signed-off-by: Christoph Hellwig Reviewed-by: Vladimir Murzin --- arch/xtensa/include/uapi/asm/mman.h | 6 +----- include/uapi/asm-generic/mman-common.h | 8 +++----- mm/nommu.c | 4 +++- 3 files changed, 7 insertions(+), 11 deletions(-) diff --git a/arch/xtensa/include/uapi/asm/mman.h b/arch/xtensa/include/uapi/asm/mman.h index be726062412b..ebbb48842190 100644 --- a/arch/xtensa/include/uapi/asm/mman.h +++ b/arch/xtensa/include/uapi/asm/mman.h @@ -56,12 +56,8 @@ #define MAP_STACK 0x40000 /* give out an address that is best suited for process/thread stacks */ #define MAP_HUGETLB 0x80000 /* create a huge page mapping */ #define MAP_FIXED_NOREPLACE 0x100000 /* MAP_FIXED which doesn't unmap underlying mapping */ -#ifdef CONFIG_MMAP_ALLOW_UNINITIALIZED -# define MAP_UNINITIALIZED 0x4000000 /* For anonymous mmap, memory could be +#define MAP_UNINITIALIZED 0x4000000 /* For anonymous mmap, memory could be * uninitialized */ -#else -# define MAP_UNINITIALIZED 0x0 /* Don't support this flag */ -#endif /* * Flags for msync diff --git a/include/uapi/asm-generic/mman-common.h b/include/uapi/asm-generic/mman-common.h index abd238d0f7a4..cb556b430e71 100644 --- a/include/uapi/asm-generic/mman-common.h +++ b/include/uapi/asm-generic/mman-common.h @@ -19,15 +19,13 @@ #define MAP_TYPE 0x0f /* Mask for type of mapping */ #define MAP_FIXED 0x10 /* Interpret addr exactly */ #define MAP_ANONYMOUS 0x20 /* don't use a file */ -#ifdef CONFIG_MMAP_ALLOW_UNINITIALIZED -# define MAP_UNINITIALIZED 0x4000000 /* For anonymous mmap, memory could be uninitialized */ -#else -# define MAP_UNINITIALIZED 0x0 /* Don't support this flag */ -#endif /* 0x0100 - 0x80000 flags are defined in asm-generic/mman.h */ #define MAP_FIXED_NOREPLACE 0x100000 /* MAP_FIXED which doesn't unmap underlying mapping */ +#define MAP_UNINITIALIZED 0x4000000 /* For anonymous mmap, memory could be + * uninitialized */ + /* * Flags for mlock */ diff --git a/mm/nommu.c b/mm/nommu.c index d8c02fbe03b5..ec75a0dffd4f 100644 --- a/mm/nommu.c +++ b/mm/nommu.c @@ -1349,7 +1349,9 @@ unsigned long do_mmap(struct file *file, add_nommu_region(region); /* clear anonymous mappings that don't ask for uninitialized data */ - if (!vma->vm_file && !(flags & MAP_UNINITIALIZED)) + if (!vma->vm_file && + (!IS_ENABLED(CONFIG_MMAP_ALLOW_UNINITIALIZED) || + !(flags & MAP_UNINITIALIZED))) memset((void *)region->vm_start, 0, region->vm_end - region->vm_start); From patchwork Mon Jun 10 22:16:08 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christoph Hellwig X-Patchwork-Id: 10985555 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id A93BA1398 for ; Mon, 10 Jun 2019 22:16:40 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 9897C27861 for ; Mon, 10 Jun 2019 22:16:40 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 8B4C628409; Mon, 10 Jun 2019 22:16:40 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.7 required=2.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,MAILING_LIST_MULTI,RCVD_IN_DNSWL_NONE autolearn=ham version=3.3.1 Received: from kanga.kvack.org (kanga.kvack.org [205.233.56.17]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id EC19327861 for ; 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[2607:7c80:54:e::133]) by mx.google.com with ESMTPS id l67si12190132plb.370.2019.06.10.15.16.36 for (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Mon, 10 Jun 2019 15:16:36 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of batv+ba9daad91d8a220a3b0a+5769+infradead.org+hch@bombadil.srs.infradead.org designates 2607:7c80:54:e::133 as permitted sender) client-ip=2607:7c80:54:e::133; Authentication-Results: mx.google.com; dkim=pass header.i=@infradead.org header.s=bombadil.20170209 header.b="VLiBuzt/"; spf=pass (google.com: best guess record for domain of batv+ba9daad91d8a220a3b0a+5769+infradead.org+hch@bombadil.srs.infradead.org designates 2607:7c80:54:e::133 as permitted sender) smtp.mailfrom=BATV+ba9daad91d8a220a3b0a+5769+infradead.org+hch@bombadil.srs.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=infradead.org; s=bombadil.20170209; h=Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From:Sender :Reply-To:Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From :Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Id:List-Help: List-Unsubscribe:List-Subscribe:List-Post:List-Owner:List-Archive; bh=vOVF1bL6OtEC3ny1W9eKFWhCTN+KLHMSW/CBbgd+PKs=; b=VLiBuzt/vCbOSNdVx6os79JBD6 vHnKMpAQlL5AlNNNY6kUIEWo3mmYqMBif4P0/ZHxfLKNTWQE6L38hwoB6FM1F0ZA1KeO9BEaW6pY3 mBFPUsqKlrtVvcfV6lhyDH/+kpOVNYu2XTmKzyeQOZJaVctSjzYIB/HsBFT04XhYZJ+yQHtRutUyY rlgjDy+3bo1jIA+zRDuX+K3H/XbszJ2OvhsNR50E2XE9haoeTXtRJ4q+QHlPLGvTWXWkeubhxn6eT LE8gxz8rM992Eh6JzZVeQKH71lO4dlkg6DVCB3M1WB/+EcR9ZHteJP6TUm4Mdw5IqZYEOLkf0fSOg zKJUUySQ==; Received: from 089144193064.atnat0002.highway.a1.net ([89.144.193.64] helo=localhost) by bombadil.infradead.org with esmtpsa (Exim 4.92 #3 (Red Hat Linux)) id 1haSag-0002rx-26; Mon, 10 Jun 2019 22:16:34 +0000 From: Christoph Hellwig To: Palmer Dabbelt Cc: Damien Le Moal , linux-riscv@lists.infradead.org, uclinux-dev@uclinux.org, linux-mm@kvack.org, linux-kernel@vger.kernel.org Subject: [PATCH 04/17] irqchip/sifive-plic: set max threshold for ignored handlers Date: Tue, 11 Jun 2019 00:16:08 +0200 Message-Id: <20190610221621.10938-5-hch@lst.de> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190610221621.10938-1-hch@lst.de> References: <20190610221621.10938-1-hch@lst.de> MIME-Version: 1.0 X-SRS-Rewrite: SMTP reverse-path rewritten from by bombadil.infradead.org. See http://www.infradead.org/rpr.html X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: X-Virus-Scanned: ClamAV using ClamSMTP When running in M-mode we still the S-mode plic handlers in the DT. Ignore them by setting the maximum threshold. Signed-off-by: Christoph Hellwig --- drivers/irqchip/irq-sifive-plic.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive-plic.c index cf755964f2f8..c72c036aea76 100644 --- a/drivers/irqchip/irq-sifive-plic.c +++ b/drivers/irqchip/irq-sifive-plic.c @@ -244,6 +244,7 @@ static int __init plic_init(struct device_node *node, struct plic_handler *handler; irq_hw_number_t hwirq; int cpu, hartid; + u32 threshold = 0; if (of_irq_parse_one(node, i, &parent)) { pr_err("failed to parse parent for context %d.\n", i); @@ -266,10 +267,16 @@ static int __init plic_init(struct device_node *node, continue; } + /* + * When running in M-mode we need to ignore the S-mode handler. + * Here we assume it always comes later, but that might be a + * little fragile. + */ handler = per_cpu_ptr(&plic_handlers, cpu); if (handler->present) { pr_warn("handler already present for context %d.\n", i); - continue; + threshold = 0xffffffff; + goto done; } handler->present = true; @@ -279,8 +286,9 @@ static int __init plic_init(struct device_node *node, handler->enable_base = plic_regs + ENABLE_BASE + i * ENABLE_PER_HART; +done: /* priority must be > threshold to trigger an interrupt */ - writel(0, handler->hart_base + CONTEXT_THRESHOLD); + writel(threshold, handler->hart_base + CONTEXT_THRESHOLD); for (hwirq = 1; hwirq <= nr_irqs; hwirq++) plic_toggle(handler, hwirq, 0); nr_handlers++; From patchwork Mon Jun 10 22:16:09 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christoph Hellwig X-Patchwork-Id: 10985559 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 10DA21515 for ; Mon, 10 Jun 2019 22:16:43 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 00C0427861 for ; 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See http://www.infradead.org/rpr.html X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: X-Virus-Scanned: ClamAV using ClamSMTP Switch to our own constant for the satp register instead of using the old name from a legacy version of the privileged spec. Signed-off-by: Christoph Hellwig --- arch/riscv/mm/context.c | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) diff --git a/arch/riscv/mm/context.c b/arch/riscv/mm/context.c index 89ceb3cbe218..beeb5d7f92ea 100644 --- a/arch/riscv/mm/context.c +++ b/arch/riscv/mm/context.c @@ -57,12 +57,7 @@ void switch_mm(struct mm_struct *prev, struct mm_struct *next, cpumask_clear_cpu(cpu, mm_cpumask(prev)); cpumask_set_cpu(cpu, mm_cpumask(next)); - /* - * Use the old spbtr name instead of using the current satp - * name to support binutils 2.29 which doesn't know about the - * privileged ISA 1.10 yet. - */ - csr_write(sptbr, virt_to_pfn(next->pgd) | SATP_MODE); + csr_write(CSR_SATP, virt_to_pfn(next->pgd) | SATP_MODE); local_flush_tlb_all(); flush_icache_deferred(next); From patchwork Mon Jun 10 22:16:10 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christoph Hellwig X-Patchwork-Id: 10985563 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id CF3FE1398 for ; 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[2607:7c80:54:e::133]) by mx.google.com with ESMTPS id 97si11234398ple.161.2019.06.10.15.16.41 for (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Mon, 10 Jun 2019 15:16:41 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of batv+ba9daad91d8a220a3b0a+5769+infradead.org+hch@bombadil.srs.infradead.org designates 2607:7c80:54:e::133 as permitted sender) client-ip=2607:7c80:54:e::133; Authentication-Results: mx.google.com; dkim=pass header.i=@infradead.org header.s=bombadil.20170209 header.b=g7MV9hKQ; spf=pass (google.com: best guess record for domain of batv+ba9daad91d8a220a3b0a+5769+infradead.org+hch@bombadil.srs.infradead.org designates 2607:7c80:54:e::133 as permitted sender) smtp.mailfrom=BATV+ba9daad91d8a220a3b0a+5769+infradead.org+hch@bombadil.srs.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=infradead.org; s=bombadil.20170209; h=Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From:Sender :Reply-To:Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From :Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Id:List-Help: List-Unsubscribe:List-Subscribe:List-Post:List-Owner:List-Archive; bh=lVE4VBqJB+KkG+FIxfoQqL75aQVlp7EZak10nik7k0k=; b=g7MV9hKQoNw5gI26t9jxExxpCz y+RoLH7nrhvOd0+tEwTwrMivkxztKInbGwugrmpiQFPeopqZoRhBHypBsX+F4rKxzss1ujMWclj2L V2ZngcPWW3tXn6sAIx1eV9VUPJfqbjvq8WK5ebICyPboFn5qZ3m95ENz1v70yAAt0F7E7bVo+1Yjv skAqfYXdAeo1RmOxNKqt2FyihTKFOXZubw9xhxq4COqdDGAHX/b2C0oRMvH5jv+ou/cPV7+SlC1LO lWDSUEv7+HmoZ2qD0Ji4RSL9S7vB/ZQg8bfcFXHneu7AvuwKzA4kPDZl+wsCwWQo8U0e+HsYnUBhM 3wbqTVdQ==; Received: from 089144193064.atnat0002.highway.a1.net ([89.144.193.64] helo=localhost) by bombadil.infradead.org with esmtpsa (Exim 4.92 #3 (Red Hat Linux)) id 1haSal-000319-AM; Mon, 10 Jun 2019 22:16:39 +0000 From: Christoph Hellwig To: Palmer Dabbelt Cc: Damien Le Moal , linux-riscv@lists.infradead.org, uclinux-dev@uclinux.org, linux-mm@kvack.org, linux-kernel@vger.kernel.org Subject: [PATCH 06/17] riscv: clear the instruction cache and all registers when booting Date: Tue, 11 Jun 2019 00:16:10 +0200 Message-Id: <20190610221621.10938-7-hch@lst.de> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190610221621.10938-1-hch@lst.de> References: <20190610221621.10938-1-hch@lst.de> MIME-Version: 1.0 X-SRS-Rewrite: SMTP reverse-path rewritten from by bombadil.infradead.org. See http://www.infradead.org/rpr.html X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: X-Virus-Scanned: ClamAV using ClamSMTP When we get booted we want a clear slate without any leaks from previous supervisors or the firmware. Flush the instruction cache and then clear all registers to known good values. This is really important for the upcoming nommu support that runs on M-mode, but can't really harm when running in S-mode either. Vaguely based on the concepts from opensbi. Signed-off-by: Christoph Hellwig --- arch/riscv/kernel/head.S | 83 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 83 insertions(+) diff --git a/arch/riscv/kernel/head.S b/arch/riscv/kernel/head.S index 4e46f31072da..5681179183d4 100644 --- a/arch/riscv/kernel/head.S +++ b/arch/riscv/kernel/head.S @@ -11,6 +11,7 @@ #include #include #include +#include __INIT ENTRY(_start) @@ -18,6 +19,12 @@ ENTRY(_start) csrw CSR_SIE, zero csrw CSR_SIP, zero + /* flush the instruction cache */ + fence.i + + /* Reset all registers except ra, a0,a1 */ + call reset_regs + /* Load the global pointer */ .option push .option norelax @@ -160,6 +167,82 @@ relocate: j .Lsecondary_park END(_start) +ENTRY(reset_regs) + li sp, 0 + li gp, 0 + li tp, 0 + li t0, 0 + li t1, 0 + li t2, 0 + li s0, 0 + li s1, 0 + li a2, 0 + li a3, 0 + li a4, 0 + li a5, 0 + li a6, 0 + li a7, 0 + li s2, 0 + li s3, 0 + li s4, 0 + li s5, 0 + li s6, 0 + li s7, 0 + li s8, 0 + li s9, 0 + li s10, 0 + li s11, 0 + li t3, 0 + li t4, 0 + li t5, 0 + li t6, 0 + csrw sscratch, 0 + +#ifdef CONFIG_FPU + csrr t0, misa + andi t0, t0, (COMPAT_HWCAP_ISA_F | COMPAT_HWCAP_ISA_D) + bnez t0, .Lreset_regs_done + + li t1, SR_FS + csrs sstatus, t1 + fmv.s.x f0, zero + fmv.s.x f1, zero + fmv.s.x f2, zero + fmv.s.x f3, zero + fmv.s.x f4, zero + fmv.s.x f5, zero + fmv.s.x f6, zero + fmv.s.x f7, zero + fmv.s.x f8, zero + fmv.s.x f9, zero + fmv.s.x f10, zero + fmv.s.x f11, zero + fmv.s.x f12, zero + fmv.s.x f13, zero + fmv.s.x f14, zero + fmv.s.x f15, zero + fmv.s.x f16, zero + fmv.s.x f17, zero + fmv.s.x f18, zero + fmv.s.x f19, zero + fmv.s.x f20, zero + fmv.s.x f21, zero + fmv.s.x f22, zero + fmv.s.x f23, zero + fmv.s.x f24, zero + fmv.s.x f25, zero + fmv.s.x f26, zero + fmv.s.x f27, zero + fmv.s.x f28, zero + fmv.s.x f29, zero + fmv.s.x f30, zero + fmv.s.x f31, zero + csrw fcsr, 0 +#endif /* CONFIG_FPU */ +.Lreset_regs_done: + ret +END(reset_regs) + __PAGE_ALIGNED_BSS /* Empty zero page */ .balign PAGE_SIZE From patchwork Mon Jun 10 22:16:11 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christoph Hellwig X-Patchwork-Id: 10985567 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 63ED31515 for ; Mon, 10 Jun 2019 22:16:49 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 535F827861 for ; Mon, 10 Jun 2019 22:16:49 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 47D8A28409; Mon, 10 Jun 2019 22:16:49 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.7 required=2.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,MAILING_LIST_MULTI,RCVD_IN_DNSWL_NONE autolearn=ham version=3.3.1 Received: from kanga.kvack.org (kanga.kvack.org [205.233.56.17]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id CA9DE27861 for ; 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[2607:7c80:54:e::133]) by mx.google.com with ESMTPS id u17si3359000pfc.210.2019.06.10.15.16.46 for (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Mon, 10 Jun 2019 15:16:46 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of batv+ba9daad91d8a220a3b0a+5769+infradead.org+hch@bombadil.srs.infradead.org designates 2607:7c80:54:e::133 as permitted sender) client-ip=2607:7c80:54:e::133; Authentication-Results: mx.google.com; dkim=pass header.i=@infradead.org header.s=bombadil.20170209 header.b=E1yML8b2; spf=pass (google.com: best guess record for domain of batv+ba9daad91d8a220a3b0a+5769+infradead.org+hch@bombadil.srs.infradead.org designates 2607:7c80:54:e::133 as permitted sender) smtp.mailfrom=BATV+ba9daad91d8a220a3b0a+5769+infradead.org+hch@bombadil.srs.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=infradead.org; s=bombadil.20170209; h=Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From:Sender :Reply-To:Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From :Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Id:List-Help: List-Unsubscribe:List-Subscribe:List-Post:List-Owner:List-Archive; bh=UEy/4Lyls0cszyUScQ4qCl6Em4CB1JokLTZUjPlbm8w=; b=E1yML8b29i76hIlU7NAyq0k3R9 IlsAjrwqtrMV5rSvZIVjbksh4yLw8z9HPXyGXRzvqVeDniIJ/ypaeeTob7ufpi5ztS2cuoIDcH5O4 hue0scRmZMTTwKa3+LP12tnFOxCj0/EbSj4GYGsYt2+nUSRmWOxBpfdbWcrn1MuQGX+E6WPn7zEig LItcuSFwwyPGSpjJPAOdMqxKU4o1BpaAt4bC8ZQn90KbVjoIzyixTM5ONrRIeproeDiwJ7HKgFffs e6sOlflVkQqvYHRWQWh7v4w1h5Su+R4f3Mgu34Ovom6EyZOgf6A3uFlETUFbJUBJR+JmUDnM7J0Eo iSptNjGg==; Received: from 089144193064.atnat0002.highway.a1.net ([89.144.193.64] helo=localhost) by bombadil.infradead.org with esmtpsa (Exim 4.92 #3 (Red Hat Linux)) id 1haSan-00039t-W3; Mon, 10 Jun 2019 22:16:42 +0000 From: Christoph Hellwig To: Palmer Dabbelt Cc: Damien Le Moal , linux-riscv@lists.infradead.org, uclinux-dev@uclinux.org, linux-mm@kvack.org, linux-kernel@vger.kernel.org Subject: [PATCH 07/17] riscv: refactor the IPI code Date: Tue, 11 Jun 2019 00:16:11 +0200 Message-Id: <20190610221621.10938-8-hch@lst.de> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190610221621.10938-1-hch@lst.de> References: <20190610221621.10938-1-hch@lst.de> MIME-Version: 1.0 X-SRS-Rewrite: SMTP reverse-path rewritten from by bombadil.infradead.org. See http://www.infradead.org/rpr.html X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: X-Virus-Scanned: ClamAV using ClamSMTP This prepare for adding native non-SBI IPI code. Signed-off-by: Christoph Hellwig --- arch/riscv/kernel/smp.c | 55 +++++++++++++++++++++++------------------ 1 file changed, 31 insertions(+), 24 deletions(-) diff --git a/arch/riscv/kernel/smp.c b/arch/riscv/kernel/smp.c index b2537ffa855c..91164204496c 100644 --- a/arch/riscv/kernel/smp.c +++ b/arch/riscv/kernel/smp.c @@ -89,13 +89,38 @@ static void ipi_stop(void) wait_for_interrupt(); } +static void send_ipi_mask(const struct cpumask *mask, enum ipi_message_type op) +{ + int cpuid, hartid; + struct cpumask hartid_mask; + + cpumask_clear(&hartid_mask); + mb(); + for_each_cpu(cpuid, mask) { + set_bit(op, &ipi_data[cpuid].bits); + hartid = cpuid_to_hartid_map(cpuid); + cpumask_set_cpu(hartid, &hartid_mask); + } + mb(); + sbi_send_ipi(cpumask_bits(&hartid_mask)); +} + +static void send_ipi_single(int cpu, enum ipi_message_type op) +{ + send_ipi_mask(cpumask_of(cpu), op); +} + +static inline void clear_ipi(void) +{ + csr_clear(CSR_SIP, SIE_SSIE); +} + void riscv_software_interrupt(void) { unsigned long *pending_ipis = &ipi_data[smp_processor_id()].bits; unsigned long *stats = ipi_data[smp_processor_id()].stats; - /* Clear pending IPI */ - csr_clear(CSR_SIP, SIE_SSIE); + clear_ipi(); while (true) { unsigned long ops; @@ -129,23 +154,6 @@ void riscv_software_interrupt(void) } } -static void -send_ipi_message(const struct cpumask *to_whom, enum ipi_message_type operation) -{ - int cpuid, hartid; - struct cpumask hartid_mask; - - cpumask_clear(&hartid_mask); - mb(); - for_each_cpu(cpuid, to_whom) { - set_bit(operation, &ipi_data[cpuid].bits); - hartid = cpuid_to_hartid_map(cpuid); - cpumask_set_cpu(hartid, &hartid_mask); - } - mb(); - sbi_send_ipi(cpumask_bits(&hartid_mask)); -} - static const char * const ipi_names[] = { [IPI_RESCHEDULE] = "Rescheduling interrupts", [IPI_CALL_FUNC] = "Function call interrupts", @@ -167,12 +175,12 @@ void show_ipi_stats(struct seq_file *p, int prec) void arch_send_call_function_ipi_mask(struct cpumask *mask) { - send_ipi_message(mask, IPI_CALL_FUNC); + send_ipi_mask(mask, IPI_CALL_FUNC); } void arch_send_call_function_single_ipi(int cpu) { - send_ipi_message(cpumask_of(cpu), IPI_CALL_FUNC); + send_ipi_single(cpu, IPI_CALL_FUNC); } void smp_send_stop(void) @@ -187,7 +195,7 @@ void smp_send_stop(void) if (system_state <= SYSTEM_RUNNING) pr_crit("SMP: stopping secondary CPUs\n"); - send_ipi_message(&mask, IPI_CPU_STOP); + send_ipi_mask(&mask, IPI_CPU_STOP); } /* Wait up to one second for other CPUs to stop */ @@ -202,6 +210,5 @@ void smp_send_stop(void) void smp_send_reschedule(int cpu) { - send_ipi_message(cpumask_of(cpu), IPI_RESCHEDULE); + send_ipi_single(cpu, IPI_RESCHEDULE); } - From patchwork Mon Jun 10 22:16:12 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christoph Hellwig X-Patchwork-Id: 10985571 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 7F1BC1398 for ; Mon, 10 Jun 2019 22:16:54 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 6907627861 for ; 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[2607:7c80:54:e::133]) by mx.google.com with ESMTPS id w23si10881580ply.230.2019.06.10.15.16.47 for (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Mon, 10 Jun 2019 15:16:47 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of batv+ba9daad91d8a220a3b0a+5769+infradead.org+hch@bombadil.srs.infradead.org designates 2607:7c80:54:e::133 as permitted sender) client-ip=2607:7c80:54:e::133; Authentication-Results: mx.google.com; dkim=pass header.i=@infradead.org header.s=bombadil.20170209 header.b="l+pd/i2d"; spf=pass (google.com: best guess record for domain of batv+ba9daad91d8a220a3b0a+5769+infradead.org+hch@bombadil.srs.infradead.org designates 2607:7c80:54:e::133 as permitted sender) smtp.mailfrom=BATV+ba9daad91d8a220a3b0a+5769+infradead.org+hch@bombadil.srs.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=infradead.org; s=bombadil.20170209; h=Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From:Sender :Reply-To:Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From :Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Id:List-Help: List-Unsubscribe:List-Subscribe:List-Post:List-Owner:List-Archive; bh=edfhO/B1ZsApTZbd8va179/6YnGC7AQPbtY4xxakn0Q=; b=l+pd/i2dlQPMV9Iu0e+URr5nZk hCZwKdiZasYcWYSFEUgblHkYsRQfZG5rYi0ke7ASmko5jWisCAh2Z1vF7QNS45068fwx8A1azmdBv y3AURB45DDQYY8rUX3NGCPENZysfF1e76JWREQold/Er4jB5uZM/pf0HGLon4Agd8G9zyoscI4zsX D4QrjF9i4nPunLq3FsEt8Nq6bBcW3ue8zIaY6o6NtGWvqOIbGMYkIOgLDhosQ1BjXZGyBblm9gQcq YM/elY5MRUXPv4rHGYegHZbI4oEE1lWk8EUIdmfLcxC5mYiEQRQb50Dl+RUeDXNKi1IT9lqz74ia7 6f/dRSJA==; Received: from 089144193064.atnat0002.highway.a1.net ([89.144.193.64] helo=localhost) by bombadil.infradead.org with esmtpsa (Exim 4.92 #3 (Red Hat Linux)) id 1haSaq-0003GB-Ut; Mon, 10 Jun 2019 22:16:45 +0000 From: Christoph Hellwig To: Palmer Dabbelt Cc: Damien Le Moal , linux-riscv@lists.infradead.org, uclinux-dev@uclinux.org, linux-mm@kvack.org, linux-kernel@vger.kernel.org Subject: [PATCH 08/17] riscv: abstract out CSR names for supervisor vs machine mode Date: Tue, 11 Jun 2019 00:16:12 +0200 Message-Id: <20190610221621.10938-9-hch@lst.de> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190610221621.10938-1-hch@lst.de> References: <20190610221621.10938-1-hch@lst.de> MIME-Version: 1.0 X-SRS-Rewrite: SMTP reverse-path rewritten from by bombadil.infradead.org. See http://www.infradead.org/rpr.html X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: X-Virus-Scanned: ClamAV using ClamSMTP Many of the privileged CSRs exist in a supervisor and machine version that are used very similarly. Provide a new X-naming layer so that we don't have to ifdef everywhere for M-mode Linux support. Contains contributions from Damien Le Moal . Signed-off-by: Christoph Hellwig --- arch/riscv/Kconfig | 4 ++ arch/riscv/include/asm/asm.h | 6 +++ arch/riscv/include/asm/csr.h | 58 ++++++++++++++++++++++++++-- arch/riscv/include/asm/irqflags.h | 12 +++--- arch/riscv/include/asm/processor.h | 2 +- arch/riscv/include/asm/ptrace.h | 16 ++++---- arch/riscv/include/asm/switch_to.h | 8 ++-- arch/riscv/kernel/asm-offsets.c | 8 ++-- arch/riscv/kernel/entry.S | 62 ++++++++++++++++-------------- arch/riscv/kernel/fpu.S | 8 ++-- arch/riscv/kernel/head.S | 16 ++++---- arch/riscv/kernel/irq.c | 4 +- arch/riscv/kernel/process.c | 15 ++++---- arch/riscv/kernel/signal.c | 21 +++++----- arch/riscv/kernel/traps.c | 16 ++++---- arch/riscv/lib/uaccess.S | 12 +++--- arch/riscv/mm/extable.c | 4 +- arch/riscv/mm/fault.c | 6 +-- drivers/clocksource/timer-riscv.c | 8 ++-- drivers/irqchip/irq-sifive-plic.c | 4 +- 20 files changed, 179 insertions(+), 111 deletions(-) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 2e3b60cdeef4..9f2ebd035e80 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -53,6 +53,10 @@ config RISCV select ARCH_HAS_MMIOWB select HAVE_EBPF_JIT if 64BIT +# set if we run in machine mode, cleared if we run in supervisor mode +config M_MODE + bool + config MMU def_bool y diff --git a/arch/riscv/include/asm/asm.h b/arch/riscv/include/asm/asm.h index 5a02b7d50940..14604f01e9f8 100644 --- a/arch/riscv/include/asm/asm.h +++ b/arch/riscv/include/asm/asm.h @@ -65,4 +65,10 @@ #error "Unexpected __SIZEOF_SHORT__" #endif +#ifdef CONFIG_M_MODE +# define Xret mret +#else +# define Xret sret +#endif + #endif /* _ASM_RISCV_ASM_H */ diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h index a18923fa23c8..026a761835b7 100644 --- a/arch/riscv/include/asm/csr.h +++ b/arch/riscv/include/asm/csr.h @@ -11,8 +11,11 @@ /* Status register flags */ #define SR_SIE _AC(0x00000002, UL) /* Supervisor Interrupt Enable */ +#define SR_MIE _AC(0x00000008, UL) /* Machine Interrupt Enable */ #define SR_SPIE _AC(0x00000020, UL) /* Previous Supervisor IE */ +#define SR_MPIE _AC(0x00000080, UL) /* Previous Machine IE */ #define SR_SPP _AC(0x00000100, UL) /* Previously Supervisor */ +#define SR_MPP _AC(0x00001800, UL) /* Previously Machine */ #define SR_SUM _AC(0x00040000, UL) /* Supervisor User Memory Access */ #define SR_FS _AC(0x00006000, UL) /* Floating-point Status */ @@ -44,8 +47,8 @@ #define SATP_MODE SATP_MODE_39 #endif -/* SCAUSE */ -#define SCAUSE_IRQ_FLAG (_AC(1, UL) << (__riscv_xlen - 1)) +/* *CAUSE */ +#define XCAUSE_IRQ_FLAG (_AC(1, UL) << (__riscv_xlen - 1)) #define IRQ_U_SOFT 0 #define IRQ_S_SOFT 1 @@ -67,11 +70,26 @@ #define EXC_LOAD_PAGE_FAULT 13 #define EXC_STORE_PAGE_FAULT 15 -/* SIE (Interrupt Enable) and SIP (Interrupt Pending) flags */ +/* MIE / MIP flags: */ +#define MIE_MSIE (_AC(0x1, UL) << IRQ_M_SOFT) +#define MIE_MTIE (_AC(0x1, UL) << IRQ_M_TIMER) +#define MIE_MEIE (_AC(0x1, UL) << IRQ_M_EXT) + +/* SIE / SIP flags: */ #define SIE_SSIE (_AC(0x1, UL) << IRQ_S_SOFT) #define SIE_STIE (_AC(0x1, UL) << IRQ_S_TIMER) #define SIE_SEIE (_AC(0x1, UL) << IRQ_S_EXT) +/* symbolic CSR names: */ +#define CSR_MSTATUS 0x300 +#define CSR_MIE 0x304 +#define CSR_MTVEC 0x305 +#define CSR_MSCRATCH 0x340 +#define CSR_MEPC 0x341 +#define CSR_MCAUSE 0x342 +#define CSR_MTVAL 0x343 +#define CSR_MIP 0x344 + #define CSR_CYCLE 0xc00 #define CSR_TIME 0xc01 #define CSR_INSTRET 0xc02 @@ -89,6 +107,40 @@ #define CSR_TIMEH 0xc81 #define CSR_INSTRETH 0xc82 +#ifdef CONFIG_M_MODE +# define CSR_XSTATUS CSR_MSTATUS +# define CSR_XIE CSR_MIE +# define CSR_XTVEC CSR_MTVEC +# define CSR_XSCRATCH CSR_MSCRATCH +# define CSR_XEPC CSR_MEPC +# define CSR_XCAUSE CSR_MCAUSE +# define CSR_XTVAL CSR_MTVAL +# define CSR_XIP CSR_MIP + +# define SR_XIE SR_MIE +# define SR_XPIE SR_MPIE +# define SR_XPP SR_MPP + +# define XIE_XTIE MIE_MTIE +# define XIE_XEIE MIE_MEIE +#else /* CONFIG_M_MODE */ +# define CSR_XSTATUS CSR_SSTATUS +# define CSR_XIE CSR_SIE +# define CSR_XTVEC CSR_STVEC +# define CSR_XSCRATCH CSR_SSCRATCH +# define CSR_XEPC CSR_SEPC +# define CSR_XCAUSE CSR_SCAUSE +# define CSR_XTVAL CSR_STVAL +# define CSR_XIP CSR_SIP + +# define SR_XIE SR_SIE +# define SR_XPIE SR_SPIE +# define SR_XPP SR_SPP + +# define XIE_XTIE SIE_STIE +# define XIE_XEIE SIE_SEIE +#endif /* CONFIG_M_MODE */ + #ifndef __ASSEMBLY__ #define csr_swap(csr, val) \ diff --git a/arch/riscv/include/asm/irqflags.h b/arch/riscv/include/asm/irqflags.h index e70f647ce3b7..ba2828a37d72 100644 --- a/arch/riscv/include/asm/irqflags.h +++ b/arch/riscv/include/asm/irqflags.h @@ -13,31 +13,31 @@ /* read interrupt enabled status */ static inline unsigned long arch_local_save_flags(void) { - return csr_read(CSR_SSTATUS); + return csr_read(CSR_XSTATUS); } /* unconditionally enable interrupts */ static inline void arch_local_irq_enable(void) { - csr_set(CSR_SSTATUS, SR_SIE); + csr_set(CSR_XSTATUS, SR_XIE); } /* unconditionally disable interrupts */ static inline void arch_local_irq_disable(void) { - csr_clear(CSR_SSTATUS, SR_SIE); + csr_clear(CSR_XSTATUS, SR_XIE); } /* get status and disable interrupts */ static inline unsigned long arch_local_irq_save(void) { - return csr_read_clear(CSR_SSTATUS, SR_SIE); + return csr_read_clear(CSR_XSTATUS, SR_XIE); } /* test flags */ static inline int arch_irqs_disabled_flags(unsigned long flags) { - return !(flags & SR_SIE); + return !(flags & SR_XIE); } /* test hardware interrupt enable bit */ @@ -49,7 +49,7 @@ static inline int arch_irqs_disabled(void) /* set interrupt enabled status */ static inline void arch_local_irq_restore(unsigned long flags) { - csr_set(CSR_SSTATUS, flags & SR_SIE); + csr_set(CSR_XSTATUS, flags & SR_XIE); } #endif /* _ASM_RISCV_IRQFLAGS_H */ diff --git a/arch/riscv/include/asm/processor.h b/arch/riscv/include/asm/processor.h index f539149d04c2..46f825e34575 100644 --- a/arch/riscv/include/asm/processor.h +++ b/arch/riscv/include/asm/processor.h @@ -42,7 +42,7 @@ struct thread_struct { ((struct pt_regs *)(task_stack_page(tsk) + THREAD_SIZE \ - ALIGN(sizeof(struct pt_regs), STACK_ALIGN))) -#define KSTK_EIP(tsk) (task_pt_regs(tsk)->sepc) +#define KSTK_EIP(tsk) (task_pt_regs(tsk)->xepc) #define KSTK_ESP(tsk) (task_pt_regs(tsk)->sp) diff --git a/arch/riscv/include/asm/ptrace.h b/arch/riscv/include/asm/ptrace.h index d48d1e13973c..7684d81d0e84 100644 --- a/arch/riscv/include/asm/ptrace.h +++ b/arch/riscv/include/asm/ptrace.h @@ -12,7 +12,7 @@ #ifndef __ASSEMBLY__ struct pt_regs { - unsigned long sepc; + unsigned long xepc; unsigned long ra; unsigned long sp; unsigned long gp; @@ -44,10 +44,10 @@ struct pt_regs { unsigned long t4; unsigned long t5; unsigned long t6; - /* Supervisor CSRs */ - unsigned long sstatus; - unsigned long sbadaddr; - unsigned long scause; + /* Supervisor/Machine CSRs */ + unsigned long xstatus; + unsigned long xbadaddr; + unsigned long xcause; /* a0 value before the syscall */ unsigned long orig_a0; }; @@ -58,18 +58,18 @@ struct pt_regs { #define REG_FMT "%08lx" #endif -#define user_mode(regs) (((regs)->sstatus & SR_SPP) == 0) +#define user_mode(regs) (((regs)->xstatus & SR_XPP) == 0) /* Helpers for working with the instruction pointer */ static inline unsigned long instruction_pointer(struct pt_regs *regs) { - return regs->sepc; + return regs->xepc; } static inline void instruction_pointer_set(struct pt_regs *regs, unsigned long val) { - regs->sepc = val; + regs->xepc = val; } #define profile_pc(regs) instruction_pointer(regs) diff --git a/arch/riscv/include/asm/switch_to.h b/arch/riscv/include/asm/switch_to.h index 853b65ef656d..4cbe33bb5dd7 100644 --- a/arch/riscv/include/asm/switch_to.h +++ b/arch/riscv/include/asm/switch_to.h @@ -16,13 +16,13 @@ extern void __fstate_restore(struct task_struct *restore_from); static inline void __fstate_clean(struct pt_regs *regs) { - regs->sstatus |= (regs->sstatus & ~(SR_FS)) | SR_FS_CLEAN; + regs->xstatus |= (regs->xstatus & ~(SR_FS)) | SR_FS_CLEAN; } static inline void fstate_save(struct task_struct *task, struct pt_regs *regs) { - if ((regs->sstatus & SR_FS) == SR_FS_DIRTY) { + if ((regs->xstatus & SR_FS) == SR_FS_DIRTY) { __fstate_save(task); __fstate_clean(regs); } @@ -31,7 +31,7 @@ static inline void fstate_save(struct task_struct *task, static inline void fstate_restore(struct task_struct *task, struct pt_regs *regs) { - if ((regs->sstatus & SR_FS) != SR_FS_OFF) { + if ((regs->xstatus & SR_FS) != SR_FS_OFF) { __fstate_restore(task); __fstate_clean(regs); } @@ -43,7 +43,7 @@ static inline void __switch_to_aux(struct task_struct *prev, struct pt_regs *regs; regs = task_pt_regs(prev); - if (unlikely(regs->sstatus & SR_SD)) + if (unlikely(regs->xstatus & SR_SD)) fstate_save(prev, regs); fstate_restore(next, task_pt_regs(next)); } diff --git a/arch/riscv/kernel/asm-offsets.c b/arch/riscv/kernel/asm-offsets.c index 9f5628c38ac9..d631ad41917b 100644 --- a/arch/riscv/kernel/asm-offsets.c +++ b/arch/riscv/kernel/asm-offsets.c @@ -71,7 +71,7 @@ void asm_offsets(void) OFFSET(TASK_THREAD_FCSR, task_struct, thread.fstate.fcsr); DEFINE(PT_SIZE, sizeof(struct pt_regs)); - OFFSET(PT_SEPC, pt_regs, sepc); + OFFSET(PT_XEPC, pt_regs, xepc); OFFSET(PT_RA, pt_regs, ra); OFFSET(PT_FP, pt_regs, s0); OFFSET(PT_S0, pt_regs, s0); @@ -105,9 +105,9 @@ void asm_offsets(void) OFFSET(PT_T6, pt_regs, t6); OFFSET(PT_GP, pt_regs, gp); OFFSET(PT_ORIG_A0, pt_regs, orig_a0); - OFFSET(PT_SSTATUS, pt_regs, sstatus); - OFFSET(PT_SBADADDR, pt_regs, sbadaddr); - OFFSET(PT_SCAUSE, pt_regs, scause); + OFFSET(PT_XSTATUS, pt_regs, xstatus); + OFFSET(PT_XBADADDR, pt_regs, xbadaddr); + OFFSET(PT_XCAUSE, pt_regs, xcause); /* * THREAD_{F,X}* might be larger than a S-type offset can handle, but diff --git a/arch/riscv/kernel/entry.S b/arch/riscv/kernel/entry.S index bc7a56e1ca6f..18eeb1eec9d5 100644 --- a/arch/riscv/kernel/entry.S +++ b/arch/riscv/kernel/entry.S @@ -26,14 +26,14 @@ /* * If coming from userspace, preserve the user thread pointer and load - * the kernel thread pointer. If we came from the kernel, sscratch - * will contain 0, and we should continue on the current TP. + * the kernel thread pointer. If we came from the kernel, the scratch + * register will contain 0, and we should continue on the current TP. */ - csrrw tp, CSR_SSCRATCH, tp + csrrw tp, CSR_XSCRATCH, tp bnez tp, _save_context _restore_kernel_tpsp: - csrr tp, CSR_SSCRATCH + csrr tp, CSR_XSCRATCH REG_S sp, TASK_TI_KERNEL_SP(tp) _save_context: REG_S sp, TASK_TI_USER_SP(tp) @@ -79,16 +79,16 @@ _save_context: li t0, SR_SUM | SR_FS REG_L s0, TASK_TI_USER_SP(tp) - csrrc s1, CSR_SSTATUS, t0 - csrr s2, CSR_SEPC - csrr s3, CSR_STVAL - csrr s4, CSR_SCAUSE - csrr s5, CSR_SSCRATCH + csrrc s1, CSR_XSTATUS, t0 + csrr s2, CSR_XEPC + csrr s3, CSR_XTVAL + csrr s4, CSR_XCAUSE + csrr s5, CSR_XSCRATCH REG_S s0, PT_SP(sp) - REG_S s1, PT_SSTATUS(sp) - REG_S s2, PT_SEPC(sp) - REG_S s3, PT_SBADADDR(sp) - REG_S s4, PT_SCAUSE(sp) + REG_S s1, PT_XSTATUS(sp) + REG_S s2, PT_XEPC(sp) + REG_S s3, PT_XBADADDR(sp) + REG_S s4, PT_XCAUSE(sp) REG_S s5, PT_TP(sp) .endm @@ -97,10 +97,10 @@ _save_context: * registers from the stack. */ .macro RESTORE_ALL - REG_L a0, PT_SSTATUS(sp) - REG_L a2, PT_SEPC(sp) - csrw CSR_SSTATUS, a0 - csrw CSR_SEPC, a2 + REG_L a0, PT_XSTATUS(sp) + REG_L a2, PT_XEPC(sp) + csrw CSR_XSTATUS, a0 + csrw CSR_XEPC, a2 REG_L x1, PT_RA(sp) REG_L x3, PT_GP(sp) @@ -144,10 +144,10 @@ ENTRY(handle_exception) SAVE_ALL /* - * Set sscratch register to 0, so that if a recursive exception + * Set the scratch register to 0, so that if a recursive exception * occurs, the exception vector knows it came from the kernel */ - csrw CSR_SSCRATCH, x0 + csrw CSR_XSCRATCH, x0 /* Load the global pointer */ .option push @@ -167,7 +167,7 @@ ENTRY(handle_exception) tail do_IRQ 1: /* Exceptions run with interrupts enabled */ - csrs sstatus, SR_SIE + csrs CSR_XSTATUS, SR_MIE /* Handle syscalls */ li t0, EXC_SYSCALL @@ -194,7 +194,7 @@ handle_syscall: * scall instruction on sret */ addi s2, s2, 0x4 - REG_S s2, PT_SEPC(sp) + REG_S s2, PT_XEPC(sp) /* Trace syscalls, but only if requested by the user. */ REG_L t0, TASK_TI_FLAGS(tp) andi t0, t0, _TIF_SYSCALL_WORK @@ -221,9 +221,15 @@ ret_from_syscall: bnez t0, handle_syscall_trace_exit ret_from_exception: - REG_L s0, PT_SSTATUS(sp) - csrc sstatus, SR_SIE + REG_L s0, PT_XSTATUS(sp) + csrc CSR_XSTATUS, SR_MIE +#ifdef CONFIG_M_MODE + /* the MPP value is too large to be used as an immediate arg for addi */ + li t0, SR_MPP + and s0, s0, t0 +#else andi s0, s0, SR_SPP +#endif bnez s0, resume_kernel resume_userspace: @@ -237,14 +243,14 @@ resume_userspace: REG_S s0, TASK_TI_KERNEL_SP(tp) /* - * Save TP into sscratch, so we can find the kernel data structures - * again. + * Save TP into the scratch register , so we can find the kernel data + * structures again. */ - csrw CSR_SSCRATCH, tp + csrw CSR_XSCRATCH, tp restore_all: RESTORE_ALL - sret + Xret #if IS_ENABLED(CONFIG_PREEMPT) resume_kernel: @@ -265,7 +271,7 @@ work_pending: bnez s1, work_resched work_notifysig: /* Handle pending signals and notify-resume requests */ - csrs sstatus, SR_SIE /* Enable interrupts for do_notify_resume() */ + csrs CSR_XSTATUS, SR_MIE /* Enable interrupts for do_notify_resume() */ move a0, sp /* pt_regs */ move a1, s0 /* current_thread_info->flags */ tail do_notify_resume diff --git a/arch/riscv/kernel/fpu.S b/arch/riscv/kernel/fpu.S index 1defb0618aff..1dade31f4564 100644 --- a/arch/riscv/kernel/fpu.S +++ b/arch/riscv/kernel/fpu.S @@ -23,7 +23,7 @@ ENTRY(__fstate_save) li a2, TASK_THREAD_F0 add a0, a0, a2 li t1, SR_FS - csrs sstatus, t1 + csrs CSR_XSTATUS, t1 frcsr t0 fsd f0, TASK_THREAD_F0_F0(a0) fsd f1, TASK_THREAD_F1_F0(a0) @@ -58,7 +58,7 @@ ENTRY(__fstate_save) fsd f30, TASK_THREAD_F30_F0(a0) fsd f31, TASK_THREAD_F31_F0(a0) sw t0, TASK_THREAD_FCSR_F0(a0) - csrc sstatus, t1 + csrc CSR_XSTATUS, t1 ret ENDPROC(__fstate_save) @@ -67,7 +67,7 @@ ENTRY(__fstate_restore) add a0, a0, a2 li t1, SR_FS lw t0, TASK_THREAD_FCSR_F0(a0) - csrs sstatus, t1 + csrs CSR_XSTATUS, t1 fld f0, TASK_THREAD_F0_F0(a0) fld f1, TASK_THREAD_F1_F0(a0) fld f2, TASK_THREAD_F2_F0(a0) @@ -101,6 +101,6 @@ ENTRY(__fstate_restore) fld f30, TASK_THREAD_F30_F0(a0) fld f31, TASK_THREAD_F31_F0(a0) fscsr t0 - csrc sstatus, t1 + csrc CSR_XSTATUS, t1 ret ENDPROC(__fstate_restore) diff --git a/arch/riscv/kernel/head.S b/arch/riscv/kernel/head.S index 5681179183d4..cb5691d82b0b 100644 --- a/arch/riscv/kernel/head.S +++ b/arch/riscv/kernel/head.S @@ -16,8 +16,8 @@ __INIT ENTRY(_start) /* Mask all interrupts */ - csrw CSR_SIE, zero - csrw CSR_SIP, zero + csrw CSR_XIE, zero + csrw CSR_XIP, zero /* flush the instruction cache */ fence.i @@ -36,7 +36,7 @@ ENTRY(_start) * floating point in kernel space */ li t0, SR_FS - csrc sstatus, t0 + csrc CSR_XSTATUS, t0 /* Pick one hart to run the main boot sequence */ la a3, hart_lottery @@ -85,7 +85,7 @@ relocate: /* Point stvec to virtual address of intruction after satp write */ la a0, 1f add a0, a0, a1 - csrw CSR_STVEC, a0 + csrw CSR_XTVEC, a0 /* Compute satp for kernel page tables, but don't load it yet */ la a2, swapper_pg_dir @@ -108,7 +108,7 @@ relocate: 1: /* Set trap vector to spin forever to help debug */ la a0, .Lsecondary_park - csrw CSR_STVEC, a0 + csrw CSR_XTVEC, a0 /* Reload the global pointer */ .option push @@ -134,7 +134,7 @@ relocate: /* Set trap vector to spin forever to help debug */ la a3, .Lsecondary_park - csrw CSR_STVEC, a3 + csrw CSR_XTVEC, a3 slli a3, a0, LGREG la a1, __cpu_up_stack_pointer @@ -196,7 +196,7 @@ ENTRY(reset_regs) li t4, 0 li t5, 0 li t6, 0 - csrw sscratch, 0 + csrw CSR_XSCRATCH, 0 #ifdef CONFIG_FPU csrr t0, misa @@ -204,7 +204,7 @@ ENTRY(reset_regs) bnez t0, .Lreset_regs_done li t1, SR_FS - csrs sstatus, t1 + csrs CSR_XSTATUS, t1 fmv.s.x f0, zero fmv.s.x f1, zero fmv.s.x f2, zero diff --git a/arch/riscv/kernel/irq.c b/arch/riscv/kernel/irq.c index 6d8659388c49..804ff70bb853 100644 --- a/arch/riscv/kernel/irq.c +++ b/arch/riscv/kernel/irq.c @@ -29,7 +29,7 @@ asmlinkage void __irq_entry do_IRQ(struct pt_regs *regs) struct pt_regs *old_regs = set_irq_regs(regs); irq_enter(); - switch (regs->scause & ~SCAUSE_IRQ_FLAG) { + switch (regs->xcause & ~XCAUSE_IRQ_FLAG) { case INTERRUPT_CAUSE_TIMER: riscv_timer_interrupt(); break; @@ -46,7 +46,7 @@ asmlinkage void __irq_entry do_IRQ(struct pt_regs *regs) handle_arch_irq(regs); break; default: - pr_alert("unexpected interrupt cause 0x%lx", regs->scause); + pr_alert("unexpected interrupt cause 0x%lx", regs->xcause); BUG(); } irq_exit(); diff --git a/arch/riscv/kernel/process.c b/arch/riscv/kernel/process.c index f23794bd1e90..1f03920d07d3 100644 --- a/arch/riscv/kernel/process.c +++ b/arch/riscv/kernel/process.c @@ -34,7 +34,7 @@ void show_regs(struct pt_regs *regs) show_regs_print_info(KERN_DEFAULT); pr_cont("sepc: " REG_FMT " ra : " REG_FMT " sp : " REG_FMT "\n", - regs->sepc, regs->ra, regs->sp); + regs->xepc, regs->ra, regs->sp); pr_cont(" gp : " REG_FMT " tp : " REG_FMT " t0 : " REG_FMT "\n", regs->gp, regs->tp, regs->t0); pr_cont(" t1 : " REG_FMT " t2 : " REG_FMT " s0 : " REG_FMT "\n", @@ -56,17 +56,17 @@ void show_regs(struct pt_regs *regs) pr_cont(" t5 : " REG_FMT " t6 : " REG_FMT "\n", regs->t5, regs->t6); - pr_cont("sstatus: " REG_FMT " sbadaddr: " REG_FMT " scause: " REG_FMT "\n", - regs->sstatus, regs->sbadaddr, regs->scause); + pr_cont("status: " REG_FMT " badaddr: " REG_FMT " cause: " REG_FMT "\n", + regs->xstatus, regs->xbadaddr, regs->xcause); } void start_thread(struct pt_regs *regs, unsigned long pc, unsigned long sp) { - regs->sstatus = SR_SPIE; + regs->xstatus = SR_XPIE; if (has_fpu) - regs->sstatus |= SR_FS_INITIAL; - regs->sepc = pc; + regs->xstatus |= SR_FS_INITIAL; + regs->xepc = pc; regs->sp = sp; set_fs(USER_DS); } @@ -101,7 +101,8 @@ int copy_thread(unsigned long clone_flags, unsigned long usp, const register unsigned long gp __asm__ ("gp"); memset(childregs, 0, sizeof(struct pt_regs)); childregs->gp = gp; - childregs->sstatus = SR_SPP | SR_SPIE; /* Supervisor, irqs on */ + /* Supervisor/Machine, irqs on: */ + childregs->xstatus = SR_XPP | SR_XPIE; p->thread.ra = (unsigned long)ret_from_kernel_thread; p->thread.s[0] = usp; /* fn */ diff --git a/arch/riscv/kernel/signal.c b/arch/riscv/kernel/signal.c index 1fe1b02e44d0..dfb26b64e17a 100644 --- a/arch/riscv/kernel/signal.c +++ b/arch/riscv/kernel/signal.c @@ -124,7 +124,7 @@ SYSCALL_DEFINE0(rt_sigreturn) pr_info_ratelimited( "%s[%d]: bad frame in %s: frame=%p pc=%p sp=%p\n", task->comm, task_pid_nr(task), __func__, - frame, (void *)regs->sepc, (void *)regs->sp); + frame, (void *)regs->xepc, (void *)regs->sp); } force_sig(SIGSEGV, task); return 0; @@ -199,7 +199,7 @@ static int setup_rt_frame(struct ksignal *ksig, sigset_t *set, * We always pass siginfo and mcontext, regardless of SA_SIGINFO, * since some things rely on this (e.g. glibc's debug/segfault.c). */ - regs->sepc = (unsigned long)ksig->ka.sa.sa_handler; + regs->xepc = (unsigned long)ksig->ka.sa.sa_handler; regs->sp = (unsigned long)frame; regs->a0 = ksig->sig; /* a0: signal number */ regs->a1 = (unsigned long)(&frame->info); /* a1: siginfo pointer */ @@ -208,7 +208,7 @@ static int setup_rt_frame(struct ksignal *ksig, sigset_t *set, #if DEBUG_SIG pr_info("SIG deliver (%s:%d): sig=%d pc=%p ra=%p sp=%p\n", current->comm, task_pid_nr(current), ksig->sig, - (void *)regs->sepc, (void *)regs->ra, frame); + (void *)regs->xepc, (void *)regs->ra, frame); #endif return 0; @@ -220,10 +220,9 @@ static void handle_signal(struct ksignal *ksig, struct pt_regs *regs) int ret; /* Are we from a system call? */ - if (regs->scause == EXC_SYSCALL) { + if (regs->xcause == EXC_SYSCALL) { /* Avoid additional syscall restarting via ret_from_exception */ - regs->scause = -1UL; - + regs->xcause = -1UL; /* If so, check system call restarting.. */ switch (regs->a0) { case -ERESTART_RESTARTBLOCK: @@ -239,7 +238,7 @@ static void handle_signal(struct ksignal *ksig, struct pt_regs *regs) /* fallthrough */ case -ERESTARTNOINTR: regs->a0 = regs->orig_a0; - regs->sepc -= 0x4; + regs->xepc -= 0x4; break; } } @@ -261,9 +260,9 @@ static void do_signal(struct pt_regs *regs) } /* Did we come from a system call? */ - if (regs->scause == EXC_SYSCALL) { + if (regs->xcause == EXC_SYSCALL) { /* Avoid additional syscall restarting via ret_from_exception */ - regs->scause = -1UL; + regs->xcause = -1UL; /* Restart the system call - no handlers present */ switch (regs->a0) { @@ -271,12 +270,12 @@ static void do_signal(struct pt_regs *regs) case -ERESTARTSYS: case -ERESTARTNOINTR: regs->a0 = regs->orig_a0; - regs->sepc -= 0x4; + regs->xepc -= 0x4; break; case -ERESTART_RESTARTBLOCK: regs->a0 = regs->orig_a0; regs->a7 = __NR_restart_syscall; - regs->sepc -= 0x4; + regs->xepc -= 0x4; break; } } diff --git a/arch/riscv/kernel/traps.c b/arch/riscv/kernel/traps.c index 6b32190ba73c..e028276928f8 100644 --- a/arch/riscv/kernel/traps.c +++ b/arch/riscv/kernel/traps.c @@ -40,7 +40,7 @@ void die(struct pt_regs *regs, const char *str) print_modules(); show_regs(regs); - ret = notify_die(DIE_OOPS, str, regs, 0, regs->scause, SIGSEGV); + ret = notify_die(DIE_OOPS, str, regs, 0, regs->xcause, SIGSEGV); bust_spinlocks(0); add_taint(TAINT_DIE, LOCKDEP_NOW_UNRELIABLE); @@ -84,7 +84,7 @@ static void do_trap_error(struct pt_regs *regs, int signo, int code, #define DO_ERROR_INFO(name, signo, code, str) \ asmlinkage void name(struct pt_regs *regs) \ { \ - do_trap_error(regs, signo, code, regs->sepc, "Oops - " str); \ + do_trap_error(regs, signo, code, regs->xepc, "Oops - " str); \ } DO_ERROR_INFO(do_trap_unknown, @@ -127,12 +127,12 @@ asmlinkage void do_trap_break(struct pt_regs *regs) if (!user_mode(regs)) { enum bug_trap_type type; - type = report_bug(regs->sepc, regs); + type = report_bug(regs->xepc, regs); switch (type) { case BUG_TRAP_TYPE_NONE: break; case BUG_TRAP_TYPE_WARN: - regs->sepc += get_break_insn_length(regs->sepc); + regs->xepc += get_break_insn_length(regs->xepc); break; case BUG_TRAP_TYPE_BUG: die(regs, "Kernel BUG"); @@ -140,7 +140,7 @@ asmlinkage void do_trap_break(struct pt_regs *regs) } #endif /* CONFIG_GENERIC_BUG */ - force_sig_fault(SIGTRAP, TRAP_BRKPT, (void __user *)(regs->sepc), current); + force_sig_fault(SIGTRAP, TRAP_BRKPT, (void __user *)(regs->xepc), current); } #ifdef CONFIG_GENERIC_BUG @@ -165,9 +165,9 @@ void __init trap_init(void) * Set sup0 scratch register to 0, indicating to exception vector * that we are presently executing in the kernel */ - csr_write(CSR_SSCRATCH, 0); + csr_write(CSR_XSCRATCH, 0); /* Set the exception vector address */ - csr_write(CSR_STVEC, &handle_exception); + csr_write(CSR_XTVEC, &handle_exception); /* Enable all interrupts */ - csr_write(CSR_SIE, -1); + csr_write(CSR_XIE, -1); } diff --git a/arch/riscv/lib/uaccess.S b/arch/riscv/lib/uaccess.S index 399e6f0c2d98..f47a2ea4dc89 100644 --- a/arch/riscv/lib/uaccess.S +++ b/arch/riscv/lib/uaccess.S @@ -18,7 +18,7 @@ ENTRY(__asm_copy_from_user) /* Enable access to user memory */ li t6, SR_SUM - csrs sstatus, t6 + csrs CSR_XSTATUS, t6 add a3, a1, a2 /* Use word-oriented copy only if low-order bits match */ @@ -47,7 +47,7 @@ ENTRY(__asm_copy_from_user) 3: /* Disable access to user memory */ - csrc sstatus, t6 + csrc CSR_XSTATUS, t6 li a0, 0 ret 4: /* Edge case: unalignment */ @@ -72,7 +72,7 @@ ENTRY(__clear_user) /* Enable access to user memory */ li t6, SR_SUM - csrs sstatus, t6 + csrs CSR_XSTATUS, t6 add a3, a0, a1 addi t0, a0, SZREG-1 @@ -94,7 +94,7 @@ ENTRY(__clear_user) 3: /* Disable access to user memory */ - csrc sstatus, t6 + csrc CSR_XSTATUS, t6 li a0, 0 ret 4: /* Edge case: unalignment */ @@ -114,11 +114,11 @@ ENDPROC(__clear_user) /* Fixup code for __copy_user(10) and __clear_user(11) */ 10: /* Disable access to user memory */ - csrs sstatus, t6 + csrs CSR_XSTATUS, t6 mv a0, a2 ret 11: - csrs sstatus, t6 + csrs CSR_XSTATUS, t6 mv a0, a1 ret .previous diff --git a/arch/riscv/mm/extable.c b/arch/riscv/mm/extable.c index 7aed9178d365..e0659deeb16b 100644 --- a/arch/riscv/mm/extable.c +++ b/arch/riscv/mm/extable.c @@ -15,9 +15,9 @@ int fixup_exception(struct pt_regs *regs) { const struct exception_table_entry *fixup; - fixup = search_exception_tables(regs->sepc); + fixup = search_exception_tables(regs->xepc); if (fixup) { - regs->sepc = fixup->fixup; + regs->xepc = fixup->fixup; return 1; } return 0; diff --git a/arch/riscv/mm/fault.c b/arch/riscv/mm/fault.c index fd7662afddea..82b110e9eaff 100644 --- a/arch/riscv/mm/fault.c +++ b/arch/riscv/mm/fault.c @@ -31,8 +31,8 @@ asmlinkage void do_page_fault(struct pt_regs *regs) int code = SEGV_MAPERR; vm_fault_t fault; - cause = regs->scause; - addr = regs->sbadaddr; + cause = regs->xcause; + addr = regs->xbadaddr; tsk = current; mm = tsk->mm; @@ -50,7 +50,7 @@ asmlinkage void do_page_fault(struct pt_regs *regs) goto vmalloc_fault; /* Enable interrupts if they were enabled in the parent context. */ - if (likely(regs->sstatus & SR_SPIE)) + if (likely(regs->xstatus & SR_XPIE)) local_irq_enable(); /* diff --git a/drivers/clocksource/timer-riscv.c b/drivers/clocksource/timer-riscv.c index 5e6038fbf115..2e2d363faabf 100644 --- a/drivers/clocksource/timer-riscv.c +++ b/drivers/clocksource/timer-riscv.c @@ -28,7 +28,7 @@ static int riscv_clock_next_event(unsigned long delta, struct clock_event_device *ce) { - csr_set(sie, SIE_STIE); + csr_set(CSR_XIE, XIE_XTIE); sbi_set_timer(get_cycles64() + delta); return 0; } @@ -70,13 +70,13 @@ static int riscv_timer_starting_cpu(unsigned int cpu) ce->cpumask = cpumask_of(cpu); clockevents_config_and_register(ce, riscv_timebase, 100, 0x7fffffff); - csr_set(sie, SIE_STIE); + csr_set(CSR_XIE, XIE_XTIE); return 0; } static int riscv_timer_dying_cpu(unsigned int cpu) { - csr_clear(sie, SIE_STIE); + csr_clear(CSR_XIE, XIE_XTIE); return 0; } @@ -85,7 +85,7 @@ void riscv_timer_interrupt(void) { struct clock_event_device *evdev = this_cpu_ptr(&riscv_clock_event); - csr_clear(sie, SIE_STIE); + csr_clear(CSR_XIE, XIE_XTIE); evdev->event_handler(evdev); } diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive-plic.c index c72c036aea76..4ee96ac90ea4 100644 --- a/drivers/irqchip/irq-sifive-plic.c +++ b/drivers/irqchip/irq-sifive-plic.c @@ -179,7 +179,7 @@ static void plic_handle_irq(struct pt_regs *regs) WARN_ON_ONCE(!handler->present); - csr_clear(sie, SIE_SEIE); + csr_clear(CSR_XIE, XIE_XEIE); while ((hwirq = readl(claim))) { int irq = irq_find_mapping(plic_irqdomain, hwirq); @@ -190,7 +190,7 @@ static void plic_handle_irq(struct pt_regs *regs) generic_handle_irq(irq); writel(hwirq, claim); } - csr_set(sie, SIE_SEIE); + csr_set(CSR_XIE, XIE_XEIE); } /* From patchwork Mon Jun 10 22:16:13 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christoph Hellwig X-Patchwork-Id: 10985575 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id F0A031515 for ; Mon, 10 Jun 2019 22:16:55 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id E0F7327861 for ; Mon, 10 Jun 2019 22:16:55 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id D59072844E; Mon, 10 Jun 2019 22:16:55 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.7 required=2.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,MAILING_LIST_MULTI,RCVD_IN_DNSWL_NONE autolearn=ham version=3.3.1 Received: from kanga.kvack.org (kanga.kvack.org [205.233.56.17]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 795D627861 for ; Mon, 10 Jun 2019 22:16:55 +0000 (UTC) Received: by kanga.kvack.org (Postfix) id 6789E6B0274; Mon, 10 Jun 2019 18:16:52 -0400 (EDT) Delivered-To: linux-mm-outgoing@kvack.org Received: by kanga.kvack.org (Postfix, from userid 40) id 629836B0275; Mon, 10 Jun 2019 18:16:52 -0400 (EDT) X-Original-To: int-list-linux-mm@kvack.org X-Delivered-To: int-list-linux-mm@kvack.org Received: by kanga.kvack.org (Postfix, from userid 63042) id 4A44F6B0276; Mon, 10 Jun 2019 18:16:52 -0400 (EDT) X-Original-To: linux-mm@kvack.org X-Delivered-To: linux-mm@kvack.org Received: from mail-pf1-f197.google.com (mail-pf1-f197.google.com [209.85.210.197]) by kanga.kvack.org (Postfix) with ESMTP id 10C356B0274 for ; Mon, 10 Jun 2019 18:16:52 -0400 (EDT) Received: by mail-pf1-f197.google.com with SMTP id u21so5010418pfn.15 for ; Mon, 10 Jun 2019 15:16:52 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:dkim-signature:from:to:cc:subject:date :message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=h6J+QiOYKdoEDaESTAbqz0t3lndQulVAC+cSepnSvyI=; b=WZSVR2AYUahexq4dS/cWZA5MhN1QLHiAP60SP+CikJHIMC+nxPepeViH/xwjrp1w8A +fAc66i8rJ1S5m1QooGuZ2/FCeRAUuU8Nh9aOwy50CzktKEK1WIOHJZJZcBDjCLPzUaG xSANjFouXFB89agOkK/H1H11Utx2vJXmZSiJj6nH7WDNaoSipRDxSlJYguonMAdX6FoX f9OIQjs20s2h8de7Z+UwNNIVBcC4JX+8pu1viTjfUKBAq7QjP1om2XRFF+exaqUcQFLU JO/YHK/9KLr25794mfgs54oDJ11XqBEUYVsMjCWCLl3ktT8423FkeWSWIHSzQ83aR36W rOaQ== X-Gm-Message-State: APjAAAUTTzatqCfb5yZMCYXFHzyr71NCnr4vzQFbf62FywUmQdeIA0KD sa8rUub9jQi+Y7kUznDVyQe7NZDs0xbRC2Wkxocb3Ns09u9q3QHFwgo6HIHnfzcDuWKyO/awHVM 3D6RXnMBpBE1pt5QHfbYvJ8kAg5qPzQv5Mhl05h81qoMMgViiLLzkc75eLSoT6x8= X-Received: by 2002:a17:902:29a7:: with SMTP id h36mr20551271plb.158.1560205011761; Mon, 10 Jun 2019 15:16:51 -0700 (PDT) X-Google-Smtp-Source: APXvYqw7WiWL591wiKyHDDtQgB1ut/+Y4S5yJhRg/ZhL+k0tAVnHcSjjrJmqjE+DnQqSn0IA6qUJ X-Received: by 2002:a17:902:29a7:: with SMTP id h36mr20551224plb.158.1560205011127; Mon, 10 Jun 2019 15:16:51 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1560205011; cv=none; d=google.com; s=arc-20160816; b=JWoJdq+i6It9KHXuoZzHVhH/AaUE+hGGnL3IOjB9u6yT8Hk318NYr5t0DXgNcYdGpC TQIWKrTr/g/OgI2yK9QqN/xaVcDi10N0Gh1EE4J6M+eAvys7i74g12ibsHf+/PsLJau/ /NQdmX88Zl1hHL4bNBShhJyXY6Ko2eRYiF8xIJro2l4LQxbyCIdWJsUPfSFh1OLYz20w iH97CGRZzFumv0MkgSe1xElGH82jzvSlCjajWHH1AwmHQh8cSjTwUn13vyToTbBjQCdd EszRrLnLSnqNZn131+0I5QGkBvkXIszmjORrvcUKIKwNPRVk2E/bQSTxSreX7sy1aCG5 /XfA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=h6J+QiOYKdoEDaESTAbqz0t3lndQulVAC+cSepnSvyI=; b=NyXt5XBX80/XwpQBnIWe8L/KfjMQyrSuNj2/XIQthaWHTU01YSMKrFe7fBA+COorrl HPZNy2s5iQd78GVkq2cAheRdTxQIHX27387XxzljAtDzs2jErD6SGLMrKSZlecIgtccg kOf8fHmVEEj9cUDhCKmGWtctGgp0X+PqMhtI6bd1n5n2RBICsJMURSmeHmYe4duTtPGR aR98xAYcmu/pM9OWIJdEyS/M8uAhk3hCsxFv5a26VJFDxZAhsJS82pZi8Oem/WXR42FX WrDqt6oRTitGY24PgIuldcMzMr5kgCr83eDo6WaGrvjsnXLovLAHT3zKhZKoej+lDEzT /pMA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@infradead.org header.s=bombadil.20170209 header.b=V8RFOZDd; spf=pass (google.com: best guess record for domain of batv+ba9daad91d8a220a3b0a+5769+infradead.org+hch@bombadil.srs.infradead.org designates 2607:7c80:54:e::133 as permitted sender) smtp.mailfrom=BATV+ba9daad91d8a220a3b0a+5769+infradead.org+hch@bombadil.srs.infradead.org Received: from bombadil.infradead.org (bombadil.infradead.org. [2607:7c80:54:e::133]) by mx.google.com with ESMTPS id p17si10519210plo.310.2019.06.10.15.16.51 for (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Mon, 10 Jun 2019 15:16:51 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of batv+ba9daad91d8a220a3b0a+5769+infradead.org+hch@bombadil.srs.infradead.org designates 2607:7c80:54:e::133 as permitted sender) client-ip=2607:7c80:54:e::133; Authentication-Results: mx.google.com; dkim=pass header.i=@infradead.org header.s=bombadil.20170209 header.b=V8RFOZDd; spf=pass (google.com: best guess record for domain of batv+ba9daad91d8a220a3b0a+5769+infradead.org+hch@bombadil.srs.infradead.org designates 2607:7c80:54:e::133 as permitted sender) smtp.mailfrom=BATV+ba9daad91d8a220a3b0a+5769+infradead.org+hch@bombadil.srs.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=infradead.org; s=bombadil.20170209; h=Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From:Sender :Reply-To:Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From :Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Id:List-Help: List-Unsubscribe:List-Subscribe:List-Post:List-Owner:List-Archive; bh=h6J+QiOYKdoEDaESTAbqz0t3lndQulVAC+cSepnSvyI=; b=V8RFOZDdLN5chLDdbnVNK9dlJ1 uM5w5wcrJO3+EZ1UHI1Wb7sGkact57SKESY7N/vrePmN6J9ymUTz0rocYalDwv/x5hQ+IMedgMgAc wl6Un4zMZ9Pe5bagqhYSEtmiqTQ5qDi9szAP/8e+L78AffT8CyyjsSzgAAzL+VkZHLWLqSw2PT+xi NPVGY7HJQr8dQJ2jazZN8KiG5Qyp03r+KVbBUNwDG4/KFvxHaoNQ4VU0M/CQbtQ3W1ydVkspsO9pe K2BhHiKUh/3u+35Jh73MILlEk6vMV5B3d6bz/+a+UG6CN8qTERqDNty7DmYmFk/eOhRcveplsenzs KD1Mi8vw==; Received: from 089144193064.atnat0002.highway.a1.net ([89.144.193.64] helo=localhost) by bombadil.infradead.org with esmtpsa (Exim 4.92 #3 (Red Hat Linux)) id 1haSat-0003Ll-PD; Mon, 10 Jun 2019 22:16:48 +0000 From: Christoph Hellwig To: Palmer Dabbelt Cc: Damien Le Moal , linux-riscv@lists.infradead.org, uclinux-dev@uclinux.org, linux-mm@kvack.org, linux-kernel@vger.kernel.org Subject: [PATCH 09/17] riscv: improve the default power off implementation Date: Tue, 11 Jun 2019 00:16:13 +0200 Message-Id: <20190610221621.10938-10-hch@lst.de> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190610221621.10938-1-hch@lst.de> References: <20190610221621.10938-1-hch@lst.de> MIME-Version: 1.0 X-SRS-Rewrite: SMTP reverse-path rewritten from by bombadil.infradead.org. See http://www.infradead.org/rpr.html X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: X-Virus-Scanned: ClamAV using ClamSMTP Only call the SBI code if we are not running in M mode, and if we didn't do the SBI call, or it didn't succeed call wfi in a loop to at least save some power. Signed-off-by: Christoph Hellwig --- arch/riscv/kernel/reset.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/arch/riscv/kernel/reset.c b/arch/riscv/kernel/reset.c index cfb6eb1d762d..17c810985ad0 100644 --- a/arch/riscv/kernel/reset.c +++ b/arch/riscv/kernel/reset.c @@ -8,8 +8,11 @@ static void default_power_off(void) { +#ifndef CONFIG_M_MODE sbi_shutdown(); - while (1); +#endif + while (1) + wait_for_interrupt(); } void (*pm_power_off)(void) = default_power_off; From patchwork Mon Jun 10 22:16:14 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christoph Hellwig X-Patchwork-Id: 10985581 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 6CFB41850 for ; Mon, 10 Jun 2019 22:16:59 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 5D46A27861 for ; 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[2607:7c80:54:e::133]) by mx.google.com with ESMTPS id m22si681537pjv.0.2019.06.10.15.16.53 for (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Mon, 10 Jun 2019 15:16:53 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of batv+ba9daad91d8a220a3b0a+5769+infradead.org+hch@bombadil.srs.infradead.org designates 2607:7c80:54:e::133 as permitted sender) client-ip=2607:7c80:54:e::133; Authentication-Results: mx.google.com; dkim=pass header.i=@infradead.org header.s=bombadil.20170209 header.b=AFD8YxeS; spf=pass (google.com: best guess record for domain of batv+ba9daad91d8a220a3b0a+5769+infradead.org+hch@bombadil.srs.infradead.org designates 2607:7c80:54:e::133 as permitted sender) smtp.mailfrom=BATV+ba9daad91d8a220a3b0a+5769+infradead.org+hch@bombadil.srs.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=infradead.org; s=bombadil.20170209; h=Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From:Sender :Reply-To:Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From :Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Id:List-Help: List-Unsubscribe:List-Subscribe:List-Post:List-Owner:List-Archive; bh=skB+ZnavO/i7RNPtU2wJ23sFxTsqRf+NEErVUiBdRM8=; b=AFD8YxeSHzKPrhOrVzUrstkaZD +8OdqXAaOst5JO4QkLywitZN4dFaWbbARKg5GXO3RJm/VkYKGOqro+hPA7tnJnDE/YgvXaNEIH4bJ B9yzk/F+V/3RLSO7rH+msjmI2PUqVhmOU7DyeYEvezXbna6F+DZ4iGYT6Bgg67977t9h+kGYB8wNJ nxJEPQzgAYpEzCGNdbpj66ymR8md3w6p0aNP+0dvUcLDPlt7nYDZHhCbyCFlKWC6NFHVKI/d5E6iC U1WGag3M8zWwklrDgiyzWAacRtBfvNTwWIjcygHWUODgqtsQ6yd374bwQK7U2lOekGf28z1VcIp4K DI1BjtIA==; Received: from 089144193064.atnat0002.highway.a1.net ([89.144.193.64] helo=localhost) by bombadil.infradead.org with esmtpsa (Exim 4.92 #3 (Red Hat Linux)) id 1haSaw-0003Rh-EJ; Mon, 10 Jun 2019 22:16:50 +0000 From: Christoph Hellwig To: Palmer Dabbelt Cc: Damien Le Moal , linux-riscv@lists.infradead.org, uclinux-dev@uclinux.org, linux-mm@kvack.org, linux-kernel@vger.kernel.org Subject: [PATCH 10/17] riscv: provide a flat entry loader Date: Tue, 11 Jun 2019 00:16:14 +0200 Message-Id: <20190610221621.10938-11-hch@lst.de> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190610221621.10938-1-hch@lst.de> References: <20190610221621.10938-1-hch@lst.de> MIME-Version: 1.0 X-SRS-Rewrite: SMTP reverse-path rewritten from by bombadil.infradead.org. See http://www.infradead.org/rpr.html X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: X-Virus-Scanned: ClamAV using ClamSMTP This allows just loading the kernel at a pre-set address without qemu going bonkers trying to map the ELF file. Signed-off-by: Christoph Hellwig --- arch/riscv/Makefile | 13 +++++++++---- arch/riscv/boot/Makefile | 7 ++++++- arch/riscv/boot/loader.S | 8 ++++++++ arch/riscv/boot/loader.lds | 14 ++++++++++++++ 4 files changed, 37 insertions(+), 5 deletions(-) create mode 100644 arch/riscv/boot/loader.S create mode 100644 arch/riscv/boot/loader.lds diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile index 6b0741c9f348..69dbb6cb72f3 100644 --- a/arch/riscv/Makefile +++ b/arch/riscv/Makefile @@ -84,13 +84,18 @@ PHONY += vdso_install vdso_install: $(Q)$(MAKE) $(build)=arch/riscv/kernel/vdso $@ -all: Image.gz +ifeq ($(CONFIG_M_MODE),y) +KBUILD_IMAGE := $(boot)/loader +else +KBUILD_IMAGE := $(boot)/Image.gz +endif +BOOT_TARGETS := Image Image.gz loader -Image: vmlinux - $(Q)$(MAKE) $(build)=$(boot) $(boot)/$@ +all: $(notdir $(KBUILD_IMAGE)) -Image.%: Image +$(BOOT_TARGETS): vmlinux $(Q)$(MAKE) $(build)=$(boot) $(boot)/$@ + @$(kecho) ' Kernel: $(boot)/$@ is ready' zinstall install: $(Q)$(MAKE) $(build)=$(boot) $@ diff --git a/arch/riscv/boot/Makefile b/arch/riscv/boot/Makefile index 0990a9fdbe5d..32d2addeddba 100644 --- a/arch/riscv/boot/Makefile +++ b/arch/riscv/boot/Makefile @@ -16,7 +16,7 @@ OBJCOPYFLAGS_Image :=-O binary -R .note -R .note.gnu.build-id -R .comment -S -targets := Image +targets := Image loader $(obj)/Image: vmlinux FORCE $(call if_changed,objcopy) @@ -24,6 +24,11 @@ $(obj)/Image: vmlinux FORCE $(obj)/Image.gz: $(obj)/Image FORCE $(call if_changed,gzip) +loader.o: $(src)/loader.S $(obj)/Image + +$(obj)/loader: $(obj)/loader.o $(obj)/Image FORCE + $(Q)$(LD) -T $(src)/loader.lds -o $@ $(obj)/loader.o + install: $(CONFIG_SHELL) $(srctree)/$(src)/install.sh $(KERNELRELEASE) \ $(obj)/Image System.map "$(INSTALL_PATH)" diff --git a/arch/riscv/boot/loader.S b/arch/riscv/boot/loader.S new file mode 100644 index 000000000000..5586e2610dbb --- /dev/null +++ b/arch/riscv/boot/loader.S @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0 + + .align 4 + .section .payload, "ax", %progbits + .globl _start +_start: + .incbin "arch/riscv/boot/Image" + diff --git a/arch/riscv/boot/loader.lds b/arch/riscv/boot/loader.lds new file mode 100644 index 000000000000..da9efd57bf44 --- /dev/null +++ b/arch/riscv/boot/loader.lds @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +OUTPUT_ARCH(riscv) +ENTRY(_start) + +SECTIONS +{ + . = 0x80000000; + + .payload : { + *(.payload) + . = ALIGN(8); + } +} From patchwork Mon Jun 10 22:16:15 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christoph Hellwig X-Patchwork-Id: 10985583 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 8E28F1398 for ; Mon, 10 Jun 2019 22:17:01 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 7E3DF27861 for ; Mon, 10 Jun 2019 22:17:01 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 72BE728409; Mon, 10 Jun 2019 22:17:01 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.7 required=2.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,MAILING_LIST_MULTI,RCVD_IN_DNSWL_NONE autolearn=ham version=3.3.1 Received: from kanga.kvack.org (kanga.kvack.org [205.233.56.17]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 1519627861 for ; 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[2607:7c80:54:e::133]) by mx.google.com with ESMTPS id s14si606387pji.28.2019.06.10.15.16.56 for (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Mon, 10 Jun 2019 15:16:56 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of batv+ba9daad91d8a220a3b0a+5769+infradead.org+hch@bombadil.srs.infradead.org designates 2607:7c80:54:e::133 as permitted sender) client-ip=2607:7c80:54:e::133; Authentication-Results: mx.google.com; dkim=pass header.i=@infradead.org header.s=bombadil.20170209 header.b=hjZqNyqd; spf=pass (google.com: best guess record for domain of batv+ba9daad91d8a220a3b0a+5769+infradead.org+hch@bombadil.srs.infradead.org designates 2607:7c80:54:e::133 as permitted sender) smtp.mailfrom=BATV+ba9daad91d8a220a3b0a+5769+infradead.org+hch@bombadil.srs.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=infradead.org; s=bombadil.20170209; h=Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From:Sender :Reply-To:Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From :Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Id:List-Help: List-Unsubscribe:List-Subscribe:List-Post:List-Owner:List-Archive; bh=j+NRg+K9rfMiwlW0bYi4vNNt08WFCywGA4nYguu1B0U=; b=hjZqNyqdr1u43sSDisZ2XDo17m RlVo9LN9scl2OxGt/dwaDGkdB83y0zZDUSm52W0+dBgXU+wK1Lk/QjvThHqlo6TtKB6j561pq+1Ek qFo2fAwKH+2lB5+dELbqJuzBoGnB1WNOZVLTuxs9NQ0dpCipCQrYd00Vc67dfe4yibJfz5Bl92zy3 YXl2c6SnHoMjqpAJ3wsTHchRvdLvjxjsDPAGWRXHA8R9YWtob/LeTvFSOlKhA+xjME9Dh7bdoFOQ2 7ZElZq9Jnb2ZWxLgtIAqJKgfTmBtTaxEAwgkIlTjeRzRWUnCEDugA31drUsWn7Sf/4Dx+7D7RYrIg RuzPWyyQ==; Received: from 089144193064.atnat0002.highway.a1.net ([89.144.193.64] helo=localhost) by bombadil.infradead.org with esmtpsa (Exim 4.92 #3 (Red Hat Linux)) id 1haSaz-0003Vu-7L; Mon, 10 Jun 2019 22:16:53 +0000 From: Christoph Hellwig To: Palmer Dabbelt Cc: Damien Le Moal , linux-riscv@lists.infradead.org, uclinux-dev@uclinux.org, linux-mm@kvack.org, linux-kernel@vger.kernel.org Subject: [PATCH 11/17] riscv: read hart ID from mhartid on boot Date: Tue, 11 Jun 2019 00:16:15 +0200 Message-Id: <20190610221621.10938-12-hch@lst.de> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190610221621.10938-1-hch@lst.de> References: <20190610221621.10938-1-hch@lst.de> MIME-Version: 1.0 X-SRS-Rewrite: SMTP reverse-path rewritten from by bombadil.infradead.org. See http://www.infradead.org/rpr.html X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: X-Virus-Scanned: ClamAV using ClamSMTP From: Damien Le Moal When in M-Mode, we can use the mhartid CSR to get the ID of the running HART. Doing so, direct M-Mode boot without firmware is possible. Signed-off-by: Damien Le Moal --- arch/riscv/kernel/head.S | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/riscv/kernel/head.S b/arch/riscv/kernel/head.S index cb5691d82b0b..e05379fd8b64 100644 --- a/arch/riscv/kernel/head.S +++ b/arch/riscv/kernel/head.S @@ -25,6 +25,14 @@ ENTRY(_start) /* Reset all registers except ra, a0,a1 */ call reset_regs +#ifdef CONFIG_M_MODE + /* + * The hartid in a0 is expected later on, and we have no firmware + * to hand it to us. + */ + csrr a0, mhartid +#endif + /* Load the global pointer */ .option push .option norelax From patchwork Mon Jun 10 22:16:16 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christoph Hellwig X-Patchwork-Id: 10985587 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 90B171398 for ; Mon, 10 Jun 2019 22:17:05 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 81AA927861 for ; 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[2607:7c80:54:e::133]) by mx.google.com with ESMTPS id a10si665410pjh.1.2019.06.10.15.17.00 for (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Mon, 10 Jun 2019 15:17:00 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of batv+ba9daad91d8a220a3b0a+5769+infradead.org+hch@bombadil.srs.infradead.org designates 2607:7c80:54:e::133 as permitted sender) client-ip=2607:7c80:54:e::133; Authentication-Results: mx.google.com; dkim=pass header.i=@infradead.org header.s=bombadil.20170209 header.b=Q5fNwQ6a; spf=pass (google.com: best guess record for domain of batv+ba9daad91d8a220a3b0a+5769+infradead.org+hch@bombadil.srs.infradead.org designates 2607:7c80:54:e::133 as permitted sender) smtp.mailfrom=BATV+ba9daad91d8a220a3b0a+5769+infradead.org+hch@bombadil.srs.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=infradead.org; s=bombadil.20170209; h=Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From:Sender :Reply-To:Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From :Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Id:List-Help: List-Unsubscribe:List-Subscribe:List-Post:List-Owner:List-Archive; bh=YGTMCWCkvPAIqxrMUQnFWBNeBjNUX65nDUARd571e3A=; b=Q5fNwQ6apOmQhrORfwQIEwDGiQ fZWhTqOdPwS0pHPDyxuWE8Q+/41Jv6To1QZiIFiNQxb65Q5GfczwZ7IxJvNPU/HRvGUqgJJuwwwlp ss8qj+eqxXY5SBJ/B1ZKGPA1Haj3OdUsvQthFlVOJvATuTyXC4+mvbQ2pkFhqH8MtcY1IVkZsIGnM +GOyIbhoCcpMq7a0jqcC0BwR+Yla8ZZOIhdRA2IXOpjjOLBPqDuNsTrozSCULLVbMI9/dFrXuNMwc yc2QVGjhnMrx7rI8KLAV2V+J6acucXevx3rX/L5rE66iIzfuy0mRgxvNNgFHydYDXy+IMnXDhNC2J EUpPtVSw==; Received: from 089144193064.atnat0002.highway.a1.net ([89.144.193.64] helo=localhost) by bombadil.infradead.org with esmtpsa (Exim 4.92 #3 (Red Hat Linux)) id 1haSb1-0003av-U9; Mon, 10 Jun 2019 22:16:56 +0000 From: Christoph Hellwig To: Palmer Dabbelt Cc: Damien Le Moal , linux-riscv@lists.infradead.org, uclinux-dev@uclinux.org, linux-mm@kvack.org, linux-kernel@vger.kernel.org Subject: [PATCH 12/17] riscv: provide native clint access for M-mode Date: Tue, 11 Jun 2019 00:16:16 +0200 Message-Id: <20190610221621.10938-13-hch@lst.de> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190610221621.10938-1-hch@lst.de> References: <20190610221621.10938-1-hch@lst.de> MIME-Version: 1.0 X-SRS-Rewrite: SMTP reverse-path rewritten from by bombadil.infradead.org. See http://www.infradead.org/rpr.html X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: X-Virus-Scanned: ClamAV using ClamSMTP RISC-V has the concept of a cpu level interrupt controller. Part of it is expose as bits in the status registers, and 2 new CSRs per privilege level in the instruction set, but the machanisms to trigger IPIs and timer events, as well as reading the actual timer value are not specified in the RISC-V spec but usually delegated to a block of MMIO registers. This patch adds support for those MMIO registers in the timer and IPI code. For now only the SiFive layout also supported by a few other implementations is supported, but the code should be easily extensible to others in the future. Signed-off-by: Christoph Hellwig --- arch/riscv/include/asm/clint.h | 17 +++++++++++ arch/riscv/include/asm/timex.h | 22 ++++++++++++++ arch/riscv/kernel/Makefile | 1 + arch/riscv/kernel/clint.c | 50 +++++++++++++++++++++++++++++++ arch/riscv/kernel/setup.c | 2 ++ arch/riscv/kernel/smp.c | 24 +++++++++++++++ arch/riscv/kernel/smpboot.c | 3 ++ drivers/clocksource/timer-riscv.c | 11 ++++++- 8 files changed, 129 insertions(+), 1 deletion(-) create mode 100644 arch/riscv/include/asm/clint.h create mode 100644 arch/riscv/kernel/clint.c diff --git a/arch/riscv/include/asm/clint.h b/arch/riscv/include/asm/clint.h new file mode 100644 index 000000000000..77559d07db33 --- /dev/null +++ b/arch/riscv/include/asm/clint.h @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0 +#ifndef _ASM_CLINT_H +#define _ASM_CLINT_H 1 + +#ifdef CONFIG_M_MODE +extern u32 __iomem *clint_ipi_base; +extern u64 __iomem *clint_time_val; +extern u64 __iomem *clint_time_cmp; + +void clint_init_one(void); +void clint_init_boot_cpu(void); +#else +#define clint_init_one() do { } while (0) +#define clint_init_boot_cpu() do { } while (0) +#endif /* CONFIG_M_MODE */ + +#endif /* _ASM_CLINT_H */ diff --git a/arch/riscv/include/asm/timex.h b/arch/riscv/include/asm/timex.h index 6a703ec9d796..2a95adf8bba0 100644 --- a/arch/riscv/include/asm/timex.h +++ b/arch/riscv/include/asm/timex.h @@ -10,6 +10,27 @@ typedef unsigned long cycles_t; +#ifdef CONFIG_M_MODE + +#include +#include + +static inline uint64_t get_cycles64(void) +{ + return readq_relaxed(clint_time_val); +} + +#ifdef CONFIG_64BIT +#define get_cycles get_cycles64 +#else +static inline cycles_t get_cycles(void) +{ + return readl_relaxed(clint_time_val); +} +#define get_cycles get_cycles +#endif /* CONFIG_64BIT */ + +#else /* CONFIG_M_MODE */ static inline cycles_t get_cycles_inline(void) { cycles_t n; @@ -40,6 +61,7 @@ static inline uint64_t get_cycles64(void) return ((u64)hi << 32) | lo; } #endif +#endif /* CONFIG_M_MODE */ #define ARCH_HAS_READ_CURRENT_TIMER diff --git a/arch/riscv/kernel/Makefile b/arch/riscv/kernel/Makefile index 2420d37d96de..f933c04f89db 100644 --- a/arch/riscv/kernel/Makefile +++ b/arch/riscv/kernel/Makefile @@ -29,6 +29,7 @@ obj-y += vdso.o obj-y += cacheinfo.o obj-y += vdso/ +obj-$(CONFIG_M_MODE) += clint.o obj-$(CONFIG_FPU) += fpu.o obj-$(CONFIG_SMP) += smpboot.o obj-$(CONFIG_SMP) += smp.o diff --git a/arch/riscv/kernel/clint.c b/arch/riscv/kernel/clint.c new file mode 100644 index 000000000000..a1089ccab9e3 --- /dev/null +++ b/arch/riscv/kernel/clint.c @@ -0,0 +1,50 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2019 Christoph Hellwig. + */ + +#include +#include +#include +#include +#include +#include + +/* + * This is the layout used by the SiFive clint, which is also shared by the qemu + * virt platform, and the Kendryte KD210 at least. + */ +#define CLINT_IPI_OFF 0 +#define CLINT_TIME_VAL_OFF 0xbff8 +#define CLINT_TIME_CMP_OFF 0x4000; + +u32 __iomem *clint_ipi_base; +u64 __iomem *clint_time_val; +u64 __iomem *clint_time_cmp; + +void clint_init_one(void) +{ + writel(0, clint_ipi_base + csr_read(mhartid)); +} + +void clint_init_boot_cpu(void) +{ + struct device_node *np; + void __iomem *base; + + np = of_find_compatible_node(NULL, NULL, "riscv,clint0"); + if (!np) { + panic("clint not found"); + return; + } + + base = of_iomap(np, 0); + if (!base) + panic("could not map CLINT"); + + clint_ipi_base = base + CLINT_IPI_OFF; + clint_time_val = base + CLINT_TIME_VAL_OFF; + clint_time_cmp = base + CLINT_TIME_CMP_OFF; + + clint_init_one(); +} diff --git a/arch/riscv/kernel/setup.c b/arch/riscv/kernel/setup.c index b92e6831d1ec..2892d82f474c 100644 --- a/arch/riscv/kernel/setup.c +++ b/arch/riscv/kernel/setup.c @@ -17,6 +17,7 @@ #include #include +#include #include #include #include @@ -67,6 +68,7 @@ void __init setup_arch(char **cmdline_p) setup_bootmem(); paging_init(); unflatten_device_tree(); + clint_init_boot_cpu(); #ifdef CONFIG_SWIOTLB swiotlb_init(1); diff --git a/arch/riscv/kernel/smp.c b/arch/riscv/kernel/smp.c index 91164204496c..e498a5e1615c 100644 --- a/arch/riscv/kernel/smp.c +++ b/arch/riscv/kernel/smp.c @@ -24,7 +24,9 @@ #include #include #include +#include +#include #include #include #include @@ -89,6 +91,27 @@ static void ipi_stop(void) wait_for_interrupt(); } +#ifdef CONFIG_M_MODE +static inline void send_ipi_single(int cpu, enum ipi_message_type op) +{ + set_bit(op, &ipi_data[cpu].bits); + writel(1, clint_ipi_base + cpuid_to_hartid_map(cpu)); +} + +static inline void send_ipi_mask(const struct cpumask *mask, + enum ipi_message_type op) +{ + int cpu; + + for_each_cpu(cpu, mask) + send_ipi_single(cpu, op); +} + +static inline void clear_ipi(void) +{ + writel(0, clint_ipi_base + cpuid_to_hartid_map(smp_processor_id())); +} +#else /* CONFIG_M_MODE */ static void send_ipi_mask(const struct cpumask *mask, enum ipi_message_type op) { int cpuid, hartid; @@ -114,6 +137,7 @@ static inline void clear_ipi(void) { csr_clear(CSR_SIP, SIE_SSIE); } +#endif /* CONFIG_M_MODE */ void riscv_software_interrupt(void) { diff --git a/arch/riscv/kernel/smpboot.c b/arch/riscv/kernel/smpboot.c index 7462a44304fe..5737c8e9c97d 100644 --- a/arch/riscv/kernel/smpboot.c +++ b/arch/riscv/kernel/smpboot.c @@ -23,6 +23,7 @@ #include #include #include +#include #include #include #include @@ -132,6 +133,8 @@ asmlinkage void __init smp_callin(void) { struct mm_struct *mm = &init_mm; + clint_init_one(); + /* All kernel threads share the same mm context. */ mmgrab(mm); current->active_mm = mm; diff --git a/drivers/clocksource/timer-riscv.c b/drivers/clocksource/timer-riscv.c index 2e2d363faabf..281915c3e6f2 100644 --- a/drivers/clocksource/timer-riscv.c +++ b/drivers/clocksource/timer-riscv.c @@ -24,7 +24,15 @@ * operations on the current hart. There is guaranteed to be exactly one timer * per hart on all RISC-V systems. */ - +#ifdef CONFIG_M_MODE +static int riscv_clock_next_event(unsigned long delta, + struct clock_event_device *ce) +{ + csr_set(CSR_XIE, XIE_XTIE); + writeq(get_cycles64() + delta, clint_time_cmp + csr_read(mhartid)); + return 0; +} +#else static int riscv_clock_next_event(unsigned long delta, struct clock_event_device *ce) { @@ -32,6 +40,7 @@ static int riscv_clock_next_event(unsigned long delta, sbi_set_timer(get_cycles64() + delta); return 0; } +#endif /* #ifdef CONFIG_M_MODE */ static DEFINE_PER_CPU(struct clock_event_device, riscv_clock_event) = { .name = "riscv_timer_clockevent", From patchwork Mon Jun 10 22:16:17 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christoph Hellwig X-Patchwork-Id: 10985591 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 504A31398 for ; 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[2607:7c80:54:e::133]) by mx.google.com with ESMTPS id y14si10121101plp.242.2019.06.10.15.17.02 for (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Mon, 10 Jun 2019 15:17:02 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of batv+ba9daad91d8a220a3b0a+5769+infradead.org+hch@bombadil.srs.infradead.org designates 2607:7c80:54:e::133 as permitted sender) client-ip=2607:7c80:54:e::133; Authentication-Results: mx.google.com; dkim=pass header.i=@infradead.org header.s=bombadil.20170209 header.b=HYzdqScq; spf=pass (google.com: best guess record for domain of batv+ba9daad91d8a220a3b0a+5769+infradead.org+hch@bombadil.srs.infradead.org designates 2607:7c80:54:e::133 as permitted sender) smtp.mailfrom=BATV+ba9daad91d8a220a3b0a+5769+infradead.org+hch@bombadil.srs.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=infradead.org; s=bombadil.20170209; h=Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From:Sender :Reply-To:Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From :Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Id:List-Help: List-Unsubscribe:List-Subscribe:List-Post:List-Owner:List-Archive; bh=QKrZKqm9xX7/gKntli3kjDV0bZW8VwVWFoBUswi6ZbI=; b=HYzdqScqmkY7UiWle5zIbeTQxB xAaMr/ZfGK4+A4BsJ5aOUoSPqE28fsB+yMZOlybdB1UXrqELmw+bYb4UkDygioEZJLyLXzSwu5b9T RR3p1S0mfl5j4HUD5uC7CVBybbIA70S1ijnk2verWrm7Kv+GloqVOyxM0s6R8ttKoZ5gVXgqe+0GW G8CVSJ8/f8L3eNpcK7/RXE+2tTBTpjjHMSHnXuvHBrLtpcjJ3j0GVBhVwxnb2HU3xQpytpJg5wQ7i AgQEsDxj3AVOp2HN3Mx75AHv9Ot77lIpZcF79Vptpno7EtiUhExdJ63JzCYn/We9DAD4KLv90G55B M8X8Gapw==; Received: from 089144193064.atnat0002.highway.a1.net ([89.144.193.64] helo=localhost) by bombadil.infradead.org with esmtpsa (Exim 4.92 #3 (Red Hat Linux)) id 1haSb4-0003fy-NB; Mon, 10 Jun 2019 22:16:59 +0000 From: Christoph Hellwig To: Palmer Dabbelt Cc: Damien Le Moal , linux-riscv@lists.infradead.org, uclinux-dev@uclinux.org, linux-mm@kvack.org, linux-kernel@vger.kernel.org Subject: [PATCH 13/17] riscv: implement remote sfence.i natively for M-mode Date: Tue, 11 Jun 2019 00:16:17 +0200 Message-Id: <20190610221621.10938-14-hch@lst.de> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190610221621.10938-1-hch@lst.de> References: <20190610221621.10938-1-hch@lst.de> MIME-Version: 1.0 X-SRS-Rewrite: SMTP reverse-path rewritten from by bombadil.infradead.org. See http://www.infradead.org/rpr.html X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: X-Virus-Scanned: ClamAV using ClamSMTP The RISC-V ISA only supports flushing the instruction cache for the local CPU core. For normal S-mode Linux remote flushing is offloaded to machine mode using ecalls, but for M-mode Linux we'll have to do it ourselves. Use the same implementation as all the existing open source SBI implementations by just doing an IPI to all remote cores to execute th sfence.i instruction on every live core. Signed-off-by: Christoph Hellwig --- arch/riscv/mm/cacheflush.c | 31 +++++++++++++++++++++++++++---- 1 file changed, 27 insertions(+), 4 deletions(-) diff --git a/arch/riscv/mm/cacheflush.c b/arch/riscv/mm/cacheflush.c index 9ebcff8ba263..10875ea1065e 100644 --- a/arch/riscv/mm/cacheflush.c +++ b/arch/riscv/mm/cacheflush.c @@ -10,10 +10,35 @@ #include +#ifdef CONFIG_M_MODE +static void ipi_remote_fence_i(void *info) +{ + return local_flush_icache_all(); +} + +void flush_icache_all(void) +{ + on_each_cpu(ipi_remote_fence_i, NULL, 1); +} + +static void flush_icache_cpumask(const cpumask_t *mask) +{ + on_each_cpu_mask(mask, ipi_remote_fence_i, NULL, 1); +} +#else /* CONFIG_M_MODE */ void flush_icache_all(void) { sbi_remote_fence_i(NULL); } +static void flush_icache_cpumask(const cpumask_t *mask) +{ + cpumask_t hmask; + + cpumask_clear(&hmask); + riscv_cpuid_to_hartid_mask(mask, &hmask); + sbi_remote_fence_i(hmask.bits); +} +#endif /* CONFIG_M_MODE */ /* * Performs an icache flush for the given MM context. RISC-V has no direct @@ -28,7 +53,7 @@ void flush_icache_all(void) void flush_icache_mm(struct mm_struct *mm, bool local) { unsigned int cpu; - cpumask_t others, hmask, *mask; + cpumask_t others, *mask; preempt_disable(); @@ -47,9 +72,7 @@ void flush_icache_mm(struct mm_struct *mm, bool local) cpumask_andnot(&others, mm_cpumask(mm), cpumask_of(cpu)); local |= cpumask_empty(&others); if (mm != current->active_mm || !local) { - cpumask_clear(&hmask); - riscv_cpuid_to_hartid_mask(&others, &hmask); - sbi_remote_fence_i(hmask.bits); + flush_icache_cpumask(&others); } else { /* * It's assumed that at least one strongly ordered operation is From patchwork Mon Jun 10 22:16:18 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christoph Hellwig X-Patchwork-Id: 10985595 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 44FFE1515 for ; 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[2607:7c80:54:e::133]) by mx.google.com with ESMTPS id 32si10879245plc.152.2019.06.10.15.17.04 for (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Mon, 10 Jun 2019 15:17:04 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of batv+ba9daad91d8a220a3b0a+5769+infradead.org+hch@bombadil.srs.infradead.org designates 2607:7c80:54:e::133 as permitted sender) client-ip=2607:7c80:54:e::133; Authentication-Results: mx.google.com; dkim=pass header.i=@infradead.org header.s=bombadil.20170209 header.b=DClxskAq; spf=pass (google.com: best guess record for domain of batv+ba9daad91d8a220a3b0a+5769+infradead.org+hch@bombadil.srs.infradead.org designates 2607:7c80:54:e::133 as permitted sender) smtp.mailfrom=BATV+ba9daad91d8a220a3b0a+5769+infradead.org+hch@bombadil.srs.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=infradead.org; s=bombadil.20170209; h=Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From:Sender :Reply-To:Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From :Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Id:List-Help: List-Unsubscribe:List-Subscribe:List-Post:List-Owner:List-Archive; bh=4ocWky3c08iK0yepv2gQs0SBg5KjT+xunPaTv4oC5uw=; b=DClxskAqPYBFK2k3TMB5K7R+nZ z9U0LsZbiV3WZgHBzl0PPjdk6qWGeEdJiS1YtZ0SKEHrHuRODqonx6dexyzM7838Hd1RDMSO1GsPI 5EP7DM/TJru3t1osBnbbuJ4pgDh64/bYNN/M2AJKc64NE8wqqi5FwaR8miqqNxK1yv+Nr7ZBLmLGY HyrwouU9iQMTFYKtVWSyaDqYnmdvhj3W95zAH6aUxsCJ0wqUzs3dI9TW92uoHJf+tzVaURVvyLntw 384Ro2sNdxWU/qybRIdirBfbpimN6YNMOLxWG2AwEV39Emf87QmpodZMzd3x4MOix5y77HeGJdgd4 ow+VBniA==; Received: from 089144193064.atnat0002.highway.a1.net ([89.144.193.64] helo=localhost) by bombadil.infradead.org with esmtpsa (Exim 4.92 #3 (Red Hat Linux)) id 1haSb7-0003jm-Gv; Mon, 10 Jun 2019 22:17:01 +0000 From: Christoph Hellwig To: Palmer Dabbelt Cc: Damien Le Moal , linux-riscv@lists.infradead.org, uclinux-dev@uclinux.org, linux-mm@kvack.org, linux-kernel@vger.kernel.org Subject: [PATCH 14/17] riscv: poison SBI calls for M-mode Date: Tue, 11 Jun 2019 00:16:18 +0200 Message-Id: <20190610221621.10938-15-hch@lst.de> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190610221621.10938-1-hch@lst.de> References: <20190610221621.10938-1-hch@lst.de> MIME-Version: 1.0 X-SRS-Rewrite: SMTP reverse-path rewritten from by bombadil.infradead.org. See http://www.infradead.org/rpr.html X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: X-Virus-Scanned: ClamAV using ClamSMTP There is no SBI when we run in M-mode, so fail the compile for any code trying to use SBI calls. Signed-off-by: Christoph Hellwig --- arch/riscv/include/asm/sbi.h | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h index 21134b3ef404..1e17f07eadaf 100644 --- a/arch/riscv/include/asm/sbi.h +++ b/arch/riscv/include/asm/sbi.h @@ -8,6 +8,7 @@ #include +#ifndef CONFIG_M_MODE #define SBI_SET_TIMER 0 #define SBI_CONSOLE_PUTCHAR 1 #define SBI_CONSOLE_GETCHAR 2 @@ -94,4 +95,5 @@ static inline void sbi_remote_sfence_vma_asid(const unsigned long *hart_mask, SBI_CALL_4(SBI_REMOTE_SFENCE_VMA_ASID, hart_mask, start, size, asid); } -#endif +#endif /* CONFIG_M_MODE */ +#endif /* _ASM_RISCV_SBI_H */ From patchwork Mon Jun 10 22:16:19 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christoph Hellwig X-Patchwork-Id: 10985601 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id A3B751850 for ; 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See http://www.infradead.org/rpr.html X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: X-Virus-Scanned: ClamAV using ClamSMTP From: Damien Le Moal Do not allow selecting SBI related options with MMU option not set. Signed-off-by: Damien Le Moal Signed-off-by: Christoph Hellwig --- drivers/tty/hvc/Kconfig | 2 +- drivers/tty/serial/Kconfig | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/tty/hvc/Kconfig b/drivers/tty/hvc/Kconfig index 4d22b911111f..5a1ab6b536ff 100644 --- a/drivers/tty/hvc/Kconfig +++ b/drivers/tty/hvc/Kconfig @@ -89,7 +89,7 @@ config HVC_DCC config HVC_RISCV_SBI bool "RISC-V SBI console support" - depends on RISCV + depends on RISCV && !M_MODE select HVC_DRIVER help This enables support for console output via RISC-V SBI calls, which diff --git a/drivers/tty/serial/Kconfig b/drivers/tty/serial/Kconfig index 0d31251e04cc..59dba9f9e466 100644 --- a/drivers/tty/serial/Kconfig +++ b/drivers/tty/serial/Kconfig @@ -88,7 +88,7 @@ config SERIAL_EARLYCON_ARM_SEMIHOST config SERIAL_EARLYCON_RISCV_SBI bool "Early console using RISC-V SBI" - depends on RISCV + depends on RISCV && !M_MODE select SERIAL_CORE select SERIAL_CORE_CONSOLE select SERIAL_EARLYCON From patchwork Mon Jun 10 22:16:20 2019 Content-Type: text/plain; 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[2607:7c80:54:e::133]) by mx.google.com with ESMTPS id r130si10745521pgr.509.2019.06.10.15.17.09 for (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Mon, 10 Jun 2019 15:17:09 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of batv+ba9daad91d8a220a3b0a+5769+infradead.org+hch@bombadil.srs.infradead.org designates 2607:7c80:54:e::133 as permitted sender) client-ip=2607:7c80:54:e::133; Authentication-Results: mx.google.com; dkim=pass header.i=@infradead.org header.s=bombadil.20170209 header.b=qU78Z5cn; spf=pass (google.com: best guess record for domain of batv+ba9daad91d8a220a3b0a+5769+infradead.org+hch@bombadil.srs.infradead.org designates 2607:7c80:54:e::133 as permitted sender) smtp.mailfrom=BATV+ba9daad91d8a220a3b0a+5769+infradead.org+hch@bombadil.srs.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=infradead.org; s=bombadil.20170209; h=Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From:Sender :Reply-To:Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From :Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Id:List-Help: List-Unsubscribe:List-Subscribe:List-Post:List-Owner:List-Archive; bh=+BjmfBU5ZU5hXn/L4jPTIPV2WW0RF6JWpSgCnxtzPjA=; b=qU78Z5cnfCWCw2IhCl3vEc+Nk4 x8G++H0NEOUJ2ys+ciqLUxac+QBlvsUkpd58ip9As/SDTEYoUd6K3iDHsMzJhb9GK/WT/8GqqNR7+ flS1vwCdfmtYwSiPtpMV9Ee/sIFyYw2+YerekgTEhM2bcO/WmW90zlrNKNFtBdzWLEm0igIIjjY8c tLXGh8crZITiRR7SGBzNoyUGtH1tmAZQaqebPQJLEKEemcHXz2qzWCI/JhExzdlzvYAAeSF/YRhBq smOc+AA8QBT/bWdWvC1lO2M8Jgu7vvrmKIOohSZNknUQvPhQEqYpq7+yut5oiPHq/CCikZkpCygu4 KCmqITAg==; Received: from 089144193064.atnat0002.highway.a1.net ([89.144.193.64] helo=localhost) by bombadil.infradead.org with esmtpsa (Exim 4.92 #3 (Red Hat Linux)) id 1haSbC-0003uj-M6; Mon, 10 Jun 2019 22:17:07 +0000 From: Christoph Hellwig To: Palmer Dabbelt Cc: Damien Le Moal , linux-riscv@lists.infradead.org, uclinux-dev@uclinux.org, linux-mm@kvack.org, linux-kernel@vger.kernel.org Subject: [PATCH 16/17] riscv: use the correct interrupt levels for M-mode Date: Tue, 11 Jun 2019 00:16:20 +0200 Message-Id: <20190610221621.10938-17-hch@lst.de> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190610221621.10938-1-hch@lst.de> References: <20190610221621.10938-1-hch@lst.de> MIME-Version: 1.0 X-SRS-Rewrite: SMTP reverse-path rewritten from by bombadil.infradead.org. See http://www.infradead.org/rpr.html X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: X-Virus-Scanned: ClamAV using ClamSMTP The numerical levels for External/Timer/Software interrupts differ between S-mode and M-mode. Signed-off-by: Christoph Hellwig --- arch/riscv/kernel/irq.c | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/arch/riscv/kernel/irq.c b/arch/riscv/kernel/irq.c index 804ff70bb853..9566aabbe50b 100644 --- a/arch/riscv/kernel/irq.c +++ b/arch/riscv/kernel/irq.c @@ -14,9 +14,15 @@ /* * Possible interrupt causes: */ -#define INTERRUPT_CAUSE_SOFTWARE IRQ_S_SOFT -#define INTERRUPT_CAUSE_TIMER IRQ_S_TIMER -#define INTERRUPT_CAUSE_EXTERNAL IRQ_S_EXT +#ifdef CONFIG_M_MODE +# define INTERRUPT_CAUSE_SOFTWARE IRQ_M_SOFT +# define INTERRUPT_CAUSE_TIMER IRQ_M_TIMER +# define INTERRUPT_CAUSE_EXTERNAL IRQ_M_EXT +#else +# define INTERRUPT_CAUSE_SOFTWARE IRQ_S_SOFT +# define INTERRUPT_CAUSE_TIMER IRQ_S_TIMER +# define INTERRUPT_CAUSE_EXTERNAL IRQ_S_EXT +#endif /* CONFIG_M_MODE */ int arch_show_interrupts(struct seq_file *p, int prec) { From patchwork Mon Jun 10 22:16:21 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christoph Hellwig X-Patchwork-Id: 10985607 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id EAC081398 for ; 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[2607:7c80:54:e::133]) by mx.google.com with ESMTPS id s201si11172047pgs.522.2019.06.10.15.17.11 for (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Mon, 10 Jun 2019 15:17:11 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of batv+ba9daad91d8a220a3b0a+5769+infradead.org+hch@bombadil.srs.infradead.org designates 2607:7c80:54:e::133 as permitted sender) client-ip=2607:7c80:54:e::133; Authentication-Results: mx.google.com; dkim=pass header.i=@infradead.org header.s=bombadil.20170209 header.b=dxGk6F2Y; spf=pass (google.com: best guess record for domain of batv+ba9daad91d8a220a3b0a+5769+infradead.org+hch@bombadil.srs.infradead.org designates 2607:7c80:54:e::133 as permitted sender) smtp.mailfrom=BATV+ba9daad91d8a220a3b0a+5769+infradead.org+hch@bombadil.srs.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=infradead.org; s=bombadil.20170209; h=Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From:Sender :Reply-To:Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From :Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Id:List-Help: List-Unsubscribe:List-Subscribe:List-Post:List-Owner:List-Archive; bh=GnQQwDoyeMsVwpNhsIl5ogtUOz8VW4eyaNutWMXN+nQ=; b=dxGk6F2Yb/3oks3mGkCGWuEPio 1j11uiQHsMpaHd49K+I1m3KSPcIJrBTdXyB3shR5ggQO1wu6kJnkKJ7QhpgjHcx2RMAbB46ue3qy/ BVOO0JLiMqaNRZu1TSCHR+Q2HX26WWRgMiUX9iEB5gteafESghHrgSyTsp5OXSW5qVlRgwc3z1GVA K5T/qfO3RdLQdPnN7mR3FQg2hq5C898Ax1mcS262iKsnbDTMLKICS2GIFyjjEotLggG+t+wepj3u8 jvS/k1wJpxBpIwTDi4EjtBoKzkSk1w8bBA7VWNyX6/Xe/KNkBB/URmP7ayxz2bGAlwt5fm+WZRbi3 tRIkfF9Q==; Received: from 089144193064.atnat0002.highway.a1.net ([89.144.193.64] helo=localhost) by bombadil.infradead.org with esmtpsa (Exim 4.92 #3 (Red Hat Linux)) id 1haSbF-0003z5-Cy; Mon, 10 Jun 2019 22:17:09 +0000 From: Christoph Hellwig To: Palmer Dabbelt Cc: Damien Le Moal , linux-riscv@lists.infradead.org, uclinux-dev@uclinux.org, linux-mm@kvack.org, linux-kernel@vger.kernel.org Subject: [PATCH 17/17] riscv: add nommu support Date: Tue, 11 Jun 2019 00:16:21 +0200 Message-Id: <20190610221621.10938-18-hch@lst.de> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190610221621.10938-1-hch@lst.de> References: <20190610221621.10938-1-hch@lst.de> MIME-Version: 1.0 X-SRS-Rewrite: SMTP reverse-path rewritten from by bombadil.infradead.org. See http://www.infradead.org/rpr.html X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: X-Virus-Scanned: ClamAV using ClamSMTP The kernel runs in M-mode without using page tables, and thus doesn't can run bare metal without help from additional firmware. Most of the patch is just stubbing out code not needed without page tables, but there is an interesting detail in the signals implementation: - The normal RISC-V syscall ABI only implements rt_sigreturn as VDSO entry point, but the ELF VDSO is not supported for nommu Linux. We instead copy the code to call the syscall onto the stack. In addition to enabling the nommu code a new defconfig for a small kernel image that can run in nommu mode on qemu is also provided, to run a kernel in qemu you can use the following command line: qemu-system-riscv64 -smp 2 -m 64 -machine virt -nographic \ -kernel arch/riscv/boot/loader \ -drive file=rootfs.ext2,format=raw,id=hd0 \ -device virtio-blk-device,drive=hd0 Contains contributions from Damien Le Moal . Signed-off-by: Christoph Hellwig --- arch/riscv/Kconfig | 24 +++++--- arch/riscv/configs/nommu_virt_defconfig | 78 +++++++++++++++++++++++++ arch/riscv/include/asm/elf.h | 4 +- arch/riscv/include/asm/futex.h | 6 ++ arch/riscv/include/asm/io.h | 4 ++ arch/riscv/include/asm/mmu.h | 3 + arch/riscv/include/asm/page.h | 12 +++- arch/riscv/include/asm/pgalloc.h | 2 + arch/riscv/include/asm/pgtable.h | 38 ++++++++---- arch/riscv/include/asm/tlbflush.h | 7 ++- arch/riscv/include/asm/uaccess.h | 4 ++ arch/riscv/kernel/Makefile | 3 +- arch/riscv/kernel/entry.S | 11 ++++ arch/riscv/kernel/head.S | 6 ++ arch/riscv/kernel/signal.c | 17 +++++- arch/riscv/lib/Makefile | 8 +-- arch/riscv/mm/Makefile | 3 +- arch/riscv/mm/cacheflush.c | 2 + arch/riscv/mm/context.c | 2 + arch/riscv/mm/init.c | 2 + 20 files changed, 200 insertions(+), 36 deletions(-) create mode 100644 arch/riscv/configs/nommu_virt_defconfig diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 9f2ebd035e80..41edb314ec67 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -27,13 +27,13 @@ config RISCV select GENERIC_IRQ_SHOW select GENERIC_PCI_IOMAP select GENERIC_SCHED_CLOCK - select GENERIC_STRNCPY_FROM_USER - select GENERIC_STRNLEN_USER + select GENERIC_STRNCPY_FROM_USER if MMU + select GENERIC_STRNLEN_USER if MMU select GENERIC_SMP_IDLE_THREAD select GENERIC_ATOMIC64 if !64BIT select HAVE_ARCH_AUDITSYSCALL select HAVE_MEMBLOCK_NODE_MAP - select HAVE_DMA_CONTIGUOUS + select HAVE_DMA_CONTIGUOUS if MMU select HAVE_FUTEX_CMPXCHG if FUTEX select HAVE_PERF_EVENTS select HAVE_SYSCALL_TRACEPOINTS @@ -48,6 +48,7 @@ config RISCV select PCI_DOMAINS_GENERIC if PCI select PCI_MSI if PCI select RISCV_TIMER + select UACCESS_MEMCPY if !MMU select GENERIC_IRQ_MULTI_HANDLER select ARCH_HAS_PTE_SPECIAL select ARCH_HAS_MMIOWB @@ -56,9 +57,14 @@ config RISCV # set if we run in machine mode, cleared if we run in supervisor mode config M_MODE bool + default y if !MMU config MMU - def_bool y + bool "MMU-based Paged Memory Management Support" + default y + help + Select if you want MMU-based virtualised addressing space + support by paged memory management. If unsure, say 'Y'. config ZONE_DMA32 bool @@ -67,6 +73,7 @@ config ZONE_DMA32 config PAGE_OFFSET hex default 0xC0000000 if 32BIT && MAXPHYSMEM_2GB + default 0x80000000 if 64BIT && !MMU default 0xffffffff80000000 if 64BIT && MAXPHYSMEM_2GB default 0xffffffe000000000 if 64BIT && MAXPHYSMEM_128GB @@ -94,7 +101,7 @@ config GENERIC_HWEIGHT def_bool y config FIX_EARLYCON_MEM - def_bool y + def_bool CONFIG_MMU config PGTABLE_LEVELS int @@ -117,6 +124,7 @@ config ARCH_RV32I select GENERIC_LIB_ASHRDI3 select GENERIC_LIB_LSHRDI3 select GENERIC_LIB_UCMPDI2 + select MMU config ARCH_RV64I bool "RV64I" @@ -125,9 +133,9 @@ config ARCH_RV64I select HAVE_FUNCTION_TRACER select HAVE_FUNCTION_GRAPH_TRACER select HAVE_FTRACE_MCOUNT_RECORD - select HAVE_DYNAMIC_FTRACE - select HAVE_DYNAMIC_FTRACE_WITH_REGS - select SWIOTLB + select HAVE_DYNAMIC_FTRACE if MMU + select HAVE_DYNAMIC_FTRACE_WITH_REGS if HAVE_DYNAMIC_FTRACE + select SWIOTLB if MMU endchoice diff --git a/arch/riscv/configs/nommu_virt_defconfig b/arch/riscv/configs/nommu_virt_defconfig new file mode 100644 index 000000000000..cf74e179bf90 --- /dev/null +++ b/arch/riscv/configs/nommu_virt_defconfig @@ -0,0 +1,78 @@ +# CONFIG_CPU_ISOLATION is not set +CONFIG_LOG_BUF_SHIFT=16 +CONFIG_PRINTK_SAFE_LOG_BUF_SHIFT=12 +CONFIG_BLK_DEV_INITRD=y +# CONFIG_RD_BZIP2 is not set +# CONFIG_RD_LZMA is not set +# CONFIG_RD_XZ is not set +# CONFIG_RD_LZO is not set +# CONFIG_RD_LZ4 is not set +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_EXPERT=y +# CONFIG_SYSFS_SYSCALL is not set +# CONFIG_FHANDLE is not set +# CONFIG_BASE_FULL is not set +# CONFIG_EPOLL is not set +# CONFIG_SIGNALFD is not set +# CONFIG_TIMERFD is not set +# CONFIG_EVENTFD is not set +# CONFIG_AIO is not set +# CONFIG_IO_URING is not set +# CONFIG_ADVISE_SYSCALLS is not set +# CONFIG_MEMBARRIER is not set +# CONFIG_KALLSYMS is not set +# CONFIG_VM_EVENT_COUNTERS is not set +# CONFIG_COMPAT_BRK is not set +CONFIG_SLOB=y +# CONFIG_SLAB_MERGE_DEFAULT is not set +# CONFIG_MMU is not set +CONFIG_MAXPHYSMEM_2GB=y +CONFIG_SMP=y +CONFIG_CMDLINE="root=/dev/vda rw earlycon=uart8250,mmio,0x10000000,115200n8 console=ttyS0" +CONFIG_CMDLINE_FORCE=y +# CONFIG_BLK_DEV_BSG is not set +CONFIG_PARTITION_ADVANCED=y +# CONFIG_MSDOS_PARTITION is not set +# CONFIG_EFI_PARTITION is not set +# CONFIG_MQ_IOSCHED_DEADLINE is not set +# CONFIG_MQ_IOSCHED_KYBER is not set +CONFIG_BINFMT_FLAT=y +# CONFIG_COREDUMP is not set +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +# CONFIG_FW_LOADER is not set +# CONFIG_ALLOW_DEV_COREDUMP is not set +CONFIG_VIRTIO_BLK=y +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_SERIO is not set +# CONFIG_LEGACY_PTYS is not set +# CONFIG_LDISC_AUTOLOAD is not set +# CONFIG_DEVMEM is not set +CONFIG_SERIAL_8250=y +# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_NR_UARTS=1 +CONFIG_SERIAL_8250_RUNTIME_UARTS=1 +CONFIG_SERIAL_OF_PLATFORM=y +# CONFIG_HW_RANDOM is not set +# CONFIG_HWMON is not set +# CONFIG_LCD_CLASS_DEVICE is not set +# CONFIG_BACKLIGHT_CLASS_DEVICE is not set +# CONFIG_VGA_CONSOLE is not set +# CONFIG_HID is not set +# CONFIG_USB_SUPPORT is not set +CONFIG_VIRTIO_MMIO=y +CONFIG_VIRTIO_MMIO_CMDLINE_DEVICES=y +CONFIG_SIFIVE_PLIC=y +# CONFIG_VALIDATE_FS_PARSER is not set +CONFIG_EXT2_FS=y +# CONFIG_DNOTIFY is not set +# CONFIG_INOTIFY_USER is not set +# CONFIG_MISC_FILESYSTEMS is not set +CONFIG_LSM="[]" +CONFIG_PRINTK_TIME=y +# CONFIG_SCHED_DEBUG is not set +# CONFIG_RCU_TRACE is not set +# CONFIG_FTRACE is not set +# CONFIG_RUNTIME_TESTING_MENU is not set diff --git a/arch/riscv/include/asm/elf.h b/arch/riscv/include/asm/elf.h index ef04084bf0de..d83a4efd052b 100644 --- a/arch/riscv/include/asm/elf.h +++ b/arch/riscv/include/asm/elf.h @@ -56,16 +56,16 @@ extern unsigned long elf_hwcap; */ #define ELF_PLATFORM (NULL) +#ifdef CONFIG_MMU #define ARCH_DLINFO \ do { \ NEW_AUX_ENT(AT_SYSINFO_EHDR, \ (elf_addr_t)current->mm->context.vdso); \ } while (0) - - #define ARCH_HAS_SETUP_ADDITIONAL_PAGES struct linux_binprm; extern int arch_setup_additional_pages(struct linux_binprm *bprm, int uses_interp); +#endif /* CONFIG_MMU */ #endif /* _ASM_RISCV_ELF_H */ diff --git a/arch/riscv/include/asm/futex.h b/arch/riscv/include/asm/futex.h index 4ad6409c4647..418564b96dc4 100644 --- a/arch/riscv/include/asm/futex.h +++ b/arch/riscv/include/asm/futex.h @@ -12,6 +12,12 @@ #include #include +/* We don't even really need the extable code, but for now keep it simple */ +#ifndef CONFIG_MMU +#define __enable_user_access() do { } while (0) +#define __disable_user_access() do { } while (0) +#endif + #define __futex_atomic_op(insn, ret, oldval, uaddr, oparg) \ { \ uintptr_t tmp; \ diff --git a/arch/riscv/include/asm/io.h b/arch/riscv/include/asm/io.h index fc1189ad3777..d39a8f03e85e 100644 --- a/arch/riscv/include/asm/io.h +++ b/arch/riscv/include/asm/io.h @@ -14,6 +14,7 @@ #include #include +#ifdef CONFIG_MMU extern void __iomem *ioremap(phys_addr_t offset, unsigned long size); /* @@ -26,6 +27,9 @@ extern void __iomem *ioremap(phys_addr_t offset, unsigned long size); #define ioremap_wt(addr, size) ioremap((addr), (size)) extern void iounmap(volatile void __iomem *addr); +#else +#define pgprot_noncached(x) (x) +#endif /* CONFIG_MMU */ /* Generic IO read/write. These perform native-endian accesses. */ #define __raw_writeb __raw_writeb diff --git a/arch/riscv/include/asm/mmu.h b/arch/riscv/include/asm/mmu.h index 151476fb58cb..967eacb01ab5 100644 --- a/arch/riscv/include/asm/mmu.h +++ b/arch/riscv/include/asm/mmu.h @@ -10,6 +10,9 @@ #ifndef __ASSEMBLY__ typedef struct { +#ifndef CONFIG_MMU + unsigned long end_brk; +#endif void *vdso; #ifdef CONFIG_SMP /* A local icache flush is needed before user execution can resume. */ diff --git a/arch/riscv/include/asm/page.h b/arch/riscv/include/asm/page.h index 8ddb6c7fedac..df0256a9a965 100644 --- a/arch/riscv/include/asm/page.h +++ b/arch/riscv/include/asm/page.h @@ -78,8 +78,14 @@ typedef struct page *pgtable_t; #define PTE_FMT "%08lx" #endif +#ifdef CONFIG_MMU extern unsigned long va_pa_offset; extern unsigned long pfn_base; +#define ARCH_PFN_OFFSET (pfn_base) +#else +#define va_pa_offset 0 +#define ARCH_PFN_OFFSET (PAGE_OFFSET >> PAGE_SHIFT) +#endif /* CONFIG_MMU */ extern unsigned long max_low_pfn; extern unsigned long min_low_pfn; @@ -101,9 +107,7 @@ extern unsigned long min_low_pfn; #define phys_to_page(paddr) (pfn_to_page(phys_to_pfn(paddr))) #define pfn_valid(pfn) \ - (((pfn) >= pfn_base) && (((pfn)-pfn_base) < max_mapnr)) - -#define ARCH_PFN_OFFSET (pfn_base) + (((pfn) >= ARCH_PFN_OFFSET) && (((pfn) - ARCH_PFN_OFFSET) < max_mapnr)) #endif /* __ASSEMBLY__ */ @@ -115,8 +119,10 @@ extern unsigned long min_low_pfn; #include #include +#ifdef CONFIG_MMU /* vDSO support */ /* We do define AT_SYSINFO_EHDR but don't use the gate mechanism */ #define __HAVE_ARCH_GATE_AREA +#endif /* CONFIG_MMU */ #endif /* _ASM_RISCV_PAGE_H */ diff --git a/arch/riscv/include/asm/pgalloc.h b/arch/riscv/include/asm/pgalloc.h index eb8b0195f27f..8d60c862d2f9 100644 --- a/arch/riscv/include/asm/pgalloc.h +++ b/arch/riscv/include/asm/pgalloc.h @@ -10,6 +10,7 @@ #include #include +#ifdef CONFIG_MMU static inline void pmd_populate_kernel(struct mm_struct *mm, pmd_t *pmd, pte_t *pte) { @@ -106,6 +107,7 @@ do { \ pgtable_page_dtor(pte); \ tlb_remove_page((tlb), pte); \ } while (0) +#endif /* CONFIG_MMU */ static inline void check_pgt_cache(void) { diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h index f7c3f7de15f2..dd6a63648e4a 100644 --- a/arch/riscv/include/asm/pgtable.h +++ b/arch/riscv/include/asm/pgtable.h @@ -24,6 +24,7 @@ #include #endif /* CONFIG_64BIT */ +#ifdef CONFIG_MMU /* Number of entries in the page global directory */ #define PTRS_PER_PGD (PAGE_SIZE / sizeof(pgd_t)) /* Number of entries in the page table */ @@ -31,7 +32,6 @@ /* Number of PGD entries that a user-mode program can use */ #define USER_PTRS_PER_PGD (TASK_SIZE / PGDIR_SIZE) -#define FIRST_USER_ADDRESS 0 /* Page protection bits */ #define _PAGE_BASE (_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_USER) @@ -81,13 +81,6 @@ extern pgd_t swapper_pg_dir[]; #define __S110 PAGE_SHARED_EXEC #define __S111 PAGE_SHARED_EXEC -/* - * ZERO_PAGE is a global shared page that is always zero, - * used for zero-mapped memory areas, etc. - */ -extern unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)]; -#define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page)) - static inline int pmd_present(pmd_t pmd) { return (pmd_val(pmd) & (_PAGE_PRESENT | _PAGE_PROT_NONE)); @@ -392,6 +385,18 @@ static inline int ptep_clear_flush_young(struct vm_area_struct *vma, #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) #define __swp_entry_to_pte(x) ((pte_t) { (x).val }) +#define VMALLOC_SIZE (KERN_VIRT_SIZE >> 1) +#define VMALLOC_END (PAGE_OFFSET - 1) +#define VMALLOC_START (PAGE_OFFSET - VMALLOC_SIZE) + +#else /* CONFIG_MMU */ + +#define PAGE_KERNEL __pgprot(0) +#define swapper_pg_dir NULL +#define VMALLOC_START 0 + +#endif /* CONFIG_MMU */ + #ifdef CONFIG_FLATMEM #define kern_addr_valid(addr) (1) /* FIXME */ #endif @@ -404,10 +409,7 @@ static inline void pgtable_cache_init(void) /* No page table caches to initialize */ } -#define VMALLOC_SIZE (KERN_VIRT_SIZE >> 1) -#define VMALLOC_END (PAGE_OFFSET - 1) -#define VMALLOC_START (PAGE_OFFSET - VMALLOC_SIZE) - +#ifdef CONFIG_MMU /* * Task size is 0x40000000000 for RV64 or 0xb800000 for RV32. * Note that PGDIR_SIZE must evenly divide TASK_SIZE. @@ -417,6 +419,18 @@ static inline void pgtable_cache_init(void) #else #define TASK_SIZE VMALLOC_START #endif +#else /* CONFIG_MMU */ +#define TASK_SIZE 0xffffffffUL +#endif /* !CONFIG_MMU */ + +#define FIRST_USER_ADDRESS 0 + +/* + * ZERO_PAGE is a global shared page that is always zero, + * used for zero-mapped memory areas, etc. + */ +extern unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)]; +#define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page)) #include diff --git a/arch/riscv/include/asm/tlbflush.h b/arch/riscv/include/asm/tlbflush.h index 687dd19735a7..f127b3d17ec2 100644 --- a/arch/riscv/include/asm/tlbflush.h +++ b/arch/riscv/include/asm/tlbflush.h @@ -10,6 +10,7 @@ #include #include +#ifdef CONFIG_MMU /* * Flush entire local TLB. 'sfence.vma' implicitly fences with the instruction * cache as well, so a 'fence.i' is not necessary. @@ -24,8 +25,12 @@ static inline void local_flush_tlb_page(unsigned long addr) { __asm__ __volatile__ ("sfence.vma %0" : : "r" (addr) : "memory"); } +#else /* CONFIG_MMU */ +#define local_flush_tlb_all() do { } while (0) +#define local_flush_tlb_page(addr) do { } while (0) +#endif /* CONFIG_MMU */ -#ifndef CONFIG_SMP +#if !defined(CONFIG_SMP) || !defined(CONFIG_MMU) #define flush_tlb_all() local_flush_tlb_all() #define flush_tlb_page(vma, addr) local_flush_tlb_page(addr) diff --git a/arch/riscv/include/asm/uaccess.h b/arch/riscv/include/asm/uaccess.h index e076437cfafe..f462a183a9c2 100644 --- a/arch/riscv/include/asm/uaccess.h +++ b/arch/riscv/include/asm/uaccess.h @@ -11,6 +11,7 @@ /* * User space memory access functions */ +#ifdef CONFIG_MMU #include #include #include @@ -475,4 +476,7 @@ unsigned long __must_check clear_user(void __user *to, unsigned long n) __ret; \ }) +#else /* CONFIG_MMU */ +#include +#endif /* CONFIG_MMU */ #endif /* _ASM_RISCV_UACCESS_H */ diff --git a/arch/riscv/kernel/Makefile b/arch/riscv/kernel/Makefile index f933c04f89db..d720666283d6 100644 --- a/arch/riscv/kernel/Makefile +++ b/arch/riscv/kernel/Makefile @@ -25,9 +25,8 @@ obj-y += time.o obj-y += traps.o obj-y += riscv_ksyms.o obj-y += stacktrace.o -obj-y += vdso.o obj-y += cacheinfo.o -obj-y += vdso/ +obj-$(CONFIG_MMU) += vdso.o vdso/ obj-$(CONFIG_M_MODE) += clint.o obj-$(CONFIG_FPU) += fpu.o diff --git a/arch/riscv/kernel/entry.S b/arch/riscv/kernel/entry.S index 18eeb1eec9d5..953c64b0b2b9 100644 --- a/arch/riscv/kernel/entry.S +++ b/arch/riscv/kernel/entry.S @@ -370,6 +370,10 @@ ENTRY(__switch_to) ret ENDPROC(__switch_to) +#ifndef CONFIG_MMU +#define do_page_fault do_trap_unknown +#endif + .section ".rodata" /* Exception vector table */ ENTRY(excp_vect_table) @@ -391,3 +395,10 @@ ENTRY(excp_vect_table) RISCV_PTR do_page_fault /* store page fault */ excp_vect_table_end: END(excp_vect_table) + +#ifndef CONFIG_MMU +ENTRY(__user_rt_sigreturn) + li a7, __NR_rt_sigreturn + scall +END(__user_rt_sigreturn) +#endif diff --git a/arch/riscv/kernel/head.S b/arch/riscv/kernel/head.S index e05379fd8b64..d869cc7c6a12 100644 --- a/arch/riscv/kernel/head.S +++ b/arch/riscv/kernel/head.S @@ -68,10 +68,12 @@ clear_bss_done: la a2, boot_cpu_hartid REG_S a0, (a2) +#ifdef CONFIG_MMU /* Initialize page tables and relocate to virtual addresses */ la sp, init_thread_union + THREAD_SIZE call setup_vm call relocate +#endif /* CONFIG_MMU */ /* Restore C environment */ la tp, init_task @@ -83,6 +85,7 @@ clear_bss_done: call parse_dtb tail start_kernel +#ifdef CONFIG_MMU relocate: /* Relocate return address */ li a1, PAGE_OFFSET @@ -134,6 +137,7 @@ relocate: sfence.vma ret +#endif /* CONFIG_MMU */ .Lsecondary_start: #ifdef CONFIG_SMP @@ -162,8 +166,10 @@ relocate: beqz tp, .Lwait_for_cpu_up fence +#ifdef CONFIG_MMU /* Enable virtual memory and relocate to virtual address */ call relocate +#endif tail smp_callin #endif diff --git a/arch/riscv/kernel/signal.c b/arch/riscv/kernel/signal.c index dfb26b64e17a..7de7e539b25b 100644 --- a/arch/riscv/kernel/signal.c +++ b/arch/riscv/kernel/signal.c @@ -17,11 +17,16 @@ #include #include +extern u32 __user_rt_sigreturn[2]; + #define DEBUG_SIG 0 struct rt_sigframe { struct siginfo info; struct ucontext uc; +#ifndef CONFIG_MMU + u32 sigreturn_code[2]; +#endif }; #ifdef CONFIG_FPU @@ -166,7 +171,6 @@ static inline void __user *get_sigframe(struct ksignal *ksig, return (void __user *)sp; } - static int setup_rt_frame(struct ksignal *ksig, sigset_t *set, struct pt_regs *regs) { @@ -189,8 +193,19 @@ static int setup_rt_frame(struct ksignal *ksig, sigset_t *set, return -EFAULT; /* Set up to return from userspace. */ +#ifdef CONFIG_MMU regs->ra = (unsigned long)VDSO_SYMBOL( current->mm->context.vdso, rt_sigreturn); +#else + /* + * For the nommu case we don't have a VDSO. Instead we push two + * instructions to call the rt_sigreturn syscall onto the user stack. + */ + if (copy_to_user(&frame->sigreturn_code, __user_rt_sigreturn, + sizeof(frame->sigreturn_code))) + return -EFAULT; + regs->ra = (unsigned long)&frame->sigreturn_code;; +#endif /* CONFIG_MMU */ /* * Set up registers for signal handler. diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile index 8e364ebf37de..5382e42d0cba 100644 --- a/arch/riscv/lib/Makefile +++ b/arch/riscv/lib/Makefile @@ -2,8 +2,6 @@ lib-y += delay.o lib-y += memcpy.o lib-y += memset.o -lib-y += uaccess.o - -lib-$(CONFIG_64BIT) += tishift.o - -lib-$(CONFIG_32BIT) += udivdi3.o +lib-$(CONFIG_MMU) += uaccess.o +lib-$(CONFIG_64BIT) += tishift.o +lib-$(CONFIG_32BIT) += udivdi3.o diff --git a/arch/riscv/mm/Makefile b/arch/riscv/mm/Makefile index fc51d3b7876e..8fc2fd148b06 100644 --- a/arch/riscv/mm/Makefile +++ b/arch/riscv/mm/Makefile @@ -6,9 +6,8 @@ CFLAGS_REMOVE_init.o = -pg endif obj-y += init.o -obj-y += fault.o obj-y += extable.o -obj-y += ioremap.o +obj-$(CONFIG_MMU) += fault.o ioremap.o obj-y += cacheflush.o obj-y += context.o obj-y += sifive_l2_cache.o diff --git a/arch/riscv/mm/cacheflush.c b/arch/riscv/mm/cacheflush.c index 10875ea1065e..0fc69eedc921 100644 --- a/arch/riscv/mm/cacheflush.c +++ b/arch/riscv/mm/cacheflush.c @@ -90,6 +90,7 @@ void flush_icache_mm(struct mm_struct *mm, bool local) #endif /* CONFIG_SMP */ +#ifdef CONFIG_MMU void flush_icache_pte(pte_t pte) { struct page *page = pte_page(pte); @@ -97,3 +98,4 @@ void flush_icache_pte(pte_t pte) if (!test_and_set_bit(PG_dcache_clean, &page->flags)) flush_icache_all(); } +#endif /* CONFIG_MMU */ diff --git a/arch/riscv/mm/context.c b/arch/riscv/mm/context.c index beeb5d7f92ea..073ff12a838a 100644 --- a/arch/riscv/mm/context.c +++ b/arch/riscv/mm/context.c @@ -57,8 +57,10 @@ void switch_mm(struct mm_struct *prev, struct mm_struct *next, cpumask_clear_cpu(cpu, mm_cpumask(prev)); cpumask_set_cpu(cpu, mm_cpumask(next)); +#ifdef CONFIG_MMU csr_write(CSR_SATP, virt_to_pfn(next->pgd) | SATP_MODE); local_flush_tlb_all(); +#endif flush_icache_deferred(next); } diff --git a/arch/riscv/mm/init.c b/arch/riscv/mm/init.c index 84747d7a1e85..782be273e714 100644 --- a/arch/riscv/mm/init.c +++ b/arch/riscv/mm/init.c @@ -142,6 +142,7 @@ void __init setup_bootmem(void) } } +#ifdef CONFIG_MMU unsigned long va_pa_offset; EXPORT_SYMBOL(va_pa_offset); unsigned long pfn_base; @@ -247,3 +248,4 @@ asmlinkage void __init setup_vm(void) __pgprot(_PAGE_TABLE)); #endif } +#endif /* CONFIG_MMU */