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[78.98.50.95]) by smtp.googlemail.com with ESMTPSA id s7sm6650738wmc.2.2019.06.13.11.38.49 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 13 Jun 2019 11:38:49 -0700 (PDT) From: afl1 To: linux-amlogic@lists.infradead.org Subject: [PATCH] pinctrl: add tsin pins for meson-gxbb/gxl/gxm Date: Thu, 13 Jun 2019 20:38:46 +0200 Message-Id: <20190613183846.18679-1-afl2001@gmail.com> X-Mailer: git-send-email 2.17.1 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190613_113852_186077_75E62D3B X-CRM114-Status: UNSURE ( 9.00 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-amlogic@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: afl1 MIME-Version: 1.0 Sender: "linux-amlogic" Errors-To: linux-amlogic-bounces+patchwork-linux-amlogic=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Sorry for previous two emails. I hoppe this will be correctly formatted. This patch adds missing pins for tsin in meson-gxbb/gxl/gxm platform. Author: afl1 Date: Sun Feb 3 11:30:17 2019 +0100 pinctrl: add tsin pins for meson-gxbb/gxl/gxm --- drivers/pinctrl/meson/pinctrl-meson-gxbb.c | 31 ++++++++++++++++++++++ drivers/pinctrl/meson/pinctrl-meson-gxl.c | 13 +++++++++ 2 files changed, 44 insertions(+) diff --git a/drivers/pinctrl/meson/pinctrl-meson-gxbb.c b/drivers/pinctrl/meson/pinctrl-meson-gxbb.c index 4edeb4cae72a..6de3d58277a1 100644 --- a/drivers/pinctrl/meson/pinctrl-meson-gxbb.c +++ b/drivers/pinctrl/meson/pinctrl-meson-gxbb.c @@ -237,10 +237,21 @@ static const unsigned int hdmi_hpd_pins[] = { GPIOH_0 }; static const unsigned int hdmi_sda_pins[] = { GPIOH_1 }; static const unsigned int hdmi_scl_pins[] = { GPIOH_2 }; +static const unsigned int tsin_a_d_valid_pins[] = { GPIOY_0 }; +static const unsigned int tsin_a_sop_pins[] = { GPIOY_1 }; +static const unsigned int tsin_a_clk_pins[] = { GPIOY_2 }; +static const unsigned int tsin_a_d0_pins[] = { GPIOY_3 }; +static const unsigned int tsin_a_dp_pins[] = { GPIOY_4, GPIOY_5, GPIOY_6, GPIOY_7, GPIOY_8, GPIOY_9, GPIOY_10 }; +static const unsigned int tsin_a_fail_pins[] = { GPIOY_11 }; static const unsigned int i2s_out_ch23_y_pins[] = { GPIOY_8 }; static const unsigned int i2s_out_ch45_y_pins[] = { GPIOY_9 }; static const unsigned int i2s_out_ch67_y_pins[] = { GPIOY_10 }; +static const unsigned int tsin_b_d_valid_pins[] = { GPIOX_6 }; +static const unsigned int tsin_b_sop_pins[] = { GPIOX_7 }; +static const unsigned int tsin_b_clk_pins[] = { GPIOX_8 }; +static const unsigned int tsin_b_d0_pins[] = { GPIOX_9 }; + static const unsigned int spdif_out_y_pins[] = { GPIOY_12 }; static const unsigned int gen_clk_out_pins[] = { GPIOY_15 }; @@ -443,8 +454,18 @@ static struct meson_pmx_group meson_gxbb_periphs_groups[] = { GROUP(pwm_a_x, 3, 17), GROUP(pwm_e, 2, 30), GROUP(pwm_f_x, 3, 18), + GROUP(tsin_b_d_valid, 3, 9), + GROUP(tsin_b_sop, 3, 8), + GROUP(tsin_b_clk, 3, 10), + GROUP(tsin_b_d0, 3, 7), /* Bank Y */ + GROUP(tsin_a_fail, 3, 3), + GROUP(tsin_a_d_valid, 3, 2), + GROUP(tsin_a_sop, 3, 1), + GROUP(tsin_a_clk, 3, 0), + GROUP(tsin_a_d0, 3, 4), + GROUP(tsin_a_dp, 3, 5), GROUP(uart_cts_c, 1, 19), GROUP(uart_rts_c, 1, 18), GROUP(uart_tx_c, 1, 17), @@ -607,6 +628,14 @@ static const char * const gpio_periphs_groups[] = { "GPIOX_20", "GPIOX_21", "GPIOX_22", }; +static const char * const tsin_a_groups[] = { + "tsin_a_clk", "tsin_a_sop", "tsin_a_d_valid", "tsin_a_d0", + "tsin_a_dp", "tsin_a_fail", +}; +static const char * const tsin_b_groups[] = { + "tsin_b_clk", "tsin_b_sop", "tsin_b_d_valid", "tsin_b_d0", +}; + static const char * const emmc_groups[] = { "emmc_nand_d07", "emmc_clk", "emmc_cmd", "emmc_ds", }; @@ -798,6 +827,8 @@ static struct meson_pmx_func meson_gxbb_periphs_functions[] = { FUNCTION(i2s_out), FUNCTION(spdif_out), FUNCTION(gen_clk_out), + FUNCTION(tsin_a), + FUNCTION(tsin_b), }; static struct meson_pmx_func meson_gxbb_aobus_functions[] = { diff --git a/drivers/pinctrl/meson/pinctrl-meson-gxl.c b/drivers/pinctrl/meson/pinctrl-meson-gxl.c index 0c0a5018102b..c14090a56b61 100644 --- a/drivers/pinctrl/meson/pinctrl-meson-gxl.c +++ b/drivers/pinctrl/meson/pinctrl-meson-gxl.c @@ -246,6 +246,10 @@ static const unsigned int tsin_a_fail_pins[] = { GPIODV_11 }; static const unsigned int tsin_a_dp_pins[] = { GPIODV_1, GPIODV_2, GPIODV_3, GPIODV_4, GPIODV_5, GPIODV_6, GPIODV_7, }; +static const unsigned int tsin_b_clk_pins[] = { GPIOH_6 }; +static const unsigned int tsin_b_d0_pins[] = { GPIOH_7 }; +static const unsigned int tsin_b_sop_pins[] = { GPIOH_8 }; +static const unsigned int tsin_b_d_valid_pins[] = { GPIOH_9 }; static const struct pinctrl_pin_desc meson_gxl_aobus_pins[] = { MESON_PIN(GPIOAO_0), @@ -460,6 +464,10 @@ static struct meson_pmx_group meson_gxl_periphs_groups[] = { GROUP(i2s_out_lr_clk, 6, 24), GROUP(i2s_out_ch01, 6, 23), GROUP(spdif_out_h, 6, 28), + GROUP(tsin_b_d0, 6, 17), + GROUP(tsin_b_sop, 6, 18), + GROUP(tsin_b_d_valid, 6, 19), + GROUP(tsin_b_clk, 6, 20), /* Bank DV */ GROUP(uart_tx_b, 2, 16), @@ -694,6 +702,10 @@ static const char * const tsin_a_groups[] = { "tsin_a_d_valid", "tsin_a_d0", "tsin_a_dp", "tsin_a_fail", }; +static const char * const tsin_b_groups[] = { + "tsin_b_clk", "tsin_b_sop", + "tsin_b_d_valid", "tsin_b_d0", +}; static const char * const gpio_aobus_groups[] = { "GPIOAO_0", "GPIOAO_1", "GPIOAO_2", "GPIOAO_3", "GPIOAO_4", @@ -770,6 +782,7 @@ static struct meson_pmx_func meson_gxl_periphs_functions[] = { FUNCTION(spdif_out), FUNCTION(eth_led), FUNCTION(tsin_a), + FUNCTION(tsin_b), }; static struct meson_pmx_func meson_gxl_aobus_functions[] = {