From patchwork Fri Jun 14 09:52:57 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lukasz Luba X-Patchwork-Id: 10994917 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 59D1976 for ; Fri, 14 Jun 2019 09:54:37 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 4C33F283F9 for ; Fri, 14 Jun 2019 09:54:37 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 2AB571FFCD; Fri, 14 Jun 2019 09:54:37 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 4C34B2841D for ; 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Fri, 14 Jun 2019 09:53:19 +0000 (GMT) From: Lukasz Luba To: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org Cc: mturquette@baylibre.com, sboyd@kernel.org, b.zolnierkie@samsung.com, krzk@kernel.org, kgene@kernel.org, cw00.choi@samsung.com, kyungmin.park@samsung.com, m.szyprowski@samsung.com, s.nawrocki@samsung.com, myungjoo.ham@samsung.com, keescook@chromium.org, tony@atomide.com, jroedel@suse.de, treding@nvidia.com, digetx@gmail.com, gregkh@linuxfoundation.org, willy.mh.wolff.ml@gmail.com, Lukasz Luba Subject: [PATCH v10 01/13] clk: samsung: add needed IDs for DMC clocks in Exynos5420 Date: Fri, 14 Jun 2019 11:52:57 +0200 Message-Id: <20190614095309.24100-2-l.luba@partner.samsung.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190614095309.24100-1-l.luba@partner.samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA0WSWUwTURSGvZ2ZdgCrYyVyRJSkxoAkgAvGq7hh1Iw8GBONMSKRChNcaIUO KILGqhEtUNEapFJZ1AewQMoWLEjYFwOyVI0bYgyoRQUMoSBGUqS26tt//vOd+5+cXJqQDFCe 9HFFPKdUyGKkQleyqu1nj/9NBRG+ylLojst0Rgq/sloonNfSTeGisUGELz8wCvGtjhwBfpom xxmD3wjc01Mqwl2XhkX4rcoLj6W/p/DzmrtCPK5pQVjXUyfAJS39Imzu2In7LhYKcfPwVQrb XpaRuP5FKO77NQ9PPhlA2zzYyQktyX5/fUXE6lVmkq3O7hex5Qa1kK3PKRaxmsujQrZxtFbA Xq80ILaiM5kdL1+21+2Q66YoLub4aU4ZuCXC9Zi+tA3F1s5PrLDokAqpxanIhQYmCDLNWkEq cqUlTCGCmSGrs7AiqPqmFzqKcQSN6ir0d+Tq0BDpaBQg+NyYT/0bmXjWNUvRtJAJAJMhzj7g zugQ6If22RmCeUTASN+7P8xC5gDobW52hmRWgPrVDGXXYmYrVBRMO8O8oai0gbBrF2YbtOYN /9kIGA0NJqPNCe2AhuJMwqEXwtf2SpFDe8FMdZ7AoXlQae45+XMwmJHjZIKhud1M2fchmJVg rAl02CFQ25RL2m1g5sHrkQV2m5iV2qoswmGL4VqKxEH7QmV6rzNoERQU33Y+zoLNmOs81S0E A2/GiBvIO/t/WD5CBuTBJfDyaI5fq+DOBPAyOZ+giA6IPCUvR7M/r9PWPmFCddNHmxBDI+lc ccNGQbiEkp3mz8qbENCE1F2cG0yES8RRsrNJnPLUEWVCDMc3oSU0KfUQJ8/5ECZhomXx3EmO i+WUf7sC2sVThWI/UcHPitI2r+632rRJiR/X3PhxMTgla8S0PLSOnZl037U+5UJ7d83NsGVT OSFra7NrFltN5sO9cWXbr/hHxELoUot6w2PD+qiPFecjbbt/7g/6cvDE8H2fvheJPiXZumL9 Hm1Y63SE77uoqc7ehxZFvqZNqfdrXZeUaZv61TF1p1dK8sdkq/0IJS/7DSB1wyJ1AwAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrKIsWRmVeSWpSXmKPExsVy+t/xe7oT8phjDXpu61tsnLGe1eL6l+es FvOPnGO1WP3xMaNF8+L1bBaTT81lsjjTnWvR//g1s8X58xvYLc42vWG3uNUgY/Gx5x6rxeVd c9gsPvceYbSYcX4fk8XaI3fZLS6ecrW43biCzeLwm3ZWi3/XNrJY7L/iZXH7N5/FtxOPGB3E Pb59ncTi8f5GK7vH7IaLLB47Z91l99i0qpPNY//cNewevc3v2DwOvtvD5NG3ZRWjx+bT1R6f N8kFcEfp2RTll5akKmTkF5fYKkUbWhjpGVpa6BmZWOoZGpvHWhmZKunb2aSk5mSWpRbp2yXo ZczecIyxYA9/xebnMxgbGDt5uxg5OSQETCTaX7xg6WLk4hASWMoosWjiFiaIhJjEpH3b2SFs YYk/17rYIIo+MUqsaLkB1MHBwSagJ7FjVSFIXERgDqPEz65tjCAOs8BZZondK96ATRIWCJE4 NukAmM0ioCrRef0/K4jNK2AvsXn5H0aIDfISqzccYAaxOQUcJI7Of8MGskAIqOb7DP4JjHwL GBlWMYqklhbnpucWG+oVJ+YWl+al6yXn525iBEbhtmM/N+9gvLQx+BCjAAejEg/vASumWCHW xLLiytxDjBIczEoivPOsmWOFeFMSK6tSi/Lji0pzUosPMZoC3TSRWUo0OR+YIPJK4g1NDc0t LA3Njc2NzSyUxHk7BA7GCAmkJ5akZqemFqQWwfQxcXBKNTDmzL43pTGnY35e/NGj818tOHfC TzJpWcUCsxvmfby91+5+jblo/M4jTqrl8E1XaeFqrlDWdyLKjd3PLlpdjP8n4ZjWnjvlfRrr Ktvs6dNaa3O7s7T/z9/b/rYwcs2TaXuiYwwyYxf19iaEzXOImRMdJCF246nUpeVLHwXnNayR ePh032dF/T9KLMUZiYZazEXFiQDXjeGl2AIAAA== X-CMS-MailID: 20190614095320eucas1p2919a6169c997bb81c80416e8a0ede538 X-Msg-Generator: CA X-RootMTR: 20190614095320eucas1p2919a6169c997bb81c80416e8a0ede538 X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20190614095320eucas1p2919a6169c997bb81c80416e8a0ede538 References: <20190614095309.24100-1-l.luba@partner.samsung.com> Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Define new IDs for clocks used by Dynamic Memory Controller in Exynos5422 SoC. Acked-by: Rob Herring Acked-by: Chanwoo Choi Acked-by: Krzysztof Kozlowski Signed-off-by: Lukasz Luba --- include/dt-bindings/clock/exynos5420.h | 18 +++++++++++++++++- 1 file changed, 17 insertions(+), 1 deletion(-) diff --git a/include/dt-bindings/clock/exynos5420.h b/include/dt-bindings/clock/exynos5420.h index 355f469943f1..02d5ac469a3d 100644 --- a/include/dt-bindings/clock/exynos5420.h +++ b/include/dt-bindings/clock/exynos5420.h @@ -60,6 +60,7 @@ #define CLK_MAU_EPLL 159 #define CLK_SCLK_HSIC_12M 160 #define CLK_SCLK_MPHY_IXTAL24 161 +#define CLK_SCLK_BPLL 162 /* gate clocks */ #define CLK_UART0 257 @@ -195,6 +196,16 @@ #define CLK_ACLK432_CAM 518 #define CLK_ACLK_FL1550_CAM 519 #define CLK_ACLK550_CAM 520 +#define CLK_CLKM_PHY0 521 +#define CLK_CLKM_PHY1 522 +#define CLK_ACLK_PPMU_DREX0_0 523 +#define CLK_ACLK_PPMU_DREX0_1 524 +#define CLK_ACLK_PPMU_DREX1_0 525 +#define CLK_ACLK_PPMU_DREX1_1 526 +#define CLK_PCLK_PPMU_DREX0_0 527 +#define CLK_PCLK_PPMU_DREX0_1 528 +#define CLK_PCLK_PPMU_DREX1_0 529 +#define CLK_PCLK_PPMU_DREX1_1 530 /* mux clocks */ #define CLK_MOUT_HDMI 640 @@ -217,6 +228,8 @@ #define CLK_MOUT_EPLL 657 #define CLK_MOUT_MAU_EPLL 658 #define CLK_MOUT_USER_MAU_EPLL 659 +#define CLK_MOUT_SCLK_SPLL 660 +#define CLK_MOUT_MX_MSPLL_CCORE_PHY 661 /* divider clocks */ #define CLK_DOUT_PIXEL 768 @@ -248,8 +261,11 @@ #define CLK_DOUT_CCLK_DREX0 794 #define CLK_DOUT_CLK2X_PHY0 795 #define CLK_DOUT_PCLK_CORE_MEM 796 +#define CLK_FF_DOUT_SPLL2 797 +#define CLK_DOUT_PCLK_DREX0 798 +#define CLK_DOUT_PCLK_DREX1 799 /* must be greater than maximal clock id */ -#define CLK_NR_CLKS 797 +#define CLK_NR_CLKS 800 #endif /* _DT_BINDINGS_CLOCK_EXYNOS_5420_H */ From patchwork Fri Jun 14 09:52:58 2019 Content-Type: text/plain; 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Fri, 14 Jun 2019 09:53:20 +0000 (GMT) From: Lukasz Luba To: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org Cc: mturquette@baylibre.com, sboyd@kernel.org, b.zolnierkie@samsung.com, krzk@kernel.org, kgene@kernel.org, cw00.choi@samsung.com, kyungmin.park@samsung.com, m.szyprowski@samsung.com, s.nawrocki@samsung.com, myungjoo.ham@samsung.com, keescook@chromium.org, tony@atomide.com, jroedel@suse.de, treding@nvidia.com, digetx@gmail.com, gregkh@linuxfoundation.org, willy.mh.wolff.ml@gmail.com, Lukasz Luba Subject: [PATCH v10 02/13] clk: samsung: add new clocks for DMC for Exynos5422 SoC Date: Fri, 14 Jun 2019 11:52:58 +0200 Message-Id: <20190614095309.24100-3-l.luba@partner.samsung.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190614095309.24100-1-l.luba@partner.samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA0WSfUhTYRTGe3d37+5Wk9uUfMmRtAhMaJakvWVWUsFFCILsn0Jq5U0jN3XX WWbEUjQ1P0ozbWZaisqm2NbIj8rptIzMrz5XS6mUDFuWuhIpra276r/fec553udweElM8h5f Th5TJTNqlSJeRoj4tx/M9a8tUmHR62rPQ2Qsa8LRS+c4jiq7+3FkmBoFKKO6iUDFjyp46PF5 JSoc/YShgYGbAtSX7hCg11opmsobwdHTtqsEmsnvBqhsoJ2HGruHBWjo0S5kP1tPoC7HORwt vDDykeVZJLL/8ELfH74H233p79+K+PQXW6aALtcO8elW3bCANulzCNpS0SCg8zMmCbpz8i6P LjDrAX2rN42eMa3Ys3i/aEsME38shVEHbT0kiivJySQSB9efrLb0AS1oC8wFQhJSG+C9sWEs F4hICVUPYKldD7jCCWD7/E+CK2YAHDQ5eH8tX61OHteoA/BNZh7+z1Lz1eYqSJKg5LBFn+Q2 +FBlAJZ/3OuewahmDH62vwHuhjcVBTsbav4wn1oNR573Em4WU9vguPkdn0vzh4abHZibhdR2 eL/SQXD6RRJaBoUc74RdHVacY2840WMWcCyFv1orPVuzUJt/HXB8Go4WVnhmwmBXz9CfnTFq DWxqC+LkCKi70Uy4ZUh5QdvnpW4Zc2HR7VKMk8UwO0vCTQdAc96gJ2gZrGu47HmchvXzDs8N i12nmp3GLgB/3f+wKgD0wJfRsMpYhg1WMSfkrELJalSx8iMJShNw/bzehR5nC2j7edgKKBLI log7NvOiJbgihU1VWgEkMZmP+FoYFi0RxyhSTzHqhINqTTzDWoEfyZf5itMWvT0goWIVycxx hklk1H+7PFK4XAsiVmIZOddF2brpYGl1hs34QagpTsk+G2VwPt+fnbTxTEiLaiy9dsW7O/lx 8r6A+rKQvprGifCdiYZXNTFYenfW5Lbj96QX5p6E+tPBQeZcH8NDfWlVRK093Hh0k1aG95b0 izTeO9SFCfdX+RXII2/ZZi9dyTXp9k1khU6U7F56R8Zn4xTrAzE1q/gNTcbVCXUDAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrCIsWRmVeSWpSXmKPExsVy+t/xe7oT85hjDXpbdC02zljPanH9y3NW i/lHzrFarP74mNGiefF6NovJp+YyWZzpzrXof/ya2eL8+Q3sFmeb3rBb3GqQsfjYc4/V4vKu OWwWn3uPMFrMOL+PyWLtkbvsFhdPuVrcblzBZnH4TTurxb9rG1ks9l/xsrj9m8/i24lHjA7i Ht++TmLxeH+jld1jdsNFFo+ds+6ye2xa1cnmsX/uGnaP3uZ3bB4H3+1h8ujbsorRY/Ppao/P m+QCuKP0bIryS0tSFTLyi0tslaINLYz0DC0t9IxMLPUMjc1jrYxMlfTtbFJSczLLUov07RL0 MqZ2trIVXDCsWLz/LGMD4y6tLkZODgkBE4kPh74wdTFycQgJLGWUmNq4iBkiISYxad92dghb WOLPtS42EFtI4BOjxJHpkV2MHBxsAnoSO1YVgvSKCMxhlPjZtY0RxGEWOMsssXvFGyaQBmGB IIlpvWvBmlkEVCXuXT0NZvMK2Es83/KQBWKBvMTqDQfAFnMKOEgcnf+GDWSBEFDN9xn8Exj5 FjAyrGIUSS0tzk3PLTbUK07MLS7NS9dLzs/dxAiMwW3Hfm7ewXhpY/AhRgEORiUe3gNWTLFC rIllxZW5hxglOJiVRHjnWTPHCvGmJFZWpRblxxeV5qQWH2I0BbppIrOUaHI+MD3klcQbmhqa W1gamhubG5tZKInzdggcjBESSE8sSc1OTS1ILYLpY+LglGpgNDWXPnBZ5rYOT8Cr6d93bfu0 amqMz70r0tVfNng+bbpz8pFxv4Xf3AlLr/v/XrH9zyO/tgsfCipdjh74aLRQy29BweqrC33b Fu3e8tF5QyuLw1GhOVdNzjrNr2eadP9nwfd8F0dh+ZdzQ0/Nv/MjdurylE/Wk8/6fbdYvV5Z 993Vm3PWLfkUd/+GEktxRqKhFnNRcSIAHayblNcCAAA= X-CMS-MailID: 20190614095321eucas1p2af62f3cdf78ba3c5a8013159da4f7502 X-Msg-Generator: CA X-RootMTR: 20190614095321eucas1p2af62f3cdf78ba3c5a8013159da4f7502 X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20190614095321eucas1p2af62f3cdf78ba3c5a8013159da4f7502 References: <20190614095309.24100-1-l.luba@partner.samsung.com> Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch provides support for clocks needed for Dynamic Memory Controller in Exynos5422 SoC. It adds CDREX base register addresses, new DIV, MUX and GATE entries. Acked-by: Chanwoo Choi Acked-by: Krzysztof Kozlowski Signed-off-by: Lukasz Luba --- drivers/clk/samsung/clk-exynos5420.c | 61 +++++++++++++++++++++++++--- 1 file changed, 55 insertions(+), 6 deletions(-) diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c index 34cce3c5898f..514e16310227 100644 --- a/drivers/clk/samsung/clk-exynos5420.c +++ b/drivers/clk/samsung/clk-exynos5420.c @@ -134,6 +134,8 @@ #define SRC_CDREX 0x20200 #define DIV_CDREX0 0x20500 #define DIV_CDREX1 0x20504 +#define GATE_BUS_CDREX0 0x20700 +#define GATE_BUS_CDREX1 0x20704 #define KPLL_LOCK 0x28000 #define KPLL_CON0 0x28100 #define SRC_KFC 0x28200 @@ -248,6 +250,8 @@ static const unsigned long exynos5x_clk_regs[] __initconst = { DIV_CDREX1, SRC_KFC, DIV_KFC0, + GATE_BUS_CDREX0, + GATE_BUS_CDREX1, }; static const unsigned long exynos5800_clk_regs[] __initconst = { @@ -425,6 +429,9 @@ PNAME(mout_group13_5800_p) = { "dout_osc_div", "mout_sw_aclkfl1_550_cam" }; PNAME(mout_group14_5800_p) = { "dout_aclk550_cam", "dout_sclk_sw" }; PNAME(mout_group15_5800_p) = { "dout_osc_div", "mout_sw_aclk550_cam" }; PNAME(mout_group16_5800_p) = { "dout_osc_div", "mout_mau_epll_clk" }; +PNAME(mout_mx_mspll_ccore_phy_p) = { "sclk_bpll", "mout_sclk_dpll", + "mout_sclk_mpll", "ff_dout_spll2", + "mout_sclk_spll", "mout_sclk_epll"}; /* fixed rate clocks generated outside the soc */ static struct samsung_fixed_rate_clock @@ -450,7 +457,7 @@ static const struct samsung_fixed_factor_clock static const struct samsung_fixed_factor_clock exynos5800_fixed_factor_clks[] __initconst = { FFACTOR(0, "ff_dout_epll2", "mout_sclk_epll", 1, 2, 0), - FFACTOR(0, "ff_dout_spll2", "mout_sclk_spll", 1, 2, 0), + FFACTOR(CLK_FF_DOUT_SPLL2, "ff_dout_spll2", "mout_sclk_spll", 1, 2, 0), }; static const struct samsung_mux_clock exynos5800_mux_clks[] __initconst = { @@ -472,11 +479,14 @@ static const struct samsung_mux_clock exynos5800_mux_clks[] __initconst = { MUX(0, "mout_aclk300_disp1", mout_group5_5800_p, SRC_TOP2, 24, 2), MUX(0, "mout_aclk300_gscl", mout_group5_5800_p, SRC_TOP2, 28, 2), + MUX(CLK_MOUT_MX_MSPLL_CCORE_PHY, "mout_mx_mspll_ccore_phy", + mout_mx_mspll_ccore_phy_p, SRC_TOP7, 0, 3), + MUX(CLK_MOUT_MX_MSPLL_CCORE, "mout_mx_mspll_ccore", - mout_mx_mspll_ccore_p, SRC_TOP7, 16, 2), + mout_mx_mspll_ccore_p, SRC_TOP7, 16, 3), MUX_F(CLK_MOUT_MAU_EPLL, "mout_mau_epll_clk", mout_mau_epll_clk_5800_p, SRC_TOP7, 20, 2, CLK_SET_RATE_PARENT, 0), - MUX(0, "sclk_bpll", mout_bpll_p, SRC_TOP7, 24, 1), + MUX(CLK_SCLK_BPLL, "sclk_bpll", mout_bpll_p, SRC_TOP7, 24, 1), MUX(0, "mout_epll2", mout_epll2_5800_p, SRC_TOP7, 28, 1), MUX(0, "mout_aclk550_cam", mout_group3_5800_p, SRC_TOP8, 16, 3), @@ -648,7 +658,7 @@ static const struct samsung_mux_clock exynos5x_mux_clks[] __initconst = { MUX(0, "mout_sclk_mpll", mout_mpll_p, SRC_TOP6, 0, 1), MUX(CLK_MOUT_VPLL, "mout_sclk_vpll", mout_vpll_p, SRC_TOP6, 4, 1), - MUX(0, "mout_sclk_spll", mout_spll_p, SRC_TOP6, 8, 1), + MUX(CLK_MOUT_SCLK_SPLL, "mout_sclk_spll", mout_spll_p, SRC_TOP6, 8, 1), MUX(0, "mout_sclk_ipll", mout_ipll_p, SRC_TOP6, 12, 1), MUX(0, "mout_sclk_rpll", mout_rpll_p, SRC_TOP6, 16, 1), MUX_F(CLK_MOUT_EPLL, "mout_sclk_epll", mout_epll_p, SRC_TOP6, 20, 1, @@ -806,8 +816,21 @@ static const struct samsung_div_clock exynos5x_div_clks[] __initconst = { "mout_aclk400_disp1", DIV_TOP2, 4, 3), /* CDREX Block */ - DIV(CLK_DOUT_PCLK_CDREX, "dout_pclk_cdrex", "dout_aclk_cdrex1", - DIV_CDREX0, 28, 3), + /* + * The three clocks below are controlled using the same register and + * bits. They are put into one because there is a need of + * synchronization between the BUS and DREXs (two external memory + * interfaces). + * They are put here to show this HW assumption and for clock + * information summary completeness. + */ + DIV_F(CLK_DOUT_PCLK_CDREX, "dout_pclk_cdrex", "dout_aclk_cdrex1", + DIV_CDREX0, 28, 3, CLK_GET_RATE_NOCACHE, 0), + DIV_F(CLK_DOUT_PCLK_DREX0, "dout_pclk_drex0", "dout_cclk_drex0", + DIV_CDREX0, 28, 3, CLK_GET_RATE_NOCACHE, 0), + DIV_F(CLK_DOUT_PCLK_DREX1, "dout_pclk_drex1", "dout_cclk_drex0", + DIV_CDREX0, 28, 3, CLK_GET_RATE_NOCACHE, 0), + DIV_F(CLK_DOUT_SCLK_CDREX, "dout_sclk_cdrex", "mout_mclk_cdrex", DIV_CDREX0, 24, 3, CLK_SET_RATE_PARENT, 0), DIV(CLK_DOUT_ACLK_CDREX1, "dout_aclk_cdrex1", "dout_clk2x_phy0", @@ -1170,6 +1193,32 @@ static const struct samsung_gate_clock exynos5x_gate_clks[] __initconst = { GATE_TOP_SCLK_ISP, 12, CLK_SET_RATE_PARENT, 0), GATE(CLK_G3D, "g3d", "mout_user_aclk_g3d", GATE_IP_G3D, 9, 0, 0), + + /* CDREX */ + GATE(CLK_CLKM_PHY0, "clkm_phy0", "dout_sclk_cdrex", + GATE_BUS_CDREX0, 0, 0, 0), + GATE(CLK_CLKM_PHY1, "clkm_phy1", "dout_sclk_cdrex", + GATE_BUS_CDREX0, 1, 0, 0), + GATE(0, "mx_mspll_ccore_phy", "mout_mx_mspll_ccore_phy", + SRC_MASK_TOP7, 0, CLK_IGNORE_UNUSED, 0), + + GATE(CLK_ACLK_PPMU_DREX1_1, "aclk_ppmu_drex1_1", "dout_aclk_cdrex1", + GATE_BUS_CDREX1, 12, CLK_IGNORE_UNUSED, 0), + GATE(CLK_ACLK_PPMU_DREX1_0, "aclk_ppmu_drex1_0", "dout_aclk_cdrex1", + GATE_BUS_CDREX1, 13, CLK_IGNORE_UNUSED, 0), + GATE(CLK_ACLK_PPMU_DREX0_1, "aclk_ppmu_drex0_1", "dout_aclk_cdrex1", + GATE_BUS_CDREX1, 14, CLK_IGNORE_UNUSED, 0), + GATE(CLK_ACLK_PPMU_DREX0_0, "aclk_ppmu_drex0_0", "dout_aclk_cdrex1", + GATE_BUS_CDREX1, 15, CLK_IGNORE_UNUSED, 0), + + GATE(CLK_PCLK_PPMU_DREX1_1, "pclk_ppmu_drex1_1", "dout_pclk_cdrex", + GATE_BUS_CDREX1, 26, CLK_IGNORE_UNUSED, 0), + GATE(CLK_PCLK_PPMU_DREX1_0, "pclk_ppmu_drex1_0", "dout_pclk_cdrex", + GATE_BUS_CDREX1, 27, CLK_IGNORE_UNUSED, 0), + GATE(CLK_PCLK_PPMU_DREX0_1, "pclk_ppmu_drex0_1", "dout_pclk_cdrex", + GATE_BUS_CDREX1, 28, CLK_IGNORE_UNUSED, 0), + GATE(CLK_PCLK_PPMU_DREX0_0, "pclk_ppmu_drex0_0", "dout_pclk_cdrex", + GATE_BUS_CDREX1, 29, CLK_IGNORE_UNUSED, 0), }; static const struct samsung_div_clock exynos5x_disp_div_clks[] __initconst = { From patchwork Fri Jun 14 09:52:59 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lukasz Luba X-Patchwork-Id: 10994907 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id AB7F314E5 for ; Fri, 14 Jun 2019 09:54:24 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 9ED16283EE for ; Fri, 14 Jun 2019 09:54:24 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 92A55283C8; Fri, 14 Jun 2019 09:54:24 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 0CE8D282E8 for ; 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Fri, 14 Jun 2019 09:53:21 +0000 (GMT) From: Lukasz Luba To: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org Cc: mturquette@baylibre.com, sboyd@kernel.org, b.zolnierkie@samsung.com, krzk@kernel.org, kgene@kernel.org, cw00.choi@samsung.com, kyungmin.park@samsung.com, m.szyprowski@samsung.com, s.nawrocki@samsung.com, myungjoo.ham@samsung.com, keescook@chromium.org, tony@atomide.com, jroedel@suse.de, treding@nvidia.com, digetx@gmail.com, gregkh@linuxfoundation.org, willy.mh.wolff.ml@gmail.com, Lukasz Luba Subject: [PATCH v10 03/13] clk: samsung: add BPLL rate table for Exynos 5422 SoC Date: Fri, 14 Jun 2019 11:52:59 +0200 Message-Id: <20190614095309.24100-4-l.luba@partner.samsung.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190614095309.24100-1-l.luba@partner.samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA0WSf0zMYRzHe+77s+PydbV6JLKLoVEasweNGm1f/EP+sKFx9N2J7qr7Vn5k c7Tq0IkaWnWq2apdUZ2WLlGuCKmUUiS7OjuNZLpwMtL5Xvz3ej6f949nzx4ak1oIXzpGlcip VfJYGSnGax/96FiZo8KiVr1LXYqqcysJ1DfxnkCFLR0EKv9iBSj1RiWJcp7qRejZBSXKsn7E UGdnFYXaz45S6LXGD33JfEugF/UFJLLrWgDK7bwvQjdbBinU9TQCDZwpI1HzaAaBfr+sxlFj zzY08NMDfXs8DMJ82G9fs3H2c38axeZrunDWlDdIsUbDOZJt1FdQrC51jGQfjDWI2Is1BsDe bkth7caFO2btEYdGc7ExyZw6eOMB8eGSBi0e/5k5XlHXLtKAux7ngTsNmTXwyt0h6jwQ01Km DEBTdhouHCYANIw3kk6VlLEDWNy3YMYx1NPqcpQCWHRnkvrncIx3TDtommSCYJ0hwWnwYnIB zB/Z5dRgzB0Mfhp4A5wLTyYSOtJ//WWcWQLf1TowJ0uYTTBn4AkQ2vxheVXT37k7EwYfFo6S wlxHQ9PIIoG3wB7zd0pgT/ihtcbFfnDKVCgSmIcaXbEr8xS0Zuldmg2wubWLcN4ZY5bDyvpg J0ImHN66FymgB+z/NNcpxqYxu/YaJowlUJsuFTKWwZrM564eb1hacdWVzcLHV1+5HicHQO09 M34J+Of97yoCwAB8uCReqeD4EBV3LIiXK/kklSLoUJzSCKb/Xdvv1vE68LX7oBkwNJDNljSt F0VJCXkyf0JpBpDGZF6S6xuwKKkkWn7iJKeO269OiuV4M5hP4zIfSYqbZa+UUcgTuaMcF8+p Z7Yi2t1XA8TiPW5JRV4ZY6Grw6DNEvBLkeDoNfoHf7iY/ShGH7Hdd0t33/zNi/Py62MDdt+c SiGao409P32WVPTOy9sXX35kp/146FTICk5XZYkTjQ9b0yJKWrJKdLaCkvcNY9bJRPVlm8LU 3zxnneFj+fprWq+RreGB1WuLJh320zpvm1uADOcPy0MCMTUv/wN40tH5cwMAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrCIsWRmVeSWpSXmKPExsVy+t/xe7qT8phjDV4s0LbYOGM9q8X1L89Z LeYfOcdqsfrjY0aL5sXr2Swmn5rLZHGmO9ei//FrZovz5zewW5xtesNucatBxuJjzz1Wi8u7 5rBZfO49wmgx4/w+Jou1R+6yW1w85Wpxu3EFm8XhN+2sFv+ubWSx2H/Fy+L2bz6LbyceMTqI e3z7OonF4/2NVnaP2Q0XWTx2zrrL7rFpVSebx/65a9g9epvfsXkcfLeHyaNvyypGj82nqz0+ b5IL4I7SsynKLy1JVcjILy6xVYo2tDDSM7S00DMysdQzNDaPtTIyVdK3s0lJzcksSy3St0vQ y1i2p4Ol4L1AxZodZ5kaGHfzdTFyckgImEg8vHKcHcQWEljKKLHjRAVEXExi0r7t7BC2sMSf a11sXYxcQDWfGCW2fd8I5HBwsAnoSexYVQgSFxGYwyjxs2sbI4jDLHCWWWL3ijdMIN3CAgES R/atZwWxWQRUJZ5s+8EMYvMK2EtMvn2SEWKDvMTqDQfA4pwCDhJH578BWyAEVPN9Bv8ERr4F jAyrGEVSS4tz03OLDfWKE3OLS/PS9ZLzczcxAmNw27Gfm3cwXtoYfIhRgINRiYf3gBVTrBBr YllxZe4hRgkOZiUR3nnWzLFCvCmJlVWpRfnxRaU5qcWHGE2BbprILCWanA9MD3kl8YamhuYW lobmxubGZhZK4rwdAgdjhATSE0tSs1NTC1KLYPqYODilGhjn991ZwuLT4FEZLmGbfDBk8+qF 7Fvczm7dvG2Kdod9uQT7tCqGZbadm789rLEI4rrs23jzyyxXU14W01/sEyV2WhxPKfvwUf79 lDrPmXqrdcVSt4YF1389+k5O6pD2s/cZVxzkJkw4N83pkWif0ZkmEQZJ40qPyOZSpc7jAprP 7kj5zDWdZajEUpyRaKjFXFScCACc0kpD1wIAAA== X-CMS-MailID: 20190614095323eucas1p1312dd7bcc5a25cbb3af28ed0f52dc7a6 X-Msg-Generator: CA X-RootMTR: 20190614095323eucas1p1312dd7bcc5a25cbb3af28ed0f52dc7a6 X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20190614095323eucas1p1312dd7bcc5a25cbb3af28ed0f52dc7a6 References: <20190614095309.24100-1-l.luba@partner.samsung.com> Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add new table rate for BPLL for Exynos5422 SoC supporting Dynamic Memory Controller frequencies for driver's DRAM timings. Acked-by: Chanwoo Choi Acked-by: Krzysztof Kozlowski Signed-off-by: Lukasz Luba --- drivers/clk/samsung/clk-exynos5420.c | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-) diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c index 514e16310227..16ad498e3f3f 100644 --- a/drivers/clk/samsung/clk-exynos5420.c +++ b/drivers/clk/samsung/clk-exynos5420.c @@ -1334,6 +1334,17 @@ static const struct samsung_pll_rate_table exynos5420_pll2550x_24mhz_tbl[] __ini PLL_35XX_RATE(24 * MHZ, 200000000, 200, 3, 3), }; +static const struct samsung_pll_rate_table exynos5422_bpll_rate_table[] = { + PLL_35XX_RATE(24 * MHZ, 825000000, 275, 4, 1), + PLL_35XX_RATE(24 * MHZ, 728000000, 182, 3, 1), + PLL_35XX_RATE(24 * MHZ, 633000000, 211, 4, 1), + PLL_35XX_RATE(24 * MHZ, 543000000, 181, 2, 2), + PLL_35XX_RATE(24 * MHZ, 413000000, 413, 6, 2), + PLL_35XX_RATE(24 * MHZ, 275000000, 275, 3, 3), + PLL_35XX_RATE(24 * MHZ, 206000000, 206, 3, 3), + PLL_35XX_RATE(24 * MHZ, 165000000, 110, 2, 3), +}; + static const struct samsung_pll_rate_table exynos5420_epll_24mhz_tbl[] = { PLL_36XX_RATE(24 * MHZ, 600000000U, 100, 2, 1, 0), PLL_36XX_RATE(24 * MHZ, 400000000U, 200, 3, 2, 0), @@ -1476,9 +1487,13 @@ static void __init exynos5x_clk_init(struct device_node *np, exynos5x_plls[apll].rate_table = exynos5420_pll2550x_24mhz_tbl; exynos5x_plls[epll].rate_table = exynos5420_epll_24mhz_tbl; exynos5x_plls[kpll].rate_table = exynos5420_pll2550x_24mhz_tbl; - exynos5x_plls[bpll].rate_table = exynos5420_pll2550x_24mhz_tbl; } + if (soc == EXYNOS5420) + exynos5x_plls[bpll].rate_table = exynos5420_pll2550x_24mhz_tbl; + else + exynos5x_plls[bpll].rate_table = exynos5422_bpll_rate_table; + samsung_clk_register_pll(ctx, exynos5x_plls, ARRAY_SIZE(exynos5x_plls), reg_base); samsung_clk_register_fixed_rate(ctx, exynos5x_fixed_rate_clks, From patchwork Fri Jun 14 09:53:00 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lukasz Luba X-Patchwork-Id: 10994895 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 0089613AF for ; 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Fri, 14 Jun 2019 09:53:22 +0000 (GMT) From: Lukasz Luba To: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org Cc: mturquette@baylibre.com, sboyd@kernel.org, b.zolnierkie@samsung.com, krzk@kernel.org, kgene@kernel.org, cw00.choi@samsung.com, kyungmin.park@samsung.com, m.szyprowski@samsung.com, s.nawrocki@samsung.com, myungjoo.ham@samsung.com, keescook@chromium.org, tony@atomide.com, jroedel@suse.de, treding@nvidia.com, digetx@gmail.com, gregkh@linuxfoundation.org, willy.mh.wolff.ml@gmail.com, Lukasz Luba Subject: [PATCH v10 04/13] dt-bindings: ddr: rename lpddr2 directory Date: Fri, 14 Jun 2019 11:53:00 +0200 Message-Id: <20190614095309.24100-5-l.luba@partner.samsung.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190614095309.24100-1-l.luba@partner.samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA0WSWUwTURSGvZ2lA1gyFpQbRNGKBjSCxCU34IIGk1EfJNEXMUSLTKiRVuhY FVmsFjdWF0QCIhgjkLbIYtkUZbUlCAJKFGWRAEZkE6wQjQFlHIxv3/nPf7abS2HSPsKZOq46 xapV8jAZaYuXmX+2rk9VYUEbZlLdUHF6IYHeff9MoOyGVwQyTA4ApHtQSKJbTVki1JygRCkD IxhqbS0So5aLo2L0QeuCJhN7CfTmyV0SWZMaAEpvfS5CBQ09YtTetBt1XcgnUf3oFQLNvi3G UXXHXtT1yx5NN/YDPydmeuomznztvCRmMrXtOFOZ0SNmSvTXSKY6yyhmknTjJFM7XiVikk16 wDx+GcVYS5YH2AXabg1hw46fZtVe24/aKvS1eiw8TnLWmFeKacEzu3hgQ0F6E2zTpeHxwJaS 0vkAVrQkkkLwHcCMWQMQAiuAxt5BcTyg/pYMJjvw1VI6D8C0VFeB5wqqRtx5C0l7wgp9BC87 0ukAZg4d4NtgdDkGx7q6AZ9woP3hpwkTwTNOr4b95l84zxJ6B/xRasWF7VyhoagG49mG9oMv skf/LgfpJAo+7ZjBBJM/LLrwkRTYAQ5bTGKBXeDvymyRwBzUJt0HAkfDgZSseY8vrLe0E/zS GO0BC594CfJOONFRIxLOtYedY4t4GZvDm2V3MEGWwKuXpYLbHZoS2+YHLYF5xrT55gxsL+Yv 5F/wFoDZHfdF14Frxv9hOQDogROr4ZShLOetYs94cnIlp1GFeh47qSwBc//u5azlWwWYeh1c B2gKyBZKanxEQVJCfpqLVNYBSGEyR8k9XyxIKgmRR55j1SePqDVhLFcHllK4zEkStaDvsJQO lZ9iT7BsOKv+lxVRNs5acLB47yFJ8A2PZZ47tpW34es2eRWsd7v2c+O0udoSG5Mbhc40L3aP 634fuKa65FGsecOloz2kY4DPxaqh33HDVz7l9jfisw9l3yzvfuhiErie/MFVa3TmCOl5Rawm eo/BLyxGdtuwcmWLXOHqu2+zIi9hOjRzhXGL//4c+y+7mqc0B2U4p5B7r8XUnPwP36mN/XMD AAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrCIsWRmVeSWpSXmKPExsVy+t/xe7qT85hjDe68VLfYOGM9q8X1L89Z LeYfOcdqsfrjY0aL5sXr2Swmn5rLZHGmO9ei//FrZovz5zewW5xtesNucatBxuJjzz1Wi8u7 5rBZfO49wmgx4/w+Jou1R+6yW1w85Wpxu3EFm8XhN+2sFv+ubWSx2H/Fy+L2bz6LbyceMTqI e3z7OonF4/2NVnaP2Q0XWTx2zrrL7rFpVSebx/65a9g9epvfsXkcfLeHyaNvyypGj82nqz0+ b5IL4I7SsynKLy1JVcjILy6xVYo2tDDSM7S00DMysdQzNDaPtTIyVdK3s0lJzcksSy3St0vQ y1h1cBVzQQtvxZrlW5kbGPdydzFycEgImEg86RPuYuTiEBJYyiix6GYbexcjJ1BcTGLSvu1Q trDEn2tdbBBFnxglNl9tYAZpZhPQk9ixqhAkLiIwh1HiZ9c2RhCHWeAss8TuFW+YQLqFBVwk nn7YwgpiswioSjw69psFxOYVsJf4sfUzC8QGeYnVGw4wg9icAg4SR+e/YQNZIARU830G/wRG vgWMDKsYRVJLi3PTc4uN9IoTc4tL89L1kvNzNzECY3DbsZ9bdjB2vQs+xCjAwajEw3vAiilW iDWxrLgy9xCjBAezkgjvPGvmWCHelMTKqtSi/Pii0pzU4kOMpkA3TWSWEk3OB6aHvJJ4Q1ND cwtLQ3Njc2MzCyVx3g6BgzFCAumJJanZqakFqUUwfUwcnFINjNOlSjKXFPOraooeU07WVxCd upbzyOpTE234j8dNz/zpu0sr6zxTvJtkRJWJFeNlhojVtg6VDckc/aqWAh6bz2aGu1vUz/R/ aJvcmzGx8fjmBZbZrec81WZEsm/2WuUw++bWjtSWDf6VqecW7j3ymOlm0B+zg8+C72dM+ch0 t+iT0EQpIUtZJZbijERDLeai4kQATkrqt9cCAAA= X-CMS-MailID: 20190614095324eucas1p2eab4def0ed8c912303e4bb3e422bb255 X-Msg-Generator: CA X-RootMTR: 20190614095324eucas1p2eab4def0ed8c912303e4bb3e422bb255 X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20190614095324eucas1p2eab4def0ed8c912303e4bb3e422bb255 References: <20190614095309.24100-1-l.luba@partner.samsung.com> Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Change directory name to be ready for new types of memories. Reviewed-by: Rob Herring Signed-off-by: Lukasz Luba --- .../devicetree/bindings/{lpddr2 => ddr}/lpddr2-timings.txt | 0 Documentation/devicetree/bindings/{lpddr2 => ddr}/lpddr2.txt | 2 +- 2 files changed, 1 insertion(+), 1 deletion(-) rename Documentation/devicetree/bindings/{lpddr2 => ddr}/lpddr2-timings.txt (100%) rename Documentation/devicetree/bindings/{lpddr2 => ddr}/lpddr2.txt (96%) diff --git a/Documentation/devicetree/bindings/lpddr2/lpddr2-timings.txt b/Documentation/devicetree/bindings/ddr/lpddr2-timings.txt similarity index 100% rename from Documentation/devicetree/bindings/lpddr2/lpddr2-timings.txt rename to Documentation/devicetree/bindings/ddr/lpddr2-timings.txt diff --git a/Documentation/devicetree/bindings/lpddr2/lpddr2.txt b/Documentation/devicetree/bindings/ddr/lpddr2.txt similarity index 96% rename from Documentation/devicetree/bindings/lpddr2/lpddr2.txt rename to Documentation/devicetree/bindings/ddr/lpddr2.txt index 58354a075e13..ddd40121e6f6 100644 --- a/Documentation/devicetree/bindings/lpddr2/lpddr2.txt +++ b/Documentation/devicetree/bindings/ddr/lpddr2.txt @@ -36,7 +36,7 @@ Child nodes: "lpddr2-timings" provides AC timing parameters of the device for a given speed-bin. The user may provide the timings for as many speed-bins as is required. Please see Documentation/devicetree/ - bindings/lpddr2/lpddr2-timings.txt for more information on "lpddr2-timings" + bindings/ddr/lpddr2-timings.txt for more information on "lpddr2-timings" Example: From patchwork Fri Jun 14 09:53:01 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lukasz Luba X-Patchwork-Id: 10994897 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 6DB2A14E5 for ; Fri, 14 Jun 2019 09:54:15 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 6025527B13 for ; Fri, 14 Jun 2019 09:54:15 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 5DDA427F8C; Fri, 14 Jun 2019 09:54:15 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id A581F27B13 for ; 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Fri, 14 Jun 2019 09:53:23 +0000 (GMT) From: Lukasz Luba To: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org Cc: mturquette@baylibre.com, sboyd@kernel.org, b.zolnierkie@samsung.com, krzk@kernel.org, kgene@kernel.org, cw00.choi@samsung.com, kyungmin.park@samsung.com, m.szyprowski@samsung.com, s.nawrocki@samsung.com, myungjoo.ham@samsung.com, keescook@chromium.org, tony@atomide.com, jroedel@suse.de, treding@nvidia.com, digetx@gmail.com, gregkh@linuxfoundation.org, willy.mh.wolff.ml@gmail.com, Lukasz Luba Subject: [PATCH v10 05/13] dt-bindings: ddr: add LPDDR3 memories Date: Fri, 14 Jun 2019 11:53:01 +0200 Message-Id: <20190614095309.24100-6-l.luba@partner.samsung.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190614095309.24100-1-l.luba@partner.samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA0WSe0hTURzHO/etObkty4Op0SJ7UPamQ0ZWJFz6ozcEldTKi4pu5q4zy/5Y 2sOm66GkopmVhras6TQfEWWmLWa2RuEjNUsJw9eyWaGZ5fVO+u9zvt/v73x/HA6Dy7tJHyZS Hcdr1MpoBeVOVL4cta24rsZDV1375YPKsk0kahnpJVF+/RsS3R/uASi5wEShDGsehl6nqtCV nn4c2WylNGpKGqDRB50vGk77SKJ3j29QyGmoByjb9hRDD+o7aWS3hqD2s8UUejFwkUQTzWUE evZ+B2r/7Yl+vuoGW7y5nz/SCc7Rep7mcnV2gqvJ6aQ5s/ESxT3LK6E5Q/IQxT0feoJxlyuM gCtvTOScZv/dMw+6bwrjoyPjec3KzUfdIwzZjdSJsoCEP33jtA50+euBGwPZdfBRygipB+6M nC0GcKLQiUuHEQBNqfUuxwlg0q9hbHpkqOoVJRlFAFrHvk8ZUyOjjjV6wDAUGwirjbGi7MVm A5j7dZ+Yx9kqHA62dwDRmM1ugWODtbTIBLsIdtTqCZFlbDBsK7hMS2Xz4f3SWlxkt8l8Q/7A VDFkLzHQWtiES6Ht8FrzPULi2bDPUuEa9oV/a/JdWwtQZ7gNJD4De67kuTJB8IXFTopL4+xS aHq8UpK3Qv2XGkyUIesJWwdniTI+iemVWbgky2DKBbmUXgIr0t66iubCopJM1+UcHDaWYtJT ZQA4NubEroL5Of/LbgFgBN68VlCF88JaNX8yUFCqBK06PPB4jMoMJn9e44TlRzV4On6sDrAM UHjIajdioXJSGS+cUtUByOAKL9nNIDxULgtTnjrNa2KOaLTRvFAH5jGEwluWOOPTITkbrozj o3j+BK+ZdjHGzUcHmnV+bz6Zi9rKs86lKFru2tItmoY5pd/X3zmwa16ENWwk3iEE39zQUK7p VHvtX9A1mJaCbH29hvbdn8PTWxb7lHhcONx/1MFYvj00248YfTNVC7Eo73Htkz2xWiq5yiPE 0bOtuu3weOzSgAT73spEedPO4haVf8wqv+WOssIhE6sghAjl6mW4RlD+A6z9UHJ1AwAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrKIsWRmVeSWpSXmKPExsVy+t/xe7pT8phjDW6/VrHYOGM9q8X1L89Z LeYfOcdqsfrjY0aL5sXr2Swmn5rLZHGmO9ei//FrZovz5zewW5xtesNucatBxuJjzz1Wi8u7 5rBZfO49wmgx4/w+Jou1R+6yW1w85Wpxu3EFm8XhN+2sFv+ubWSx2H/Fy+L2bz6LbyceMTqI e3z7OonF4/2NVnaP2Q0XWTx2zrrL7rFpVSebx/65a9g9epvfsXkcfLeHyaNvyypGj82nqz0+ b5IL4I7SsynKLy1JVcjILy6xVYo2tDDSM7S00DMysdQzNDaPtTIyVdK3s0lJzcksSy3St0vQ y+idcZqtYKNaxd9Xf9gbGO/LdTFyckgImEi8236CrYuRi0NIYCmjxJ8T55ghEmISk/ZtZ4ew hSX+XOuCKvrEKPHxVR9LFyMHB5uAnsSOVYUgcRGBOYwSP7u2MYI4zAJnmSV2r3jDBNItLOAg 8evtAbBJLAKqEncOdLGA2LwC9hI3F/dBbZCXWL3hANhmTqD6o/PfsIEsEAKq+T6DfwIj3wJG hlWMIqmlxbnpucWGesWJucWleel6yfm5mxiBUbjt2M/NOxgvbQw+xCjAwajEw3vAiilWiDWx rLgy9xCjBAezkgjvPGvmWCHelMTKqtSi/Pii0pzU4kOMpkA3TWSWEk3OByaIvJJ4Q1NDcwtL Q3Njc2MzCyVx3g6BgzFCAumJJanZqakFqUUwfUwcnFINjKlnHp0SytxbqtSh4ssdZKXyh0G2 tKv9U7SM8pYnqxK/8u/7FvqmSUDrcVnTtvgL3/dJpzWI7uXhTxRqL5q3Vu5T/0GLrZ+3m2ny 6fxb6PPqpOpWxuk5DEFJr55d0o9taX5dt0r78rbs1liuCwx7uCxer7rw9/bdt7eOrWNh+KuX xbGwnn9vshJLcUaioRZzUXEiAMZaAnHYAgAA X-CMS-MailID: 20190614095324eucas1p247ee87a9ca69733e7aebd601f5d96a94 X-Msg-Generator: CA X-RootMTR: 20190614095324eucas1p247ee87a9ca69733e7aebd601f5d96a94 X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20190614095324eucas1p247ee87a9ca69733e7aebd601f5d96a94 References: <20190614095309.24100-1-l.luba@partner.samsung.com> Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Specifies the AC timing parameters of the LPDDR3 memory device. Reviewed-by: Rob Herring Signed-off-by: Lukasz Luba --- .../bindings/ddr/lpddr3-timings.txt | 58 +++++++++++ .../devicetree/bindings/ddr/lpddr3.txt | 97 +++++++++++++++++++ 2 files changed, 155 insertions(+) create mode 100644 Documentation/devicetree/bindings/ddr/lpddr3-timings.txt create mode 100644 Documentation/devicetree/bindings/ddr/lpddr3.txt diff --git a/Documentation/devicetree/bindings/ddr/lpddr3-timings.txt b/Documentation/devicetree/bindings/ddr/lpddr3-timings.txt new file mode 100644 index 000000000000..84705e50a3fd --- /dev/null +++ b/Documentation/devicetree/bindings/ddr/lpddr3-timings.txt @@ -0,0 +1,58 @@ +* AC timing parameters of LPDDR3 memories for a given speed-bin. + +The structures are based on LPDDR2 and extended where needed. + +Required properties: +- compatible : Should be "jedec,lpddr3-timings" +- min-freq : minimum DDR clock frequency for the speed-bin. Type is +- reg : maximum DDR clock frequency for the speed-bin. Type is + +Optional properties: + +The following properties represent AC timing parameters from the memory +data-sheet of the device for a given speed-bin. All these properties are +of type and the default unit is ps (pico seconds). +- tRFC +- tRRD +- tRPab +- tRPpb +- tRCD +- tRC +- tRAS +- tWTR +- tWR +- tRTP +- tW2W-C2C +- tR2R-C2C +- tFAW +- tXSR +- tXP +- tCKE +- tCKESR +- tMRD + +Example: + +timings_samsung_K3QF2F20DB_800mhz: lpddr3-timings@800000000 { + compatible = "jedec,lpddr3-timings"; + reg = <800000000>; /* workaround: it shows max-freq */ + min-freq = <100000000>; + tRFC = <65000>; + tRRD = <6000>; + tRPab = <12000>; + tRPpb = <12000>; + tRCD = <10000>; + tRC = <33750>; + tRAS = <23000>; + tWTR = <3750>; + tWR = <7500>; + tRTP = <3750>; + tW2W-C2C = <0>; + tR2R-C2C = <0>; + tFAW = <25000>; + tXSR = <70000>; + tXP = <3750>; + tCKE = <3750>; + tCKESR = <3750>; + tMRD = <7000>; +}; diff --git a/Documentation/devicetree/bindings/ddr/lpddr3.txt b/Documentation/devicetree/bindings/ddr/lpddr3.txt new file mode 100644 index 000000000000..3b2485b84b3f --- /dev/null +++ b/Documentation/devicetree/bindings/ddr/lpddr3.txt @@ -0,0 +1,97 @@ +* LPDDR3 SDRAM memories compliant to JEDEC JESD209-3C + +Required properties: +- compatible : Should be - "jedec,lpddr3" +- density : representing density in Mb (Mega bits) +- io-width : representing bus width. Possible values are 8, 16, 32, 64 +- #address-cells: Must be set to 1 +- #size-cells: Must be set to 0 + +Optional properties: + +The following optional properties represent the minimum value of some AC +timing parameters of the DDR device in terms of number of clock cycles. +These values shall be obtained from the device data-sheet. +- tRFC-min-tck +- tRRD-min-tck +- tRPab-min-tck +- tRPpb-min-tck +- tRCD-min-tck +- tRC-min-tck +- tRAS-min-tck +- tWTR-min-tck +- tWR-min-tck +- tRTP-min-tck +- tW2W-C2C-min-tck +- tR2R-C2C-min-tck +- tWL-min-tck +- tDQSCK-min-tck +- tRL-min-tck +- tFAW-min-tck +- tXSR-min-tck +- tXP-min-tck +- tCKE-min-tck +- tCKESR-min-tck +- tMRD-min-tck + +Child nodes: +- The lpddr3 node may have one or more child nodes of type "lpddr3-timings". + "lpddr3-timings" provides AC timing parameters of the device for + a given speed-bin. Please see Documentation/devicetree/ + bindings/ddr/lpddr3-timings.txt for more information on "lpddr3-timings" + +Example: + +samsung_K3QF2F20DB: lpddr3 { + compatible = "Samsung,K3QF2F20DB", "jedec,lpddr3"; + density = <16384>; + io-width = <32>; + #address-cells = <1>; + #size-cells = <0>; + + tRFC-min-tck = <17>; + tRRD-min-tck = <2>; + tRPab-min-tck = <2>; + tRPpb-min-tck = <2>; + tRCD-min-tck = <3>; + tRC-min-tck = <6>; + tRAS-min-tck = <5>; + tWTR-min-tck = <2>; + tWR-min-tck = <7>; + tRTP-min-tck = <2>; + tW2W-C2C-min-tck = <0>; + tR2R-C2C-min-tck = <0>; + tWL-min-tck = <8>; + tDQSCK-min-tck = <5>; + tRL-min-tck = <14>; + tFAW-min-tck = <5>; + tXSR-min-tck = <12>; + tXP-min-tck = <2>; + tCKE-min-tck = <2>; + tCKESR-min-tck = <2>; + tMRD-min-tck = <5>; + + timings_samsung_K3QF2F20DB_800mhz: lpddr3-timings@800000000 { + compatible = "jedec,lpddr3-timings"; + reg = <800000000>; /* workaround: it shows max-freq */ + min-freq = <100000000>; + tRFC = <65000>; + tRRD = <6000>; + tRPab = <12000>; + tRPpb = <12000>; + tRCD = <10000>; + tRC = <33750>; + tRAS = <23000>; + tWTR = <3750>; + tWR = <7500>; + tRTP = <3750>; + tW2W-C2C = <0>; + tR2R-C2C = <0>; + tFAW = <25000>; + tXSR = <70000>; + tXP = <3750>; + tCKE = <3750>; + tCKESR = <3750>; + tMRD = <7000>; + }; +} From patchwork Fri Jun 14 09:53:02 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lukasz Luba X-Patchwork-Id: 10994875 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id BB5AA76 for ; Fri, 14 Jun 2019 09:53:58 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id A991D283E8 for ; Fri, 14 Jun 2019 09:53:58 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 9DD5E283BF; Fri, 14 Jun 2019 09:53:58 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id D4A89283E8 for ; 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Fri, 14 Jun 2019 09:53:24 +0000 (GMT) From: Lukasz Luba To: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org Cc: mturquette@baylibre.com, sboyd@kernel.org, b.zolnierkie@samsung.com, krzk@kernel.org, kgene@kernel.org, cw00.choi@samsung.com, kyungmin.park@samsung.com, m.szyprowski@samsung.com, s.nawrocki@samsung.com, myungjoo.ham@samsung.com, keescook@chromium.org, tony@atomide.com, jroedel@suse.de, treding@nvidia.com, digetx@gmail.com, gregkh@linuxfoundation.org, willy.mh.wolff.ml@gmail.com, Lukasz Luba Subject: [PATCH v10 06/13] drivers: memory: extend of_memory by LPDDR3 support Date: Fri, 14 Jun 2019 11:53:02 +0200 Message-Id: <20190614095309.24100-7-l.luba@partner.samsung.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190614095309.24100-1-l.luba@partner.samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA0VSayyVYRzvee/UsbdDeSaynVVDJbY+PKnQqu1dl2WrPlRDb7xhOYfOm1Ra neiCiNEQDt1EUqcwuS1CKUdutdgRKrVUItcz1cjxUt9+1+f3//AwuPwDacMEqY4JahUfrKDM iZLnE02rU1S4t0tkph16lKYjUfvoFxJl1zWR6N5QL0BRt3QUSm7QYqjxshIl9H7HUXPzQxq9 iuynkUFji4biukn0ujyTQiPxdQClNT/B0P26Lhq1NmxFnefyKFTbf4lEk28fEajqzTbU+dsC jb/4CDytufGxJIIb7LhAcxmaVoIrS++iucL8GIqr0hbQXHzUAMU9HajEuCvF+YAr0kdwI4VL vebvN9/gLwQHHRfUa9wPmge2Fz6hQrN2nPgVOYhpwE2PWGDGQHYtzOi5RcUCc0bO5gH4+dJ3 WiKjALZUGEiJjAB4d6gbm6vkjFTikpEL4NfUfvJfRf9SO00YhmKdYWn+UVPBik0DMKNvtymD s49x+KPzHTAZlqwXjOxooUx5gl0OxxtdTLKM9YBTFYmkNGYP7z2sxk3YjPWEz7L7Z26FbAwD H2haKSm0BTbG5xAStoTf6otpCdvCqbLs2atFqIm/ASR8GvYmaGcz62FtfevMzTjrCHXlayR5 Exx+1oCZZMhawI4fC00yPg2TSlJxSZbB6ItyKe0Ai+NaZocWw9yClNnHOZjyxTijy9lkAI3p zonAPv3/1nUA8oG1ECYqAwTRVSWEO4u8UgxTBTj7hSgLwfTH00/WD5eCsbZDNYBlgGKBrNoN 85aT/HHxpLIGQAZXWMmy1uPecpk/f/KUoA7xVYcFC2INWMIQCmtZxLz3B+RsAH9MOCIIoYJ6 zsUYMxsNKDhz9tN5Nz91ZtXdPsdVK7brIpqcjgSltuOHqz1qizzGhtdNaD37DJtfGK/XVls2 LrNgYkeH9+Ts5ekpp2h2X3jN3nJ/ksDCjD63fef32C5KLv3zM9mw+fDO8KsI++bpPmFM5Q12 ep+MydBdZhvvoClHvUPAoFeezrAyO6HtWoKCEAN5VydcLfJ/AQ4aYIh0AwAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrMIsWRmVeSWpSXmKPExsVy+t/xe7pT85hjDRYsUrHYOGM9q8X1L89Z LeYfOcdqsfrjY0aL5sXr2Swmn5rLZHGmO9ei//FrZovz5zewW5xtesNucatBxuJjzz1Wi8u7 5rBZfO49wmgx4/w+Jou1R+6yW1w85Wpxu3EFm8XhN+2sFv+ubWSx2H/Fy+L2bz6LbyceMTqI e3z7OonF4/2NVnaP2Q0XWTx2zrrL7rFpVSebx/65a9g9epvfsXkcfLeHyaNvyypGj82nqz0+ b5IL4I7SsynKLy1JVcjILy6xVYo2tDDSM7S00DMysdQzNDaPtTIyVdK3s0lJzcksSy3St0vQ y7i+aR9bwTyfil9N75kaGBfZdzFyckgImEgs/byHGcQWEljKKLGqByouJjFp33Z2CFtY4s+1 LrYuRi6gmk+MEh+vLQJKcHCwCehJ7FhVCBIXEZjDKPGzaxsjiMMscJZZYveKN0wg3cICfhLP D30Ea2ARUJX4dsYAJMwrYC/xf/cEVogF8hKrNxwAO4JTwEHi6Pw3bCDlQkA132fwT2DkW8DI sIpRJLW0ODc9t9hIrzgxt7g0L10vOT93EyMwArcd+7llB2PXu+BDjAIcjEo8vAesmGKFWBPL iitzDzFKcDArifDOs2aOFeJNSaysSi3Kjy8qzUktPsRoCnTSRGYp0eR8YHLIK4k3NDU0t7A0 NDc2NzazUBLn7RA4GCMkkJ5YkpqdmlqQWgTTx8TBKdXA2CeZFC1un/ZN9zmn203JiI49oQzW l2e4iqsk2DIpexy0OrU37b6a8feILvdeh53TLIM/VzW6fPFzLBG7MWVPw+EtyrcU1rLeiRHi 0D0u5LZ6csIP1wNnjjh2TWCY5t262ZpNJEJi1xkDBW6xi2q5cq/ELZmyNa/9fh3poS6uI9TX uox1Zp0SS3FGoqEWc1FxIgC7tb2W1gIAAA== X-CMS-MailID: 20190614095325eucas1p20083d9290b36eca945ec3f1428bdbd4f X-Msg-Generator: CA X-RootMTR: 20190614095325eucas1p20083d9290b36eca945ec3f1428bdbd4f X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20190614095325eucas1p20083d9290b36eca945ec3f1428bdbd4f References: <20190614095309.24100-1-l.luba@partner.samsung.com> Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The patch adds AC timings information needed to support LPDDR3 and memory controllers. The structure is used in of_memory and currently in Exynos 5422 DMC. Add parsing data needed for LPDDR3 support. It is currently used in Exynos5422 Dynamic Memory Controller. Acked-by: Krzysztof Kozlowski Signed-off-by: Lukasz Luba --- drivers/memory/of_memory.c | 154 +++++++++++++++++++++++++++++++++++++ drivers/memory/of_memory.h | 18 +++++ include/memory/jedec_ddr.h | 62 +++++++++++++++ 3 files changed, 234 insertions(+) diff --git a/drivers/memory/of_memory.c b/drivers/memory/of_memory.c index 12a61f558644..30f3a3e75063 100644 --- a/drivers/memory/of_memory.c +++ b/drivers/memory/of_memory.c @@ -3,6 +3,12 @@ * OpenFirmware helpers for memory drivers * * Copyright (C) 2012 Texas Instruments, Inc. + * Copyright (C) 2019 Samsung Electronics Co., Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. */ #include @@ -148,3 +154,151 @@ const struct lpddr2_timings *of_get_ddr_timings(struct device_node *np_ddr, return lpddr2_jedec_timings; } EXPORT_SYMBOL(of_get_ddr_timings); + +/** + * of_lpddr3_get_min_tck() - extract min timing values for lpddr3 + * @np: pointer to ddr device tree node + * @device: device requesting for min timing values + * + * Populates the lpddr3_min_tck structure by extracting data + * from device tree node. Returns a pointer to the populated + * structure. If any error in populating the structure, returns NULL. + */ +const struct lpddr3_min_tck *of_lpddr3_get_min_tck(struct device_node *np, + struct device *dev) +{ + int ret = 0; + struct lpddr3_min_tck *min; + + min = devm_kzalloc(dev, sizeof(*min), GFP_KERNEL); + if (!min) + goto default_min_tck; + + ret |= of_property_read_u32(np, "tRFC-min-tck", &min->tRFC); + ret |= of_property_read_u32(np, "tRRD-min-tck", &min->tRRD); + ret |= of_property_read_u32(np, "tRPab-min-tck", &min->tRPab); + ret |= of_property_read_u32(np, "tRPpb-min-tck", &min->tRPpb); + ret |= of_property_read_u32(np, "tRCD-min-tck", &min->tRCD); + ret |= of_property_read_u32(np, "tRC-min-tck", &min->tRC); + ret |= of_property_read_u32(np, "tRAS-min-tck", &min->tRAS); + ret |= of_property_read_u32(np, "tWTR-min-tck", &min->tWTR); + ret |= of_property_read_u32(np, "tWR-min-tck", &min->tWR); + ret |= of_property_read_u32(np, "tRTP-min-tck", &min->tRTP); + ret |= of_property_read_u32(np, "tW2W-C2C-min-tck", &min->tW2W_C2C); + ret |= of_property_read_u32(np, "tR2R-C2C-min-tck", &min->tR2R_C2C); + ret |= of_property_read_u32(np, "tWL-min-tck", &min->tWL); + ret |= of_property_read_u32(np, "tDQSCK-min-tck", &min->tDQSCK); + ret |= of_property_read_u32(np, "tRL-min-tck", &min->tRL); + ret |= of_property_read_u32(np, "tFAW-min-tck", &min->tFAW); + ret |= of_property_read_u32(np, "tXSR-min-tck", &min->tXSR); + ret |= of_property_read_u32(np, "tXP-min-tck", &min->tXP); + ret |= of_property_read_u32(np, "tCKE-min-tck", &min->tCKE); + ret |= of_property_read_u32(np, "tCKESR-min-tck", &min->tCKESR); + ret |= of_property_read_u32(np, "tMRD-min-tck", &min->tMRD); + + if (ret) { + dev_warn(dev, "%s: errors while parsing min-tck values\n", + __func__); + devm_kfree(dev, min); + goto default_min_tck; + } + + return min; + +default_min_tck: + dev_warn(dev, "%s: using default min-tck values\n", __func__); + return NULL; +} +EXPORT_SYMBOL(of_lpddr3_get_min_tck); + +static int of_lpddr3_do_get_timings(struct device_node *np, + struct lpddr3_timings *tim) +{ + int ret; + + /* The 'reg' param required since DT has changed, used as 'max-freq' */ + ret = of_property_read_u32(np, "reg", &tim->max_freq); + ret |= of_property_read_u32(np, "min-freq", &tim->min_freq); + ret |= of_property_read_u32(np, "tRFC", &tim->tRFC); + ret |= of_property_read_u32(np, "tRRD", &tim->tRRD); + ret |= of_property_read_u32(np, "tRPab", &tim->tRPab); + ret |= of_property_read_u32(np, "tRPpb", &tim->tRPpb); + ret |= of_property_read_u32(np, "tRCD", &tim->tRCD); + ret |= of_property_read_u32(np, "tRC", &tim->tRC); + ret |= of_property_read_u32(np, "tRAS", &tim->tRAS); + ret |= of_property_read_u32(np, "tWTR", &tim->tWTR); + ret |= of_property_read_u32(np, "tWR", &tim->tWR); + ret |= of_property_read_u32(np, "tRTP", &tim->tRTP); + ret |= of_property_read_u32(np, "tW2W-C2C", &tim->tW2W_C2C); + ret |= of_property_read_u32(np, "tR2R-C2C", &tim->tR2R_C2C); + ret |= of_property_read_u32(np, "tFAW", &tim->tFAW); + ret |= of_property_read_u32(np, "tXSR", &tim->tXSR); + ret |= of_property_read_u32(np, "tXP", &tim->tXP); + ret |= of_property_read_u32(np, "tCKE", &tim->tCKE); + ret |= of_property_read_u32(np, "tCKESR", &tim->tCKESR); + ret |= of_property_read_u32(np, "tMRD", &tim->tMRD); + + return ret; +} + +/** + * of_lpddr3_get_ddr_timings() - extracts the lpddr3 timings and updates no of + * frequencies available. + * @np_ddr: Pointer to ddr device tree node + * @dev: Device requesting for ddr timings + * @device_type: Type of ddr + * @nr_frequencies: No of frequencies available for ddr + * (updated by this function) + * + * Populates lpddr3_timings structure by extracting data from device + * tree node. Returns pointer to populated structure. If any error + * while populating, returns NULL. + */ +const struct lpddr3_timings +*of_lpddr3_get_ddr_timings(struct device_node *np_ddr, struct device *dev, + u32 device_type, u32 *nr_frequencies) +{ + struct lpddr3_timings *timings = NULL; + u32 arr_sz = 0, i = 0; + struct device_node *np_tim; + char *tim_compat = NULL; + + switch (device_type) { + case DDR_TYPE_LPDDR3: + tim_compat = "jedec,lpddr3-timings"; + break; + default: + dev_warn(dev, "%s: un-supported memory type\n", __func__); + } + + for_each_child_of_node(np_ddr, np_tim) + if (of_device_is_compatible(np_tim, tim_compat)) + arr_sz++; + + if (arr_sz) + timings = devm_kcalloc(dev, arr_sz, sizeof(*timings), + GFP_KERNEL); + + if (!timings) + goto default_timings; + + for_each_child_of_node(np_ddr, np_tim) { + if (of_device_is_compatible(np_tim, tim_compat)) { + if (of_lpddr3_do_get_timings(np_tim, &timings[i])) { + devm_kfree(dev, timings); + goto default_timings; + } + i++; + } + } + + *nr_frequencies = arr_sz; + + return timings; + +default_timings: + dev_warn(dev, "%s: using default timings\n", __func__); + *nr_frequencies = 0; + return NULL; +} +EXPORT_SYMBOL(of_lpddr3_get_ddr_timings); diff --git a/drivers/memory/of_memory.h b/drivers/memory/of_memory.h index b077cc836b0b..e39ecc4c733d 100644 --- a/drivers/memory/of_memory.h +++ b/drivers/memory/of_memory.h @@ -14,6 +14,11 @@ extern const struct lpddr2_min_tck *of_get_min_tck(struct device_node *np, extern const struct lpddr2_timings *of_get_ddr_timings(struct device_node *np_ddr, struct device *dev, u32 device_type, u32 *nr_frequencies); +extern const struct lpddr3_min_tck + *of_lpddr3_get_min_tck(struct device_node *np, struct device *dev); +extern const struct lpddr3_timings + *of_lpddr3_get_ddr_timings(struct device_node *np_ddr, + struct device *dev, u32 device_type, u32 *nr_frequencies); #else static inline const struct lpddr2_min_tck *of_get_min_tck(struct device_node *np, struct device *dev) @@ -27,6 +32,19 @@ static inline const struct lpddr2_timings { return NULL; } + +static inline const struct lpddr3_min_tck + *of_lpddr3_get_min_tck(struct device_node *np, struct device *dev) +{ + return NULL; +} + +static inline const struct lpddr3_timings + *of_lpddr3_get_ddr_timings(struct device_node *np_ddr, + struct device *dev, u32 device_type, u32 *nr_frequencies) +{ + return NULL; +} #endif /* CONFIG_OF && CONFIG_DDR */ #endif /* __LINUX_MEMORY_OF_REG_ */ diff --git a/include/memory/jedec_ddr.h b/include/memory/jedec_ddr.h index ddad0f870e5d..3601825f807d 100644 --- a/include/memory/jedec_ddr.h +++ b/include/memory/jedec_ddr.h @@ -32,6 +32,7 @@ #define DDR_TYPE_LPDDR2_S4 3 #define DDR_TYPE_LPDDR2_S2 4 #define DDR_TYPE_LPDDR2_NVM 5 +#define DDR_TYPE_LPDDR3 6 /* DDR IO width */ #define DDR_IO_WIDTH_4 1 @@ -172,4 +173,65 @@ extern const struct lpddr2_timings lpddr2_jedec_timings[NUM_DDR_TIMING_TABLE_ENTRIES]; extern const struct lpddr2_min_tck lpddr2_jedec_min_tck; + +/* + * Structure for timings for LPDDR3 based on LPDDR2 plus additional fields. + * All parameters are in pico seconds(ps) unless explicitly indicated + * with a suffix like tRAS_max_ns below + */ +struct lpddr3_timings { + u32 max_freq; + u32 min_freq; + u32 tRFC; + u32 tRRD; + u32 tRPab; + u32 tRPpb; + u32 tRCD; + u32 tRC; + u32 tRAS; + u32 tWTR; + u32 tWR; + u32 tRTP; + u32 tW2W_C2C; + u32 tR2R_C2C; + u32 tWL; + u32 tDQSCK; + u32 tRL; + u32 tFAW; + u32 tXSR; + u32 tXP; + u32 tCKE; + u32 tCKESR; + u32 tMRD; +}; + +/* + * Min value for some parameters in terms of number of tCK cycles(nCK) + * Please set to zero parameters that are not valid for a given memory + * type + */ +struct lpddr3_min_tck { + u32 tRFC; + u32 tRRD; + u32 tRPab; + u32 tRPpb; + u32 tRCD; + u32 tRC; + u32 tRAS; + u32 tWTR; + u32 tWR; + u32 tRTP; + u32 tW2W_C2C; + u32 tR2R_C2C; + u32 tWL; + u32 tDQSCK; + u32 tRL; + u32 tFAW; + u32 tXSR; + u32 tXP; + u32 tCKE; + u32 tCKESR; + u32 tMRD; +}; + #endif /* __LINUX_JEDEC_DDR_H */ From patchwork Fri Jun 14 09:53:03 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lukasz Luba X-Patchwork-Id: 10994849 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 0AF0076 for ; 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Fri, 14 Jun 2019 09:53:25 +0000 (GMT) From: Lukasz Luba To: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org Cc: mturquette@baylibre.com, sboyd@kernel.org, b.zolnierkie@samsung.com, krzk@kernel.org, kgene@kernel.org, cw00.choi@samsung.com, kyungmin.park@samsung.com, m.szyprowski@samsung.com, s.nawrocki@samsung.com, myungjoo.ham@samsung.com, keescook@chromium.org, tony@atomide.com, jroedel@suse.de, treding@nvidia.com, digetx@gmail.com, gregkh@linuxfoundation.org, willy.mh.wolff.ml@gmail.com, Lukasz Luba Subject: [PATCH v10 07/13] dt-bindings: memory-controllers: add Exynos5422 DMC device description Date: Fri, 14 Jun 2019 11:53:03 +0200 Message-Id: <20190614095309.24100-8-l.luba@partner.samsung.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190614095309.24100-1-l.luba@partner.samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA0VSayyVYRzveW/npQ6vw/IkS52pZEuaLg+nRZvWu+aD1taHynTiHZZz6Lzo otVB7k6UDR33+eA+HJcwcztKURxqJaKLlVZopaQJOd5Tffv9f5f/5dlD45K3pB0doozgVEp5 qJQyJ5oe/BrYna3E/Vzn725CdTk1JHrxfYpEhT0DJKr8OglQXEkNhTL78jH0OFWB0ic/42hw sFaEnsROi9Co2h59TZsg0dPWPArNaXoAyhlsx1B1z7gIDfUdRWMxZRTSTyeSaPl5HYE6nh1H Y4sWaP7hO+Bly87/uEOwX0biRWyueohgW7TjIlZXkUyxHflVIlYTN0uxXbNtGHuroQKw9f3R 7Jxui+/60+aHArnQkChOtefwOfPg9+XxRPiiw+XUnwmkGnTZpQCahsw+WKT1SAHmtIQpA3Cq fIQSiu8AZqQ1YUIxB+DL2HEiBZitJUZH0ghBKAXQMFWG/YsULH8Axr4U4wKbKy4aAzZMDoC5 H08aPThzD4czY6+AUbBmAmBe+xBpxASzHU7ezV3jxYwnfBJz2zTNAVbWduJGbMZ4wfuF02v7 QUZDw9iMfko4whumzNkLfmv4qbdBJGB7uNJSiAmYh2pNMRDwNTiZnm/yyKC+17gDvbrcLljT ukegj0B1nd7U3QKOzFgZaXwV3mnKxgVaDJMSJILbCTakGUyDNsLSqixTcxYmN9WaXicTwIYP S1QGcND+H1YEQAWw5SJ5RRDHuym5Sy68XMFHKoNcAsIUOrD68fqXe380g/bf57sBQwPpBnGn B+YnIeVR/BVFN4A0LrURF8hwP4k4UH7lKqcK81dFhnJ8N9hME1JbcfS6N2ckTJA8grvAceGc 6q+K0WZ2anAq2yBznLEY190o+fZoIfOa7KxO7EEVl7kHk9WyEzcN5ZYR7hhQ8Ve3fT4Q7Omm JKZiuRLr4h0JR2/oXZfGspxaZoOKHZ31w20xiZoJm95j9X2+W60uvLaUZPmkeg/s3F/amLRw PZX29nNQ1DprvH0CDlpHb1qp0w77FxiuLzRKCT5YvtcZV/HyP4Mxd2x0AwAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrKIsWRmVeSWpSXmKPExsVy+t/xe7rT8phjDf5+ULTYOGM9q8X1L89Z LeYfOcdqsfrjY0aL5sXr2Swmn5rLZHGmO9ei//FrZovz5zewW5xtesNucatBxuJjzz1Wi8u7 5rBZfO49wmgx4/w+Jou1R+6yW1w85Wpxu3EFm8XhN+2sFv+ubWSx2H/Fy+L2bz6LbyceMTqI e3z7OonF4/2NVnaP2Q0XWTx2zrrL7rFpVSebx/65a9g9epvfsXkcfLeHyaNvyypGj82nqz0+ b5IL4I7SsynKLy1JVcjILy6xVYo2tDDSM7S00DMysdQzNDaPtTIyVdK3s0lJzcksSy3St0vQ y3i6spWl4Ld8Rff3NtYGxoNSXYycHBICJhK3bvSwdDFycQgJLGWUeLPlBjNEQkxi0r7t7BC2 sMSfa11sEEWfGCWe3rnB2MXIwcEmoCexY1UhSFxEYA6jxM+ubYwgDrPAWWaJ3SveMIF0Cwsk ShzZ9oANxGYRUJV4PHM2I4jNK2AvcbZxIgvEBnmJ1RsOgG3mFHCQODr/DRvIAiGgmu8z+Ccw 8i1gZFjFKJJaWpybnltspFecmFtcmpeul5yfu4kRGIXbjv3csoOx613wIUYBDkYlHt4DVkyx QqyJZcWVuYcYJTiYlUR451kzxwrxpiRWVqUW5ccXleakFh9iNAW6aSKzlGhyPjBB5JXEG5oa mltYGpobmxubWSiJ83YIHIwREkhPLEnNTk0tSC2C6WPi4JRqYDymd+9u8nmnlIWZFW5lUk3G UvO/W1zVKej6lHTlitt9tmtVN+ccnzfrcc/XLTG1HVcK9/fvW5v8afXqZoEzrT7hUw9zBAl9 nGMj2LJnkZu6vs0+DX9LdweTY53CP7K9vb7NZ0txXnO+4PCS0tS+5/m6yau/h/w6vc+AuYdB qckocYZsbMFcHyWW4oxEQy3mouJEAFTe3TLYAgAA X-CMS-MailID: 20190614095326eucas1p22e27d86d886d7a33acdd59c7f0f6d7d8 X-Msg-Generator: CA X-RootMTR: 20190614095326eucas1p22e27d86d886d7a33acdd59c7f0f6d7d8 X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20190614095326eucas1p22e27d86d886d7a33acdd59c7f0f6d7d8 References: <20190614095309.24100-1-l.luba@partner.samsung.com> Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The patch adds description for DT binding for a new Exynos5422 Dynamic Memory Controller device. Acked-by: Krzysztof Kozlowski Reviewed-by: Rob Herring Signed-off-by: Lukasz Luba --- .../memory-controllers/exynos5422-dmc.txt | 75 +++++++++++++++++++ 1 file changed, 75 insertions(+) create mode 100644 Documentation/devicetree/bindings/memory-controllers/exynos5422-dmc.txt diff --git a/Documentation/devicetree/bindings/memory-controllers/exynos5422-dmc.txt b/Documentation/devicetree/bindings/memory-controllers/exynos5422-dmc.txt new file mode 100644 index 000000000000..3d9bfecf573b --- /dev/null +++ b/Documentation/devicetree/bindings/memory-controllers/exynos5422-dmc.txt @@ -0,0 +1,75 @@ +* Exynos5422 frequency and voltage scaling for Dynamic Memory Controller device + +The Samsung Exynos5422 SoC has DMC (Dynamic Memory Controller) to which the DRAM +memory chips are connected. The driver is to monitor the controller in runtime +and switch frequency and voltage. To monitor the usage of the controller in +runtime, the driver uses the PPMU (Platform Performance Monitoring Unit), which +is able to measure the current load of the memory. +When 'userspace' governor is used for the driver, an application is able to +switch the DMC and memory frequency. + +Required properties for DMC device for Exynos5422: +- compatible: Should be "samsung,exynos5422-dmc". +- clocks : list of clock specifiers, must contain an entry for each + required entry in clock-names for CLK_FOUT_SPLL, CLK_MOUT_SCLK_SPLL, + CLK_FF_DOUT_SPLL2, CLK_FOUT_BPLL, CLK_MOUT_BPLL, CLK_SCLK_BPLL, + CLK_MOUT_MX_MSPLL_CCORE, CLK_MOUT_MX_MSPLL_CCORE_PHY, CLK_MOUT_MCLK_CDREX, +- clock-names : should include "fout_spll", "mout_sclk_spll", "ff_dout_spll2", + "fout_bpll", "mout_bpll", "sclk_bpll", "mout_mx_mspll_ccore", + "mout_mx_mspll_ccore_phy", "mout_mclk_cdrex" entries +- devfreq-events : phandles for PPMU devices connected to this DMC. +- vdd-supply : phandle for voltage regulator which is connected. +- reg : registers of two CDREX controllers. +- operating-points-v2 : phandle for OPPs described in v2 definition. +- device-handle : phandle of the connected DRAM memory device. For more + information please refer to documentation file: + Documentation/devicetree/bindings/ddr/lpddr3.txt +- devfreq-events : phandles of the PPMU events used by the controller. +- samsung,syscon-clk : phandle of the clock register set used by the controller, + these registers are used for enabling a 'pause' feature and are not + exposed by clock framework but they must be used in a safe way. + The register offsets are in the driver code and specyfic for this SoC + type. + +Example: + + ppmu_dmc0_0: ppmu@10d00000 { + compatible = "samsung,exynos-ppmu"; + reg = <0x10d00000 0x2000>; + clocks = <&clock CLK_PCLK_PPMU_DREX0_0>; + clock-names = "ppmu"; + events { + ppmu_event_dmc0_0: ppmu-event3-dmc0_0 { + event-name = "ppmu-event3-dmc0_0"; + }; + }; + }; + + dmc: memory-controller@10c20000 { + compatible = "samsung,exynos5422-dmc"; + reg = <0x10c20000 0x100>, <0x10c30000 0x100>, + clocks = <&clock CLK_FOUT_SPLL>, + <&clock CLK_MOUT_SCLK_SPLL>, + <&clock CLK_FF_DOUT_SPLL2>, + <&clock CLK_FOUT_BPLL>, + <&clock CLK_MOUT_BPLL>, + <&clock CLK_SCLK_BPLL>, + <&clock CLK_MOUT_MX_MSPLL_CCORE>, + <&clock CLK_MOUT_MX_MSPLL_CCORE_PHY>, + <&clock CLK_MOUT_MCLK_CDREX>, + clock-names = "fout_spll", + "mout_sclk_spll", + "ff_dout_spll2", + "fout_bpll", + "mout_bpll", + "sclk_bpll", + "mout_mx_mspll_ccore", + "mout_mx_mspll_ccore_phy", + "mout_mclk_cdrex", + operating-points-v2 = <&dmc_opp_table>; + devfreq-events = <&ppmu_event3_dmc0_0>, <&ppmu_event3_dmc0_1>, + <&ppmu_event3_dmc1_0>, <&ppmu_event3_dmc1_1>; + device-handle = <&samsung_K3QF2F20DB>; + vdd-supply = <&buck1_reg>; + samsung,syscon-clk = <&clock>; + }; From patchwork Fri Jun 14 09:53:04 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lukasz Luba X-Patchwork-Id: 10994891 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 976E913AF for ; Fri, 14 Jun 2019 09:54:06 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 87C1D282E8 for ; Fri, 14 Jun 2019 09:54:06 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 85BAE283EE; Fri, 14 Jun 2019 09:54:06 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 49FC5283C9 for ; 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Fri, 14 Jun 2019 09:53:26 +0000 (GMT) From: Lukasz Luba To: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org Cc: mturquette@baylibre.com, sboyd@kernel.org, b.zolnierkie@samsung.com, krzk@kernel.org, kgene@kernel.org, cw00.choi@samsung.com, kyungmin.park@samsung.com, m.szyprowski@samsung.com, s.nawrocki@samsung.com, myungjoo.ham@samsung.com, keescook@chromium.org, tony@atomide.com, jroedel@suse.de, treding@nvidia.com, digetx@gmail.com, gregkh@linuxfoundation.org, willy.mh.wolff.ml@gmail.com, Lukasz Luba Subject: [PATCH v10 08/13] drivers: memory: add DMC driver for Exynos5422 Date: Fri, 14 Jun 2019 11:53:04 +0200 Message-Id: <20190614095309.24100-9-l.luba@partner.samsung.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190614095309.24100-1-l.luba@partner.samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA0WSWUwTURSGvZ3OQmXIUIg9QQKk7kZBgzFXccOIGUlcEvVFQrTKCEZasCNu +FBFFEEQQaEBKiIBScEg2AAawr4oKpUIaEQMUhKJgEuQxh0dp8a3//znO/c/9+YyhHqY9GEO GY4KRoMuVkuplDUdX7uXmg1E5LKRpABcZa4k8fPPb0lc2NZN4vJPDoSTiispnN1lUeDHaXp8 2TFGYLv9Do2fnB2n8UuTL/506TWJn90voPBkehvCZnuDAt9uG6RxT1cYHjhTRuHW8Qsk/tVf pcSNveF44LsHdj4YRhs0vHMqS8l/eJFM8/mmHiV/L2+Q5qutFym+0VJB8+lJ7ym++X29gs+w WRF/91EiP1ntt2PmHtWaKCH20DHBGLRunyrmWlUDGf/6oeLEdEo+MqGfaYpU5MYAtwJyix+S qUjFqLkyBI6bNkIuPiNoLrngKiYRWApGqH8jJc8rXI1bCGqcXX8bf0deflyVihiG4gKhznpE sr05M4L80Z0ST3C1BEwMvEIS48Vtgb66zRKj5OZBZ/8YKWmWWw9PKoaUcpY/lN9pIiTtxm2A 9sJxSjoHuCsMDI5WEjK0CVq+WV0DXvCu00bL2hem7xW67imCKb0Iyfo0OC5bXEwItHb2kNI+ BLcIKu8HyXYoZBS9UUg2cB7wYsJTsok/Mqsml5BtFlLOq2V6IdguPXUFzYJbFTm0jPBw3R4n P1Q2gqaenygT+ef9z7qBkBVphARRHy2IwQbheKCo04sJhujAA3H6avTn5z361TlVhxp+7G9B HIO07mzTakWkmtQdE0/qWxAwhNabvR5CRKrZKN3JU4Ixbq8xIVYQW9BsRqnVsIkzhiLUXLTu qHBYEOIF47+ugnHzMaFt6lLPMjb5nX1/xJeR9aPsfLB1e/aO+eVFb1wZ7vRrYLf7bT0X3m8P y4rJ9F0Q3LfpeIhXju/kcGxqu6bVTVOaRDs+pMQPxfWdWOD1eMnIbtK6drgjdI6l3z3Ae+GZ tt6p9Nrg6Xa2dIsm7SDy7/Wpn+uu2rXdWZQcqrtam6hp1irFGN3yxYRR1P0GdL8fs3UDAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrGIsWRmVeSWpSXmKPExsVy+t/xe7rT85hjDZb+U7bYOGM9q8X1L89Z LeYfOcdqsfrjY0aL5sXr2Swmn5rLZHGmO9ei//FrZovz5zewW5xtesNucatBxuJjzz1Wi8u7 5rBZfO49wmgx4/w+Jou1R+6yW1w85Wpxu3EFm8XhN+2sFv+ubWSx2H/Fy+L2bz6LbyceMTqI e3z7OonF4/2NVnaP2Q0XWTx2zrrL7rFpVSebx/65a9g9epvfsXkcfLeHyaNvyypGj82nqz0+ b5IL4I7SsynKLy1JVcjILy6xVYo2tDDSM7S00DMysdQzNDaPtTIyVdK3s0lJzcksSy3St0vQ y5i6cR9rwb2TTBX/O2YzNjD+7WbqYuTkkBAwkVh6fQ1zFyMXh5DAUkaJ69MXsUMkxCQm7dsO ZQtL/LnWxQZR9IlRYvnC04xdjBwcbAJ6EjtWFYLERQTmMEr87NrGCOIwC5xllti94g0TSJGw gKfE1R1uIINYBFQljl97zQpi8wrYS5xd84AFYoG8xOoNB5hBbE4BB4mj89+wgbQKAdV8n8E/ gZFvASPDKkaR1NLi3PTcYiO94sTc4tK8dL3k/NxNjMA43Hbs55YdjF3vgg8xCnAwKvHwHrBi ihViTSwrrsw9xCjBwawkwjvPmjlWiDclsbIqtSg/vqg0J7X4EKMp0E0TmaVEk/OBKSKvJN7Q 1NDcwtLQ3Njc2MxCSZy3Q+BgjJBAemJJanZqakFqEUwfEwenVANjU/eqpx4Fr9Oiqg/MXm7/ Jfssz06HmRxv/uoFMp2ao7bQ75bDX4/w35kXXD5Un+PZfjfFctf+hMDN8obz2lY0Ju3xOGLw 8YKjX4Gs2RXzhO8sjQLn7/mJh5qoWbC++WW5aUpv8M6W8tTOkkVqayQ0p1suiJQN5dPYzLDu ZUZkBO/70tpnHJ1KLMUZiYZazEXFiQD9vYkW2QIAAA== X-CMS-MailID: 20190614095327eucas1p19b6e522efa15c8fd21c51f3900e376e9 X-Msg-Generator: CA X-RootMTR: 20190614095327eucas1p19b6e522efa15c8fd21c51f3900e376e9 X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20190614095327eucas1p19b6e522efa15c8fd21c51f3900e376e9 References: <20190614095309.24100-1-l.luba@partner.samsung.com> Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch adds driver for Exynos5422 Dynamic Memory Controller. The driver provides support for dynamic frequency and voltage scaling for DMC and DRAM. It supports changing timings of DRAM running with different frequency. There is also an algorithm to calculate timigns based on memory description provided in DT. The patch also contains needed MAINTAINERS file update. Signed-off-by: Lukasz Luba --- MAINTAINERS | 8 + drivers/memory/samsung/Kconfig | 17 + drivers/memory/samsung/Makefile | 1 + drivers/memory/samsung/exynos5422-dmc.c | 1262 +++++++++++++++++++++++ 4 files changed, 1288 insertions(+) create mode 100644 drivers/memory/samsung/exynos5422-dmc.c diff --git a/MAINTAINERS b/MAINTAINERS index 57f496cff999..6ffccfd95351 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -3470,6 +3470,14 @@ S: Maintained F: drivers/devfreq/exynos-bus.c F: Documentation/devicetree/bindings/devfreq/exynos-bus.txt +DMC FREQUENCY DRIVER FOR SAMSUNG EXYNOS5422 +M: Lukasz Luba +L: linux-pm@vger.kernel.org +L: linux-samsung-soc@vger.kernel.org +S: Maintained +F: drivers/memory/samsung/exynos5422-dmc.c +F: Documentation/devicetree/bindings/memory-controllers/exynos5422-dmc.txt + BUSLOGIC SCSI DRIVER M: Khalid Aziz L: linux-scsi@vger.kernel.org diff --git a/drivers/memory/samsung/Kconfig b/drivers/memory/samsung/Kconfig index 79ce7ea58903..c93baa029654 100644 --- a/drivers/memory/samsung/Kconfig +++ b/drivers/memory/samsung/Kconfig @@ -5,6 +5,23 @@ config SAMSUNG_MC Support for the Memory Controller (MC) devices found on Samsung Exynos SoCs. +config ARM_EXYNOS5422_DMC + tristate "ARM EXYNOS5422 Dynamic Memory Controller driver" + depends on ARCH_EXYNOS + select DDR + select PM_DEVFREQ + select DEVFREQ_GOV_SIMPLE_ONDEMAND + select DEVFREQ_GOV_USERSPACE + select PM_DEVFREQ_EVENT + select PM_OPP + help + This adds driver for Exynos5422 DMC (Dynamic Memory Controller). + The driver provides support for Dynamic Voltage and Frequency Scaling in + DMC and DRAM. It also supports changing timings of DRAM running with + different frequency. The timings are calculated based on DT memory + information. + + if SAMSUNG_MC config EXYNOS_SROM diff --git a/drivers/memory/samsung/Makefile b/drivers/memory/samsung/Makefile index 00587be66211..4f6e4383bab7 100644 --- a/drivers/memory/samsung/Makefile +++ b/drivers/memory/samsung/Makefile @@ -1,2 +1,3 @@ # SPDX-License-Identifier: GPL-2.0 +obj-$(CONFIG_ARM_EXYNOS5422_DMC) += exynos5422-dmc.o obj-$(CONFIG_EXYNOS_SROM) += exynos-srom.o diff --git a/drivers/memory/samsung/exynos5422-dmc.c b/drivers/memory/samsung/exynos5422-dmc.c new file mode 100644 index 000000000000..b397efe0da57 --- /dev/null +++ b/drivers/memory/samsung/exynos5422-dmc.c @@ -0,0 +1,1262 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2019 Samsung Electronics Co., Ltd. + * Author: Lukasz Luba + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "../of_memory.h" + +#define EXYNOS5_DREXI_TIMINGAREF (0x0030) +#define EXYNOS5_DREXI_TIMINGROW0 (0x0034) +#define EXYNOS5_DREXI_TIMINGDATA0 (0x0038) +#define EXYNOS5_DREXI_TIMINGPOWER0 (0x003C) +#define EXYNOS5_DREXI_TIMINGROW1 (0x00E4) +#define EXYNOS5_DREXI_TIMINGDATA1 (0x00E8) +#define EXYNOS5_DREXI_TIMINGPOWER1 (0x00EC) +#define CDREX_PAUSE (0x2091c) +#define CDREX_LPDDR3PHY_CON3 (0x20a20) +#define EXYNOS5_TIMING_SET_SWI (1UL << 28) +#define USE_MX_MSPLL_TIMINGS (1) +#define USE_BPLL_TIMINGS (0) +#define EXYNOS5_AREF_NORMAL (0x2e) + +/** + * struct dmc_opp_table - Operating level desciption + * + * Covers frequency and voltage settings of the DMC operating mode. + */ +struct dmc_opp_table { + u32 freq_hz; + u32 volt_uv; +}; + +/** + * struct exynos5_dmc - main structure describing DMC device + * + * The main structure for the Dynamic Memory Controller which covers clocks, + * memory regions, HW information, parameters and current operating mode. + */ +struct exynos5_dmc { + struct device *dev; + struct devfreq *df; + struct devfreq_simple_ondemand_data gov_data; + void __iomem *base_drexi0; + void __iomem *base_drexi1; + struct regmap *clk_regmap; + struct mutex lock; + unsigned long curr_rate; + unsigned long curr_volt; + unsigned long bypass_rate; + struct dmc_opp_table *opp; + struct dmc_opp_table opp_bypass; + int opp_count; + u32 timings_arr_size; + u32 *timing_row; + u32 *timing_data; + u32 *timing_power; + const struct lpddr3_timings *timings; + const struct lpddr3_min_tck *min_tck; + u32 bypass_timing_row; + u32 bypass_timing_data; + u32 bypass_timing_power; + struct regulator *vdd_mif; + struct clk *fout_spll; + struct clk *fout_bpll; + struct clk *mout_spll; + struct clk *mout_bpll; + struct clk *mout_mclk_cdrex; + struct clk *mout_mx_mspll_ccore; + struct clk *mx_mspll_ccore_phy; + struct clk *mout_mx_mspll_ccore_phy; + struct devfreq_event_dev **counter; + int num_counters; +}; + +#define TIMING_FIELD(t_name, t_bit_beg, t_bit_end) \ + { .name = t_name, .bit_beg = t_bit_beg, .bit_end = t_bit_end } + +#define TIMING_VAL(timing_array, id, t_val) \ +({ \ + u32 __val; \ + __val = t_val << timing_array[id].bit_beg; \ + __val; \ +}) + +#define TIMING_VAL2REG(timing, t_val) \ +({ \ + u32 __val; \ + __val = t_val << timing->bit_beg; \ + __val; \ +}) + +#define TIMING_REG2VAL(reg, timing) \ +({ \ + u32 __val; \ + reg <<= (31 - timing->bit_end); \ + reg >>= (31 - timing->bit_end); \ + __val = reg >> timing->bit_beg; \ + __val; \ +}) + +struct timing_reg { + char *name; + int bit_beg; + int bit_end; + unsigned int val; +}; + +static const struct timing_reg timing_row[] = { + TIMING_FIELD("tRFC", 24, 31), + TIMING_FIELD("tRRD", 20, 23), + TIMING_FIELD("tRP", 16, 19), + TIMING_FIELD("tRCD", 12, 15), + TIMING_FIELD("tRC", 6, 11), + TIMING_FIELD("tRAS", 0, 5), +}; + +static const struct timing_reg timing_data[] = { + TIMING_FIELD("tWTR", 28, 31), + TIMING_FIELD("tWR", 24, 27), + TIMING_FIELD("tRTP", 20, 23), + TIMING_FIELD("tW2W-C2C", 14, 14), + TIMING_FIELD("tR2R-C2C", 12, 12), + TIMING_FIELD("WL", 8, 11), + TIMING_FIELD("tDQSCK", 4, 7), + TIMING_FIELD("RL", 0, 3), +}; + +static const struct timing_reg timing_power[] = { + TIMING_FIELD("tFAW", 26, 31), + TIMING_FIELD("tXSR", 16, 25), + TIMING_FIELD("tXP", 8, 15), + TIMING_FIELD("tCKE", 4, 7), + TIMING_FIELD("tMRD", 0, 3), +}; + +#define TIMING_COUNT (ARRAY_SIZE(timing_row) + ARRAY_SIZE(timing_data) + \ + ARRAY_SIZE(timing_power)) + +static int exynos5_counters_set_event(struct exynos5_dmc *dmc) +{ + int i, ret; + + for (i = 0; i < dmc->num_counters; i++) { + if (!dmc->counter[i]) + continue; + ret = devfreq_event_set_event(dmc->counter[i]); + if (ret < 0) + return ret; + } + return 0; +} + +static int exynos5_counters_enable_edev(struct exynos5_dmc *dmc) +{ + int i, ret; + + for (i = 0; i < dmc->num_counters; i++) { + if (!dmc->counter[i]) + continue; + ret = devfreq_event_enable_edev(dmc->counter[i]); + if (ret < 0) + return ret; + } + return 0; +} + +static int exynos5_counters_disable_edev(struct exynos5_dmc *dmc) +{ + int i, ret; + + for (i = 0; i < dmc->num_counters; i++) { + if (!dmc->counter[i]) + continue; + ret = devfreq_event_disable_edev(dmc->counter[i]); + if (ret < 0) + return ret; + } + return 0; +} + +/** + * find_target_freq_id() - Finds requested frequency in local DMC configuration + * @dmc: device for which the information is checked + * @target_rate: requested frequency in KHz + * + * Seeks in the local DMC driver structure for the requested frequency value + * and returns index or error value. + */ +static int find_target_freq_idx(struct exynos5_dmc *dmc, + unsigned long target_rate) +{ + int i; + + for (i = dmc->opp_count - 1; i >= 0; i--) + if (dmc->opp[i].freq_hz <= target_rate) + return i; + + return -EINVAL; +} + +/** + * exynos5_switch_timing_regs() - Changes bank register set for DRAM timings + * @dmc: device for which the new settings is going to be applied + * @set: boolean variable passing set value + * + * Changes the register set, which holds timing parameters. + * There is two register sets: 0 and 1. The register set 0 + * is used in normal operation when the clock is provided from main PLL. + * The bank register set 1 is used when the main PLL frequency is going to be + * changed and the clock is taken from alternative, stable source. + * This function switches between these banks according to the + * currently used clock source. + */ +static void exynos5_switch_timing_regs(struct exynos5_dmc *dmc, bool set) +{ + unsigned int reg; + int ret; + + ret = regmap_read(dmc->clk_regmap, CDREX_LPDDR3PHY_CON3, ®); + + if (set) + reg |= EXYNOS5_TIMING_SET_SWI; + else + reg &= ~EXYNOS5_TIMING_SET_SWI; + + regmap_write(dmc->clk_regmap, CDREX_LPDDR3PHY_CON3, reg); +} + +/** + * exynos5_init_freq_table() - Initialized PM OPP framework + * @dmc: DMC device for which the frequencies are used for OPP init + * @profile: devfreq device's profile + * + * Populate the devfreq device's OPP table based on current frequency, voltage. + */ +static int exynos5_init_freq_table(struct exynos5_dmc *dmc, + struct devfreq_dev_profile *profile) +{ + int i, ret; + int idx; + unsigned long freq; + + ret = dev_pm_opp_of_add_table(dmc->dev); + if (ret < 0) { + dev_err(dmc->dev, "Failed to get OPP table\n"); + return ret; + } + + dmc->opp_count = dev_pm_opp_get_opp_count(dmc->dev); + + dmc->opp = devm_kmalloc_array(dmc->dev, dmc->opp_count, + sizeof(struct dmc_opp_table), GFP_KERNEL); + if (!dmc->opp) + goto err_opp; + + idx = dmc->opp_count - 1; + for (i = 0, freq = ULONG_MAX; i < dmc->opp_count; i++, freq--) { + struct dev_pm_opp *opp; + + opp = dev_pm_opp_find_freq_floor(dmc->dev, &freq); + if (IS_ERR(opp)) + goto err_free_tables; + + dmc->opp[idx - i].freq_hz = freq; + dmc->opp[idx - i].volt_uv = dev_pm_opp_get_voltage(opp); + + dev_pm_opp_put(opp); + } + + return 0; + +err_free_tables: + kfree(dmc->opp); +err_opp: + dev_pm_opp_of_remove_table(dmc->dev); + + return -EINVAL; +} + +/** + * exynos5_set_bypass_dram_timings() - Low-level changes of the DRAM timings + * @dmc: device for which the new settings is going to be applied + * @param: DRAM parameters which passes timing data + * + * Low-level function for changing timings for DRAM memory clocking from + * 'bypass' clock source (fixed frequency @400MHz). + * It uses timing bank registers set 1. + */ +static void exynos5_set_bypass_dram_timings(struct exynos5_dmc *dmc) +{ + writel(EXYNOS5_AREF_NORMAL, + dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGAREF); + + writel(dmc->bypass_timing_row, + dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGROW1); + writel(dmc->bypass_timing_row, + dmc->base_drexi1 + EXYNOS5_DREXI_TIMINGROW1); + writel(dmc->bypass_timing_data, + dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGDATA1); + writel(dmc->bypass_timing_data, + dmc->base_drexi1 + EXYNOS5_DREXI_TIMINGDATA1); + writel(dmc->bypass_timing_power, + dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGPOWER1); + writel(dmc->bypass_timing_power, + dmc->base_drexi1 + EXYNOS5_DREXI_TIMINGPOWER1); +} + +/** + * exynos5_dram_change_timings() - Low-level changes of the DRAM final timings + * @dmc: device for which the new settings is going to be applied + * @target_rate: target frequency of the DMC + * + * Low-level function for changing timings for DRAM memory operating from main + * clock source (BPLL), which can have different frequencies. Thus, each + * frequency must have corresponding timings register values in order to keep + * the needed delays. + * It uses timing bank registers set 0. + */ +static int exynos5_dram_change_timings(struct exynos5_dmc *dmc, + unsigned long target_rate) +{ + int idx; + + for (idx = dmc->opp_count - 1; idx >= 0; idx--) + if (dmc->opp[idx].freq_hz <= target_rate) + break; + + if (idx < 0) + return -EINVAL; + + writel(EXYNOS5_AREF_NORMAL, + dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGAREF); + + writel(dmc->timing_row[idx], + dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGROW0); + writel(dmc->timing_row[idx], + dmc->base_drexi1 + EXYNOS5_DREXI_TIMINGROW0); + writel(dmc->timing_data[idx], + dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGDATA0); + writel(dmc->timing_data[idx], + dmc->base_drexi1 + EXYNOS5_DREXI_TIMINGDATA0); + writel(dmc->timing_power[idx], + dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGPOWER0); + writel(dmc->timing_power[idx], + dmc->base_drexi1 + EXYNOS5_DREXI_TIMINGPOWER0); + + return 0; +} + +/** + * exynos5_dmc_align_target_voltage() - Sets the final voltage for the DMC + * @dmc: device for which it is going to be set + * @target_volt: new voltage which is chosen to be final + * + * Function tries to align voltage to the safe level for 'normal' mode. + * It checks the need of higher voltage and changes the value. The target + * voltage might be lower that currently set and still the system will be + * stable. + */ +static int exynos5_dmc_align_target_voltage(struct exynos5_dmc *dmc, + unsigned long target_volt) +{ + int ret = 0; + + if (dmc->curr_volt <= target_volt) + return 0; + + ret = regulator_set_voltage(dmc->vdd_mif, target_volt, + target_volt); + if (!ret) + dmc->curr_volt = target_volt; + + return ret; +} + +/** + * exynos5_dmc_align_bypass_voltage() - Sets the voltage for the DMC + * @dmc: device for which it is going to be set + * @target_volt: new voltage which is chosen to be final + * + * Function tries to align voltage to the safe level for the 'bypass' mode. + * It checks the need of higher voltage and changes the value. + * The target voltage must not be less than currently needed, because + * for current frequency the device might become unstable. + */ +static int exynos5_dmc_align_bypass_voltage(struct exynos5_dmc *dmc, + unsigned long target_volt) +{ + int ret = 0; + unsigned long bypass_volt = dmc->opp_bypass.volt_uv; + + target_volt = max(bypass_volt, target_volt); + + if (dmc->curr_volt >= target_volt) + return 0; + + ret = regulator_set_voltage(dmc->vdd_mif, target_volt, + target_volt); + if (!ret) + dmc->curr_volt = target_volt; + + return ret; +} + +/** + * exynos5_dmc_align_bypass_dram_timings() - Chooses and sets DRAM timings + * @dmc: device for which it is going to be set + * @target_rate: new frequency which is chosen to be final + * + * Function changes the DRAM timings for the temporary 'bypass' mode. + */ +static int exynos5_dmc_align_bypass_dram_timings(struct exynos5_dmc *dmc, + unsigned long target_rate) +{ + int idx = find_target_freq_idx(dmc, target_rate); + + if (idx < 0) + return -EINVAL; + + exynos5_set_bypass_dram_timings(dmc); + + return 0; +} + +/** + * exynos5_dmc_switch_to_bypass_configuration() - Switching to temporary clock + * @dmc: DMC device for which the switching is going to happen + * @target_rate: new frequency which is going to be set as a final + * @target_volt: new voltage which is going to be set as a final + * + * Function configures DMC and clocks for operating in temporary 'bypass' mode. + * This mode is used only temporary but if required, changes voltage and timings + * for DRAM chips. It switches the main clock to stable clock source for the + * period of the main PLL reconfiguration. + */ +static int exynos5_dmc_switch_to_bypass_configuration(struct exynos5_dmc *dmc, + unsigned long target_rate, + unsigned long target_volt) +{ + int ret; + + /* + * Having higher voltage for a particular frequency does not harm + * the chip. Use it for the temporary frequency change when one + * voltage manipulation might be avoided. + */ + ret = exynos5_dmc_align_bypass_voltage(dmc, target_volt); + if (ret) + return ret; + + /* + * Longer delays for DRAM does not cause crash, the opposite does. + */ + ret = exynos5_dmc_align_bypass_dram_timings(dmc, target_rate); + if (ret) + return ret; + + /* + * Delays are long enough, so use them for the new coming clock. + */ + exynos5_switch_timing_regs(dmc, USE_MX_MSPLL_TIMINGS); + + return ret; +} + +/** + * exynos5_dmc_change_freq_and_volt() - Changes voltage and frequency of the DMC + * using safe procedure + * @dmc: device for which the frequency is going to be changed + * @target_rate: requested new frequency + * @target_volt: requested voltage which corresponds to the new frequency + * + * The DMC frequency change procedure requires a few steps. + * The main requirement is to change the clock source in the clk mux + * for the time of main clock PLL locking. The assumption is that the + * alternative clock source set as parent is stable. + * The second parent's clock frequency is fixed to 400MHz, it is named 'bypass' + * clock. This requires alignment in DRAM timing parameters for the new + * T-period. There is two bank sets for keeping DRAM + * timings: set 0 and set 1. The set 0 is used when main clock source is + * chosen. The 2nd set of regs is used for 'bypass' clock. Switching between + * the two bank sets is part of the process. + * The voltage must also be aligned to the minimum required level. There is + * this intermediate step with switching to 'bypass' parent clock source. + * if the old voltage is lower, it requires an increase of the voltage level. + * The complexity of the voltage manipulation is hidden in low level function. + * In this function there is last alignment of the voltage level at the end. + */ +static int +exynos5_dmc_change_freq_and_volt(struct exynos5_dmc *dmc, + unsigned long target_rate, + unsigned long target_volt) +{ + int ret; + + ret = exynos5_dmc_switch_to_bypass_configuration(dmc, target_rate, + target_volt); + if (ret) + return ret; + + /* + * Voltage is set at least to a level needed for this frequency, + * so switching clock source is safe now. + */ + clk_prepare_enable(dmc->fout_spll); + clk_prepare_enable(dmc->mout_spll); + clk_prepare_enable(dmc->mout_mx_mspll_ccore); + + ret = clk_set_parent(dmc->mout_mclk_cdrex, dmc->mout_mx_mspll_ccore); + if (ret) + goto disable_clocks; + + /* + * We are safe to increase the timings for current bypass frequency. + * Thanks to this the settings we be ready for the upcoming clock source + * change. + */ + exynos5_dram_change_timings(dmc, target_rate); + + clk_set_rate(dmc->fout_bpll, target_rate); + + exynos5_switch_timing_regs(dmc, USE_BPLL_TIMINGS); + + ret = clk_set_parent(dmc->mout_mclk_cdrex, dmc->mout_bpll); + if (ret) + goto disable_clocks; + + /* + * Make sure if the voltage is not from 'bypass' settings and align to + * the right level for power efficiency. + */ + ret = exynos5_dmc_align_target_voltage(dmc, target_volt); + +disable_clocks: + clk_disable_unprepare(dmc->mout_mx_mspll_ccore); + clk_disable_unprepare(dmc->mout_spll); + clk_disable_unprepare(dmc->fout_spll); + + return ret; +} + +/** + * exynos5_dmc_get_volt_freq() - Gets the frequency and voltage from the OPP + * table. + * @dmc: device for which the frequency is going to be changed + * @freq: requested frequency in KHz + * @target_rate: returned frequency which is the same or lower than + * requested + * @target_volt: returned voltage which corresponds to the returned + * frequency + * + * Function gets requested frequency and checks OPP framework for needed + * frequency and voltage. It populates the values 'target_rate' and + * 'target_volt' or returns error value when OPP framework fails. + */ +static int exynos5_dmc_get_volt_freq(struct exynos5_dmc *dmc, + unsigned long *freq, + unsigned long *target_rate, + unsigned long *target_volt, u32 flags) +{ + struct dev_pm_opp *opp; + + opp = devfreq_recommended_opp(dmc->dev, freq, flags); + if (IS_ERR(opp)) + return PTR_ERR(opp); + + *target_rate = dev_pm_opp_get_freq(opp); + *target_volt = dev_pm_opp_get_voltage(opp); + dev_pm_opp_put(opp); + + return 0; +} + +/** + * exynos5_dmc_target() - Function responsible for changing frequency of DMC + * @dev: device for which the frequency is going to be changed + * @freq: requested frequency in KHz + * @flags: flags provided for this frequency change request + * + * An entry function provided to the devfreq framework which provides frequency + * change of the DMC. The function gets the possible rate from OPP table based + * on requested frequency. It calls the next function responsible for the + * frequency and voltage change. In case of failure, does not set 'curr_rate' + * and returns error value to the framework. + */ +static int exynos5_dmc_target(struct device *dev, unsigned long *freq, + u32 flags) +{ + struct exynos5_dmc *dmc = dev_get_drvdata(dev); + unsigned long target_rate = 0; + unsigned long target_volt = 0; + int ret; + + ret = exynos5_dmc_get_volt_freq(dmc, freq, &target_rate, &target_volt, + flags); + + if (ret) + return ret; + + if (target_rate == dmc->curr_rate) + return 0; + + mutex_lock(&dmc->lock); + + ret = exynos5_dmc_change_freq_and_volt(dmc, target_rate, target_volt); + + if (ret) { + mutex_unlock(&dmc->lock); + return ret; + } + + dmc->curr_rate = target_rate; + + mutex_unlock(&dmc->lock); + return 0; +} + +/** + * exynos5_counters_get() - Gets the performance counters values. + * @dmc: device for which the counters are going to be checked + * @load_count: variable which is populated with counter value + * @total_count: variable which is used as 'wall clock' reference + * + * Function which provides performance counters values. It sums up counters for + * two DMC channels. The 'total_count' is used as a reference and max value. + * The ratio 'load_count/total_count' shows the busy percentage [0%, 100%]. + */ +static int exynos5_counters_get(struct exynos5_dmc *dmc, + unsigned long *load_count, + unsigned long *total_count) +{ + unsigned long total = 0; + struct devfreq_event_data event; + int ret, i; + + *load_count = 0; + + /* Take into account only read+write counters, but stop all */ + for (i = 0; i < dmc->num_counters; i++) { + if (!dmc->counter[i]) + continue; + + ret = devfreq_event_get_event(dmc->counter[i], &event); + if (ret < 0) + return ret; + + *load_count += event.load_count; + + if (total < event.total_count) + total = event.total_count; + } + + *total_count = total; + + return 0; +} + +/** + * exynos5_dmc_get_status() - Read current DMC performance statistics. + * @dev: device for which the statistics are requested + * @stat: structure which has statistic fields + * + * Function reads the DMC performance counters and calculates 'busy_time' + * and 'total_time'. To protect from overflow, the values are shifted right + * by 10. After read out the counters are setup to count again. + */ +static int exynos5_dmc_get_status(struct device *dev, + struct devfreq_dev_status *stat) +{ + struct exynos5_dmc *dmc = dev_get_drvdata(dev); + unsigned long load, total; + int ret; + + ret = exynos5_counters_get(dmc, &load, &total); + if (ret < 0) + return -EINVAL; + + /* To protect from overflow in calculation ratios, divide by 1024 */ + stat->busy_time = load >> 10; + stat->total_time = total >> 10; + + ret = exynos5_counters_set_event(dmc); + if (ret < 0) { + dev_err(dev, "could not set event counter\n"); + return ret; + } + + return 0; +} + +/** + * exynos5_dmc_get_cur_freq() - Function returns current DMC frequency + * @dev: device for which the framework checks operating frequency + * @freq: returned frequency value + * + * It returns the currently used frequency of the DMC. The real operating + * frequency might be lower when the clock source value could not be divided + * to the requested value. + */ +static int exynos5_dmc_get_cur_freq(struct device *dev, unsigned long *freq) +{ + struct exynos5_dmc *dmc = dev_get_drvdata(dev); + + mutex_lock(&dmc->lock); + *freq = dmc->curr_rate; + mutex_unlock(&dmc->lock); + + return 0; +} + +/** + * exynos5_dmc_df_profile - Devfreq governor's profile structure + * + * It provides to the devfreq framework needed functions and polling period. + */ +static struct devfreq_dev_profile exynos5_dmc_df_profile = { + .polling_ms = 500, + .target = exynos5_dmc_target, + .get_dev_status = exynos5_dmc_get_status, + .get_cur_freq = exynos5_dmc_get_cur_freq, +}; + +/** + * exynos5_dmc_align_initial_frequency() - Align initial frequency value + * @dmc: device for which the frequency is going to be set + * @bootloader_init_freq: initial frequency set by the bootloader in KHz + * + * The initial bootloader frequency, which is present during boot, might be + * different that supported frequency values in the driver. It is possible + * due to different PLL settings or used PLL as a source. + * This function provides the 'initial_freq' for the devfreq framework + * statistics engine which supports only registered values. Thus, some alignment + * must be made. + */ +unsigned long +exynos5_dmc_align_init_freq(struct exynos5_dmc *dmc, + unsigned long bootloader_init_freq) +{ + unsigned long aligned_freq; + int idx; + + idx = find_target_freq_idx(dmc, bootloader_init_freq); + if (idx >= 0) + aligned_freq = dmc->opp[idx].freq_hz; + else + aligned_freq = dmc->opp[dmc->opp_count - 1].freq_hz; + + return aligned_freq; +} + +/** + * create_timings_aligned() - Create register values and align with standard + * @dmc: device for which the frequency is going to be set + * @idx: speed bin in the OPP table + * @clk_period_ps: the period of the clock, known as tCK + * + * The function calculates timings and creates a register value ready for + * a frequency transition. The register contains a few timings. They are + * shifted by a known offset. The timing value is calculated based on memory + * specyfication: minimal time required and minimal cycles required. + */ +static int create_timings_aligned(struct exynos5_dmc *dmc, u32 *reg_timing_row, + u32 *reg_timing_data, u32 *reg_timing_power, + u32 clk_period_ps) +{ + u32 val; + const struct timing_reg *reg; + + if (clk_period_ps == 0) + return -EINVAL; + + *reg_timing_row = 0; + *reg_timing_data = 0; + *reg_timing_power = 0; + + val = dmc->timings->tRFC / clk_period_ps; + val += dmc->timings->tRFC % clk_period_ps ? 1 : 0; + val = max(val, dmc->min_tck->tRFC); + reg = &timing_row[0]; + *reg_timing_row |= TIMING_VAL2REG(reg, val); + + val = dmc->timings->tRRD / clk_period_ps; + val += dmc->timings->tRRD % clk_period_ps ? 1 : 0; + val = max(val, dmc->min_tck->tRRD); + reg = &timing_row[1]; + *reg_timing_row |= TIMING_VAL2REG(reg, val); + + val = dmc->timings->tRPab / clk_period_ps; + val += dmc->timings->tRPab % clk_period_ps ? 1 : 0; + val = max(val, dmc->min_tck->tRPab); + reg = &timing_row[2]; + *reg_timing_row |= TIMING_VAL2REG(reg, val); + + val = dmc->timings->tRCD / clk_period_ps; + val += dmc->timings->tRCD % clk_period_ps ? 1 : 0; + val = max(val, dmc->min_tck->tRCD); + reg = &timing_row[3]; + *reg_timing_row |= TIMING_VAL2REG(reg, val); + + val = dmc->timings->tRC / clk_period_ps; + val += dmc->timings->tRC % clk_period_ps ? 1 : 0; + val = max(val, dmc->min_tck->tRC); + reg = &timing_row[4]; + *reg_timing_row |= TIMING_VAL2REG(reg, val); + + val = dmc->timings->tRAS / clk_period_ps; + val += dmc->timings->tRAS % clk_period_ps ? 1 : 0; + val = max(val, dmc->min_tck->tRAS); + reg = &timing_row[5]; + *reg_timing_row |= TIMING_VAL2REG(reg, val); + + /* data related timings */ + val = dmc->timings->tWTR / clk_period_ps; + val += dmc->timings->tWTR % clk_period_ps ? 1 : 0; + val = max(val, dmc->min_tck->tWTR); + reg = &timing_data[0]; + *reg_timing_data |= TIMING_VAL2REG(reg, val); + + val = dmc->timings->tWR / clk_period_ps; + val += dmc->timings->tWR % clk_period_ps ? 1 : 0; + val = max(val, dmc->min_tck->tWR); + reg = &timing_data[1]; + *reg_timing_data |= TIMING_VAL2REG(reg, val); + + val = dmc->timings->tRTP / clk_period_ps; + val += dmc->timings->tRTP % clk_period_ps ? 1 : 0; + val = max(val, dmc->min_tck->tRTP); + reg = &timing_data[2]; + *reg_timing_data |= TIMING_VAL2REG(reg, val); + + val = dmc->timings->tW2W_C2C / clk_period_ps; + val += dmc->timings->tW2W_C2C % clk_period_ps ? 1 : 0; + val = max(val, dmc->min_tck->tW2W_C2C); + reg = &timing_data[3]; + *reg_timing_data |= TIMING_VAL2REG(reg, val); + + val = dmc->timings->tR2R_C2C / clk_period_ps; + val += dmc->timings->tR2R_C2C % clk_period_ps ? 1 : 0; + val = max(val, dmc->min_tck->tR2R_C2C); + reg = &timing_data[4]; + *reg_timing_data |= TIMING_VAL2REG(reg, val); + + val = dmc->timings->tWL / clk_period_ps; + val += dmc->timings->tWL % clk_period_ps ? 1 : 0; + val = max(val, dmc->min_tck->tWL); + reg = &timing_data[5]; + *reg_timing_data |= TIMING_VAL2REG(reg, val); + + val = dmc->timings->tDQSCK / clk_period_ps; + val += dmc->timings->tDQSCK % clk_period_ps ? 1 : 0; + val = max(val, dmc->min_tck->tDQSCK); + reg = &timing_data[6]; + *reg_timing_data |= TIMING_VAL2REG(reg, val); + + val = dmc->timings->tRL / clk_period_ps; + val += dmc->timings->tRL % clk_period_ps ? 1 : 0; + val = max(val, dmc->min_tck->tRL); + reg = &timing_data[7]; + *reg_timing_data |= TIMING_VAL2REG(reg, val); + + /* power related timings */ + val = dmc->timings->tFAW / clk_period_ps; + val += dmc->timings->tFAW % clk_period_ps ? 1 : 0; + val = max(val, dmc->min_tck->tXP); + reg = &timing_power[0]; + *reg_timing_power |= TIMING_VAL2REG(reg, val); + + val = dmc->timings->tXSR / clk_period_ps; + val += dmc->timings->tXSR % clk_period_ps ? 1 : 0; + val = max(val, dmc->min_tck->tXSR); + reg = &timing_power[1]; + *reg_timing_power |= TIMING_VAL2REG(reg, val); + + val = dmc->timings->tXP / clk_period_ps; + val += dmc->timings->tXP % clk_period_ps ? 1 : 0; + val = max(val, dmc->min_tck->tXP); + reg = &timing_power[2]; + *reg_timing_power |= TIMING_VAL2REG(reg, val); + + val = dmc->timings->tCKE / clk_period_ps; + val += dmc->timings->tCKE % clk_period_ps ? 1 : 0; + val = max(val, dmc->min_tck->tCKE); + reg = &timing_power[3]; + *reg_timing_power |= TIMING_VAL2REG(reg, val); + + val = dmc->timings->tMRD / clk_period_ps; + val += dmc->timings->tMRD % clk_period_ps ? 1 : 0; + val = max(val, dmc->min_tck->tMRD); + reg = &timing_power[4]; + *reg_timing_power |= TIMING_VAL2REG(reg, val); + + return 0; +} + +/** + * of_get_dram_timings() - helper function for parsing DT settings for DRAM + * @dmc: device for which the frequency is going to be set + * + * The function parses DT entries with DRAM information. + */ +static int of_get_dram_timings(struct exynos5_dmc *dmc) +{ + int ret = 0; + int idx; + struct device_node *np_ddr; + u32 freq_mhz, clk_period_ps; + + np_ddr = of_parse_phandle(dmc->dev->of_node, "device-handle", 0); + if (!np_ddr) { + dev_warn(dmc->dev, "could not find 'device-handle' in DT\n"); + return -EINVAL; + } + + dmc->timing_row = devm_kmalloc_array(dmc->dev, TIMING_COUNT, + sizeof(u32), GFP_KERNEL); + if (!dmc->timing_row) + return -ENOMEM; + + dmc->timing_data = devm_kmalloc_array(dmc->dev, TIMING_COUNT, + sizeof(u32), GFP_KERNEL); + if (!dmc->timing_data) + return -ENOMEM; + + dmc->timing_power = devm_kmalloc_array(dmc->dev, TIMING_COUNT, + sizeof(u32), GFP_KERNEL); + if (!dmc->timing_power) + return -ENOMEM; + + dmc->timings = of_lpddr3_get_ddr_timings(np_ddr, dmc->dev, + DDR_TYPE_LPDDR3, + &dmc->timings_arr_size); + if (!dmc->timings) { + of_node_put(np_ddr); + dev_warn(dmc->dev, "could not get timings from DT\n"); + return -EINVAL; + } + + dmc->min_tck = of_lpddr3_get_min_tck(np_ddr, dmc->dev); + if (!dmc->min_tck) { + of_node_put(np_ddr); + dev_warn(dmc->dev, "could not get tck from DT\n"); + return -EINVAL; + } + + /* Sorted array of OPPs with frequency ascending */ + for (idx = 0; idx < dmc->opp_count; idx++) { + freq_mhz = dmc->opp[idx].freq_hz / 1000000; + clk_period_ps = 1000000 / freq_mhz; + + ret = create_timings_aligned(dmc, &dmc->timing_row[idx], + &dmc->timing_data[idx], + &dmc->timing_power[idx], + clk_period_ps); + } + + of_node_put(np_ddr); + + /* Take the highest frequency's timings as 'bypass' */ + dmc->bypass_timing_row = dmc->timing_row[idx - 1]; + dmc->bypass_timing_data = dmc->timing_data[idx - 1]; + dmc->bypass_timing_power = dmc->timing_power[idx - 1]; + + return ret; +} + +/** + * exynos5_dmc_init_clks() - Initialize clocks needed for DMC operation. + * @dmc: DMC structure containing needed fields + * + * Get the needed clocks defined in DT device, enable and set the right parents. + * Read current frequency and initialize the initial rate for governor. + */ +static int exynos5_dmc_init_clks(struct exynos5_dmc *dmc) +{ + int ret; + unsigned long target_volt = 0; + unsigned long target_rate = 0; + + dmc->fout_spll = devm_clk_get(dmc->dev, "fout_spll"); + if (IS_ERR(dmc->fout_spll)) + return PTR_ERR(dmc->fout_spll); + + dmc->fout_bpll = devm_clk_get(dmc->dev, "fout_bpll"); + if (IS_ERR(dmc->fout_bpll)) + return PTR_ERR(dmc->fout_bpll); + + dmc->mout_mclk_cdrex = devm_clk_get(dmc->dev, "mout_mclk_cdrex"); + if (IS_ERR(dmc->mout_mclk_cdrex)) + return PTR_ERR(dmc->mout_mclk_cdrex); + + dmc->mout_bpll = devm_clk_get(dmc->dev, "mout_bpll"); + if (IS_ERR(dmc->mout_bpll)) + return PTR_ERR(dmc->mout_bpll); + + dmc->mout_mx_mspll_ccore = devm_clk_get(dmc->dev, + "mout_mx_mspll_ccore"); + if (IS_ERR(dmc->mout_mx_mspll_ccore)) + return PTR_ERR(dmc->mout_mx_mspll_ccore); + + dmc->mout_spll = devm_clk_get(dmc->dev, "ff_dout_spll2"); + if (IS_ERR(dmc->mout_spll)) { + dmc->mout_spll = devm_clk_get(dmc->dev, "mout_sclk_spll"); + if (IS_ERR(dmc->mout_spll)) + return PTR_ERR(dmc->mout_spll); + } + + /* + * Convert frequency to KHz values and set it for the governor. + */ + dmc->curr_rate = clk_get_rate(dmc->mout_mclk_cdrex); + dmc->curr_rate = exynos5_dmc_align_init_freq(dmc, dmc->curr_rate); + exynos5_dmc_df_profile.initial_freq = dmc->curr_rate; + + ret = exynos5_dmc_get_volt_freq(dmc, &dmc->curr_rate, &target_rate, + &target_volt, 0); + if (ret) + return ret; + + dmc->curr_volt = target_volt; + + clk_set_parent(dmc->mout_mx_mspll_ccore, dmc->mout_spll); + + dmc->bypass_rate = clk_get_rate(dmc->mout_mx_mspll_ccore); + + clk_prepare_enable(dmc->fout_bpll); + clk_prepare_enable(dmc->mout_bpll); + + return 0; +} + +/** + * exynos5_performance_counters_init() - Initializes performance DMC's counters + * @dmc: DMC for which it does the setup + * + * Initialization of performance counters in DMC for estimating usage. + * The counter's values are used for calculation of a memory bandwidth and based + * on that the governor changes the frequency. + * The counters are not used when the governor is GOVERNOR_USERSPACE. + */ +static int exynos5_performance_counters_init(struct exynos5_dmc *dmc) +{ + int counters_size; + int ret, i; + + dmc->num_counters = devfreq_event_get_edev_count(dmc->dev); + if (dmc->num_counters < 0) { + dev_err(dmc->dev, "could not get devfreq-event counters\n"); + return dmc->num_counters; + } + + counters_size = sizeof(struct devfreq_event_dev) * dmc->num_counters; + dmc->counter = devm_kzalloc(dmc->dev, counters_size, GFP_KERNEL); + if (!dmc->counter) + return -ENOMEM; + + for (i = 0; i < dmc->num_counters; i++) { + dmc->counter[i] = + devfreq_event_get_edev_by_phandle(dmc->dev, i); + if (IS_ERR_OR_NULL(dmc->counter[i])) + return -EPROBE_DEFER; + } + + ret = exynos5_counters_enable_edev(dmc); + if (ret < 0) { + dev_err(dmc->dev, "could not enable event counter\n"); + return ret; + } + + ret = exynos5_counters_set_event(dmc); + if (ret < 0) { + exynos5_counters_disable_edev(dmc); + dev_err(dmc->dev, "counld not set event counter\n"); + return ret; + } + + return 0; +} + +/** + * exynos5_dmc_set_pause_on_switching() - Controls a pause feature in DMC + * @dmc: device which is used for changing this feature + * @set: a boolean state passing enable/disable request + * + * There is a need of pausing DREX DMC when divider or MUX in clock tree + * changes its configuration. In such situation access to the memory is blocked + * in DMC automatically. This feature is used when clock frequency change + * request appears and touches clock tree. + */ +static inline int exynos5_dmc_set_pause_on_switching(struct exynos5_dmc *dmc) +{ + unsigned int val; + int ret; + + ret = regmap_read(dmc->clk_regmap, CDREX_PAUSE, &val); + if (ret) + return ret; + + val |= 1UL; + regmap_write(dmc->clk_regmap, CDREX_PAUSE, val); + + return 0; +} + +/** + * exynos5_dmc_probe() - Probe function for the DMC driver + * @pdev: platform device for which the driver is going to be initialized + * + * Initialize basic components: clocks, regulators, performance counters, etc. + * Read out product version and based on the information setup + * internal structures for the controller (frequency and voltage) and for DRAM + * memory parameters: timings for each operating frequency. + * Register new devfreq device for controlling DVFS of the DMC. + */ +static int exynos5_dmc_probe(struct platform_device *pdev) +{ + int ret = 0; + struct device *dev = &pdev->dev; + struct device_node *np = dev->of_node; + struct exynos5_dmc *dmc; + struct resource *res; + + dmc = devm_kzalloc(dev, sizeof(*dmc), GFP_KERNEL); + if (!dmc) + return -ENOMEM; + + mutex_init(&dmc->lock); + + dmc->dev = dev; + platform_set_drvdata(pdev, dmc); + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + dmc->base_drexi0 = devm_ioremap_resource(dev, res); + if (IS_ERR(dmc->base_drexi0)) + return PTR_ERR(dmc->base_drexi0); + + res = platform_get_resource(pdev, IORESOURCE_MEM, 1); + dmc->base_drexi1 = devm_ioremap_resource(dev, res); + if (IS_ERR(dmc->base_drexi1)) + return PTR_ERR(dmc->base_drexi1); + + dmc->clk_regmap = syscon_regmap_lookup_by_phandle(np, + "samsung,syscon-clk"); + if (IS_ERR(dmc->clk_regmap)) + return PTR_ERR(dmc->clk_regmap); + + ret = exynos5_init_freq_table(dmc, &exynos5_dmc_df_profile); + if (ret) { + dev_warn(dev, "couldn't initialize frequency settings\n"); + return ret; + } + + dmc->vdd_mif = devm_regulator_get(dev, "vdd"); + if (IS_ERR(dmc->vdd_mif)) { + ret = PTR_ERR(dmc->vdd_mif); + return ret; + } + + ret = exynos5_dmc_init_clks(dmc); + if (ret) + return ret; + + ret = of_get_dram_timings(dmc); + if (ret) { + dev_warn(dev, "couldn't initialize timings settings\n"); + goto remove_clocks; + } + + ret = exynos5_performance_counters_init(dmc); + if (ret) { + dev_warn(dev, "couldn't probe performance counters\n"); + goto remove_clocks; + } + + ret = exynos5_dmc_set_pause_on_switching(dmc); + if (ret) { + dev_warn(dev, "couldn't get access to PAUSE register\n"); + goto err_devfreq_add; + } + + /* + * Setup default thresholds for the devfreq governor. + * The values are chosen based on experiments. + */ + dmc->gov_data.upthreshold = 30; + dmc->gov_data.downdifferential = 5; + + dmc->df = devm_devfreq_add_device(dev, &exynos5_dmc_df_profile, + DEVFREQ_GOV_USERSPACE, + &dmc->gov_data); + + if (IS_ERR(dmc->df)) { + ret = PTR_ERR(dmc->df); + goto err_devfreq_add; + } + + dev_info(dev, "DMC initialized\n"); + + return 0; + +err_devfreq_add: + exynos5_counters_disable_edev(dmc); +remove_clocks: + clk_disable_unprepare(dmc->mout_bpll); + clk_disable_unprepare(dmc->fout_bpll); + + return ret; +} + +/** + * exynos5_dmc_remove() - Remove function for the platform device + * @pdev: platform device which is going to be removed + * + * The function relies on 'devm' framework function which automatically + * clean the device's resources. It just calls explicitly disable function for + * the performance counters. + */ +static int exynos5_dmc_remove(struct platform_device *pdev) +{ + struct exynos5_dmc *dmc = dev_get_drvdata(&pdev->dev); + + exynos5_counters_disable_edev(dmc); + + clk_disable_unprepare(dmc->mout_bpll); + clk_disable_unprepare(dmc->fout_bpll); + + dev_pm_opp_remove_table(dmc->dev); + + return 0; +} + +static const struct of_device_id exynos5_dmc_of_match[] = { + { .compatible = "samsung,exynos5422-dmc", }, + { }, +}; +MODULE_DEVICE_TABLE(of, exynos5_dmc_of_match); + +static struct platform_driver exynos5_dmc_platdrv = { + .probe = exynos5_dmc_probe, + .remove = exynos5_dmc_remove, + .driver = { + .name = "exynos5-dmc", + .of_match_table = exynos5_dmc_of_match, + }, +}; +module_platform_driver(exynos5_dmc_platdrv); +MODULE_DESCRIPTION("Driver for Exynos5422 Dynamic Memory Controller dynamic frequency and voltage change"); +MODULE_LICENSE("GPL v2"); +MODULE_AUTHOR("Samsung"); From patchwork Fri Jun 14 09:53:05 2019 Content-Type: text/plain; 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Fri, 14 Jun 2019 09:53:27 +0000 (GMT) From: Lukasz Luba To: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org Cc: mturquette@baylibre.com, sboyd@kernel.org, b.zolnierkie@samsung.com, krzk@kernel.org, kgene@kernel.org, cw00.choi@samsung.com, kyungmin.park@samsung.com, m.szyprowski@samsung.com, s.nawrocki@samsung.com, myungjoo.ham@samsung.com, keescook@chromium.org, tony@atomide.com, jroedel@suse.de, treding@nvidia.com, digetx@gmail.com, gregkh@linuxfoundation.org, willy.mh.wolff.ml@gmail.com, Lukasz Luba Subject: [PATCH v10 09/13] drivers: devfreq: events: add Exynos PPMU new events Date: Fri, 14 Jun 2019 11:53:05 +0200 Message-Id: <20190614095309.24100-10-l.luba@partner.samsung.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190614095309.24100-1-l.luba@partner.samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA0VSWUwTURT1dToLSMlYUV7ciFUSIFps4vICrokmo8ZEQvhQg1p1WCIt0AEV 8aOCuIAVBUEWoRhUtEAKlGAVEGQRA0hBDBIRg2KUyKK0IG4ptp2qf+eee8495yWPwsRD+CIq UhnHqpTyKAnhKqx5+sO0OleJha65bV6JKnP0OHo19QlH2pYuHJVODgOUXKwnUGZ7gQB1pilQ +vAohkymChI9Txoj0Wv1EjR5+S2Oeh/dJJBF0wJQjumxAJW3DJKop30HGjh7j0DNYxdwZO2r FKKGl7vQwC939O3Ze7DVk/k2nSFkvvSnkEy+ukfIPMwbJJkq3SWCaSgoIxlN8gTBPJmoEzBX qnWAMXQkMpaqZXvn7nfdeIyNijzBqvw3H3aNqE8Ni/lBnGrtTCPV4CeeClwoSK+FPer3IBW4 UmL6HoCTfR8E/DAFYPvH7wQ/WAAc784S/LWkjBY5VSUA1n41Cv9ZrIUlNgtFEbQUGnWxdoMH nQNg/kiwXYPRDzA4PvAG2Bfz6SDYZbnrwELaG1Z11TpKieit8H6mGePTvGBpRaMDu9j4Vu2Y oxKkNRRMyr7jCIP0dmh4F8Dr58PPbdUkj5fA2YdaZ2sOqjW3AI/PwOH0AqcmEDa39eD2Mxjt C/WP/Hl6GyxsnBHw191h//g8O43ZYEbNDYynRfDieTGv9oHVl7udQQthSVm28zgDZ2avOx4l pjMBvFsXdxV45f3PKgJABzzZeE4RznIyJXtSyskVXLwyXHo0WlEFbP+uw9pmNoLpF0eaAE0B iZuoMUAQKsblJ7gERROAFCbxEBUGYqFi0TF5wmlWFX1IFR/Fck1gMSWUeIoS5wwdENPh8jj2 OMvGsKq/WwHlskgNlCEXKsUbFjS4rT/gq1l1zVzuoz8XNFPry2XvK0o5lJVl3OCV36o/eL+4 YMXOpUX+m46QZ0JiR2SN/YZOWWWxdvevvIw9Ku+PYZuTDWUnp7ckpgUePOwevFyaWppdERE4 tE5Wr/HLjSmt8Tl//ep4sl+nYdb4O7035E6Am4r1MFr3S4RchFzmh6k4+R9siQ0rcwMAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrCIsWRmVeSWpSXmKPExsVy+t/xe7oz8phjDWbNUrbYOGM9q8X1L89Z LeYfOcdqsfrjY0aL5sXr2Swmn5rLZHGmO9ei//FrZovz5zewW5xtesNucatBxuJjzz1Wi8u7 5rBZfO49wmgx4/w+Jou1R+6yW1w85Wpxu3EFm8XhN+2sFv+ubWSx2H/Fy+L2bz6LbyceMTqI e3z7OonF4/2NVnaP2Q0XWTx2zrrL7rFpVSebx/65a9g9epvfsXkcfLeHyaNvyypGj82nqz0+ b5IL4I7SsynKLy1JVcjILy6xVYo2tDDSM7S00DMysdQzNDaPtTIyVdK3s0lJzcksSy3St0vQ y9jblVbwk63i6Jlu9gbGX6xdjJwcEgImEq2vFzB1MXJxCAksZZR4dGY3C0RCTGLSvu3sELaw xJ9rXWwQRZ8YJaYvPw+U4OBgE9CT2LGqECQuIjCHUeJn1zZGEIdZ4CyzxO4Vb5hAuoUF/CUO n33HBmKzCKhKbDq3G2w1r4CDxMrJn5ghNshLrN5wAMzmBIofnf+GDWSBkIC9xPcZ/BMY+RYw MqxiFEktLc5Nzy020itOzC0uzUvXS87P3cQIjMFtx35u2cHY9S74EKMAB6MSD+8BK6ZYIdbE suLK3EOMEhzMSiK886yZY4V4UxIrq1KL8uOLSnNSiw8xmgLdNJFZSjQ5H5ge8kriDU0NzS0s Dc2NzY3NLJTEeTsEDsYICaQnlqRmp6YWpBbB9DFxcEo1MOqfY/wVKtkUaRbz7vZFN7a2DZOl X3bt1eL5lzifd6Hlc/fGlrMPnORfbPh9OfDi4yc1UX/+b34vouqwttB/WuASl6ev/XaH/y/T Mlns/lv8sY5UfKq78m3Jzvg9vb/efWhnPDFtmdWjeSni7OdVpDjvv2v7G9fH2Jh56+zleBO9 a7HP5rV/jVJiKc5INNRiLipOBAAbKQBQ1wIAAA== X-CMS-MailID: 20190614095328eucas1p24009b3a07322fd12e49eabb7a08baf50 X-Msg-Generator: CA X-RootMTR: 20190614095328eucas1p24009b3a07322fd12e49eabb7a08baf50 X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20190614095328eucas1p24009b3a07322fd12e49eabb7a08baf50 References: <20190614095309.24100-1-l.luba@partner.samsung.com> Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Define new performance events supported by Exynos5422 SoC counters. The counters are built-in in Dynamic Memory Controller and provide information regarding memory utilization. Signed-off-by: Lukasz Luba Acked-by: Chanwoo Choi --- drivers/devfreq/event/exynos-ppmu.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/devfreq/event/exynos-ppmu.c b/drivers/devfreq/event/exynos-ppmu.c index c2ea94957501..ce658c262c27 100644 --- a/drivers/devfreq/event/exynos-ppmu.c +++ b/drivers/devfreq/event/exynos-ppmu.c @@ -89,6 +89,12 @@ static struct __exynos_ppmu_events { PPMU_EVENT(d1-cpu), PPMU_EVENT(d1-general), PPMU_EVENT(d1-rt), + + /* For Exynos5422 SoC */ + PPMU_EVENT(dmc0_0), + PPMU_EVENT(dmc0_1), + PPMU_EVENT(dmc1_0), + PPMU_EVENT(dmc1_1), }; static int exynos_ppmu_find_ppmu_id(struct devfreq_event_dev *edev) From patchwork Fri Jun 14 09:53:06 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lukasz Luba X-Patchwork-Id: 10994877 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 22C4413AF for ; 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Fri, 14 Jun 2019 09:53:28 +0000 (GMT) From: Lukasz Luba To: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org Cc: mturquette@baylibre.com, sboyd@kernel.org, b.zolnierkie@samsung.com, krzk@kernel.org, kgene@kernel.org, cw00.choi@samsung.com, kyungmin.park@samsung.com, m.szyprowski@samsung.com, s.nawrocki@samsung.com, myungjoo.ham@samsung.com, keescook@chromium.org, tony@atomide.com, jroedel@suse.de, treding@nvidia.com, digetx@gmail.com, gregkh@linuxfoundation.org, willy.mh.wolff.ml@gmail.com, Lukasz Luba Subject: [PATCH v10 10/13] ARM: dts: exynos: add chipid label and syscon compatible Date: Fri, 14 Jun 2019 11:53:06 +0200 Message-Id: <20190614095309.24100-11-l.luba@partner.samsung.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190614095309.24100-1-l.luba@partner.samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA0WSe0hTYRjG+3Z2Lq4mxyn5ZVGwblY4uxEfWlmRcIqCQDQyRq08qbhN21HT jFjKrKxVJNmy5rTswso0XZZWXqZmrMuyiUVmaAuM1Mx0gqSWp7Pqv+d93t/7Pu8HH4XJuvEg KlGbyuq0KrWckIirn469CinUYsrlnUML0D1TOY7ejvTiyNL8Cke3h9wA5VwrJ1C+wyxCL05p 0Fl3H4aczgoSvczuJ9F7/Rw0dPojjly1Vwg0bGwGyOSsE6Gy5i4StTkiUeexWwRq6j+Oo8mO e2JU374Vdf70RaPPPoENgcyo57yYGXxnIJnL+jYxU1PYRTKV1pMEU2++QzLGnG8E0/jtsYg5 Y7MCpup5FjNcOXfH9FjJ2jhWnZjO6kLX75UkOFo8WMoLIqO92AP0wIbnAR8K0quhJbeDzAMS SkbfArB97CUQihEA9YMluFAMA3j8e6soD1B/RpoeJAv+TQAdJof430Rxn5nkIYJWwIfWg3xE AG0C8PKXKJ7B6AcYHOj8AHjGn46G9w1JPCOmF8LxMZeI11J6AzT1NAPhvHnwdkUDxmufKb/F 0k/weyBtpGBVj0EkQJuhte8kJmh/+LXVRgp6DvxVY/EyHNQbS7xLj0D3WbOXCYdNrW04fw9G L4HltaGCvRGea+z1vtcXvhvw421sSp6vvogJthSeyJUJdDC0nX7tDZoJb94p8C5n4If7RQSv ZXQ+gCOl88+BeYX/s4oBsIJANo3TxLPcKi17SMGpNFyaNl6xP1lTCab+3fPJVs9DUDe+zw5o CshnSBvCREoZrkrnMjV2AClMHiAtCseUMmmcKvMwq0veo0tTs5wdzKbE8kBp1rTu3TI6XpXK JrFsCqv72xVRPkF6sLMkaKhhZd3VjTMsE1HVs4wTbMiWiAhnmvJLr2ua+sbrTa7DCmlWU3Qw 5nGlLI2N3V61+FNPTJmsfCGM6fh8gUvfNPdRtq85MnLZyusKv5yquz6ll7b1F7l3/Xjiv843 UvnGXJERZjAdKMg+FbfG7uyWLBo+at+n9ntryLCsComOlou5BNWKpZiOU/0GuqDQ5HMDAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrMIsWRmVeSWpSXmKPExsVy+t/xe7oz85hjDVqfKFpsnLGe1eL6l+es FvOPnGO1WP3xMaNF8+L1bBaTT81lsjjTnWvR//g1s8X58xvYLc42vWG3uNUgY/Gx5x6rxeVd c9gsPvceYbSYcX4fk8XaI3fZLS6ecrW43biCzeLwm3ZWi3/XNrJY7L/iZXH7N5/FtxOPGB3E Pb59ncTi8f5GK7vH7IaLLB47Z91l99i0qpPNY//cNewevc3v2DwOvtvD5NG3ZRWjx+bT1R6f N8kFcEfp2RTll5akKmTkF5fYKkUbWhjpGVpa6BmZWOoZGpvHWhmZKunb2aSk5mSWpRbp2yXo ZZw6+pW54AxbxZUFXxkbGLewdjFycEgImEgc3p7fxcjFISSwlFGi5+oepi5GTqC4mMSkfdvZ IWxhiT/XuthAbCGBT4wS7x66gvSyCehJ7FhVCNIrIjCHUeJn1zZGEIdZ4CyzxO4Vb8AGCQsE S8y89hOsmUVAVeLPz8tgcV4BB4kZD48wQiyQl1i94QAziM0JFD86/w0byAIhAXuJ7zP4JzDy LWBkWMUoklpanJueW2ykV5yYW1yal66XnJ+7iREYgduO/dyyg7HrXfAhRgEORiUe3gNWTLFC rIllxZW5hxglOJiVRHjnWTPHCvGmJFZWpRblxxeV5qQWH2I0BbppIrOUaHI+MDnklcQbmhqa W1gamhubG5tZKInzdggcjBESSE8sSc1OTS1ILYLpY+LglGpgnNjlpVqiWWz1Vvi9+7RClr6w k78nOGR91Cra++UcV97r6xtr5uv94rq5eI+12qRdGRM+/lDrzIiMiVMNfOaXqHdXlEsm5MuG b+v/bfGunNo/oangoWncfRbJqFtCttKh0zpPFxjs2XSL93TQBSG7BrllWSUFuvuUIjf2/V2m do7nuemnDQZ+SizFGYmGWsxFxYkAOuKcwdYCAAA= X-CMS-MailID: 20190614095329eucas1p267244e53d4f5612c46d6cc2c6bc0ed75 X-Msg-Generator: CA X-RootMTR: 20190614095329eucas1p267244e53d4f5612c46d6cc2c6bc0ed75 X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20190614095329eucas1p267244e53d4f5612c46d6cc2c6bc0ed75 References: <20190614095309.24100-1-l.luba@partner.samsung.com> Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add the chipid label which allows to use it in phandle from other device. Use syscon in compatible to get the regmap of the device register set. The chipid is used in DMC during initialization to compare compatibility. Signed-off-by: Lukasz Luba --- arch/arm/boot/dts/exynos5.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/exynos5.dtsi b/arch/arm/boot/dts/exynos5.dtsi index 67f9b4504a42..4801ca759feb 100644 --- a/arch/arm/boot/dts/exynos5.dtsi +++ b/arch/arm/boot/dts/exynos5.dtsi @@ -35,8 +35,8 @@ #size-cells = <1>; ranges; - chipid@10000000 { - compatible = "samsung,exynos4210-chipid"; + chipid: chipid@10000000 { + compatible = "samsung,exynos4210-chipid", "syscon"; reg = <0x10000000 0x100>; }; From patchwork Fri Jun 14 09:53:07 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lukasz Luba X-Patchwork-Id: 10994869 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 247AD14E5 for ; Fri, 14 Jun 2019 09:53:51 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 164BA28426 for ; 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Fri, 14 Jun 2019 09:53:30 +0000 (GMT) Received: from eusmgms2.samsung.com (unknown [182.198.249.180]) by eusmtrp2.samsung.com (KnoxPortal) with ESMTP id 20190614095330eusmtrp2860581b0046f331e7b4c7da0e4e24230~oB-Lc2EHh2148621486eusmtrp2H; Fri, 14 Jun 2019 09:53:30 +0000 (GMT) X-AuditID: cbfec7f4-113ff70000001119-34-5d036e9b715e Received: from eusmtip2.samsung.com ( [203.254.199.222]) by eusmgms2.samsung.com (EUCPMTA) with SMTP id CA.EA.04140.A9E630D5; Fri, 14 Jun 2019 10:53:30 +0100 (BST) Received: from AMDC3778.DIGITAL.local (unknown [106.120.51.20]) by eusmtip2.samsung.com (KnoxPortal) with ESMTPA id 20190614095329eusmtip235d4f4c89b2f064166a50d31022a4e15~oB-KjK-v82261522615eusmtip2x; Fri, 14 Jun 2019 09:53:29 +0000 (GMT) From: Lukasz Luba To: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org Cc: mturquette@baylibre.com, sboyd@kernel.org, b.zolnierkie@samsung.com, krzk@kernel.org, kgene@kernel.org, cw00.choi@samsung.com, kyungmin.park@samsung.com, m.szyprowski@samsung.com, s.nawrocki@samsung.com, myungjoo.ham@samsung.com, keescook@chromium.org, tony@atomide.com, jroedel@suse.de, treding@nvidia.com, digetx@gmail.com, gregkh@linuxfoundation.org, willy.mh.wolff.ml@gmail.com, Lukasz Luba Subject: [PATCH v10 11/13] ARM: dts: exynos: add syscon to clock compatible Date: Fri, 14 Jun 2019 11:53:07 +0200 Message-Id: <20190614095309.24100-12-l.luba@partner.samsung.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190614095309.24100-1-l.luba@partner.samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA0WSf0yMcRzH+z6/7uk4e5zUd0rlNiu2fpnsSxgb9siYITYWjp6dpju5px8K 2+VWka5aWVKdWHSpKAnVqCQuoZNQk0gpId2stNEPenou/nt/X5/3+/v+7Lsvjcs/kvPoUE0E p9UowxSUlLjz+FezV44GD/a1jsvRzaxSErUNfyZRXkMziYp/9ACkzy+lUEaTEUPPzqpRas83 HFksZRL0/NSABL3VuaAfye9J1FqdS6EhQwNAWZYaDF1v6JSglqb1qCOukEIPBxJJNPHmJoFq XwWijtFZaKSxG6xxYkd+phOstT1ewuboWgi2KrtTwpYXnaHYWmOJhDXoByn2weA9jE2pKALs rafH2aFy160zdktXhnBhoVGc1mf1fukhq6WNDG+2P2ZIvUjoQDydBOxpyCyF554UEElASsuZ QgCv5mdR4mEYwHRjDyW45MwQgH29AdOJUUsGLppMAFpf/Zb8S3QXpE0maJpivGFl0VEh4MBk AZjTv13w4MxdHH7veAeEwRxmE3xZdgUTNMEshE1m41RWxqyBfambxTI3WFxWhwvafhI/yhuY 2g4yBhrmd12hRNM6WDl+GhP1HPjVXCERtQv8U5Vn4zzUGS4DUZ+APalGmycAPjS3kEIvziyC pdU+Il4Lu2pMQMCQmQXbv88WMD4p0++cx0Usg6cT5KLbE1Ykv7AVOUJTSabtchZmNKbY3jMD wLTeOCINuGX/L7sEQBFw4iJ5tYrjl2i4aG9eqeYjNSrvg0fU5WDy4z2dMA9XguqxA/WAoYFi pqxuBRYsJ5VRfIy6HkAaVzjILgbgwXJZiDImltMe2aeNDOP4euBMEwon2XG7rj1yRqWM4A5z XDinnZ5itP08HXCu+WO65Gw9WIfdlxp1y5vdE/QnXPS3NzL983OD7La36m9kj/ENPn4Oez0U gwmqMfRoU8WqTP+TQOrh2+6VmDDT9cXqC7s8af+d/dc+STFHx7j8penWBZ6hX167t44GwNgN cwPVA9sat4yOZLP6jnU7TkVHLWurCvKiHsTqn38wKwj+kNJvMa7llX8BfNBSH3QDAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrMIsWRmVeSWpSXmKPExsVy+t/xe7qz8phjDR71y1lsnLGe1eL6l+es FvOPnGO1WP3xMaNF8+L1bBaTT81lsjjTnWvR//g1s8X58xvYLc42vWG3uNUgY/Gx5x6rxeVd c9gsPvceYbSYcX4fk8XaI3fZLS6ecrW43biCzeLwm3ZWi3/XNrJY7L/iZXH7N5/FtxOPGB3E Pb59ncTi8f5GK7vH7IaLLB47Z91l99i0qpPNY//cNewevc3v2DwOvtvD5NG3ZRWjx+bT1R6f N8kFcEfp2RTll5akKmTkF5fYKkUbWhjpGVpa6BmZWOoZGpvHWhmZKunb2aSk5mSWpRbp2yXo Zbw/f5214BxnRW//PJYGxlaOLkZODgkBE4nf5yczdzFycQgJLGWUuP31FhNEQkxi0r7t7BC2 sMSfa11sILaQwCdGiW9v+bsYOTjYBPQkdqwqBOkVEZjDKPGzaxsjiMMscJZZYveKN2CDhAW8 JS5tWAJmswioSpw6PpcNpJlXwEHiWb8vxHx5idUbDjCD2JxA4aPz34CVCAnYS3yfwT+BkW8B I8MqRpHU0uLc9NxiI73ixNzi0rx0veT83E2MwAjcduznlh2MXe+CDzEKcDAq8fAesGKKFWJN LCuuzD3EKMHBrCTCO8+aOVaINyWxsiq1KD++qDQntfgQoynQSROZpUST84HJIa8k3tDU0NzC 0tDc2NzYzEJJnLdD4GCMkEB6YklqdmpqQWoRTB8TB6dUA6NY76oplrMunVr2kCFIIzip44nu tAVHHV9M9+VLvu5+Ojaodcu1nXNZTaIONrXyr39v9uPx4XTrV8KbDBx5JZ53rpTY2rR//7cp Si/Krp2MODiHx/34/aW83SYxt34uVdG+cca75JjRiwXqaktu3+FRN9ZZdN7x9JP/VQpTvs3Z +Wue+/1HGgZXlViKMxINtZiLihMBkuS70tYCAAA= X-CMS-MailID: 20190614095330eucas1p1e5a73f31251af7d16caf951054ec9def X-Msg-Generator: CA X-RootMTR: 20190614095330eucas1p1e5a73f31251af7d16caf951054ec9def X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20190614095330eucas1p1e5a73f31251af7d16caf951054ec9def References: <20190614095309.24100-1-l.luba@partner.samsung.com> Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP In order to get the clock by phandle and use it with regmap it needs to be compatible with syscon. The DMC driver uses two registers from clock register set and needs the regmap of them. Signed-off-by: Lukasz Luba --- arch/arm/boot/dts/exynos5420.dtsi | 2 +- arch/arm/boot/dts/exynos5800.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi index 5fb2326875dc..d153617ff1a3 100644 --- a/arch/arm/boot/dts/exynos5420.dtsi +++ b/arch/arm/boot/dts/exynos5420.dtsi @@ -173,7 +173,7 @@ }; clock: clock-controller@10010000 { - compatible = "samsung,exynos5420-clock"; + compatible = "samsung,exynos5420-clock", "syscon"; reg = <0x10010000 0x30000>; #clock-cells = <1>; }; diff --git a/arch/arm/boot/dts/exynos5800.dtsi b/arch/arm/boot/dts/exynos5800.dtsi index 57d3b319fd65..0a2b3287ed92 100644 --- a/arch/arm/boot/dts/exynos5800.dtsi +++ b/arch/arm/boot/dts/exynos5800.dtsi @@ -17,7 +17,7 @@ }; &clock { - compatible = "samsung,exynos5800-clock"; + compatible = "samsung,exynos5800-clock", "syscon"; }; &cluster_a15_opp_table { From patchwork Fri Jun 14 09:53:08 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lukasz Luba X-Patchwork-Id: 10994865 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 64F5D14E5 for ; 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Fri, 14 Jun 2019 09:53:30 +0000 (GMT) From: Lukasz Luba To: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org Cc: mturquette@baylibre.com, sboyd@kernel.org, b.zolnierkie@samsung.com, krzk@kernel.org, kgene@kernel.org, cw00.choi@samsung.com, kyungmin.park@samsung.com, m.szyprowski@samsung.com, s.nawrocki@samsung.com, myungjoo.ham@samsung.com, keescook@chromium.org, tony@atomide.com, jroedel@suse.de, treding@nvidia.com, digetx@gmail.com, gregkh@linuxfoundation.org, willy.mh.wolff.ml@gmail.com, Lukasz Luba Subject: [PATCH v10 12/13] ARM: dts: exynos: add DMC device for exynos5422 Date: Fri, 14 Jun 2019 11:53:08 +0200 Message-Id: <20190614095309.24100-13-l.luba@partner.samsung.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190614095309.24100-1-l.luba@partner.samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA0WSe0hTURzHPbuP3VmT23ydnsLKKCE1ijjNioKSqxREEZIyaulFJTdrN+1h xSrLnK5CSUVdWhKOaanTLe2l+cjQdJpWllmS9PIV5qMnK6931X/f8/19fuf7+x0OhcneEPOo WM0hVqtRxclJV9z28Lt9Rb4GUwa2VHiiipwyAj2f+ECggsZ2ApWMDQB0pqiMRJktRhF6nKZG FweGMGS3l4tR2+lhMXqpW4DG0l8TqOt2PonGDY0A5djvi9CNxj4x6mzZgnpPmUjUMJxCIMez ChzVdoei3p9uaOrRW7DRm5mazMCZzz1nxUyerhNnanL7xIzFnEoytcZSMWM4M0oyD0bvipgL VWbAVLYmMeOWRdtnhbuui2LjYhNZbcCGva4x6Ze7wYHqwCPXnmThOtC2RA8kFKRXw6KzRSI9 cKVktAnAp6V1YuEwAWD7o3ckT8nocQDvWBP1gJrpcJiUAlMMYPEnPfmvwZaTRvIQSfvDavNB vteDzgEw7+NOnsHoWxgc6X0F+II7HQq//RwkeB6nfaFNv4a3pfRG+EHXIRam84El5XUYryXT flPB8EwWpA0UrC6zOaHNMM2RTAraHQ42Vzn9BfB3TYFI0BzUGa4CQR+HAxeNTiYINjR3zsyA 0cth2e0Awd4E3w99AcK+brBnZA5vY9Myw5aNCbYUnj8nE+hlsCq9wxnkBYtLs5yXMzDlXq1I eMFMAA2ZkkvAJ/d/ViEAZuDNJnDqaJZbpWEP+3MqNZegifaPjFdbwPS3a3U0T1aD+7/21QOa AvLZ0jqFSCkjVIncUXU9gBQm95BeCcKUMmmU6ugxVhu/R5sQx3L1YD6Fy72lSS79ETI6WnWI 3c+yB1jt36qIkszTgY4khcfaQhVsStpuMzZk4X6bO43Z+38kv5NeCAqJqEEPgirbpjLaF3p5 rsfDPnmfv35ya7hiYuloqSK4cWDDCZN1d3/bM0jUWhfnf00dDbhhCk5M3SHxNc8NWb9lV0NX eLlX34gtcuSmNVQ+ceXJ3mMvtvU4wk4HWwn/nnwXS1OKHOdiVCv9MC2n+gM2Ks9/cgMAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrMIsWRmVeSWpSXmKPExsVy+t/xe7qz85hjDRZMkrLYOGM9q8X1L89Z LeYfOcdqsfrjY0aL5sXr2Swmn5rLZHGmO9ei//FrZovz5zewW5xtesNucatBxuJjzz1Wi8u7 5rBZfO49wmgx4/w+Jou1R+6yW1w85Wpxu3EFm8XhN+2sFv+ubWSx2H/Fy+L2bz6LbyceMTqI e3z7OonF4/2NVnaP2Q0XWTx2zrrL7rFpVSebx/65a9g9epvfsXkcfLeHyaNvyypGj82nqz0+ b5IL4I7SsynKLy1JVcjILy6xVYo2tDDSM7S00DMysdQzNDaPtTIyVdK3s0lJzcksSy3St0vQ y+iZeoWxYIdBxaJL01gaGM+qdDFycEgImEj8WxHbxcjFISSwlFHi7vtNzF2MnEBxMYlJ+7az Q9jCEn+udbFBFH1ilFjycx4bSDObgJ7EjlWFIHERgTmMEj+7tjGCOMwCZ5kldq94wwTSLSzg JfHj9ytWkAYWAVWJbV1mIGFeAQeJ5w0XoBbIS6zecABsMSdQ/Oj8N2DzhQTsJb7P4J/AyLeA kWEVo0hqaXFuem6xkV5xYm5xaV66XnJ+7iZGYARuO/Zzyw7GrnfBhxgFOBiVeHgPWDHFCrEm lhVX5h5ilOBgVhLhnWfNHCvEm5JYWZValB9fVJqTWnyI0RTopInMUqLJ+cDkkFcSb2hqaG5h aWhubG5sZqEkztshcDBGSCA9sSQ1OzW1ILUIpo+Jg1OqgXHPCoEzUwRy/x/9JaFXUT5B8OgE Jq8D88968u3/9l6vlLfswt7nxYtZ1p2M2aMux2OyRnTit3Xrz4pmuhlNjHisv0CoynHltJNL Jq8/sz1xk32VQsvquN8HpS5KHmZc3Dnto+7S7BVNE6b/aNLlUVgUtjP3YyHX6oo6br3p1XY5 L4p2S3JvTApXYinOSDTUYi4qTgQAInPcONYCAAA= X-CMS-MailID: 20190614095331eucas1p138707301cac47902f0d0d9a41bd4a8a4 X-Msg-Generator: CA X-RootMTR: 20190614095331eucas1p138707301cac47902f0d0d9a41bd4a8a4 X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20190614095331eucas1p138707301cac47902f0d0d9a41bd4a8a4 References: <20190614095309.24100-1-l.luba@partner.samsung.com> Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add description of Dynamic Memory Controller and PPMU counters. They are used by exynos5422-dmc driver. There is a definition of the memory chip, which is then used during calculation of timings for each OPP. The algorithm in the driver needs these two sets to bound the timings. Signed-off-by: Lukasz Luba --- arch/arm/boot/dts/exynos5420.dtsi | 73 +++++++++++ arch/arm/boot/dts/exynos5422-odroid-core.dtsi | 116 ++++++++++++++++++ 2 files changed, 189 insertions(+) diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi index d153617ff1a3..79e74ae80938 100644 --- a/arch/arm/boot/dts/exynos5420.dtsi +++ b/arch/arm/boot/dts/exynos5420.dtsi @@ -235,6 +235,31 @@ status = "disabled"; }; + dmc: memory-controller@10c20000 { + compatible = "samsung,exynos5422-dmc"; + reg = <0x10c20000 0x100>, <0x10c30000 0x100>; + clocks = <&clock CLK_FOUT_SPLL>, + <&clock CLK_MOUT_SCLK_SPLL>, + <&clock CLK_FF_DOUT_SPLL2>, + <&clock CLK_FOUT_BPLL>, + <&clock CLK_MOUT_BPLL>, + <&clock CLK_SCLK_BPLL>, + <&clock CLK_MOUT_MX_MSPLL_CCORE>, + <&clock CLK_MOUT_MX_MSPLL_CCORE_PHY>, + <&clock CLK_MOUT_MCLK_CDREX>; + clock-names = "fout_spll", + "mout_sclk_spll", + "ff_dout_spll2", + "fout_bpll", + "mout_bpll", + "sclk_bpll", + "mout_mx_mspll_ccore", + "mout_mx_mspll_ccore_phy", + "mout_mclk_cdrex"; + samsung,syscon-clk = <&clock>; + status = "disabled"; + }; + nocp_mem0_0: nocp@10ca1000 { compatible = "samsung,exynos5420-nocp"; reg = <0x10CA1000 0x200>; @@ -271,6 +296,54 @@ status = "disabled"; }; + ppmu_dmc0_0: ppmu@10d00000 { + compatible = "samsung,exynos-ppmu"; + reg = <0x10d00000 0x2000>; + clocks = <&clock CLK_PCLK_PPMU_DREX0_0>; + clock-names = "ppmu"; + events { + ppmu_event3_dmc0_0: ppmu-event3-dmc0_0 { + event-name = "ppmu-event3-dmc0_0"; + }; + }; + }; + + ppmu_dmc0_1: ppmu@10d10000 { + compatible = "samsung,exynos-ppmu"; + reg = <0x10d10000 0x2000>; + clocks = <&clock CLK_PCLK_PPMU_DREX0_1>; + clock-names = "ppmu"; + events { + ppmu_event3_dmc0_1: ppmu-event3-dmc0_1 { + event-name = "ppmu-event3-dmc0_1"; + }; + }; + }; + + ppmu_dmc1_0: ppmu@10d60000 { + compatible = "samsung,exynos-ppmu"; + reg = <0x10d60000 0x2000>; + clocks = <&clock CLK_PCLK_PPMU_DREX1_0>; + clock-names = "ppmu"; + events { + ppmu_event3_dmc1_0: ppmu-event3-dmc1_0 { + event-name = "ppmu-event3-dmc1_0"; + }; + }; + }; + + ppmu_dmc1_1: ppmu@10d70000 { + compatible = "samsung,exynos-ppmu"; + reg = <0x10d70000 0x2000>; + clocks = <&clock CLK_PCLK_PPMU_DREX1_1>; + clock-names = "ppmu"; + events { + ppmu_event3_dmc1_1: ppmu-event3-dmc1_1 { + event-name = "ppmu-event3-dmc1_1"; + }; + }; + }; + gsc_pd: power-domain@10044000 { compatible = "samsung,exynos4210-pd"; reg = <0x10044000 0x20>; diff --git a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi index 25d95de15c9b..30e569c13ee7 100644 --- a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi +++ b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi @@ -34,6 +34,97 @@ clock-frequency = <24000000>; }; }; + + dmc_opp_table: opp_table2 { + compatible = "operating-points-v2"; + + opp00 { + opp-hz = /bits/ 64 <165000000>; + opp-microvolt = <875000>; + }; + opp01 { + opp-hz = /bits/ 64 <206000000>; + opp-microvolt = <875000>; + }; + opp02 { + opp-hz = /bits/ 64 <275000000>; + opp-microvolt = <875000>; + }; + opp03 { + opp-hz = /bits/ 64 <413000000>; + opp-microvolt = <887500>; + }; + opp04 { + opp-hz = /bits/ 64 <543000000>; + opp-microvolt = <937500>; + }; + opp05 { + opp-hz = /bits/ 64 <633000000>; + opp-microvolt = <1012500>; + }; + opp06 { + opp-hz = /bits/ 64 <728000000>; + opp-microvolt = <1037500>; + }; + opp07 { + opp-hz = /bits/ 64 <825000000>; + opp-microvolt = <1050000>; + }; + }; + + samsung_K3QF2F20DB: lpddr3 { + compatible = "samsung,K3QF2F20DB", "jedec,lpddr3"; + density = <16384>; + io-width = <32>; + #address-cells = <1>; + #size-cells = <0>; + + tRFC-min-tck = <17>; + tRRD-min-tck = <2>; + tRPab-min-tck = <2>; + tRPpb-min-tck = <2>; + tRCD-min-tck = <3>; + tRC-min-tck = <6>; + tRAS-min-tck = <5>; + tWTR-min-tck = <2>; + tWR-min-tck = <7>; + tRTP-min-tck = <2>; + tW2W-C2C-min-tck = <0>; + tR2R-C2C-min-tck = <0>; + tWL-min-tck = <8>; + tDQSCK-min-tck = <5>; + tRL-min-tck = <14>; + tFAW-min-tck = <5>; + tXSR-min-tck = <12>; + tXP-min-tck = <2>; + tCKE-min-tck = <2>; + tCKESR-min-tck = <2>; + tMRD-min-tck = <5>; + + timings_samsung_K3QF2F20DB_800mhz: lpddr3-timings@800000000 { + compatible = "jedec,lpddr3-timings"; + reg = <800000000>; /* workaround: it shows max-freq */ + min-freq = <100000000>; + tRFC = <65000>; + tRRD = <6000>; + tRPab = <12000>; + tRPpb = <12000>; + tRCD = <10000>; + tRC = <33750>; + tRAS = <23000>; + tWTR = <3750>; + tWR = <7500>; + tRTP = <3750>; + tW2W-C2C = <0>; + tR2R-C2C = <0>; + tFAW = <25000>; + tXSR = <70000>; + tXP = <3750>; + tCKE = <3750>; + tCKESR = <3750>; + tMRD = <7000>; + }; + }; }; &adc { @@ -132,6 +223,15 @@ cpu-supply = <&buck2_reg>; }; +&dmc { + devfreq-events = <&ppmu_event3_dmc0_0>, <&ppmu_event3_dmc0_1>, + <&ppmu_event3_dmc1_0>, <&ppmu_event3_dmc1_1>; + device-handle = <&samsung_K3QF2F20DB>; + operating-points-v2 = <&dmc_opp_table>; + vdd-supply = <&buck1_reg>; + status = "okay"; +}; + &hsi2c_4 { status = "okay"; @@ -540,6 +640,22 @@ }; }; +&ppmu_dmc0_0 { + status = "okay"; +}; + +&ppmu_dmc0_1 { + status = "okay"; +}; + +&ppmu_dmc1_0 { + status = "okay"; +}; + +&ppmu_dmc1_1 { + status = "okay"; +}; + &tmu_cpu0 { vtmu-supply = <&ldo7_reg>; }; From patchwork Fri Jun 14 09:53:09 2019 Content-Type: text/plain; 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Fri, 14 Jun 2019 09:53:31 +0000 (GMT) From: Lukasz Luba To: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org Cc: mturquette@baylibre.com, sboyd@kernel.org, b.zolnierkie@samsung.com, krzk@kernel.org, kgene@kernel.org, cw00.choi@samsung.com, kyungmin.park@samsung.com, m.szyprowski@samsung.com, s.nawrocki@samsung.com, myungjoo.ham@samsung.com, keescook@chromium.org, tony@atomide.com, jroedel@suse.de, treding@nvidia.com, digetx@gmail.com, gregkh@linuxfoundation.org, willy.mh.wolff.ml@gmail.com, Lukasz Luba Subject: [PATCH v10 13/13] ARM: exynos_defconfig: enable DMC driver Date: Fri, 14 Jun 2019 11:53:09 +0200 Message-Id: <20190614095309.24100-14-l.luba@partner.samsung.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190614095309.24100-1-l.luba@partner.samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA0VSe0hTURzu7D7VJrct8lCRNAgqSTOCTilRlHAzKDGhqMxW3VRy0+71kWmw FT18TEvJTF0rIrJZqHMsLdPlI9d6mD3MNEtcDzU1bSrM6OHcrP++3/f4fT8Oh8YkNmI+HatM 5HilPE5GeuKmR47nK7RKLHLlRYcUVRaWE+jt2FcC6ZqeE6hs1AbQqevlJMq3akXoaZYC5dq+ Yai1tYJCz04OUqhTtRCNZn8g0Kt7JSSya5oAKmytE6E7Td0UarOGoC51KYkaB88S6Hd7JY7q X4eirp/eaMLSCzb4sBPjeTj7veM0xRar2nC2pqibYg36DJKt196mWM2pYZJ9OFwrYnOMesBW PUlj7YZFYV67PYMPcXGxyRwfsH6/Z4zJWksmjBDHxi+/w1WggMgEHjRkVsPezEZRJvCkJUwp gB9z9bhrGAPws8ZOugY7gFX5J/GZSP/9SbdwE8AHLSbqX8T4Szu1jKZJxh9W6486A3OZQgCL +3Y4PRhzF4NDXe+BU5Aym2DFhdfTW3FmCTR+KRA5sZjZADs/2YGrzReWVZgxJ/aY4pt1g9PN kMmgYY3FIXKZNsO+yRJ3QAoHWoyUCy+Ef2p0bo8AVZprbk86tOVq3Z4g2NjSRjiPxphlsPxe gIveCF92OignDRlv2DE0x0ljUzDPdAlz0WJ47ozE5V4Kjdkv3EXz4M3bBe7lLJwYGXa/VT6A 6tp+cB74Fv0vuwqAHvhwSYIimhMClVyKvyBXCEnKaP+D8QoDmPp6T363/KgG4y8PNACGBrLZ YvM6UaSEkCcLqYoGAGlMNld8JQiLlIgPyVOPc3x8FJ8UxwkNYAGNy3zEabN69kiYaHkid4Tj Ejh+RhXRHvNVwLdntF+Xslu9/Y6l1LxmLbPoSqApY9W6cHNtRcezhL7QG5uLNSHqiI07w17c qiuGhzOpAdtQ2/Gf5n220Tf8Yq/H9r4TW6r94o9Kf/Ee6eut0oCY4J5Q69alEWFk+wSD7c1d 4hduWOaw+ORE7YrwHTPwlmadwyaO35bYnjWZ+kaGCzHywOUYL8j/Av5WhQV2AwAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrKIsWRmVeSWpSXmKPExsVy+t/xe7pz8phjDWbekbTYOGM9q8X1L89Z LeYfOcdqsfrjY0aL5sXr2Swmn5rLZHGmO9ei//FrZovz5zewW5xtesNucatBxuJjzz1Wi8u7 5rBZfO49wmgx4/w+Jou1R+6yW1w85Wpxu3EFm8XhN+2sFv+ubWSx2H/Fy+L2bz6LbyceMTqI e3z7OonF4/2NVnaP2Q0XWTx2zrrL7rFpVSebx/65a9g9epvfsXkcfLeHyaNvyypGj82nqz0+ b5IL4I7SsynKLy1JVcjILy6xVYo2tDDSM7S00DMysdQzNDaPtTIyVdK3s0lJzcksSy3St0vQ y9h2ag9bwQfWiq8zb7I0ME5j7WLk5JAQMJF4ufsXWxcjF4eQwFJGiVXndzFDJMQkJu3bzg5h C0v8udYFVfSJUeLu2p1ADgcHm4CexI5VhSBxEYE5jBI/u7YxgjjMAmeZJXaveMME0i0s4Cyx YeIVFhCbRUBVYsuzaWBxXgEHiVtPPjNCbJCXWL3hANhmTqD40flvwBYICdhLfJ/BP4GRbwEj wypGkdTS4tz03GJDveLE3OLSvHS95PzcTYzAKNx27OfmHYyXNgYfYhTgYFTi4T1gxRQrxJpY VlyZe4hRgoNZSYR3njVzrBBvSmJlVWpRfnxRaU5q8SFGU6CbJjJLiSbnAxNEXkm8oamhuYWl obmxubGZhZI4b4fAwRghgfTEktTs1NSC1CKYPiYOTqkGxr5GP5VA3VUZDA/1NDL7/sYEfdJt 8iq3E0tW6l7a4X6kT7HJe/dWVxN2U8fzVeICU90lOCzsGO779oXe32nlOcVhYeHv7Zw3nz0W vf5XpevLimvuQv08iwLmF4g+nOpds9w4QVRhhdOneLUTN6Wvekzr859ScDXXh79Lz9xEwYNj 0vOHLy8osRRnJBpqMRcVJwIALtZL0NgCAAA= X-CMS-MailID: 20190614095332eucas1p10e0a690604c6210d5f61c55175532785 X-Msg-Generator: CA X-RootMTR: 20190614095332eucas1p10e0a690604c6210d5f61c55175532785 X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20190614095332eucas1p10e0a690604c6210d5f61c55175532785 References: <20190614095309.24100-1-l.luba@partner.samsung.com> Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Enable driver for Exynos5422 Dynamic Memory Controller supporting dynamic frequency and voltage scaling in Exynos5422 SoCs. Signed-off-by: Lukasz Luba --- arch/arm/configs/exynos_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/configs/exynos_defconfig b/arch/arm/configs/exynos_defconfig index c95c54284da2..0cd16c924941 100644 --- a/arch/arm/configs/exynos_defconfig +++ b/arch/arm/configs/exynos_defconfig @@ -290,6 +290,7 @@ CONFIG_DEVFREQ_GOV_PERFORMANCE=y CONFIG_DEVFREQ_GOV_POWERSAVE=y CONFIG_DEVFREQ_GOV_USERSPACE=y CONFIG_ARM_EXYNOS_BUS_DEVFREQ=y +CONFIG_ARM_EXYNOS5422_DMC=y CONFIG_DEVFREQ_EVENT_EXYNOS_NOCP=y CONFIG_EXYNOS_IOMMU=y CONFIG_EXTCON=y