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Signed-off-by: Ganapatrao Kulkarni --- Documentation/perf/thunderx2-pmu.txt | 20 +++++++++++--------- 1 file changed, 11 insertions(+), 9 deletions(-) diff --git a/Documentation/perf/thunderx2-pmu.txt b/Documentation/perf/thunderx2-pmu.txt index dffc57143736..62243230abc3 100644 --- a/Documentation/perf/thunderx2-pmu.txt +++ b/Documentation/perf/thunderx2-pmu.txt @@ -2,24 +2,26 @@ Cavium ThunderX2 SoC Performance Monitoring Unit (PMU UNCORE) ============================================================= The ThunderX2 SoC PMU consists of independent, system-wide, per-socket -PMUs such as the Level 3 Cache (L3C) and DDR4 Memory Controller (DMC). +PMUs such as the Level 3 Cache (L3C), DDR4 Memory Controller (DMC) and +Cavium Coherent Processor Interconnect (CCPI2). The DMC has 8 interleaved channels and the L3C has 16 interleaved tiles. Events are counted for the default channel (i.e. channel 0) and prorated to the total number of channels/tiles. -The DMC and L3C support up to 4 counters. Counters are independently -programmable and can be started and stopped individually. Each counter -can be set to a different event. Counters are 32-bit and do not support -an overflow interrupt; they are read every 2 seconds. +The DMC, L3C support up to 4 counters and CCPI2 support up to 8 counters. +Counters are independently programmable and can be started and stopped +individually. Each counter can be set to a different event. DMC and L3C +Counters are 32-bit and do not support an overflow interrupt; they are read +every 2 seconds. CCPI2 counters are 64-bit. PMU UNCORE (perf) driver: The thunderx2_pmu driver registers per-socket perf PMUs for the DMC and -L3C devices. Each PMU can be used to count up to 4 events -simultaneously. The PMUs provide a description of their available events -and configuration options under sysfs, see -/sys/devices/uncore_; S is the socket id. +L3C devices. Each PMU can be used to count up to 4(DMC/L3C) or up to 8 +(CCPI2) events simultaneously. The PMUs provide a description of their +available events and configuration options under sysfs, see +/sys/devices/uncore_; S is the socket id. The driver does not support sampling, therefore "perf record" will not work. Per-task perf sessions are also not supported. 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Fri, 14 Jun 2019 17:42:47 +0000 Received: from MWHPR1801MB2030.namprd18.prod.outlook.com ([fe80::7c5a:e2f5:64e0:5b70]) by MWHPR1801MB2030.namprd18.prod.outlook.com ([fe80::7c5a:e2f5:64e0:5b70%7]) with mapi id 15.20.1987.013; Fri, 14 Jun 2019 17:42:47 +0000 From: Ganapatrao Kulkarni To: "linux-doc@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" Subject: [PATCH 2/2] drivers/perf: Add CCPI2 PMU support in ThunderX2 UNCORE driver. Thread-Topic: [PATCH 2/2] drivers/perf: Add CCPI2 PMU support in ThunderX2 UNCORE driver. Thread-Index: AQHVItiTGPBTb6KSH0SsUcu0vn4B3A== Date: Fri, 14 Jun 2019 17:42:46 +0000 Message-ID: <1560534144-13896-3-git-send-email-gkulkarni@marvell.com> References: <1560534144-13896-1-git-send-email-gkulkarni@marvell.com> In-Reply-To: <1560534144-13896-1-git-send-email-gkulkarni@marvell.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: BYAPR07CA0058.namprd07.prod.outlook.com (2603:10b6:a03:60::35) To MWHPR1801MB2030.namprd18.prod.outlook.com (2603:10b6:301:69::31) x-ms-exchange-messagesentrepresentingtype: 1 x-mailer: git-send-email 1.8.3.1 x-originating-ip: [199.233.59.128] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: e477d7ee-9650-40db-a8e1-08d6f0efb62d x-microsoft-antispam: BCL:0; PCL:0; RULEID:(2390118)(7020095)(4652040)(8989299)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(5600148)(711020)(4605104)(1401327)(2017052603328)(7193020); SRVR:MWHPR1801MB1936; x-ms-traffictypediagnostic: MWHPR1801MB1936: x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:8273; x-forefront-prvs: 0068C7E410 x-forefront-antispam-report: SFV:NSPM; SFS:(10009020)(136003)(346002)(39850400004)(396003)(376002)(366004)(199004)(189003)(66946007)(6116002)(71200400001)(76176011)(2501003)(102836004)(3846002)(7416002)(4720700003)(52116002)(66066001)(99286004)(6512007)(14454004)(6506007)(446003)(71190400001)(4326008)(386003)(478600001)(6436002)(2906002)(54906003)(110136005)(68736007)(5660300002)(256004)(8936002)(2616005)(305945005)(2201001)(476003)(36756003)(7736002)(53936002)(11346002)(81166006)(66556008)(66476007)(30864003)(26005)(50226002)(25786009)(186003)(64756008)(66446008)(73956011)(486006)(81156014)(316002)(86362001)(8676002)(6486002)(14444005); DIR:OUT; SFP:1101; SCL:1; SRVR:MWHPR1801MB1936; H:MWHPR1801MB2030.namprd18.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; A:1; MX:1; received-spf: None (protection.outlook.com: marvell.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: IFdR+DoMqiIlN6xY8mwhp1oIfHST009HQoBr4We70DTcDR0hCkgw4WiVz/NDOCLPlIqS4ymr6TjPGdyCO6y7viUdrIOKdGoDBTXe2EMtdcN/gSL4yvuH5zQIvuKYEduk489Qrh6dfxi72RSWmF1WyyfXxcezF1J7zvVG2+EwN1jJNCx8T+ei7WCcA9Sf8zzBOUmiB6CnfmTUfbJ/YT4DbRV5GNGWhFz7XmkYDQu3psnZV9R4W+fPg5lHbUiyrBdXrneFp34AqWSjpNPwN2WWzWT0tLEhvAalj1TusNMhxAKbDldKNkErTWzg9XavVL08m0pf8uYlGGV4E5NYRu0mISRhZAWWZ3nyf8YyIiFrTqEpHjWLT7H4izrXE3CaxffQHcUPRgpQo5Q5kPen90hwuOdMQ3+xbyuEl9EOVsk8s6A= MIME-Version: 1.0 X-MS-Exchange-CrossTenant-Network-Message-Id: e477d7ee-9650-40db-a8e1-08d6f0efb62d X-MS-Exchange-CrossTenant-originalarrivaltime: 14 Jun 2019 17:42:46.7927 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 70e1fb47-1155-421d-87fc-2e58f638b6e0 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: gkulkarni@marvell.com X-MS-Exchange-Transport-CrossTenantHeadersStamped: MWHPR1801MB1936 X-OriginatorOrg: marvell.com X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-06-14_07:, , signatures=0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190614_104259_743175_626743E4 X-CRM114-Status: GOOD ( 17.19 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "mark.rutland@arm.com" , "Jan.Glauber@cavium.com" , "corbet@lwn.net" , "Will.Deacon@arm.com" , "gklkml16@gmail.com" , "Robert.Richter@cavium.com" , "jnair@caviumnetworks.com" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP CCPI2 is a low-latency high-bandwidth serial interface for connecting ThunderX2 processors. This patch adds support to capture CCPI2 perf events. Signed-off-by: Ganapatrao Kulkarni --- drivers/perf/thunderx2_pmu.c | 179 ++++++++++++++++++++++++++++++----- 1 file changed, 157 insertions(+), 22 deletions(-) diff --git a/drivers/perf/thunderx2_pmu.c b/drivers/perf/thunderx2_pmu.c index 43d76c85da56..3791ac9b897d 100644 --- a/drivers/perf/thunderx2_pmu.c +++ b/drivers/perf/thunderx2_pmu.c @@ -16,7 +16,9 @@ * they need to be sampled before overflow(i.e, at every 2 seconds). */ -#define TX2_PMU_MAX_COUNTERS 4 +#define TX2_PMU_DMC_L3C_MAX_COUNTERS 4 +#define TX2_PMU_CCPI2_MAX_COUNTERS 8 + #define TX2_PMU_DMC_CHANNELS 8 #define TX2_PMU_L3_TILES 16 @@ -28,11 +30,22 @@ */ #define DMC_EVENT_CFG(idx, val) ((val) << (((idx) * 8) + 1)) +#define GET_EVENTID_CCPI2(ev) ((ev->hw.config) & 0x1ff) +/* bits[3:0] to select counters, starts from 8, bit[3] set always. */ +#define GET_COUNTERID_CCPI2(ev) ((ev->hw.idx) & 0x7) +#define CCPI2_COUNTER_OFFSET 8 + #define L3C_COUNTER_CTL 0xA8 #define L3C_COUNTER_DATA 0xAC #define DMC_COUNTER_CTL 0x234 #define DMC_COUNTER_DATA 0x240 +#define CCPI2_PERF_CTL 0x108 +#define CCPI2_COUNTER_CTL 0x10C +#define CCPI2_COUNTER_SEL 0x12c +#define CCPI2_COUNTER_DATA_L 0x130 +#define CCPI2_COUNTER_DATA_H 0x134 + /* L3C event IDs */ #define L3_EVENT_READ_REQ 0xD #define L3_EVENT_WRITEBACK_REQ 0xE @@ -51,9 +64,16 @@ #define DMC_EVENT_READ_TXNS 0xF #define DMC_EVENT_MAX 0x10 +#define CCPI2_EVENT_REQ_PKT_SENT 0x3D +#define CCPI2_EVENT_SNOOP_PKT_SENT 0x65 +#define CCPI2_EVENT_DATA_PKT_SENT 0x105 +#define CCPI2_EVENT_GIC_PKT_SENT 0x12D +#define CCPI2_EVENT_MAX 0x200 + enum tx2_uncore_type { PMU_TYPE_L3C, PMU_TYPE_DMC, + PMU_TYPE_CCPI2, PMU_TYPE_INVALID, }; @@ -73,8 +93,8 @@ struct tx2_uncore_pmu { u32 max_events; u64 hrtimer_interval; void __iomem *base; - DECLARE_BITMAP(active_counters, TX2_PMU_MAX_COUNTERS); - struct perf_event *events[TX2_PMU_MAX_COUNTERS]; + DECLARE_BITMAP(active_counters, TX2_PMU_CCPI2_MAX_COUNTERS); + struct perf_event *events[TX2_PMU_DMC_L3C_MAX_COUNTERS]; struct device *dev; struct hrtimer hrtimer; const struct attribute_group **attr_groups; @@ -92,7 +112,21 @@ static inline struct tx2_uncore_pmu *pmu_to_tx2_pmu(struct pmu *pmu) return container_of(pmu, struct tx2_uncore_pmu, pmu); } -PMU_FORMAT_ATTR(event, "config:0-4"); +#define TX2_PMU_FORMAT_ATTR(_var, _name, _format) \ +static ssize_t \ +__tx2_pmu_##_var##_show(struct device *dev, \ + struct device_attribute *attr, \ + char *page) \ +{ \ + BUILD_BUG_ON(sizeof(_format) >= PAGE_SIZE); \ + return sprintf(page, _format "\n"); \ +} \ + \ +static struct device_attribute format_attr_##_var = \ + __ATTR(_name, 0444, __tx2_pmu_##_var##_show, NULL) + +TX2_PMU_FORMAT_ATTR(event, event, "config:0-4"); +TX2_PMU_FORMAT_ATTR(event_ccpi2, event, "config:0-9"); static struct attribute *l3c_pmu_format_attrs[] = { &format_attr_event.attr, @@ -104,6 +138,11 @@ static struct attribute *dmc_pmu_format_attrs[] = { NULL, }; +static struct attribute *ccpi2_pmu_format_attrs[] = { + &format_attr_event_ccpi2.attr, + NULL, +}; + static const struct attribute_group l3c_pmu_format_attr_group = { .name = "format", .attrs = l3c_pmu_format_attrs, @@ -114,6 +153,11 @@ static const struct attribute_group dmc_pmu_format_attr_group = { .attrs = dmc_pmu_format_attrs, }; +static const struct attribute_group ccpi2_pmu_format_attr_group = { + .name = "format", + .attrs = ccpi2_pmu_format_attrs, +}; + /* * sysfs event attributes */ @@ -164,6 +208,19 @@ static struct attribute *dmc_pmu_events_attrs[] = { NULL, }; +TX2_EVENT_ATTR(req_pktsent, CCPI2_EVENT_REQ_PKT_SENT); +TX2_EVENT_ATTR(snoop_pktsent, CCPI2_EVENT_SNOOP_PKT_SENT); +TX2_EVENT_ATTR(data_pktsent, CCPI2_EVENT_DATA_PKT_SENT); +TX2_EVENT_ATTR(gic_pktsent, CCPI2_EVENT_GIC_PKT_SENT); + +static struct attribute *ccpi2_pmu_events_attrs[] = { + &tx2_pmu_event_attr_req_pktsent.attr.attr, + &tx2_pmu_event_attr_snoop_pktsent.attr.attr, + &tx2_pmu_event_attr_data_pktsent.attr.attr, + &tx2_pmu_event_attr_gic_pktsent.attr.attr, + NULL, +}; + static const struct attribute_group l3c_pmu_events_attr_group = { .name = "events", .attrs = l3c_pmu_events_attrs, @@ -174,6 +231,11 @@ static const struct attribute_group dmc_pmu_events_attr_group = { .attrs = dmc_pmu_events_attrs, }; +static const struct attribute_group ccpi2_pmu_events_attr_group = { + .name = "events", + .attrs = ccpi2_pmu_events_attrs, +}; + /* * sysfs cpumask attributes */ @@ -213,6 +275,13 @@ static const struct attribute_group *dmc_pmu_attr_groups[] = { NULL }; +static const struct attribute_group *ccpi2_pmu_attr_groups[] = { + &ccpi2_pmu_format_attr_group, + &pmu_cpumask_attr_group, + &ccpi2_pmu_events_attr_group, + NULL +}; + static inline u32 reg_readl(unsigned long addr) { return readl((void __iomem *)addr); @@ -265,6 +334,17 @@ static void init_cntr_base_dmc(struct perf_event *event, + DMC_COUNTER_DATA + (0xc * GET_COUNTERID(event)); } +static void init_cntr_base_ccpi2(struct perf_event *event, + struct tx2_uncore_pmu *tx2_pmu) +{ + + struct hw_perf_event *hwc = &event->hw; + + hwc->config_base = (unsigned long)tx2_pmu->base + + CCPI2_COUNTER_CTL + (4 * GET_COUNTERID_CCPI2(event)); + hwc->event_base = (unsigned long)tx2_pmu->base; +} + static void uncore_start_event_l3c(struct perf_event *event, int flags) { u32 val; @@ -312,6 +392,29 @@ static void uncore_stop_event_dmc(struct perf_event *event) reg_writel(val, hwc->config_base); } +static void uncore_start_event_ccpi2(struct perf_event *event, int flags) +{ + u32 val; + struct hw_perf_event *hwc = &event->hw; + + /* Bit [09:00] to set event id, set level and type to 1 */ + val = reg_readl(hwc->config_base); + reg_writel((val & ~0xFFF) | (3 << 10) | + GET_EVENTID_CCPI2(event), hwc->config_base); + /* reset[4], enable[0] and start[1] counters */ + reg_writel(0x13, hwc->event_base + CCPI2_PERF_CTL); + local64_set(&event->hw.prev_count, 0ULL); +} + +static void uncore_stop_event_ccpi2(struct perf_event *event) +{ + struct hw_perf_event *hwc = &event->hw; + + /* disable and stop counter */ + reg_writel(0, hwc->event_base + CCPI2_PERF_CTL); + reg_writel(0, hwc->config_base); +} + static void tx2_uncore_event_update(struct perf_event *event) { s64 prev, delta, new = 0; @@ -323,12 +426,20 @@ static void tx2_uncore_event_update(struct perf_event *event) tx2_pmu = pmu_to_tx2_pmu(event->pmu); type = tx2_pmu->type; prorate_factor = tx2_pmu->prorate_factor; - - new = reg_readl(hwc->event_base); - prev = local64_xchg(&hwc->prev_count, new); - - /* handles rollover of 32 bit counter */ - delta = (u32)(((1UL << 32) - prev) + new); + if (type == PMU_TYPE_CCPI2) { + reg_writel(CCPI2_COUNTER_OFFSET + GET_COUNTERID_CCPI2(event), + hwc->event_base + CCPI2_COUNTER_SEL); + new = reg_readl(hwc->event_base + CCPI2_COUNTER_DATA_L); + new |= (u64)reg_readl(hwc->event_base + + CCPI2_COUNTER_DATA_H) << 32; + prev = local64_xchg(&hwc->prev_count, new); + delta = new - prev; + } else { + new = reg_readl(hwc->event_base); + prev = local64_xchg(&hwc->prev_count, new); + /* handles rollover of 32 bit counter */ + delta = (u32)(((1UL << 32) - prev) + new); + } /* DMC event data_transfers granularity is 16 Bytes, convert it to 64 */ if (type == PMU_TYPE_DMC && @@ -351,6 +462,7 @@ static enum tx2_uncore_type get_tx2_pmu_type(struct acpi_device *adev) } devices[] = { {"CAV901D", PMU_TYPE_L3C}, {"CAV901F", PMU_TYPE_DMC}, + {"CAV901E", PMU_TYPE_CCPI2}, {"", PMU_TYPE_INVALID} }; @@ -380,7 +492,8 @@ static bool tx2_uncore_validate_event(struct pmu *pmu, * Make sure the group of events can be scheduled at once * on the PMU. */ -static bool tx2_uncore_validate_event_group(struct perf_event *event) +static bool tx2_uncore_validate_event_group(struct perf_event *event, + int max_counters) { struct perf_event *sibling, *leader = event->group_leader; int counters = 0; @@ -403,7 +516,7 @@ static bool tx2_uncore_validate_event_group(struct perf_event *event) * If the group requires more counters than the HW has, * it cannot ever be scheduled. */ - return counters <= TX2_PMU_MAX_COUNTERS; + return counters <= max_counters; } @@ -439,7 +552,7 @@ static int tx2_uncore_event_init(struct perf_event *event) hwc->config = event->attr.config; /* Validate the group */ - if (!tx2_uncore_validate_event_group(event)) + if (!tx2_uncore_validate_event_group(event, tx2_pmu->max_counters)) return -EINVAL; return 0; @@ -457,7 +570,8 @@ static void tx2_uncore_event_start(struct perf_event *event, int flags) perf_event_update_userpage(event); /* Start timer for first event */ - if (bitmap_weight(tx2_pmu->active_counters, + if (tx2_pmu->type != PMU_TYPE_CCPI2 && + bitmap_weight(tx2_pmu->active_counters, tx2_pmu->max_counters) == 1) { hrtimer_start(&tx2_pmu->hrtimer, ns_to_ktime(tx2_pmu->hrtimer_interval), @@ -495,7 +609,8 @@ static int tx2_uncore_event_add(struct perf_event *event, int flags) if (hwc->idx < 0) return -EAGAIN; - tx2_pmu->events[hwc->idx] = event; + if (tx2_pmu->type != PMU_TYPE_CCPI2) + tx2_pmu->events[hwc->idx] = event; /* set counter control and data registers base address */ tx2_pmu->init_cntr_base(event, tx2_pmu); @@ -514,10 +629,14 @@ static void tx2_uncore_event_del(struct perf_event *event, int flags) tx2_uncore_event_stop(event, PERF_EF_UPDATE); /* clear the assigned counter */ - free_counter(tx2_pmu, GET_COUNTERID(event)); + if (tx2_pmu->type == PMU_TYPE_CCPI2) + free_counter(tx2_pmu, GET_COUNTERID_CCPI2(event)); + else + free_counter(tx2_pmu, GET_COUNTERID(event)); perf_event_update_userpage(event); - tx2_pmu->events[hwc->idx] = NULL; + if (tx2_pmu->type != PMU_TYPE_CCPI2) + tx2_pmu->events[hwc->idx] = NULL; hwc->idx = -1; } @@ -580,8 +699,12 @@ static int tx2_uncore_pmu_add_dev(struct tx2_uncore_pmu *tx2_pmu) cpu_online_mask); tx2_pmu->cpu = cpu; - hrtimer_init(&tx2_pmu->hrtimer, CLOCK_MONOTONIC, HRTIMER_MODE_REL); - tx2_pmu->hrtimer.function = tx2_hrtimer_callback; + /* CCPI2 counters are 64 bit counters. */ + if (tx2_pmu->type != PMU_TYPE_CCPI2) { + hrtimer_init(&tx2_pmu->hrtimer, + CLOCK_MONOTONIC, HRTIMER_MODE_REL); + tx2_pmu->hrtimer.function = tx2_hrtimer_callback; + } ret = tx2_uncore_pmu_register(tx2_pmu); if (ret) { @@ -653,7 +776,7 @@ static struct tx2_uncore_pmu *tx2_uncore_pmu_init_dev(struct device *dev, switch (tx2_pmu->type) { case PMU_TYPE_L3C: - tx2_pmu->max_counters = TX2_PMU_MAX_COUNTERS; + tx2_pmu->max_counters = TX2_PMU_DMC_L3C_MAX_COUNTERS; tx2_pmu->prorate_factor = TX2_PMU_L3_TILES; tx2_pmu->max_events = L3_EVENT_MAX; tx2_pmu->hrtimer_interval = TX2_PMU_HRTIMER_INTERVAL; @@ -665,7 +788,7 @@ static struct tx2_uncore_pmu *tx2_uncore_pmu_init_dev(struct device *dev, tx2_pmu->stop_event = uncore_stop_event_l3c; break; case PMU_TYPE_DMC: - tx2_pmu->max_counters = TX2_PMU_MAX_COUNTERS; + tx2_pmu->max_counters = TX2_PMU_DMC_L3C_MAX_COUNTERS; tx2_pmu->prorate_factor = TX2_PMU_DMC_CHANNELS; tx2_pmu->max_events = DMC_EVENT_MAX; tx2_pmu->hrtimer_interval = TX2_PMU_HRTIMER_INTERVAL; @@ -676,6 +799,17 @@ static struct tx2_uncore_pmu *tx2_uncore_pmu_init_dev(struct device *dev, tx2_pmu->start_event = uncore_start_event_dmc; tx2_pmu->stop_event = uncore_stop_event_dmc; break; + case PMU_TYPE_CCPI2: + tx2_pmu->max_counters = TX2_PMU_CCPI2_MAX_COUNTERS; + tx2_pmu->prorate_factor = 1; + tx2_pmu->max_events = CCPI2_EVENT_MAX; + tx2_pmu->attr_groups = ccpi2_pmu_attr_groups; + tx2_pmu->name = devm_kasprintf(dev, GFP_KERNEL, + "uncore_ccpi2_%d", tx2_pmu->node); + tx2_pmu->init_cntr_base = init_cntr_base_ccpi2; + tx2_pmu->start_event = uncore_start_event_ccpi2; + tx2_pmu->stop_event = uncore_stop_event_ccpi2; + break; case PMU_TYPE_INVALID: devm_kfree(dev, tx2_pmu); return NULL; @@ -744,7 +878,8 @@ static int tx2_uncore_pmu_offline_cpu(unsigned int cpu, if (cpu != tx2_pmu->cpu) return 0; - hrtimer_cancel(&tx2_pmu->hrtimer); + if (tx2_pmu->type != PMU_TYPE_CCPI2) + hrtimer_cancel(&tx2_pmu->hrtimer); cpumask_copy(&cpu_online_mask_temp, cpu_online_mask); cpumask_clear_cpu(cpu, &cpu_online_mask_temp); new_cpu = cpumask_any_and(