From patchwork Thu Aug 30 19:43:52 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 10582749 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id DB6B9180E for ; Thu, 30 Aug 2018 19:47:29 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id CB24D2C48E for ; Thu, 30 Aug 2018 19:47:29 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id BEEEC2C4C1; Thu, 30 Aug 2018 19:47:29 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FROM,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 66FDE2C48E for ; Thu, 30 Aug 2018 19:47:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727529AbeH3Xum (ORCPT ); Thu, 30 Aug 2018 19:50:42 -0400 Received: from mail-lf1-f67.google.com ([209.85.167.67]:41211 "EHLO mail-lf1-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726959AbeH3Xul (ORCPT ); Thu, 30 Aug 2018 19:50:41 -0400 Received: by mail-lf1-f67.google.com with SMTP id l26-v6so8149310lfc.8; Thu, 30 Aug 2018 12:46:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=J4DgLMSYNnZB6dnaOj/ZHug8J8zcGBQkyGiNMTFAyOA=; b=MJinfBC0S7ygek0Yigh1yUHEKxr9VYOiCjwHviS5RX+AFfmiZmx5CwtZNmmkKPl7ry R36vP8TsXksvfPzapUMyFAMkle3RaZ5GyxOjn0wkSApoG3GNof4UJ/NyK9pwvVzBZ2Xw po+EkcXQBo+uwHoyIyvV/WLIq8EAgRLj77mDWF0s1wnxFOu7TpZpGlUyo3jDDhamO3vc s6eA5n7QNUMxjP3LHlSzZfh3B+IEgPAD9z1LfW5yuOo6V6aVutQ53PgEp3L2ze/Drxsd h8xwbKbbi6Zs0h02K/6qSwJoeZ7LNcizM+zCofrjgoQU7Iv6qJUak2I5Dn5pj1/AgyWc AXWg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=J4DgLMSYNnZB6dnaOj/ZHug8J8zcGBQkyGiNMTFAyOA=; b=b0vGfYql+rEBsC+FTQc1/73GQ342ar98Drdb7gMN7wZriDRJlNqKg+7Opt+taAuoeE +e3dHt50c58i13z6fwU/9swIBvanaotxYRU3pi/38JtthIiSBkUVuWKm3+gZFPXvjKhx rJCMml21zmdv4O9LrAlUTLfHAKPZFtm39lLWS1wRdYxWf09pV0ceiihtMISpvd1pq2wf 4TCZIu3vfuJnbkH7ThcJlPgvmoNTny/uE+hF7wXjfLB2TcuNWAxo917XsPFzjMMh6zIi cJB847PFg+WhJR23YIM5B7JbWn4ph7Y3wQf1PnWyZpGNf3FL59sU04AKe54achPO2fz2 UBbQ== X-Gm-Message-State: APzg51BWk67KzusrRNIoe/aWH3Hi5o0RTDLaXIONRKeIxe+fNrWo/pMv yV3ss6jaagsXztrto+7YW0w= X-Google-Smtp-Source: ANB0VdZh0eX/p8t90yulmSF4LytIqHHT3mhc6AbQ4nDEYAc0r0CZiZJPl5hDkSrIne/DKYJeuuJViA== X-Received: by 2002:a19:ef18:: with SMTP id n24-v6mr8701156lfh.36.1535658412551; Thu, 30 Aug 2018 12:46:52 -0700 (PDT) Received: from localhost.localdomain (109-252-90-13.nat.spd-mgts.ru. [109.252.90.13]) by smtp.gmail.com with ESMTPSA id x3-v6sm1381191ljb.25.2018.08.30.12.46.51 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 30 Aug 2018 12:46:52 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Peter De Schrijver , "Rafael J. Wysocki" , Viresh Kumar , Rob Herring Cc: linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v1 1/5] dt-bindings: cpufreq: Add binding for NVIDIA Tegra20/30 Date: Thu, 30 Aug 2018 22:43:52 +0300 Message-Id: <20180830194356.14059-2-digetx@gmail.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20180830194356.14059-1-digetx@gmail.com> References: <20180830194356.14059-1-digetx@gmail.com> Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add device-tree binding that describes CPU frequency-scaling hardware found on NVIDIA Tegra20/30 SoC's. Signed-off-by: Dmitry Osipenko --- .../cpufreq/nvidia,tegra20-cpufreq.txt | 38 +++++++++++++++++++ 1 file changed, 38 insertions(+) create mode 100644 Documentation/devicetree/bindings/cpufreq/nvidia,tegra20-cpufreq.txt diff --git a/Documentation/devicetree/bindings/cpufreq/nvidia,tegra20-cpufreq.txt b/Documentation/devicetree/bindings/cpufreq/nvidia,tegra20-cpufreq.txt new file mode 100644 index 000000000000..2c51f676e958 --- /dev/null +++ b/Documentation/devicetree/bindings/cpufreq/nvidia,tegra20-cpufreq.txt @@ -0,0 +1,38 @@ +Binding for NVIDIA Tegra20 CPUFreq +================================== + +Required properties: +- clocks: Must contain an entry for each entry in clock-names. + See ../clocks/clock-bindings.txt for details. +- clock-names: Must include the following entries: + - pll_x: main-parent for CPU clock, must be the first entry + - backup: intermediate-parent for CPU clock + - cpu: the CPU clock +- operating-points-v2: See ../bindings/opp/opp.txt for details. +- #cooling-cells: Should be 2. See ../thermal/thermal.txt for details. + +Example: + cpu0_opp_table: opp_table0 { + compatible = "operating-points-v2"; + + opp@216000000 { + clock-latency-ns = <300000>; + opp-hz = /bits/ 64 <216000000>; + opp-microvolt = <7500000>; + opp-suspend; + }; + + ... + }; + + cpus { + cpu@0 { + compatible = "arm,cortex-a9"; + clocks = <&tegra_car TEGRA20_CLK_PLL_X>, + <&tegra_car TEGRA20_CLK_PLL_P>, + <&tegra_car TEGRA20_CLK_CCLK>; + clock-names = "pll_x", "backup", "cpu"; + operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; + }; + }; From patchwork Thu Aug 30 19:43:53 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 10582741 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id A1802175A for ; Thu, 30 Aug 2018 19:46:59 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 918002C48E for ; Thu, 30 Aug 2018 19:46:59 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 855B62C4C1; Thu, 30 Aug 2018 19:46:59 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FROM,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 8657A2C48E for ; Thu, 30 Aug 2018 19:46:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727614AbeH3Xun (ORCPT ); Thu, 30 Aug 2018 19:50:43 -0400 Received: from mail-lf1-f65.google.com ([209.85.167.65]:45209 "EHLO mail-lf1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727247AbeH3Xun (ORCPT ); Thu, 30 Aug 2018 19:50:43 -0400 Received: by mail-lf1-f65.google.com with SMTP id r4-v6so8142372lff.12; Thu, 30 Aug 2018 12:46:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=6GFkJgIko56TQksR/BsAqKZFuBijnMvkpCNMpYoaJ+k=; b=skciQvBWKfpoRdEtj8FAsxeuAjrn3O0degJ3eJ2D9hPwLWc09YfemF3oZ738iJD7qB hcxRiE+44OYljzwvVtIXTDUCZaU4EfM87LhFGJKexf85FeAimY66Hl5c1T5vhYtByOZ4 lBZScWB/S7ga4eccuyloAWEdb1QtA8SFfKBsrh+K2y0MpDoxcj6yoZhVhEmDp9+4Zgbn fN1ekJRobTT3jrvzvmKXP2SBZKrmPRBpgy6Locpp4gy2r9XtXgaAV1CR3FJHBPz/8PZ+ h0FYT9s8ZAtqvpH6ltENhGxQDYaCfEqerrCmwXtiqv1Ti6B9eY/HuU/nM4SxOED/X9hC Zoog== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=6GFkJgIko56TQksR/BsAqKZFuBijnMvkpCNMpYoaJ+k=; b=ShoE+AAronzYX/zpBipFTn7tRRYeOBZePUTBAPYOoUAyUypmr1bvyaJLsBoFjgDzeC C3Zb5tbWUEPDcjfUY7WcCq96nOuk/WBET+3aszCXfeksSkEFzns2C5k8UBLiJt/4tJ50 iigUdK76FLFbBllyb3IDIyfkmZaK+6SsIzm0RP9O2th+OJttIMQfGOeb/UDVqTCrJQ2A An7tQwYwlPdQ/7psvRHQpSiX/3gwTFi5VjA45vc3jqxVRhoxathTMURAFVIyY+UvHU+k 7ODhuQrU+7Vdk4MQ5gFIGfnQwh3GxjyFZXGwgrU4NTLOZjgNPmNEPllw7tM7CrCWz/Fg /8Tw== X-Gm-Message-State: APzg51AaL7Bz6UqLVQvtqT8KMDE9p2e3O2ZW7ONoQnAYfjFTbkeAcJUg 6eWDzsaKIpzo8xruYOzkorA= X-Google-Smtp-Source: ANB0Vda7P4yeKRWHrYTzPTqojpUCkPzJEe9sWiMXuKQAHlxou/a0QyMeLtDat17RrJO4BjqmmDXc+w== X-Received: by 2002:a19:2c8e:: with SMTP id s136-v6mr2444878lfs.78.1535658413523; Thu, 30 Aug 2018 12:46:53 -0700 (PDT) Received: from localhost.localdomain (109-252-90-13.nat.spd-mgts.ru. [109.252.90.13]) by smtp.gmail.com with ESMTPSA id x3-v6sm1381191ljb.25.2018.08.30.12.46.52 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 30 Aug 2018 12:46:53 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Peter De Schrijver , "Rafael J. Wysocki" , Viresh Kumar , Rob Herring Cc: linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v1 2/5] cpufreq: tegra20: Support OPP, thermal cooling and Tegra30 Date: Thu, 30 Aug 2018 22:43:53 +0300 Message-Id: <20180830194356.14059-3-digetx@gmail.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20180830194356.14059-1-digetx@gmail.com> References: <20180830194356.14059-1-digetx@gmail.com> Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add support for thermal throttling and Operating Performance Points. Driver now relies on OPP's supplied via device tree and therefore will work only on devices that use the updated device tree. The generalization of the driver allows to transparently support Tegra30. Signed-off-by: Dmitry Osipenko --- drivers/cpufreq/Kconfig.arm | 2 + drivers/cpufreq/cpufreq-dt-platdev.c | 2 + drivers/cpufreq/tegra20-cpufreq.c | 334 ++++++++++++++++++++------- 3 files changed, 257 insertions(+), 81 deletions(-) diff --git a/drivers/cpufreq/Kconfig.arm b/drivers/cpufreq/Kconfig.arm index 0cd8eb76ad59..78795d108f5e 100644 --- a/drivers/cpufreq/Kconfig.arm +++ b/drivers/cpufreq/Kconfig.arm @@ -262,7 +262,9 @@ config ARM_TANGO_CPUFREQ config ARM_TEGRA20_CPUFREQ tristate "Tegra20 CPUFreq support" + depends on !CPU_THERMAL || THERMAL depends on ARCH_TEGRA + select PM_OPP default y help This adds the CPUFreq driver support for Tegra20 SOCs. diff --git a/drivers/cpufreq/cpufreq-dt-platdev.c b/drivers/cpufreq/cpufreq-dt-platdev.c index fe14c57de6ca..3c4709159995 100644 --- a/drivers/cpufreq/cpufreq-dt-platdev.c +++ b/drivers/cpufreq/cpufreq-dt-platdev.c @@ -114,6 +114,8 @@ static const struct of_device_id blacklist[] __initconst = { { .compatible = "mediatek,mt8173", }, { .compatible = "mediatek,mt8176", }, + { .compatible = "nvidia,tegra20", }, + { .compatible = "nvidia,tegra30", }, { .compatible = "nvidia,tegra124", }, { .compatible = "qcom,apq8096", }, diff --git a/drivers/cpufreq/tegra20-cpufreq.c b/drivers/cpufreq/tegra20-cpufreq.c index 05f57dcd5215..fd6c40a64175 100644 --- a/drivers/cpufreq/tegra20-cpufreq.c +++ b/drivers/cpufreq/tegra20-cpufreq.c @@ -17,163 +17,347 @@ */ #include +#include +#include #include #include #include #include +#include #include +#include #include -static struct cpufreq_frequency_table freq_table[] = { - { .frequency = 216000 }, - { .frequency = 312000 }, - { .frequency = 456000 }, - { .frequency = 608000 }, - { .frequency = 760000 }, - { .frequency = 816000 }, - { .frequency = 912000 }, - { .frequency = 1000000 }, - { .frequency = CPUFREQ_TABLE_END }, -}; +#define PLLX_PREPARE BIT(0) +#define PLLX_PREPARED BIT(1) struct tegra20_cpufreq { struct device *dev; + struct device *cpu_dev; + struct cpumask cpu_mask; struct cpufreq_driver driver; + struct thermal_cooling_device *cdev; + struct cpufreq_frequency_table *freq_table; struct clk *cpu_clk; struct clk *pll_x_clk; - struct clk *pll_p_clk; - bool pll_x_prepared; + struct clk *backup_clk; + unsigned long backup_rate; + unsigned int state; }; static unsigned int tegra_get_intermediate(struct cpufreq_policy *policy, unsigned int index) { struct tegra20_cpufreq *cpufreq = cpufreq_get_driver_data(); - unsigned int ifreq = clk_get_rate(cpufreq->pll_p_clk) / 1000; + struct clk *cpu_parent = clk_get_parent(cpufreq->cpu_clk); + unsigned long new_rate = cpufreq->freq_table[index].frequency * 1000; + int err; + + /* + * Make sure that backup clock rate stays consistent during + * transition by entering into critical section of the backup clock. + */ + err = clk_rate_exclusive_get(cpufreq->backup_clk); + /* this shouldn't fail */ + WARN_ON_ONCE(err); /* - * Don't switch to intermediate freq if: - * - we are already at it, i.e. policy->cur == ifreq - * - index corresponds to ifreq + * When target rate is equal to backup rate, we don't need to + * switch to backup clock and so the intermediate routine isn't + * called. Also, we wouldn't be using PLLX anymore and must not + * take extra reference to it, as it can be disabled to save some + * power. */ - if (freq_table[index].frequency == ifreq || policy->cur == ifreq) + cpufreq->backup_rate = clk_get_rate(cpufreq->backup_clk); + + if (new_rate == cpufreq->backup_rate) + cpufreq->state &= ~PLLX_PREPARE; + else + cpufreq->state |= PLLX_PREPARE; + + /* don't switch to intermediate freq if we are already at it */ + if (clk_is_match(cpu_parent, cpufreq->backup_clk)) return 0; - return ifreq; + return cpufreq->backup_rate / 1000; } static int tegra_target_intermediate(struct cpufreq_policy *policy, unsigned int index) { struct tegra20_cpufreq *cpufreq = cpufreq_get_driver_data(); - int ret; + unsigned int state = cpufreq->state; + int err; /* - * Take an extra reference to the main pll so it doesn't turn - * off when we move the cpu off of it as enabling it again while we - * switch to it from tegra_target() would take additional time. - * - * When target-freq is equal to intermediate freq we don't need to - * switch to an intermediate freq and so this routine isn't called. - * Also, we wouldn't be using pll_x anymore and must not take extra - * reference to it, as it can be disabled now to save some power. + * Take an extra reference to the main PLLX so it doesn't turn off + * when we move the CPU clock to backup clock as enabling it again + * while we switch to it from tegra_target() would take additional + * time. */ - clk_prepare_enable(cpufreq->pll_x_clk); + if ((state & (PLLX_PREPARED | PLLX_PREPARE)) == PLLX_PREPARE) { + err = clk_prepare_enable(cpufreq->pll_x_clk); + if (err) + goto err_exclusive_put; - ret = clk_set_parent(cpufreq->cpu_clk, cpufreq->pll_p_clk); - if (ret) + cpufreq->state |= PLLX_PREPARED; + } + + err = clk_set_parent(cpufreq->cpu_clk, cpufreq->backup_clk); + if (err) + goto err_exclusive_put; + + return 0; + +err_exclusive_put: + clk_rate_exclusive_put(cpufreq->backup_clk); + + if (cpufreq->state & PLLX_PREPARED) { clk_disable_unprepare(cpufreq->pll_x_clk); - else - cpufreq->pll_x_prepared = true; + cpufreq->state &= ~PLLX_PREPARED; + } - return ret; + /* this shouldn't fail */ + return WARN_ON_ONCE(err); } static int tegra_target(struct cpufreq_policy *policy, unsigned int index) { struct tegra20_cpufreq *cpufreq = cpufreq_get_driver_data(); - unsigned long rate = freq_table[index].frequency; - unsigned int ifreq = clk_get_rate(cpufreq->pll_p_clk) / 1000; + unsigned long new_rate = cpufreq->freq_table[index].frequency * 1000; + unsigned int state = cpufreq->state; int ret; /* - * target freq == pll_p, don't need to take extra reference to pll_x_clk - * as it isn't used anymore. + * Drop refcount to PLLX only if we switched to backup clock earlier + * during transitioning to a target frequency and we are going to + * stay with the backup clock. */ - if (rate == ifreq) - return clk_set_parent(cpufreq->cpu_clk, cpufreq->pll_p_clk); + if ((state & (PLLX_PREPARED | PLLX_PREPARE)) == PLLX_PREPARED) { + clk_disable_unprepare(cpufreq->pll_x_clk); + state &= ~PLLX_PREPARED; + } - ret = clk_set_rate(cpufreq->pll_x_clk, rate * 1000); - /* Restore to earlier frequency on error, i.e. pll_x */ + /* + * Switch to new OPP, note that this will change PLLX rate and + * not the CCLK. + */ + ret = dev_pm_opp_set_rate(cpufreq->cpu_dev, new_rate); if (ret) - dev_err(cpufreq->dev, "Failed to change pll_x to %lu\n", rate); + goto exclusive_put; + + /* + * Target rate == backup rate leaves PLLX turned off, CPU is kept + * running off the backup clock. This should save us some power by + * keeping one more PLL disabled because the backup clock assumed + * to be always-on. In this case PLLX_PREPARE flag will be omitted. + */ + if (state & PLLX_PREPARE) { + /* + * CCF doesn't return error if clock-enabling fails on + * re-parent, hence enable it now. + */ + ret = clk_prepare_enable(cpufreq->pll_x_clk); + if (ret) + goto exclusive_put; + + ret = clk_set_parent(cpufreq->cpu_clk, cpufreq->pll_x_clk); - ret = clk_set_parent(cpufreq->cpu_clk, cpufreq->pll_x_clk); - /* This shouldn't fail while changing or restoring */ - WARN_ON(ret); + clk_disable_unprepare(cpufreq->pll_x_clk); + } /* - * Drop count to pll_x clock only if we switched to intermediate freq - * earlier while transitioning to a target frequency. + * Drop refcount to PLLX only if we switched to backup clock earlier + * during transitioning to a target frequency. */ - if (cpufreq->pll_x_prepared) { + if (state & PLLX_PREPARED) { clk_disable_unprepare(cpufreq->pll_x_clk); - cpufreq->pll_x_prepared = false; + state &= ~PLLX_PREPARED; } +exclusive_put: + clk_rate_exclusive_put(cpufreq->backup_clk); + + cpufreq->state = state; + + /* this shouldn't fail */ + return WARN_ON_ONCE(ret); +} + +static int tegra_cpu_setup_opp(struct tegra20_cpufreq *cpufreq) +{ + struct device *dev = cpufreq->cpu_dev; + int err; + + err = dev_pm_opp_of_cpumask_add_table(cpu_possible_mask); + if (err) + return err; + + err = dev_pm_opp_init_cpufreq_table(dev, &cpufreq->freq_table); + if (err) + goto err_remove_table; + + return 0; + +err_remove_table: + dev_pm_opp_of_cpumask_remove_table(cpu_possible_mask); + + return err; +} + +static void tegra_cpu_release_opp(struct tegra20_cpufreq *cpufreq) +{ + dev_pm_opp_free_cpufreq_table(cpufreq->cpu_dev, &cpufreq->freq_table); + dev_pm_opp_of_cpumask_remove_table(cpu_possible_mask); +} + +static int tegra_cpu_init_clk(struct tegra20_cpufreq *cpufreq) +{ + unsigned long backup_rate; + int ret; + + ret = clk_rate_exclusive_get(cpufreq->backup_clk); + if (ret) + return ret; + + ret = clk_set_parent(cpufreq->cpu_clk, cpufreq->backup_clk); + if (ret) + goto exclusive_put; + + backup_rate = clk_get_rate(cpufreq->backup_clk); + + /* + * The CCLK has its own clock divider, that divider isn't getting + * disabled on clock reparent. Hence set CCLK parent to backup clock + * in order to disable the divider if it happens to be enabled, + * otherwise clk_set_rate() has no effect. + */ + ret = clk_set_rate(cpufreq->cpu_clk, backup_rate); + +exclusive_put: + clk_rate_exclusive_put(cpufreq->backup_clk); + return ret; } static int tegra_cpu_init(struct cpufreq_policy *policy) { struct tegra20_cpufreq *cpufreq = cpufreq_get_driver_data(); - int ret; + struct device *cpu = cpufreq->cpu_dev; + int err; - clk_prepare_enable(cpufreq->cpu_clk); + err = tegra_cpu_setup_opp(cpufreq); + if (err) { + dev_err(cpufreq->dev, "Failed to setup OPP: %d\n", err); + return err; + } - /* FIXME: what's the actual transition time? */ - ret = cpufreq_generic_init(policy, freq_table, 300 * 1000); - if (ret) { - clk_disable_unprepare(cpufreq->cpu_clk); - return ret; + err = clk_prepare_enable(cpufreq->cpu_clk); + if (err) { + dev_err(cpufreq->dev, + "Failed to enable CPU clock: %d\n", err); + goto er_release_opp; } + err = clk_prepare_enable(cpufreq->backup_clk); + if (err) { + dev_err(cpufreq->dev, + "Failed to enable backup clock: %d\n", err); + goto err_cpu_disable; + } + + err = clk_rate_exclusive_get(cpufreq->cpu_clk); + if (err) { + dev_err(cpufreq->dev, + "Failed to make CPU clock exclusive: %d\n", err); + goto err_backup_disable; + } + + err = tegra_cpu_init_clk(cpufreq); + if (err) { + dev_err(cpufreq->dev, + "Failed to initialize CPU clock: %d\n", err); + goto err_exclusive_put; + } + + err = cpufreq_generic_init(policy, cpufreq->freq_table, + dev_pm_opp_get_max_transition_latency(cpu)); + if (err) + goto err_exclusive_put; + policy->clk = cpufreq->cpu_clk; - policy->suspend_freq = freq_table[0].frequency; + policy->suspend_freq = dev_pm_opp_get_suspend_opp_freq(cpu) / 1000; + return 0; + +err_exclusive_put: + clk_rate_exclusive_put(cpufreq->cpu_clk); +err_backup_disable: + clk_disable_unprepare(cpufreq->backup_clk); +err_cpu_disable: + clk_disable_unprepare(cpufreq->cpu_clk); +er_release_opp: + tegra_cpu_release_opp(cpufreq); + + return err; } static int tegra_cpu_exit(struct cpufreq_policy *policy) { struct tegra20_cpufreq *cpufreq = cpufreq_get_driver_data(); + cpufreq_cooling_unregister(cpufreq->cdev); + clk_rate_exclusive_put(cpufreq->cpu_clk); + clk_disable_unprepare(cpufreq->backup_clk); clk_disable_unprepare(cpufreq->cpu_clk); + tegra_cpu_release_opp(cpufreq); + return 0; } +static void tegra_cpu_ready(struct cpufreq_policy *policy) +{ + struct tegra20_cpufreq *cpufreq = cpufreq_get_driver_data(); + + cpufreq->cdev = of_cpufreq_cooling_register(policy); +} + static int tegra20_cpufreq_probe(struct platform_device *pdev) { struct tegra20_cpufreq *cpufreq; + struct device_node *np; int err; cpufreq = devm_kzalloc(&pdev->dev, sizeof(*cpufreq), GFP_KERNEL); if (!cpufreq) return -ENOMEM; - cpufreq->cpu_clk = clk_get_sys(NULL, "cclk"); - if (IS_ERR(cpufreq->cpu_clk)) - return PTR_ERR(cpufreq->cpu_clk); + cpufreq->cpu_dev = get_cpu_device(0); + if (!cpufreq->cpu_dev) + return -ENODEV; + + np = cpufreq->cpu_dev->of_node; - cpufreq->pll_x_clk = clk_get_sys(NULL, "pll_x"); + cpufreq->cpu_clk = devm_get_clk_from_child(&pdev->dev, np, "cpu"); + if (IS_ERR(cpufreq->cpu_clk)) { + err = PTR_ERR(cpufreq->cpu_clk); + dev_err(&pdev->dev, "Failed to get cpu clock: %d\n", err); + dev_err(&pdev->dev, "Please update your device tree\n"); + return err; + } + + cpufreq->pll_x_clk = devm_get_clk_from_child(&pdev->dev, np, "pll_x"); if (IS_ERR(cpufreq->pll_x_clk)) { err = PTR_ERR(cpufreq->pll_x_clk); - goto put_cpu; + dev_err(&pdev->dev, "Failed to get pll_x clock: %d\n", err); + return err; } - cpufreq->pll_p_clk = clk_get_sys(NULL, "pll_p"); - if (IS_ERR(cpufreq->pll_p_clk)) { - err = PTR_ERR(cpufreq->pll_p_clk); - goto put_pll_x; + cpufreq->backup_clk = devm_get_clk_from_child(&pdev->dev, np, "backup"); + if (IS_ERR(cpufreq->backup_clk)) { + err = PTR_ERR(cpufreq->backup_clk); + dev_err(&pdev->dev, "Failed to get backup clock: %d\n", err); + return err; } cpufreq->dev = &pdev->dev; @@ -181,6 +365,7 @@ static int tegra20_cpufreq_probe(struct platform_device *pdev) cpufreq->driver.attr = cpufreq_generic_attr; cpufreq->driver.init = tegra_cpu_init; cpufreq->driver.exit = tegra_cpu_exit; + cpufreq->driver.ready = tegra_cpu_ready; cpufreq->driver.flags = CPUFREQ_NEED_INITIAL_FREQ_CHECK; cpufreq->driver.verify = cpufreq_generic_frequency_table_verify; cpufreq->driver.suspend = cpufreq_generic_suspend; @@ -192,20 +377,11 @@ static int tegra20_cpufreq_probe(struct platform_device *pdev) err = cpufreq_register_driver(&cpufreq->driver); if (err) - goto put_pll_p; + return err; platform_set_drvdata(pdev, cpufreq); return 0; - -put_pll_p: - clk_put(cpufreq->pll_p_clk); -put_pll_x: - clk_put(cpufreq->pll_x_clk); -put_cpu: - clk_put(cpufreq->cpu_clk); - - return err; } static int tegra20_cpufreq_remove(struct platform_device *pdev) @@ -214,10 +390,6 @@ static int tegra20_cpufreq_remove(struct platform_device *pdev) cpufreq_unregister_driver(&cpufreq->driver); - clk_put(cpufreq->pll_p_clk); - clk_put(cpufreq->pll_x_clk); - clk_put(cpufreq->cpu_clk); - return 0; } From patchwork Thu Aug 30 19:43:54 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 10582747 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 9742A14BD for ; Thu, 30 Aug 2018 19:47:23 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 864B62C48E for ; Thu, 30 Aug 2018 19:47:23 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 7A9D02C4C1; Thu, 30 Aug 2018 19:47:23 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FROM,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 3335A2C48E for ; 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[109.252.90.13]) by smtp.gmail.com with ESMTPSA id x3-v6sm1381191ljb.25.2018.08.30.12.46.53 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 30 Aug 2018 12:46:53 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Peter De Schrijver , "Rafael J. Wysocki" , Viresh Kumar , Rob Herring Cc: linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v1 3/5] ARM: tegra: Create tegra20-cpufreq device on Tegra30 Date: Thu, 30 Aug 2018 22:43:54 +0300 Message-Id: <20180830194356.14059-4-digetx@gmail.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20180830194356.14059-1-digetx@gmail.com> References: <20180830194356.14059-1-digetx@gmail.com> Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Tegra20-cpufreq driver require a platform device in order to be loaded, instantiate a simple platform device for the driver during of the machines late initialization. Driver now supports Tegra30 SoC's, hence create the device on Tegra30 machines. Signed-off-by: Dmitry Osipenko --- arch/arm/mach-tegra/tegra.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/mach-tegra/tegra.c b/arch/arm/mach-tegra/tegra.c index 67d8ae60ac67..b559e22eab76 100644 --- a/arch/arm/mach-tegra/tegra.c +++ b/arch/arm/mach-tegra/tegra.c @@ -111,6 +111,10 @@ static void __init tegra_dt_init_late(void) if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC) && of_machine_is_compatible("nvidia,tegra20")) platform_device_register_simple("tegra20-cpufreq", -1, NULL, 0); + + if (IS_ENABLED(CONFIG_ARCH_TEGRA_3x_SOC) && + of_machine_is_compatible("nvidia,tegra30")) + platform_device_register_simple("tegra20-cpufreq", -1, NULL, 0); } static const char * const tegra_dt_board_compat[] = { From patchwork Thu Aug 30 19:43:55 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 10582743 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 84E2414BD for ; Thu, 30 Aug 2018 19:47:10 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 5026A2C4C0 for ; Thu, 30 Aug 2018 19:47:10 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 43FA72C4C2; Thu, 30 Aug 2018 19:47:10 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FROM,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id DBE922C4C0 for ; Thu, 30 Aug 2018 19:47:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727617AbeH3Xuo (ORCPT ); Thu, 30 Aug 2018 19:50:44 -0400 Received: from mail-lj1-f193.google.com ([209.85.208.193]:46334 "EHLO mail-lj1-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727525AbeH3Xuo (ORCPT ); Thu, 30 Aug 2018 19:50:44 -0400 Received: by mail-lj1-f193.google.com with SMTP id 203-v6so8209901ljj.13; Thu, 30 Aug 2018 12:46:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=oAdTGbI6yFO7xBr8XZdwHyZzxbUESQyzxbd3CtAslzU=; b=mVHxGQvBpMQlTgZHlFAb0FzCSiJFunZqJAaqzNKxB6cfHqP948zdBJass9AjZSjMmn mgFNm+Q/KbQ+glkmwIX3B3I+rcC39zRwb56Wag49TAplhzYl98XnEU8hbjuab0N9C9kX Dliy3g867yMeBBTqLjnsCNwDUdSirQXezGfZPcxPK4WdEzJwF1miQFUKgXhoxkUfjNYv SRbw3ZuQp+WJb62uXiHZyuQb8FQwNdKXBcsmwRNmTc74ZsrSgnR/ZwCs1p0uSvCEzJSZ BED+jREWgP6O7e+el+Ji2IQoCVQF5IhSJ5I2PE9VxxZcH9FcOIz2r9tmH6M7NxFIupAS uNAw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=oAdTGbI6yFO7xBr8XZdwHyZzxbUESQyzxbd3CtAslzU=; b=RMbO7Bawo2zqRKriWxytsOV2rLa6gh2YZITlUJXqXd2bLcuIz2vIIsJplkvqSqKK6C HVJddShhcWkxDDcxK45Ro2dfoyyEA64Xfw0Fo6m/xAcKLSjMf+NaeOTJZNCD8kV0UeHj p+XdU0UKOWI4VfGS9cPGqErPueiqGbRqAZJNfZzMyeqnxCjFWwxEBlVzi5YpXnZTQ+mL C29CIQCztqOrCMlKbGwOpSXasz+SI58qZumj5Sggo+xnKUo6KmeZ4UKDVzcI5S7UAhs/ 62lho5uXn8qkwq8UXeqvYb5KNVs3i2Jq1GFubUTkZdDWmVT8pMthvHjtPSpsSVi8CR8X VZCQ== X-Gm-Message-State: APzg51D+c+UiD2Z9NWJGE3hlnvLPEFRX3Hpk+57700gbS97WGnrIMj+U dSKIdFmDJMKSYMTw1UNptkI= X-Google-Smtp-Source: ANB0VdbcbEmQf1ZNr2wuO7hnLxghrf1wwzyZcvjziDf1OTBU8Whsr2d8SC8pTX4Vga42KK8sQfAiRg== X-Received: by 2002:a2e:752:: with SMTP id i18-v6mr8121452ljd.118.1535658415356; Thu, 30 Aug 2018 12:46:55 -0700 (PDT) Received: from localhost.localdomain (109-252-90-13.nat.spd-mgts.ru. [109.252.90.13]) by smtp.gmail.com with ESMTPSA id x3-v6sm1381191ljb.25.2018.08.30.12.46.54 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 30 Aug 2018 12:46:54 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Peter De Schrijver , "Rafael J. Wysocki" , Viresh Kumar , Rob Herring Cc: linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v1 4/5] ARM: dts: tegra20: Add CPU Operating Performance Points Date: Thu, 30 Aug 2018 22:43:55 +0300 Message-Id: <20180830194356.14059-5-digetx@gmail.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20180830194356.14059-1-digetx@gmail.com> References: <20180830194356.14059-1-digetx@gmail.com> Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add CPU's Operating Performance Points to the device tree, they are used by the CPUFreq driver and allow to setup thermal throttling for the boards by linking the cooling device (CPU) with thermal sensors via thermal-zones description. Signed-off-by: Dmitry Osipenko --- arch/arm/boot/dts/tegra20.dtsi | 58 ++++++++++++++++++++++++++++++++++ 1 file changed, 58 insertions(+) diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi index 01398db0c9c7..4415de0f7c65 100644 --- a/arch/arm/boot/dts/tegra20.dtsi +++ b/arch/arm/boot/dts/tegra20.dtsi @@ -859,6 +859,52 @@ status = "disabled"; }; + cpu0_opp_table: opp_table0 { + compatible = "operating-points-v2"; + opp-shared; + + opp@216000000 { + clock-latency-ns = <2000>; + opp-hz = /bits/ 64 <216000000>; + opp-suspend; + }; + + opp@312000000 { + clock-latency-ns = <125000>; + opp-hz = /bits/ 64 <312000000>; + }; + + opp@456000000 { + clock-latency-ns = <125000>; + opp-hz = /bits/ 64 <456000000>; + }; + + opp@608000000 { + clock-latency-ns = <125000>; + opp-hz = /bits/ 64 <608000000>; + }; + + opp@760000000 { + clock-latency-ns = <125000>; + opp-hz = /bits/ 64 <760000000>; + }; + + opp@816000000 { + clock-latency-ns = <125000>; + opp-hz = /bits/ 64 <816000000>; + }; + + opp@912000000 { + clock-latency-ns = <125000>; + opp-hz = /bits/ 64 <912000000>; + }; + + opp@1000000000 { + clock-latency-ns = <125000>; + opp-hz = /bits/ 64 <1000000000>; + }; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -867,12 +913,24 @@ device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <0>; + clocks = <&tegra_car TEGRA20_CLK_PLL_X>, + <&tegra_car TEGRA20_CLK_PLL_P>, + <&tegra_car TEGRA20_CLK_CCLK>; + clock-names = "pll_x", "backup", "cpu"; + operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; }; cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <1>; + clocks = <&tegra_car TEGRA20_CLK_PLL_X>, + <&tegra_car TEGRA20_CLK_PLL_P>, + <&tegra_car TEGRA20_CLK_CCLK>; + clock-names = "pll_x", "backup", "cpu"; + operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; }; }; From patchwork Thu Aug 30 19:43:56 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 10582745 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 36D3B13AC for ; Thu, 30 Aug 2018 19:47:10 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 284A42C48E for ; Thu, 30 Aug 2018 19:47:10 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 1C6E72C4C2; Thu, 30 Aug 2018 19:47:10 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FROM,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 762502C48E for ; Thu, 30 Aug 2018 19:47:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727639AbeH3Xut (ORCPT ); Thu, 30 Aug 2018 19:50:49 -0400 Received: from mail-lj1-f195.google.com ([209.85.208.195]:34648 "EHLO mail-lj1-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726959AbeH3Xuo (ORCPT ); Thu, 30 Aug 2018 19:50:44 -0400 Received: by mail-lj1-f195.google.com with SMTP id f8-v6so8251688ljk.1; Thu, 30 Aug 2018 12:46:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Lag49zHaI7W74KHWcSc1GzDVdrmpI5PrH+/bPU7poCc=; b=PAqnRknaQwgnyChMjVs8bnX/oCeIvGEyTnrtpq+cDQe0L/1E/OvoVp+nV5Ar9Hebmn PMrGbqTvzstfM5uqEP7W3jbLRxMDwoI1xUup4CKMQmpNniJOi0waMSqw2Tngfo0LXCI6 0ICsR34newHI8VsdXDw258oFe32qqqxiz5o14f+3uHkR6eoyc7jHA4C3tgI1UXxRwWT9 nM6fBpvb/0RfqrahsC8uNzdWp/cxEsVRXaJQ7ejev9Yow7axmmXw10njJ+Qr/k7xjE7T QTo/cHSEjFZ5O9FHX5adJaU1pw2ZF2Tq5Hf1dxjRigqwgFwfIQhBplf7/MOX11j+y9kk pfrw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Lag49zHaI7W74KHWcSc1GzDVdrmpI5PrH+/bPU7poCc=; b=kWbMSXtgkwWC+6B/Z7D9ZKlHU7FGtEg9r5ZeA1Iqor/QKtwdeTm2Qz+fT3ttOfwX9t 5lcS4sJ+ROsxEwTXVEc5eoMExvrkon+ZSPKbjPJSqN2UYm5foktofJkFNsNrCdD1tmJx Dohno3JkGWqnsMVxqXq0BxJWVd1va5m+wQNlPpD8LhwDMoTzBmwhWFOwRom4tIgvv4Uw gKTSD/9kOAxNCzuQkjPyLc265jK8j4jBOdt/8MEetulNd/WwXC34oKpW3tJa9k8AyBK4 rtemZuyP2QUvjZ1AvCV1ClSPWP1EGvYWGvJqD9Gjyiea4FRCQeZ2xvK90GLBmQSFPzdK NWXQ== X-Gm-Message-State: APzg51BYctd7VgVVCls3zV0c7wY3WQj/tiwZadevX87ucu4la4d8PHhL xY7J01DNAFj8XFeKs1j8MR4= X-Google-Smtp-Source: ANB0VdZHtqjnqZvaHmj8/RcSttsKyrS5cjytlPOuD4qHPQQpXqBmQqLK4Kx+NT/40qDtKGqFtCsxHg== X-Received: by 2002:a2e:4619:: with SMTP id t25-v6mr8739856lja.96.1535658416275; Thu, 30 Aug 2018 12:46:56 -0700 (PDT) Received: from localhost.localdomain (109-252-90-13.nat.spd-mgts.ru. [109.252.90.13]) by smtp.gmail.com with ESMTPSA id x3-v6sm1381191ljb.25.2018.08.30.12.46.55 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 30 Aug 2018 12:46:55 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Peter De Schrijver , "Rafael J. Wysocki" , Viresh Kumar , Rob Herring Cc: linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v1 5/5] ARM: dts: tegra30: Add CPU Operating Performance Points Date: Thu, 30 Aug 2018 22:43:56 +0300 Message-Id: <20180830194356.14059-6-digetx@gmail.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20180830194356.14059-1-digetx@gmail.com> References: <20180830194356.14059-1-digetx@gmail.com> Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add CPU's Operating Performance Points to the device tree, they are used by the CPUFreq driver and allow to setup thermal throttling for the boards by linking the cooling device (CPU) with thermal sensors via thermal-zones description. Signed-off-by: Dmitry Osipenko --- arch/arm/boot/dts/tegra30.dtsi | 65 ++++++++++++++++++++++++++++++++++ 1 file changed, 65 insertions(+) diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi index 37c4757516d2..5c8098bdfb2a 100644 --- a/arch/arm/boot/dts/tegra30.dtsi +++ b/arch/arm/boot/dts/tegra30.dtsi @@ -980,6 +980,47 @@ status = "disabled"; }; + cpu0_opp_table: opp_table0 { + compatible = "operating-points-v2"; + opp-shared; + + opp@408000000 { + clock-latency-ns = <2000>; + opp-hz = /bits/ 64 <408000000>; + opp-suspend; + }; + + opp@456000000 { + clock-latency-ns = <50000>; + opp-hz = /bits/ 64 <456000000>; + }; + + opp@608000000 { + clock-latency-ns = <50000>; + opp-hz = /bits/ 64 <608000000>; + }; + + opp@760000000 { + clock-latency-ns = <50000>; + opp-hz = /bits/ 64 <760000000>; + }; + + opp@816000000 { + clock-latency-ns = <50000>; + opp-hz = /bits/ 64 <816000000>; + }; + + opp@912000000 { + clock-latency-ns = <50000>; + opp-hz = /bits/ 64 <912000000>; + }; + + opp@1000000000 { + clock-latency-ns = <50000>; + opp-hz = /bits/ 64 <1000000000>; + }; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -988,24 +1029,48 @@ device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <0>; + clocks = <&tegra_car TEGRA30_CLK_PLL_X>, + <&tegra_car TEGRA30_CLK_PLL_P>, + <&tegra_car TEGRA30_CLK_CCLK_G>; + clock-names = "pll_x", "backup", "cpu"; + operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; }; cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <1>; + clocks = <&tegra_car TEGRA30_CLK_PLL_X>, + <&tegra_car TEGRA30_CLK_PLL_P>, + <&tegra_car TEGRA30_CLK_CCLK_G>; + clock-names = "pll_x", "backup", "cpu"; + operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; }; cpu@2 { device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <2>; + clocks = <&tegra_car TEGRA30_CLK_PLL_X>, + <&tegra_car TEGRA30_CLK_PLL_P>, + <&tegra_car TEGRA30_CLK_CCLK_G>; + clock-names = "pll_x", "backup", "cpu"; + operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; }; cpu@3 { device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <3>; + clocks = <&tegra_car TEGRA30_CLK_PLL_X>, + <&tegra_car TEGRA30_CLK_PLL_P>, + <&tegra_car TEGRA30_CLK_CCLK_G>; + clock-names = "pll_x", "backup", "cpu"; + operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; }; };