From patchwork Thu Jun 20 15:00:00 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neil Armstrong X-Patchwork-Id: 11006931 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id B4D7214BB for ; Thu, 20 Jun 2019 15:01:51 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id A4D19287E2 for ; Thu, 20 Jun 2019 15:01:51 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 98FC2287D2; Thu, 20 Jun 2019 15:01:51 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 441DB287E2 for ; Thu, 20 Jun 2019 15:01:51 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=rZtWiav3ZiCt+BXP3kM3a0U9/XAfVowm0Cy3/rmqAoE=; b=lg10joSYoyUpVC v/2QoY92xIsqikvenJpNuIC4CbVY3nXcZu+xPPf8BoKlZFbJ9dkuLFyDZEa03txvW962ONdc+jAjs Yzgj0TqrN6ikyb6el1dHd0Dme+7Z4RuGf4NZHxLhzbjcwUsrdrGNRFmk5waKIk8Zguvprcjzzca1v NpT5J9qs4sBMtVxnmkg11onS28L/3LaAhwdvdbzPbmwhk03eIWnKadMQGCAUudTHsGS6rI8MSIPJ4 GwLuoTZaKcobEBJfyVlXzybdN7QVsnOt29u3DFp3foo6SRulUH0jLSbgAQWO3y5JPGwFSsFpstwQB uJzK5QvuZvGxTk3YIP3g==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92 #3 (Red Hat Linux)) id 1hdyZS-0003nJ-H5; Thu, 20 Jun 2019 15:01:50 +0000 Received: from mail-wm1-x341.google.com ([2a00:1450:4864:20::341]) by bombadil.infradead.org with esmtps (Exim 4.92 #3 (Red Hat Linux)) id 1hdyY3-0003BM-26 for linux-amlogic@lists.infradead.org; Thu, 20 Jun 2019 15:00:25 +0000 Received: by mail-wm1-x341.google.com with SMTP id s3so3409016wms.2 for ; Thu, 20 Jun 2019 08:00:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=LYe7DDXQIL9cgrU/J6+VemHeiSBNByBQZKqrYUm/eeo=; b=SZ6V1yjLoHGVxYhYdXZ8SkshTMpt0KSi4NFSU2/xx/+B0QFCZ/xBQx3++HsNUvz09q f8371/tpFqWte+O1B0mJZDY/m+oXsJXHnkEbSDAAnhNkUO8PnzGSlg4II9sJ3hdcTjOd J9WFwVcXw1Db8/Z5WDM1EbNM6t7arljsdr1fNxbt9cblHpMLQs1tfjOgBG2COUK6/X/6 7OSdVHmMLNv3VZoB/VKHC6lVJjxUgqUX9LPBujDSjUYkKdwn8GW7yX10YVjW2J9tabmQ cir+m7HPer+bOdYUNrInyBmC6SndMtZN6uaPzr+/1Qtquu9r+rrXslmH7bFbqZz3QtqX JdnA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=LYe7DDXQIL9cgrU/J6+VemHeiSBNByBQZKqrYUm/eeo=; b=Z68oM7G3tZVJgKUnZMlK88Z8zNE5ijj5T4v7GF9b+RSJbILa00HiDJykkwTsuTT6EH JsDm2YvEdiWv3HmC+DXz9r/9qTJYJJyQcb3qSxYv0NjaaCJhWwVfSTIYr1tZ6LWx8Or5 Wh5UHRfux2O6ea9NRMDvLSTKfW6TIdCTFpht6GGv60bCC6aVsvgiXRaae+3LOO5aUamg 3eAcETbl73QgKLI6HyEY2l1ecoxU0Outo+2O/3ziimAlRt6ZJIV03kklJxFjJsrL3k9E XhIfd0hJtq/0u4kzKI4YYeoYDs5kGW6mD8MtgU/r3lF3ftSlKYrHYzz5/BvsiJ0vZKdw S8EQ== X-Gm-Message-State: APjAAAW/4/VExjMWzWDOyW0/3ffAIg7egdVAHfw7x5tzd/FR4qPqKbZ8 ow/52xxQYrI1Hh1BrkP4smHp4Q== X-Google-Smtp-Source: APXvYqyNNg0N3Vh+whUhU6uiroJxzDG3nOrILtRfiPwOSwkxjLjsRkVzUds9/M79qG+gl3Xaq9YOhg== X-Received: by 2002:a1c:3587:: with SMTP id c129mr69933wma.90.1561042821614; Thu, 20 Jun 2019 08:00:21 -0700 (PDT) Received: from bender.baylibre.local (lmontsouris-657-1-212-31.w90-63.abo.wanadoo.fr. [90.63.244.31]) by smtp.gmail.com with ESMTPSA id o126sm6802520wmo.1.2019.06.20.08.00.20 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 20 Jun 2019 08:00:20 -0700 (PDT) From: Neil Armstrong To: jbrunet@baylibre.com, khilman@baylibre.com Subject: [RFC/RFT 01/14] pinctrl: meson-g12a: add pwm_a on GPIOE_2 pinmux Date: Thu, 20 Jun 2019 17:00:00 +0200 Message-Id: <20190620150013.13462-2-narmstrong@baylibre.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190620150013.13462-1-narmstrong@baylibre.com> References: <20190620150013.13462-1-narmstrong@baylibre.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190620_080023_097535_E10BDED5 X-CRM114-Status: UNSURE ( 9.82 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-amlogic@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Neil Armstrong , martin.blumenstingl@googlemail.com, linux-kernel@vger.kernel.org, linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org Sender: "linux-amlogic" Errors-To: linux-amlogic-bounces+patchwork-linux-amlogic=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Add the missing pinmux for the pwm_a function on the GPIOE_2 pin. Signed-off-by: Neil Armstrong --- drivers/pinctrl/meson/pinctrl-meson-g12a.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/pinctrl/meson/pinctrl-meson-g12a.c b/drivers/pinctrl/meson/pinctrl-meson-g12a.c index 3475cd7bd2af..582665fd362a 100644 --- a/drivers/pinctrl/meson/pinctrl-meson-g12a.c +++ b/drivers/pinctrl/meson/pinctrl-meson-g12a.c @@ -801,6 +801,9 @@ static const unsigned int remote_ao_input_pins[] = { GPIOAO_5 }; /* ir_out */ static const unsigned int remote_ao_out_pins[] = { GPIOAO_4 }; +/* pwm_a_e */ +static const unsigned int pwm_a_e_pins[] = { GPIOE_2 }; + /* pwm_ao_a */ static const unsigned int pwm_ao_a_pins[] = { GPIOAO_11 }; static const unsigned int pwm_ao_a_hiz_pins[] = { GPIOAO_11 }; @@ -888,6 +891,7 @@ static struct meson_pmx_group meson_g12a_aobus_groups[] = { GROUP(i2c_ao_slave_sda, 3), GROUP(remote_ao_input, 1), GROUP(remote_ao_out, 1), + GROUP(pwm_a_e, 3), GROUP(pwm_ao_a, 3), GROUP(pwm_ao_a_hiz, 2), GROUP(pwm_ao_b, 3), @@ -1192,6 +1196,10 @@ static const char * const remote_ao_out_groups[] = { "remote_ao_out", }; +static const char * const pwm_a_e_groups[] = { + "pwm_a_e", +}; + static const char * const pwm_ao_a_groups[] = { "pwm_ao_a", "pwm_ao_a_hiz", }; @@ -1290,6 +1298,7 @@ static struct meson_pmx_func meson_g12a_aobus_functions[] = { FUNCTION(i2c_ao_slave), FUNCTION(remote_ao_input), FUNCTION(remote_ao_out), + FUNCTION(pwm_a_e), FUNCTION(pwm_ao_a), FUNCTION(pwm_ao_b), FUNCTION(pwm_ao_c), From patchwork Thu Jun 20 15:00:01 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neil Armstrong X-Patchwork-Id: 11006933 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 39DDC14BB for ; Thu, 20 Jun 2019 15:01:56 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 29DBA2880A for ; Thu, 20 Jun 2019 15:01:56 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 1E187287E9; Thu, 20 Jun 2019 15:01:56 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id BAE36287E9 for ; Thu, 20 Jun 2019 15:01:55 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=NHW4CKaHuA0VP4IcuHzl12BguJ+Q/wzcs1dDSSb/H5E=; b=ATVeluWs3yHBn+ jSs4iSD1Kuo/MEygHEQF1s7NSf86nPt0QfJ5ZXdE4WR6EmqE0p55AweRV4+lnQIw9o0+ge5l6FcWx BEvDJUD/fx4/K24PjdoEApEZ/mhOJzaoxwucw4UGEMqhyslSmWMfbKrAEeDJLp8TslkN3R14n/XBe RwAhdons3mVrln+BM26ckP5gwt01uz3JS5pQdZjz9N+FAPg/Bafyd3kna3R+LlXWhuAKsn2q54jkW WdliWtbrpALv/Vozrxu3wU8hO2s7ZocC/RswewiPxrWAAmktoQ5CjtQP5r50NUmQnX9nTmxGRtpKy WXecPE8H81mdy/AaOokw==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92 #3 (Red Hat Linux)) id 1hdyZW-0003qX-Q8; Thu, 20 Jun 2019 15:01:54 +0000 Received: from mail-wm1-x344.google.com ([2a00:1450:4864:20::344]) by bombadil.infradead.org with esmtps (Exim 4.92 #3 (Red Hat Linux)) id 1hdyY3-0003BQ-Qr for linux-amlogic@lists.infradead.org; Thu, 20 Jun 2019 15:00:25 +0000 Received: by mail-wm1-x344.google.com with SMTP id f17so3510289wme.2 for ; Thu, 20 Jun 2019 08:00:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=By2vibD8ed5SvKJiLslQhTFpnxDveNnIcoeXnTW3Wf0=; b=aQf+Iy0nQ0FQz8qVhHiGfNhuG8rZz4Xwl8uToXWSA9d/lK5cjgTn5CJbCx89xFVaUY zhvkAyBr0XVnDpxdj7Os7AjgRlMh3uMWCzy7V7QqvOBDr9m3wKmhkzqxgw02c/jmoZDd pkYbaHjQAE+XlY0OUqp+Tm3cMJVRI8gogX6H21TYpYDn6V0yTXXjkgr6zLhR1ccb/Qur Sy0w50kZ1kuE5m2WZZog4dyJjKa5qzizHbfwjscF+BBrU/SGTkIKzLvD9lbMoJIKyhFF vpshSB7255OsuDSy8vFEEwplNxQtoiCs3MhaVO1BfwvwWxNTNrQGApMOsLU8dmjwWgSg zkrw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=By2vibD8ed5SvKJiLslQhTFpnxDveNnIcoeXnTW3Wf0=; b=Xiv1h42zb1wSNDXChoIZnvsDCDbR/vyx+Ei0fRp+dH+qGCcdVHAEZ//G65U7UQOMHU Tgq5a/EOtvcQHsD72dP2BpQeIWaUna14NfWNcMeKxv3Khj8a6GLTmcpTxy3JWsvV3o1u HOj8WJxVzRx6Kc3tNr6la1lElwuSLgjxzr9hCp4vXItB2gSd61t4I3l5e5MFBpSNtW2w gfQVzeeBbdG1CeeTa/1qjWsZUk5wa0DLELEe4Sk70JO+5hA9oMFeh3Qw2RS/rw+iQExP m75IkVezn7tvEec3sbPb/3ZumnN8QQYo8WEtQy0BLJoSGUODgDPzzsI7enbeG1uoWlnz Fn4w== X-Gm-Message-State: APjAAAXhN+XCD9mceoFWeESL4IsOqayKWoN+iB6DeIzZc4a5GimNrXvL r8fmz16OGIYymT9bEmXOmrfhMeL7G3bvfQ== X-Google-Smtp-Source: APXvYqy4PpfMpc89fPxuLdkIg+PgewzWYS4fDQc+uPktXcbMW544oq2gwfbsa8I3ngP0nFcrvQzD3A== X-Received: by 2002:a1c:f205:: with SMTP id s5mr81645wmc.14.1561042822413; Thu, 20 Jun 2019 08:00:22 -0700 (PDT) Received: from bender.baylibre.local (lmontsouris-657-1-212-31.w90-63.abo.wanadoo.fr. [90.63.244.31]) by smtp.gmail.com with ESMTPSA id o126sm6802520wmo.1.2019.06.20.08.00.21 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 20 Jun 2019 08:00:21 -0700 (PDT) From: Neil Armstrong To: jbrunet@baylibre.com, khilman@baylibre.com Subject: [RFC/RFT 02/14] clk: core: introduce clk_hw_set_parent() Date: Thu, 20 Jun 2019 17:00:01 +0200 Message-Id: <20190620150013.13462-3-narmstrong@baylibre.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190620150013.13462-1-narmstrong@baylibre.com> References: <20190620150013.13462-1-narmstrong@baylibre.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190620_080023_898883_D60FF200 X-CRM114-Status: GOOD ( 10.31 ) X-BeenThere: linux-amlogic@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Neil Armstrong , martin.blumenstingl@googlemail.com, linux-kernel@vger.kernel.org, linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org Sender: "linux-amlogic" Errors-To: linux-amlogic-bounces+patchwork-linux-amlogic=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Introduce the clk_hw_set_parent() provider call to change parent of a clock by using the clk_hw pointers. This eases the clock reparenting from clock rate notifiers and implementing DVFS with simpler code avoiding the boilerplates functions as __clk_lookup(clk_hw_get_name()) then clk_set_parent(). Signed-off-by: Neil Armstrong --- drivers/clk/clk.c | 5 +++++ include/linux/clk-provider.h | 1 + 2 files changed, 6 insertions(+) diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c index aa51756fd4d6..3e98f7dec626 100644 --- a/drivers/clk/clk.c +++ b/drivers/clk/clk.c @@ -2490,6 +2490,11 @@ static int clk_core_set_parent_nolock(struct clk_core *core, return ret; } +int clk_hw_set_parent(struct clk_hw *hw, struct clk_hw *parent) +{ + return clk_core_set_parent_nolock(hw->core, parent->core); +} + /** * clk_set_parent - switch the parent of a mux clk * @clk: the mux clk whose input we are switching diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h index bb6118f79784..8a453380f9a4 100644 --- a/include/linux/clk-provider.h +++ b/include/linux/clk-provider.h @@ -812,6 +812,7 @@ unsigned int clk_hw_get_num_parents(const struct clk_hw *hw); struct clk_hw *clk_hw_get_parent(const struct clk_hw *hw); struct clk_hw *clk_hw_get_parent_by_index(const struct clk_hw *hw, unsigned int index); +int clk_hw_set_parent(struct clk_hw *hw, struct clk_hw *new_parent); unsigned int __clk_get_enable_count(struct clk *clk); unsigned long clk_hw_get_rate(const struct clk_hw *hw); unsigned long __clk_get_flags(struct clk *clk); From patchwork Thu Jun 20 15:00:02 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neil Armstrong X-Patchwork-Id: 11006941 X-Patchwork-Delegate: neil.armstrong@linaro.org Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 1B82C14BB for ; Thu, 20 Jun 2019 15:02:55 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 0BCF22880A for ; Thu, 20 Jun 2019 15:02:55 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id F3FF6287B5; Thu, 20 Jun 2019 15:02:54 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED autolearn=unavailable version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id A8188287D2 for ; Thu, 20 Jun 2019 15:02:54 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=jUA2HnTbIR8loP0SpSPPgWY25HWDQpKDDNlg4gxBpuY=; b=ip0FHaSUBu+Ywz RR2+QcEN/WED2blf3J1UZVd2mIOENJEQZ2t2OGMpkpJamJbVlb7hP934TeBWukkMCBNNYZUMoFhkY XW6mIcHMa/WPUhmEHqhrFNhYkdBF4w/opp7mPH78KK5bgX+7+piS89K30zwz/XXqddxNuFipHt4ju UiRXJIwBZAXCHlOo72Dp1PSqL2BXoTejbPIyGBVux1u54TCGLfoGe4bTmCzcye6yK7QJpgIDNCO4R dZnhULd3ta0ewKi3JdTdiA1Hz0tN/TJd9iI9FFdYlwR8ASPeIUyMlWua6nglLzH+HR6J4tw2PF9Oh 73wTBeLTyY3wYJungoZQ==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92 #3 (Red Hat Linux)) id 1hdyaU-0004fR-3h; Thu, 20 Jun 2019 15:02:54 +0000 Received: from mail-wm1-x341.google.com ([2a00:1450:4864:20::341]) by bombadil.infradead.org with esmtps (Exim 4.92 #3 (Red Hat Linux)) id 1hdyY4-0003Cl-V3 for linux-amlogic@lists.infradead.org; Thu, 20 Jun 2019 15:00:27 +0000 Received: by mail-wm1-x341.google.com with SMTP id x15so3392077wmj.3 for ; Thu, 20 Jun 2019 08:00:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=QF6xtFv2zQ8ZUqjO9Cs7FIQcWQGqk9AuakROnInyaSE=; b=nSkCypdicbMvzFde8ADW9XsWBHulHw3kmRE8NVsSDhiNU9QV9y34VQOdlTCfxpb+sw X+G3BrQTyvHKj7eQwbrTOepLT7WcjxFVj3A5M89EbKEa9Axioltwu5qzvF9jTkZ8edEN Q4Mv0UdlWa6iOfYosGgzfWMkKj04C3u5usJyfcuEUJWvXRSl8+P3pKsmM3bAyuVPVeD2 kxXfFRjwB47pasGLL+C+A5Qa3ZetS84bsJOjMy1giV4UjPZX6uZubJnzIIv4x86hxMUp 3TIBs5eImSfag7zw6MSXwlV0hnojcV3godzRrRFFRaH5+Voy92CeN5TMVbfUTwHPTiO9 DNGw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=QF6xtFv2zQ8ZUqjO9Cs7FIQcWQGqk9AuakROnInyaSE=; b=aOtad0S17XtygpDP4wnxlGYWVvf/DOy3U9clcOHOCGqKucHPsDFdZ9aqFrD/JiafYG aR3HzKSdRvfjAYZce3Rks2y67E6T/tpmiiIGh3XpDFsjs+uSmgezRXzmSLHQD2asSX/k gDpCVVhn5xTFP8WXGWx9KBfkURqubSkM4zvO30kgD7HYuq4WG8S9TkARs+EspmLOD81/ 0vHlIdZPn2UmhgPbf1A0dnXz+XEXLKLEiEiK/dKzGso9/o2Ug19oFA0s/E2bUcZnyupe 0lybRjuKjHnkqVNgofOLbf2fSB5wl6DZ+MLuurA+OW5vXY8Noq1SnRLvBA9rUTaWVutr wVVg== X-Gm-Message-State: APjAAAX0RfY+Ncl8aG76oHcoVAGQjs3CsTBpLRXtv/tr7SdAJbqlv+5L 6doCrnWMmBM7YS6ns8NmSXu9Qg== X-Google-Smtp-Source: APXvYqzjmqHVz8xwAG831JB73JOZR/BWWaiZvTceHova+YlkcqDqCYo2mGzLMMF5bUKcnzoT/ZYDHg== X-Received: by 2002:a1c:3c8a:: with SMTP id j132mr52731wma.172.1561042823556; Thu, 20 Jun 2019 08:00:23 -0700 (PDT) Received: from bender.baylibre.local (lmontsouris-657-1-212-31.w90-63.abo.wanadoo.fr. [90.63.244.31]) by smtp.gmail.com with ESMTPSA id o126sm6802520wmo.1.2019.06.20.08.00.22 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 20 Jun 2019 08:00:22 -0700 (PDT) From: Neil Armstrong To: jbrunet@baylibre.com, khilman@baylibre.com Subject: [RFC/RFT 03/14] clk: meson: regmap: export regmap_div ops functions Date: Thu, 20 Jun 2019 17:00:02 +0200 Message-Id: <20190620150013.13462-4-narmstrong@baylibre.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190620150013.13462-1-narmstrong@baylibre.com> References: <20190620150013.13462-1-narmstrong@baylibre.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190620_080024_998659_69424FEB X-CRM114-Status: GOOD ( 10.21 ) X-BeenThere: linux-amlogic@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Neil Armstrong , martin.blumenstingl@googlemail.com, linux-kernel@vger.kernel.org, linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org Sender: "linux-amlogic" Errors-To: linux-amlogic-bounces+patchwork-linux-amlogic=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP The G12A CPU Clock Postmux divider needs a custom div_set_rate() call. Export the clk_regmap_div_round_rate() and clk_regmap_div_recalc_rate() to be able to override the default clk_regmap_div_set_rate() callback. Signed-off-by: Neil Armstrong --- drivers/clk/meson/clk-regmap.c | 10 ++++++---- drivers/clk/meson/clk-regmap.h | 5 +++++ 2 files changed, 11 insertions(+), 4 deletions(-) diff --git a/drivers/clk/meson/clk-regmap.c b/drivers/clk/meson/clk-regmap.c index dcd1757cc5df..26c8c74a8cf0 100644 --- a/drivers/clk/meson/clk-regmap.c +++ b/drivers/clk/meson/clk-regmap.c @@ -56,8 +56,8 @@ const struct clk_ops clk_regmap_gate_ro_ops = { }; EXPORT_SYMBOL_GPL(clk_regmap_gate_ro_ops); -static unsigned long clk_regmap_div_recalc_rate(struct clk_hw *hw, - unsigned long prate) +unsigned long clk_regmap_div_recalc_rate(struct clk_hw *hw, + unsigned long prate) { struct clk_regmap *clk = to_clk_regmap(hw); struct clk_regmap_div_data *div = clk_get_regmap_div_data(clk); @@ -74,9 +74,10 @@ static unsigned long clk_regmap_div_recalc_rate(struct clk_hw *hw, return divider_recalc_rate(hw, prate, val, div->table, div->flags, div->width); } +EXPORT_SYMBOL_GPL(clk_regmap_div_recalc_rate); -static long clk_regmap_div_round_rate(struct clk_hw *hw, unsigned long rate, - unsigned long *prate) +long clk_regmap_div_round_rate(struct clk_hw *hw, unsigned long rate, + unsigned long *prate) { struct clk_regmap *clk = to_clk_regmap(hw); struct clk_regmap_div_data *div = clk_get_regmap_div_data(clk); @@ -100,6 +101,7 @@ static long clk_regmap_div_round_rate(struct clk_hw *hw, unsigned long rate, return divider_round_rate(hw, rate, prate, div->table, div->width, div->flags); } +EXPORT_SYMBOL_GPL(clk_regmap_div_round_rate); static int clk_regmap_div_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) diff --git a/drivers/clk/meson/clk-regmap.h b/drivers/clk/meson/clk-regmap.h index 1dd0abe3ba91..d22b83fb9bad 100644 --- a/drivers/clk/meson/clk-regmap.h +++ b/drivers/clk/meson/clk-regmap.h @@ -78,6 +78,11 @@ clk_get_regmap_div_data(struct clk_regmap *clk) return (struct clk_regmap_div_data *)clk->data; } +unsigned long clk_regmap_div_recalc_rate(struct clk_hw *hw, + unsigned long prate); +long clk_regmap_div_round_rate(struct clk_hw *hw, unsigned long rate, + unsigned long *prate); + extern const struct clk_ops clk_regmap_divider_ops; extern const struct clk_ops clk_regmap_divider_ro_ops; From patchwork Thu Jun 20 15:00:03 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neil Armstrong X-Patchwork-Id: 11006943 X-Patchwork-Delegate: neil.armstrong@linaro.org Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id F40C014BB for ; Thu, 20 Jun 2019 15:02:57 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id E46401FF83 for ; Thu, 20 Jun 2019 15:02:57 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id D837228818; Thu, 20 Jun 2019 15:02:57 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 6A23228837 for ; Thu, 20 Jun 2019 15:02:57 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=Fw8TTa2Agc/y4tz+ncp1vAW085lTZRV2pIvmshsGX9Q=; b=Ml5p291jTkrAsa Qoqahdb0dfQFwkWYGov9DhhZnAwT+aA/buH0meYmokzSZk45sST3uVuPVBhOTDjf0jsrwBmC+gSgt P95qaJIRb/FQbQUg1wpNG2C95ZPGSDfBHJB9iO8HMfBCt5al2dYL8saFwsST8vMA/fUs8j9LTREH8 r+6ANWeGNnn+vxQIJEMfHdnl4Ur9wgXR9Rc71hjvOHhSmAakLOOXdjbhxEI3hLH0qBY8vXLj3DB23 RAGhCWseYRSl2WAJErJg4I7MHEqH+P7tBSaqfk4L4he9TrUagkp6nvyqh52l8vwoGblafkb1j5O2x LYVzr4Zotd1uTRMc77Tw==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92 #3 (Red Hat Linux)) id 1hdyaW-0004hZ-I5; Thu, 20 Jun 2019 15:02:56 +0000 Received: from mail-wm1-x341.google.com ([2a00:1450:4864:20::341]) by bombadil.infradead.org with esmtps (Exim 4.92 #3 (Red Hat Linux)) id 1hdyY6-0003DL-3N for linux-amlogic@lists.infradead.org; Thu, 20 Jun 2019 15:00:27 +0000 Received: by mail-wm1-x341.google.com with SMTP id g135so3389348wme.4 for ; Thu, 20 Jun 2019 08:00:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=BTgzDGLM/ROVQf5F0ngjAOq0Ibk1O1YBIUhnq8jWYwo=; b=sVjb13m/4Abjxcelx9dk0B2n0Gz48wNUKtEvFQSB6xjURfrJ8rVJunYzemrjIso0+O w1nuS/IZOyrwLZjCU/rKMeGAmxQNp35eHQcKJ4WmO8fHr0xXb4hkFZxWbWAa0yyS02Sj LubycPz4gZcpi6SRA+gvfvmvLemvvjHI/OQK9g8H5FLFwO6XfIDRKtml019xxHEv1iDK 4YDCXsWc+bscbSaOySuV/XfMZobok6vF5h9JuKY43v9AC+RymMy+mStnpkUqOMalExwk Hcuz1qHDK8vh8koQP3omgI0YxWklCijA3BABZFVBnjpZjLUVwxnN1nHEzuzL42GfNpuQ +PVg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=BTgzDGLM/ROVQf5F0ngjAOq0Ibk1O1YBIUhnq8jWYwo=; b=bpCvnXXgC+9hDnC2XlTfRC9ibii4xYJPJV1UCM4bBopzGYFBfQwL2Ve39UdiPP41Qz pRf+eLFgMgr/Ru7NohlKs7tW6qeyt0YKNNdwGT/YbgkO9frYVQWY7k8ARQwbt9cVSjBt QUleMk4Cp2sWr6TeuhIq44WAia9sRckJLj2sL/nCtuDvmh77yy0rBeJ1rBkGCvFF7N/c Kdm1T8L1VatQpXITmpf46UNuFjEn0AmDWciYCpo75dxL9i1qAfMHm9kYzbEeS3nYL2nr TAs4d0pYDGUWb91UlOV1wEVqD3kU5scYmoOy0P5YGOuROWB5IubUdVh/APzI/N5x26mw pD1A== X-Gm-Message-State: APjAAAV0xgbmABl1nIQckHUoZ5MuClQZFQ8XJP3NohKjbWCWio5MIfd2 cZk9pmMdB2jm/hlFukqCLyOKIQ== X-Google-Smtp-Source: APXvYqzMhLhcvV17323ZfwIYU4iAPa4KaU3gRalLKZq0KpBFZBYD+bml5U5CtROED7DHXD+AIE9uOg== X-Received: by 2002:a1c:a952:: with SMTP id s79mr85112wme.28.1561042824707; Thu, 20 Jun 2019 08:00:24 -0700 (PDT) Received: from bender.baylibre.local (lmontsouris-657-1-212-31.w90-63.abo.wanadoo.fr. [90.63.244.31]) by smtp.gmail.com with ESMTPSA id o126sm6802520wmo.1.2019.06.20.08.00.23 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 20 Jun 2019 08:00:23 -0700 (PDT) From: Neil Armstrong To: jbrunet@baylibre.com, khilman@baylibre.com Subject: [RFC/RFT 04/14] clk: meson: eeclk: add setup callback Date: Thu, 20 Jun 2019 17:00:03 +0200 Message-Id: <20190620150013.13462-5-narmstrong@baylibre.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190620150013.13462-1-narmstrong@baylibre.com> References: <20190620150013.13462-1-narmstrong@baylibre.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190620_080026_165240_DB9F9575 X-CRM114-Status: GOOD ( 11.67 ) X-BeenThere: linux-amlogic@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Neil Armstrong , martin.blumenstingl@googlemail.com, linux-kernel@vger.kernel.org, linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org Sender: "linux-amlogic" Errors-To: linux-amlogic-bounces+patchwork-linux-amlogic=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Add a setup() callback in the eeclk structure, to call an optional call() function at end of eeclk probe to setup clocks. It's used for the G12A clock controller to setup the CPU clock notifiers. Signed-off-by: Neil Armstrong --- drivers/clk/meson/meson-eeclk.c | 6 ++++++ drivers/clk/meson/meson-eeclk.h | 1 + 2 files changed, 7 insertions(+) diff --git a/drivers/clk/meson/meson-eeclk.c b/drivers/clk/meson/meson-eeclk.c index 6ba2094be257..81fd2abcd173 100644 --- a/drivers/clk/meson/meson-eeclk.c +++ b/drivers/clk/meson/meson-eeclk.c @@ -61,6 +61,12 @@ int meson_eeclkc_probe(struct platform_device *pdev) } } + if (data->setup) { + ret = data->setup(pdev); + if (ret) + return ret; + } + return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, data->hw_onecell_data); } diff --git a/drivers/clk/meson/meson-eeclk.h b/drivers/clk/meson/meson-eeclk.h index 9ab5d6fa7ccb..c22b57781e3e 100644 --- a/drivers/clk/meson/meson-eeclk.h +++ b/drivers/clk/meson/meson-eeclk.h @@ -20,6 +20,7 @@ struct meson_eeclkc_data { const struct reg_sequence *init_regs; unsigned int init_count; struct clk_hw_onecell_data *hw_onecell_data; + int (*setup)(struct platform_device *pdev); }; int meson_eeclkc_probe(struct platform_device *pdev); From patchwork Thu Jun 20 15:00:04 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neil Armstrong X-Patchwork-Id: 11006951 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 562E9924 for ; Thu, 20 Jun 2019 15:03:34 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 45A8A28474 for ; Thu, 20 Jun 2019 15:03:34 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 39EEA2886E; Thu, 20 Jun 2019 15:03:34 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id DEC7528864 for ; Thu, 20 Jun 2019 15:03:33 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=xiQochgAF0cqjsvHKUh+hgzvhQ6Qh6wiUm7eoTcowx4=; b=beO/XuKCCwQ2It Rh8DQdjBI/T/ZS+7FN0KmXhC1p2YH3EXBe4fXIFuD7P2CChAAh+/sr7zEjwgJRihhxJJtMpv09OcS rM8Emw7jiuZBEXjuW3asmULNIWMx2keEpeE6/ynzgmPzxMBRgQs8dLkvdXTFxr792mkLzr7otzalM 6OkB7wUcJImoAtKrfY/zVNnHha2HWwKKthazNEpBe2zbujc6NDdSJuOZcPXZ0dCNNN6T5EYFBhe1y wJjYGCziuitmIv/Cgky0EwXPI/PEA9VPv/FVtDYawVKTcMtMzu8m7HaCioSpjDKF6jcsQFasAFG+E zeVoEcmyr0xzKYRZ7Rjw==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92 #3 (Red Hat Linux)) id 1hdyb7-0005Eh-2a; Thu, 20 Jun 2019 15:03:33 +0000 Received: from mail-wm1-x343.google.com ([2a00:1450:4864:20::343]) by bombadil.infradead.org with esmtps (Exim 4.92 #3 (Red Hat Linux)) id 1hdyY7-0003EJ-Ns for linux-amlogic@lists.infradead.org; Thu, 20 Jun 2019 15:00:29 +0000 Received: by mail-wm1-x343.google.com with SMTP id z23so3509477wma.4 for ; Thu, 20 Jun 2019 08:00:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=j3tTOMHSiFLp+myEpmzmt12jpkjBS7JqoQLTAOWEufU=; b=BViqmsQ5foznBhU97cwBP9VbZrKPmLd0cybtB6EXw4tXt0WePDI0JEDxWIpG6iSQoi jXseiSDXzCZWAH+hUXGclwQSkU023IAkyoO97sLtfKaqWDVbwm78SitxkIeQKCPp1MTq Ipmp5yuUb24kxuvvJmJE6bdQCpPMwVR0R/yhHa+9DehOo8HgmZUNNP5VCS+9Wb4mVMiT r6C/0RSeH3nc/Ru8H7RLDkhx2opcrmeoWebTXbTKOz52XCEKlt7nv+Vs9z8xYJYpYDBx Tm8ix/M+0NDe8ba6+KDU/X67qmImXaCr3+SnJAhFIlcOZC361jVgiugWBSPWcwG6wJ1Z yvRg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=j3tTOMHSiFLp+myEpmzmt12jpkjBS7JqoQLTAOWEufU=; b=iR256xPcApzQlox6Y4STlCBt0/16k/axu6q+hEdN0xmMJ/zG+CscUvevkA26nmP0uX NtGV8FI2E4VRH1JgqXW9w3/StU1USKuJWCw9TM9i3AJ/orgTXW5SxjnNGH0NiWMAr/0L fZfYnokhFTd9UcEpBwFQ7Os3F8PDBIqfXzg4+cU9KNMlSYOPCkgfp9z19PuHSyQi67Bt gQkNKPJusOWE1kH6n86Lr+eIWPjZvUPT5zvtA7d9qnLkiJV+6lgWqFAFPc0wPn6MkI1w hQaTInwukUhPcfgeKefgREpQIMVOlImt3zBcqo7Ix25mkzO5+SJPby9F9QkuWJvFWWIi dDmA== X-Gm-Message-State: APjAAAWbEOIzm5xRip+sN/vp7Dwy5CRXU2EVnEcvnTImITrP/SFzuJU5 slLQ2ZiEwXGtxP5K4fKO2TCDjA== X-Google-Smtp-Source: APXvYqwW09JatGavk0kfkKK3QI+iY3OiKQCr/aYkFwqWsgEoBB3fJbciAsuTmwz4Yh3rFxMBDCYTQA== X-Received: by 2002:a1c:a7ca:: with SMTP id q193mr60560wme.150.1561042826032; Thu, 20 Jun 2019 08:00:26 -0700 (PDT) Received: from bender.baylibre.local (lmontsouris-657-1-212-31.w90-63.abo.wanadoo.fr. [90.63.244.31]) by smtp.gmail.com with ESMTPSA id o126sm6802520wmo.1.2019.06.20.08.00.24 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 20 Jun 2019 08:00:25 -0700 (PDT) From: Neil Armstrong To: jbrunet@baylibre.com, khilman@baylibre.com Subject: [RFC/RFT 05/14] soc: amlogic: meson-clk-measure: protect measure with a mutex Date: Thu, 20 Jun 2019 17:00:04 +0200 Message-Id: <20190620150013.13462-6-narmstrong@baylibre.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190620150013.13462-1-narmstrong@baylibre.com> References: <20190620150013.13462-1-narmstrong@baylibre.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190620_080027_789725_C808E48E X-CRM114-Status: GOOD ( 11.78 ) X-BeenThere: linux-amlogic@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Neil Armstrong , martin.blumenstingl@googlemail.com, linux-kernel@vger.kernel.org, linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org Sender: "linux-amlogic" Errors-To: linux-amlogic-bounces+patchwork-linux-amlogic=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP In order to protect clock measuring when multiple process asks for a mesure, protect the main measure function with mutexes. Signed-off-by: Neil Armstrong --- drivers/soc/amlogic/meson-clk-measure.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/drivers/soc/amlogic/meson-clk-measure.c b/drivers/soc/amlogic/meson-clk-measure.c index 19d4cbc93a17..c470e24f1dfa 100644 --- a/drivers/soc/amlogic/meson-clk-measure.c +++ b/drivers/soc/amlogic/meson-clk-measure.c @@ -11,6 +11,8 @@ #include #include +static DEFINE_MUTEX(measure_lock); + #define MSR_CLK_DUTY 0x0 #define MSR_CLK_REG0 0x4 #define MSR_CLK_REG1 0x8 @@ -360,6 +362,10 @@ static int meson_measure_id(struct meson_msr_id *clk_msr_id, unsigned int val; int ret; + ret = mutex_lock_interruptible(&measure_lock); + if (ret) + return ret; + regmap_write(priv->regmap, MSR_CLK_REG0, 0); /* Set measurement duration */ @@ -377,8 +383,10 @@ static int meson_measure_id(struct meson_msr_id *clk_msr_id, ret = regmap_read_poll_timeout(priv->regmap, MSR_CLK_REG0, val, !(val & MSR_BUSY), 10, 10000); - if (ret) + if (ret) { + mutex_unlock(&measure_lock); return ret; + } /* Disable */ regmap_update_bits(priv->regmap, MSR_CLK_REG0, MSR_ENABLE, 0); @@ -386,6 +394,8 @@ static int meson_measure_id(struct meson_msr_id *clk_msr_id, /* Get the value in multiple of gate time counts */ regmap_read(priv->regmap, MSR_CLK_REG2, &val); + mutex_unlock(&measure_lock); + if (val >= MSR_VAL_MASK) return -EINVAL; From patchwork Thu Jun 20 15:00:05 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neil Armstrong X-Patchwork-Id: 11006989 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 18ADE924 for ; Thu, 20 Jun 2019 15:03:56 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 09DD028762 for ; Thu, 20 Jun 2019 15:03:56 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id F29E62887A; Thu, 20 Jun 2019 15:03:55 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id A7BBC2885F for ; Thu, 20 Jun 2019 15:03:55 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=Pgto+ejrVDEego03nFylMnhGPGfVjtDVHgyDkkc7xtc=; b=bQFmmNE/03ZRk6 Al30+S/k8uj6PZabg7wrHe5UzlEo0zffVxOPeF48vjgX0PyeifPKwVYqWT1+dPjxPNlBi62ojV7Aj ihHMsDWc23DlhHqSgueSXygltRoFw9tqaMhqpKQQ1x3EAwLRKJtjuIKQm0K6791I6r8VDX1T9rwH4 UJkRjIxPktkuqDird+n7/IR1PqduiXQBV4kU6ztXTFvdg9O5aczxVeAjpviYMqdfdO9ZZBiGpelts GD90rcnYonZL3YotFutn29/W/Lc/YfE3DFLnXtaiQFwEIfHm8p/nvEE98Qwaw9MeSsz15YAMCcjGW PBiVyQPXQuhnn3varLYw==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92 #3 (Red Hat Linux)) id 1hdybS-0005by-P0; Thu, 20 Jun 2019 15:03:54 +0000 Received: from mail-wr1-x442.google.com ([2a00:1450:4864:20::442]) by bombadil.infradead.org with esmtps (Exim 4.92 #3 (Red Hat Linux)) id 1hdyY8-0003FJ-PX for linux-amlogic@lists.infradead.org; Thu, 20 Jun 2019 15:00:30 +0000 Received: by mail-wr1-x442.google.com with SMTP id r16so3351020wrl.11 for ; Thu, 20 Jun 2019 08:00:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=xpe6ifKz7SuClVLyY+/xaKksjob7YtLZf3uysFqr17Y=; b=jiMFQLFWtay0rRLzh+SDB1Dk3ZblEFbfmuUEilGmgJhW7Qz4KUAOuTU5opeNKO7nWt 3n6KP2WFOgh4jIbh0CB9N9m692nzvHycKqZRsgw92Mlfi9t2kewxfiNiBnBP5KlFLxic 9sQlOpOiP0tLfshVxMI7gTuXYR4gXXsG0+JRzy1uCzshnXvPYB+bAiQslnrgRGdC0QLh NMa/SVGZJA10pDNrdq1V2bwTLxwVHMR7VPnGXjDgUXHQq/AVt4tl6/UlAxL1WAvBtdy6 2FmQiQyKUnniVQIQw0J8yoVz/rtn/FkGaG8a51HsMYSRhJKY5QMSsch1/WLNdyKN+7zC oXzw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=xpe6ifKz7SuClVLyY+/xaKksjob7YtLZf3uysFqr17Y=; b=neZOYHhSnZidRXt5teowU0KaJj8pWKoApDT229I5lPsPjgMQnQELk/zewsvvGmU93N oXCPritbW7CIq6hLjwTTWivfniJMqiJggKPBQls/1avzpz0Ye7fWQS3MYbBtj8mq3cH9 wsm4KTY8B5M2LHO5YjcSiAFijYFrqn37EGVSXGUbb63Cgq/2MkOICtiBc6X+Ioij0Pgo CQ4b18fjpIzrd2ylHLrrxuvzC62fjw53iAJ+e5ACtjx27xAlla04uJ/dzDsk3ZTRUrwe ZtelvNDAokDZtArI5T+HrfjobaEeE7P32drenB7hhD+W1qMRPJwBBz+XCwVmGkJ03Ixn o1+w== X-Gm-Message-State: APjAAAXjZ5T90X37RblnrIAYBEazDFoQ5xhbYS6e8LgHcPDLOjUs6iW2 hw50qCfjMVA41kOAFUQmvXj3+g== X-Google-Smtp-Source: APXvYqz/51ebhU5rXHGYChuENG7sgffban6b+i1SauMMfobKCffeLHRbzIr3Iq24zACKZETqEf1n9Q== X-Received: by 2002:adf:f046:: with SMTP id t6mr41634172wro.307.1561042827408; Thu, 20 Jun 2019 08:00:27 -0700 (PDT) Received: from bender.baylibre.local (lmontsouris-657-1-212-31.w90-63.abo.wanadoo.fr. [90.63.244.31]) by smtp.gmail.com with ESMTPSA id o126sm6802520wmo.1.2019.06.20.08.00.26 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 20 Jun 2019 08:00:26 -0700 (PDT) From: Neil Armstrong To: jbrunet@baylibre.com, khilman@baylibre.com Subject: [RFC/RFT 06/14] soc: amlogic: meson-clk-measure: add G12B second cluster cpu clk Date: Thu, 20 Jun 2019 17:00:05 +0200 Message-Id: <20190620150013.13462-7-narmstrong@baylibre.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190620150013.13462-1-narmstrong@baylibre.com> References: <20190620150013.13462-1-narmstrong@baylibre.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190620_080028_828680_B702E3FA X-CRM114-Status: UNSURE ( 8.69 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-amlogic@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Neil Armstrong , martin.blumenstingl@googlemail.com, linux-kernel@vger.kernel.org, linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org Sender: "linux-amlogic" Errors-To: linux-amlogic-bounces+patchwork-linux-amlogic=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Add the G12B second CPU cluster CPU and SYS_PLL measure IDs. These IDs returns 0Hz on G12A. Signed-off-by: Neil Armstrong --- drivers/soc/amlogic/meson-clk-measure.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/soc/amlogic/meson-clk-measure.c b/drivers/soc/amlogic/meson-clk-measure.c index c470e24f1dfa..f09b404b39d3 100644 --- a/drivers/soc/amlogic/meson-clk-measure.c +++ b/drivers/soc/amlogic/meson-clk-measure.c @@ -324,6 +324,8 @@ static struct meson_msr_id clk_msr_g12a[CLK_MSR_MAX] = { CLK_MSR_ID(84, "co_tx"), CLK_MSR_ID(89, "hdmi_todig"), CLK_MSR_ID(90, "hdmitx_sys"), + CLK_MSR_ID(91, "sys_cpub_div16"), + CLK_MSR_ID(92, "sys_pll_cpub_div16"), CLK_MSR_ID(94, "eth_phy_rx"), CLK_MSR_ID(95, "eth_phy_pll"), CLK_MSR_ID(96, "vpu_b"), From patchwork Thu Jun 20 15:00:06 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neil Armstrong X-Patchwork-Id: 11007063 X-Patchwork-Delegate: neil.armstrong@linaro.org Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id AC6B414BB for ; Thu, 20 Jun 2019 15:04:17 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 9B24228857 for ; Thu, 20 Jun 2019 15:04:17 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 8F23A28880; Thu, 20 Jun 2019 15:04:17 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED autolearn=unavailable version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 57C3628857 for ; Thu, 20 Jun 2019 15:04:16 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=pT+QglixDuvKHOD5kSpvMcTLVox9lHngLzNSynpmSKI=; b=dROdNIft55vetL 5SicyYcxncjWG2emWXLwcnmEgjX3kFpg9gdL5FCg8tfuceAbbx3b35ZTThyF7HfCbe72W52+qFX28 T1bL16+JvOBoeJKS4U9jAF1jPJseloqOpXmQQpXzidayInXEqzHAppDUpWpkiHLkEUwoUAdhlXeVM sumoCnoxNwR4LboVn019HCZvWJwbRuvnXVn+NJQ9oQOxm5KNlLxse0kDzlhYtpA1IqA40GCoVpbRE A5lpMQURkizdz38nfdiuugs0n4rDqUOGhG1AeqourkhUdHtYY/6hGmcGXkEzwzqVeYAdSJfqB9iJ7 HvL1sf+ATfNTNWMzlKvg==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92 #3 (Red Hat Linux)) id 1hdybn-00064L-Op; Thu, 20 Jun 2019 15:04:15 +0000 Received: from mail-wr1-x441.google.com ([2a00:1450:4864:20::441]) by bombadil.infradead.org with esmtps (Exim 4.92 #3 (Red Hat Linux)) id 1hdyYA-0003Fj-Ky for linux-amlogic@lists.infradead.org; Thu, 20 Jun 2019 15:00:33 +0000 Received: by mail-wr1-x441.google.com with SMTP id d18so3385380wrs.5 for ; Thu, 20 Jun 2019 08:00:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=lKmOGrps6tEUGlhf4zF+W6R5tZkP1+lE5RNEiYZ1rEc=; b=qGz3D2B+DktJG/SSKywZ+VL2Y6jbz8qJscha8l8+2sykMCUyqM9n+n86cIgJ6ov3QT 9kWNCKYTseu8M9YiHIgilKhGxbyMl9LgRQJY1BvuZfDjqsXHJ4ZTV6sOECMghIwAGQ10 lwkEVW3kihFvbCu7sSOrBbdr9b/3mpFgLQdNPWwENg3Lfyf1txHGDKHbjrhh261kafcZ 0h3oewQFyRCsNTKXxEe21xdXVjzrmG/Ca01rMiIbDcVr/YUzWD1xdSq8OP47/xhfMMBD sNHF2+vQ+TcYbkL6Hwe60RPQapV3yHDFG5WSu+4CgEVR4kq3dWtTWV6vN+8CxOg9JivW 5YJQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=lKmOGrps6tEUGlhf4zF+W6R5tZkP1+lE5RNEiYZ1rEc=; b=OijrWx77Mc+jVxn4IZkQqJ1dsonBIvlZAs6zsXBCoK8CZJMx7JH3Cz1QknXPDhYSUD dUjl87GSav867S+Ocwpu0eppNcX9CryfJvSSDwwbFISJeAGxHKCcefm1DA0eSD9cnTuW QKcaJzOJCEu0BiOxhmT4R3pDTX+gOY+Q6xSawtX05re52zVZ6gFDKYd+aYlcp2Mke2o5 wqmVdYcl8EWytKcxjKwG938oqop745tIeviEnAyLdL9pdmo8AM5jsfGzEM3tohVeaZRi FG02onPckJ+Yk7bKSEA0DFwzEWXy3ppXhH/Ji/eqeTT6GNblh4ZNNOvN/Nxt18TH1H38 O+vg== X-Gm-Message-State: APjAAAVi+JQzk+GOv6CRCvLVjArZymfbPt4IDtYYjBx7scgAfVz/5/sP WuriIckrhz8NN4uBRJs0shFYmg== X-Google-Smtp-Source: APXvYqxHath92L/HcOzG0r+DQmff4/nNqasJnZ6xvZZxrUsCCwWAuasRwhk+n00C6cxtbDfe6XYkCw== X-Received: by 2002:a5d:46c7:: with SMTP id g7mr41307173wrs.215.1561042828590; Thu, 20 Jun 2019 08:00:28 -0700 (PDT) Received: from bender.baylibre.local (lmontsouris-657-1-212-31.w90-63.abo.wanadoo.fr. [90.63.244.31]) by smtp.gmail.com with ESMTPSA id o126sm6802520wmo.1.2019.06.20.08.00.27 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 20 Jun 2019 08:00:28 -0700 (PDT) From: Neil Armstrong To: jbrunet@baylibre.com, khilman@baylibre.com Subject: [RFC/RFT 07/14] clk: meson: g12a: add notifiers to handle cpu clock change Date: Thu, 20 Jun 2019 17:00:06 +0200 Message-Id: <20190620150013.13462-8-narmstrong@baylibre.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190620150013.13462-1-narmstrong@baylibre.com> References: <20190620150013.13462-1-narmstrong@baylibre.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190620_080030_709074_E35DC6EA X-CRM114-Status: GOOD ( 15.51 ) X-BeenThere: linux-amlogic@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Neil Armstrong , martin.blumenstingl@googlemail.com, linux-kernel@vger.kernel.org, linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org Sender: "linux-amlogic" Errors-To: linux-amlogic-bounces+patchwork-linux-amlogic=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP In order to implement clock switching for the CLKID_CPU_CLK and CLKID_CPUB_CLK, notifiers are added on specific points of the clock tree : cpu_clk / cpub_clk | \- cpu_clk_dyn | | \- cpu_clk_premux0 | | |- cpu_clk_postmux0 | | | |- cpu_clk_dyn0_div | | | \- xtal/fclk_div2/fclk_div3 | | \- xtal/fclk_div2/fclk_div3 | \- cpu_clk_premux1 | |- cpu_clk_postmux1 | | |- cpu_clk_dyn1_div | | \- xtal/fclk_div2/fclk_div3 | \- xtal/fclk_div2/fclk_div3 \ sys_pll / sys1_pll This for each cluster, a single one for G12A, two for G12B. Each cpu_clk_premux1 tree is marked as read-only and CLK_SET_RATE_NO_REPARENT, to be used as "parking" clock in a safe clock frequency. A notifier is added on each cpu_clk_premux0 to detech when CCF want to change the frequency of the cpu_clk_dyn tree. In this notifier, the cpu_clk_premux1 tree is configured to use the xtal clock and then the cpu_clk_dyn is switch to cpu_clk_premux1 while CCF updates the cpu_clk_premux0 tree. A notifier is added on each sys_pll/sys1_pll to detect when CCF wants to change the PLL clock source of the cpu_clk. In this notifier, the cpu_clk is switched to cpu_clk_dyn while CCF updates the sys_pll/sys1_pll frequency. A third small notifier is added on each cpu_clk / cpub_clk and cpu_clk_dyn, add a small delay at PRE_RATE_CHANGE/POST_RATE_CHANGE to let the other notofiers change propagate before changing the cpu_clk_premux0 and sys_pll clock trees. This notifier set permits switching the cpu_clk / cpub_clk without any glitches and using a safe parking clock while switching between sub-GHz clocks using the cpu_clk_dyn tree. This setup has been tested and validated on the Amlogic G12A and G12B SoCs running the arm64 cpuburn at [1] and cycling between all the possible cpufreq translations of each cluster and checking the final frequency using the clock-measurer, script at [2]. [1] https://github.com/ssvb/cpuburn-arm/blob/master/cpuburn-a53.S [2] https://gist.github.com/superna9999/d4de964dbc0f84b7d527e1df2ddea25f Signed-off-by: Neil Armstrong --- drivers/clk/meson/g12a.c | 500 ++++++++++++++++++++++++++++++++++++--- 1 file changed, 468 insertions(+), 32 deletions(-) diff --git a/drivers/clk/meson/g12a.c b/drivers/clk/meson/g12a.c index 3c75ef5e4d24..2f3ecbbc98d9 100644 --- a/drivers/clk/meson/g12a.c +++ b/drivers/clk/meson/g12a.c @@ -14,6 +14,7 @@ #include #include #include +#include #include "clk-input.h" #include "clk-mpll.h" @@ -85,16 +86,9 @@ static struct clk_regmap g12a_fixed_pll = { }, }; -/* - * Internal sys pll emulation configuration parameters - */ -static const struct reg_sequence g12a_sys_init_regs[] = { - { .reg = HHI_SYS_PLL_CNTL1, .def = 0x00000000 }, - { .reg = HHI_SYS_PLL_CNTL2, .def = 0x00000000 }, - { .reg = HHI_SYS_PLL_CNTL3, .def = 0x48681c00 }, - { .reg = HHI_SYS_PLL_CNTL4, .def = 0x88770290 }, - { .reg = HHI_SYS_PLL_CNTL5, .def = 0x39272000 }, - { .reg = HHI_SYS_PLL_CNTL6, .def = 0x56540000 }, +static const struct pll_mult_range g12a_sys_pll_mult_range = { + .min = 128, + .max = 250, }; static struct clk_regmap g12a_sys_pll_dco = { @@ -124,14 +118,15 @@ static struct clk_regmap g12a_sys_pll_dco = { .shift = 29, .width = 1, }, - .init_regs = g12a_sys_init_regs, - .init_count = ARRAY_SIZE(g12a_sys_init_regs), + .range = &g12a_sys_pll_mult_range, }, .hw.init = &(struct clk_init_data){ .name = "sys_pll_dco", - .ops = &meson_clk_pll_ro_ops, + .ops = &meson_clk_pll_ops, .parent_names = (const char *[]){ IN_PREFIX "xtal" }, .num_parents = 1, + /* This clock feeds the CPU, avoid disabling it */ + .flags = CLK_IS_CRITICAL, }, }; @@ -144,9 +139,10 @@ static struct clk_regmap g12a_sys_pll = { }, .hw.init = &(struct clk_init_data){ .name = "sys_pll", - .ops = &clk_regmap_divider_ro_ops, + .ops = &clk_regmap_divider_ops, .parent_names = (const char *[]){ "sys_pll_dco" }, .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, }, }; @@ -177,12 +173,15 @@ static struct clk_regmap g12b_sys1_pll_dco = { .shift = 29, .width = 1, }, + .range = &g12a_sys_pll_mult_range, }, .hw.init = &(struct clk_init_data){ .name = "sys1_pll_dco", - .ops = &meson_clk_pll_ro_ops, + .ops = &meson_clk_pll_ops, .parent_names = (const char *[]){ IN_PREFIX "xtal" }, .num_parents = 1, + /* This clock feeds the CPU, avoid disabling it */ + .flags = CLK_IS_CRITICAL, }, }; @@ -195,9 +194,10 @@ static struct clk_regmap g12b_sys1_pll = { }, .hw.init = &(struct clk_init_data){ .name = "sys1_pll", - .ops = &clk_regmap_divider_ro_ops, + .ops = &clk_regmap_divider_ops, .parent_names = (const char *[]){ "sys1_pll_dco" }, .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, }, }; @@ -266,7 +266,7 @@ static struct clk_regmap g12a_cpu_clk_premux0 = { }, .hw.init = &(struct clk_init_data){ .name = "cpu_clk_dyn0_sel", - .ops = &clk_regmap_mux_ro_ops, + .ops = &clk_regmap_mux_ops, .parent_names = (const char *[]){ IN_PREFIX "xtal", "fclk_div2", "fclk_div3" }, @@ -275,6 +275,37 @@ static struct clk_regmap g12a_cpu_clk_premux0 = { }; /* Datasheet names this field as "mux0_divn_tcnt" */ +#define SYS_CPU_DYN_ENABLE BIT(26) + +/* This divider uses bit 26 to take change in account */ +static int g12a_cpu_clk_mux0_div_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + struct clk_regmap *clk = to_clk_regmap(hw); + struct clk_regmap_div_data *div = clk_get_regmap_div_data(clk); + unsigned int val; + int ret; + + ret = divider_get_val(rate, parent_rate, div->table, div->width, + div->flags); + if (ret < 0) + return ret; + + val = (unsigned int)ret << div->shift; + + regmap_update_bits(clk->map, HHI_SYS_CPU_CLK_CNTL0, + SYS_CPU_DYN_ENABLE, SYS_CPU_DYN_ENABLE); + + return regmap_update_bits(clk->map, div->offset, + clk_div_mask(div->width) << div->shift | SYS_CPU_DYN_ENABLE, val); +}; + +const struct clk_ops g12a_cpu_clk_mux0_div_ops = { + .recalc_rate = clk_regmap_div_recalc_rate, + .round_rate = clk_regmap_div_round_rate, + .set_rate = g12a_cpu_clk_mux0_div_set_rate, +}; + static struct clk_regmap g12a_cpu_clk_mux0_div = { .data = &(struct clk_regmap_div_data){ .offset = HHI_SYS_CPU_CLK_CNTL0, @@ -283,9 +314,10 @@ static struct clk_regmap g12a_cpu_clk_mux0_div = { }, .hw.init = &(struct clk_init_data){ .name = "cpu_clk_dyn0_div", - .ops = &clk_regmap_divider_ro_ops, + .ops = &g12a_cpu_clk_mux0_div_ops, .parent_names = (const char *[]){ "cpu_clk_dyn0_sel" }, .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, }, }; @@ -298,10 +330,11 @@ static struct clk_regmap g12a_cpu_clk_postmux0 = { }, .hw.init = &(struct clk_init_data){ .name = "cpu_clk_dyn0", - .ops = &clk_regmap_mux_ro_ops, + .ops = &clk_regmap_mux_ops, .parent_names = (const char *[]){ "cpu_clk_dyn0_sel", "cpu_clk_dyn0_div" }, .num_parents = 2, + .flags = CLK_SET_RATE_PARENT, }, }; @@ -314,11 +347,13 @@ static struct clk_regmap g12a_cpu_clk_premux1 = { }, .hw.init = &(struct clk_init_data){ .name = "cpu_clk_dyn1_sel", - .ops = &clk_regmap_mux_ro_ops, + .ops = &clk_regmap_mux_ops, .parent_names = (const char *[]){ IN_PREFIX "xtal", "fclk_div2", "fclk_div3" }, .num_parents = 3, + /* This sub-tree is used a parking clock */ + .flags = CLK_SET_RATE_NO_REPARENT, }, }; @@ -346,10 +381,12 @@ static struct clk_regmap g12a_cpu_clk_postmux1 = { }, .hw.init = &(struct clk_init_data){ .name = "cpu_clk_dyn1", - .ops = &clk_regmap_mux_ro_ops, + .ops = &clk_regmap_mux_ops, .parent_names = (const char *[]){ "cpu_clk_dyn1_sel", "cpu_clk_dyn1_div" }, .num_parents = 2, + /* This sub-tree is used a parking clock */ + .flags = CLK_SET_RATE_NO_REPARENT, }, }; @@ -362,10 +399,11 @@ static struct clk_regmap g12a_cpu_clk_dyn = { }, .hw.init = &(struct clk_init_data){ .name = "cpu_clk_dyn", - .ops = &clk_regmap_mux_ro_ops, + .ops = &clk_regmap_mux_ops, .parent_names = (const char *[]){ "cpu_clk_dyn0", "cpu_clk_dyn1" }, .num_parents = 2, + .flags = CLK_SET_RATE_PARENT, }, }; @@ -378,10 +416,11 @@ static struct clk_regmap g12a_cpu_clk = { }, .hw.init = &(struct clk_init_data){ .name = "cpu_clk", - .ops = &clk_regmap_mux_ro_ops, + .ops = &clk_regmap_mux_ops, .parent_names = (const char *[]){ "cpu_clk_dyn", "sys_pll" }, .num_parents = 2, + .flags = CLK_SET_RATE_PARENT, }, }; @@ -394,10 +433,11 @@ static struct clk_regmap g12b_cpu_clk = { }, .hw.init = &(struct clk_init_data){ .name = "cpu_clk", - .ops = &clk_regmap_mux_ro_ops, + .ops = &clk_regmap_mux_ops, .parent_names = (const char *[]){ "cpu_clk_dyn", "sys1_pll" }, .num_parents = 2, + .flags = CLK_SET_RATE_PARENT, }, }; @@ -410,7 +450,7 @@ static struct clk_regmap g12b_cpub_clk_premux0 = { }, .hw.init = &(struct clk_init_data){ .name = "cpub_clk_dyn0_sel", - .ops = &clk_regmap_mux_ro_ops, + .ops = &clk_regmap_mux_ops, .parent_names = (const char *[]){ IN_PREFIX "xtal", "fclk_div2", "fclk_div3" }, @@ -418,6 +458,35 @@ static struct clk_regmap g12b_cpub_clk_premux0 = { }, }; +/* This divider uses bit 26 to take change in account */ +static int g12b_cpub_clk_mux0_div_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + struct clk_regmap *clk = to_clk_regmap(hw); + struct clk_regmap_div_data *div = clk_get_regmap_div_data(clk); + unsigned int val; + int ret; + + ret = divider_get_val(rate, parent_rate, div->table, div->width, + div->flags); + if (ret < 0) + return ret; + + val = (unsigned int)ret << div->shift; + + regmap_update_bits(clk->map, HHI_SYS_CPUB_CLK_CNTL, + SYS_CPU_DYN_ENABLE, SYS_CPU_DYN_ENABLE); + + return regmap_update_bits(clk->map, div->offset, + clk_div_mask(div->width) << div->shift | SYS_CPU_DYN_ENABLE, val); +}; + +const struct clk_ops g12b_cpub_clk_mux0_div_ops = { + .recalc_rate = clk_regmap_div_recalc_rate, + .round_rate = clk_regmap_div_round_rate, + .set_rate = g12b_cpub_clk_mux0_div_set_rate, +}; + /* Datasheet names this field as "mux0_divn_tcnt" */ static struct clk_regmap g12b_cpub_clk_mux0_div = { .data = &(struct clk_regmap_div_data){ @@ -427,9 +496,10 @@ static struct clk_regmap g12b_cpub_clk_mux0_div = { }, .hw.init = &(struct clk_init_data){ .name = "cpub_clk_dyn0_div", - .ops = &clk_regmap_divider_ro_ops, + .ops = &g12b_cpub_clk_mux0_div_ops, .parent_names = (const char *[]){ "cpub_clk_dyn0_sel" }, .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, }, }; @@ -442,10 +512,11 @@ static struct clk_regmap g12b_cpub_clk_postmux0 = { }, .hw.init = &(struct clk_init_data){ .name = "cpub_clk_dyn0", - .ops = &clk_regmap_mux_ro_ops, + .ops = &clk_regmap_mux_ops, .parent_names = (const char *[]){ "cpub_clk_dyn0_sel", "cpub_clk_dyn0_div" }, .num_parents = 2, + .flags = CLK_SET_RATE_PARENT, }, }; @@ -458,11 +529,13 @@ static struct clk_regmap g12b_cpub_clk_premux1 = { }, .hw.init = &(struct clk_init_data){ .name = "cpub_clk_dyn1_sel", - .ops = &clk_regmap_mux_ro_ops, + .ops = &clk_regmap_mux_ops, .parent_names = (const char *[]){ IN_PREFIX "xtal", "fclk_div2", "fclk_div3" }, .num_parents = 3, + /* This sub-tree is used a parking clock */ + .flags = CLK_SET_RATE_NO_REPARENT, }, }; @@ -490,10 +563,12 @@ static struct clk_regmap g12b_cpub_clk_postmux1 = { }, .hw.init = &(struct clk_init_data){ .name = "cpub_clk_dyn1", - .ops = &clk_regmap_mux_ro_ops, + .ops = &clk_regmap_mux_ops, .parent_names = (const char *[]){ "cpub_clk_dyn1_sel", "cpub_clk_dyn1_div" }, .num_parents = 2, + /* This sub-tree is used a parking clock */ + .flags = CLK_SET_RATE_NO_REPARENT, }, }; @@ -506,10 +581,11 @@ static struct clk_regmap g12b_cpub_clk_dyn = { }, .hw.init = &(struct clk_init_data){ .name = "cpub_clk_dyn", - .ops = &clk_regmap_mux_ro_ops, + .ops = &clk_regmap_mux_ops, .parent_names = (const char *[]){ "cpub_clk_dyn0", "cpub_clk_dyn1" }, .num_parents = 2, + .flags = CLK_SET_RATE_PARENT, }, }; @@ -522,13 +598,228 @@ static struct clk_regmap g12b_cpub_clk = { }, .hw.init = &(struct clk_init_data){ .name = "cpub_clk", - .ops = &clk_regmap_mux_ro_ops, + .ops = &clk_regmap_mux_ops, .parent_names = (const char *[]){ "cpub_clk_dyn", "sys_pll" }, .num_parents = 2, + .flags = CLK_SET_RATE_PARENT, }, }; +static int g12a_cpu_clk_mux_notifier_cb(struct notifier_block *nb, + unsigned long event, void *data) +{ + switch (event) { + case POST_RATE_CHANGE: + case PRE_RATE_CHANGE: + /* Wait for clock propagation before/after changing the mux */ + udelay(100); + return NOTIFY_OK; + + default: + return NOTIFY_DONE; + } +} + +struct notifier_block g12a_cpu_clk_mux_nb = { + .notifier_call = g12a_cpu_clk_mux_notifier_cb, +}; + +struct g12a_cpu_clk_postmux_nb_data { + struct notifier_block nb; + struct clk_hw *xtal; + struct clk_hw *cpu_clk_dyn; + struct clk_hw *cpu_clk_postmux0; + struct clk_hw *cpu_clk_postmux1; + struct clk_hw *cpu_clk_premux1; +}; + +static int g12a_cpu_clk_postmux_notifier_cb(struct notifier_block *nb, + unsigned long event, void *data) +{ + struct g12a_cpu_clk_postmux_nb_data *nb_data = + container_of(nb, struct g12a_cpu_clk_postmux_nb_data, nb); + + switch (event) { + case PRE_RATE_CHANGE: + /* + * This notifier means cpu_clk_postmux0 clock will be changed + * to feed cpu_clk, this the current path : + * cpu_clk + * \- cpu_clk_dyn + * \- cpu_clk_postmux0 + * \- cpu_clk_muxX_div + * \- cpu_clk_premux0 + * \- fclk_div3 or fclk_div2 + * OR + * \- cpu_clk_premux0 + * \- fclk_div3 or fclk_div2 + */ + + /* Setup cpu_clk_premux1 to xtal */ + clk_hw_set_parent(nb_data->cpu_clk_premux1, + nb_data->xtal); + + /* Setup cpu_clk_postmux1 to bypass divider */ + clk_hw_set_parent(nb_data->cpu_clk_postmux1, + nb_data->cpu_clk_premux1); + + /* Switch to parking clk on cpu_clk_postmux1 */ + clk_hw_set_parent(nb_data->cpu_clk_dyn, + nb_data->cpu_clk_postmux1); + + /* + * Now, cpu_clk is 24MHz in the current path : + * cpu_clk + * \- cpu_clk_dyn + * \- cpu_clk_postmux1 + * \- cpu_clk_premux1 + * \- xtal + */ + + udelay(100); + + return NOTIFY_OK; + + case POST_RATE_CHANGE: + /* + * The cpu_clk_postmux0 has ben updated, now switch back + * cpu_clk_dyn to cpu_clk_postmux0 and take the changes + * in account. + */ + + /* Configure cpu_clk_dyn back to cpu_clk_postmux0 */ + clk_hw_set_parent(nb_data->cpu_clk_dyn, + nb_data->cpu_clk_postmux0); + + /* + * new path : + * cpu_clk + * \- cpu_clk_dyn + * \- cpu_clk_postmux0 + * \- cpu_clk_muxX_div + * \- cpu_clk_premux0 + * \- fclk_div3 or fclk_div2 + * OR + * \- cpu_clk_premux0 + * \- fclk_div3 or fclk_div2 + */ + + udelay(100); + + return NOTIFY_OK; + + default: + return NOTIFY_DONE; + } +} + +static struct g12a_cpu_clk_postmux_nb_data g12a_cpu_clk_postmux0_nb_data = { + .cpu_clk_dyn = &g12a_cpu_clk_dyn.hw, + .cpu_clk_postmux0 = &g12a_cpu_clk_postmux0.hw, + .cpu_clk_postmux1 = &g12a_cpu_clk_postmux1.hw, + .cpu_clk_premux1 = &g12a_cpu_clk_premux1.hw, + .nb.notifier_call = g12a_cpu_clk_postmux_notifier_cb, +}; + +static struct g12a_cpu_clk_postmux_nb_data g12b_cpub_clk_postmux0_nb_data = { + .cpu_clk_dyn = &g12b_cpub_clk_dyn.hw, + .cpu_clk_postmux0 = &g12b_cpub_clk_postmux0.hw, + .cpu_clk_postmux1 = &g12b_cpub_clk_postmux1.hw, + .cpu_clk_premux1 = &g12b_cpub_clk_premux1.hw, + .nb.notifier_call = g12a_cpu_clk_postmux_notifier_cb, +}; + +struct g12a_sys_pll_nb_data { + struct notifier_block nb; + struct clk_hw *sys_pll; + struct clk_hw *cpu_clk; + struct clk_hw *cpu_clk_dyn; +}; + +static int g12a_sys_pll_notifier_cb(struct notifier_block *nb, + unsigned long event, void *data) +{ + struct g12a_sys_pll_nb_data *nb_data = + container_of(nb, struct g12a_sys_pll_nb_data, nb); + + switch (event) { + case PRE_RATE_CHANGE: + /* + * This notifier means sys_pll clock will be changed + * to feed cpu_clk, this the current path : + * cpu_clk + * \- sys_pll + * \- sys_pll_dco + */ + + /* Configure cpu_clk to use cpu_clk_dyn */ + clk_hw_set_parent(nb_data->cpu_clk, + nb_data->cpu_clk_dyn); + + /* + * Now, cpu_clk uses the dyn path + * cpu_clk + * \- cpu_clk_dyn + * \- cpu_clk_dynX + * \- cpu_clk_dynX_sel + * \- cpu_clk_dynX_div + * \- xtal/fclk_div2/fclk_div3 + * \- xtal/fclk_div2/fclk_div3 + */ + + udelay(100); + + return NOTIFY_OK; + + case POST_RATE_CHANGE: + /* + * The sys_pll has ben updated, now switch back cpu_clk to + * sys_pll + */ + + /* Configure cpu_clk to use sys_pll */ + clk_hw_set_parent(nb_data->cpu_clk, + nb_data->sys_pll); + + udelay(100); + + /* new path : + * cpu_clk + * \- sys_pll + * \- sys_pll_dco + */ + + return NOTIFY_OK; + + default: + return NOTIFY_DONE; + } +} + +static struct g12a_sys_pll_nb_data g12a_sys_pll_nb_data = { + .sys_pll = &g12a_sys_pll.hw, + .cpu_clk = &g12a_cpu_clk.hw, + .cpu_clk_dyn = &g12a_cpu_clk_dyn.hw, + .nb.notifier_call = g12a_sys_pll_notifier_cb, +}; + +/* G12B first CPU cluster uses sys1_pll */ +static struct g12a_sys_pll_nb_data g12b_cpu_clk_sys1_pll_nb_data = { + .sys_pll = &g12b_sys1_pll.hw, + .cpu_clk = &g12b_cpu_clk.hw, + .cpu_clk_dyn = &g12a_cpu_clk_dyn.hw, + .nb.notifier_call = g12a_sys_pll_notifier_cb, +}; + +/* G12B second CPU cluster uses sys_pll */ +static struct g12a_sys_pll_nb_data g12b_cpub_clk_sys_pll_nb_data = { + .sys_pll = &g12a_sys_pll.hw, + .cpu_clk = &g12b_cpub_clk.hw, + .cpu_clk_dyn = &g12b_cpub_clk_dyn.hw, + .nb.notifier_call = g12a_sys_pll_notifier_cb, +}; + static struct clk_regmap g12a_cpu_clk_div16_en = { .data = &(struct clk_regmap_gate_data){ .offset = HHI_SYS_CPU_CLK_CNTL1, @@ -3792,18 +4083,163 @@ static const struct reg_sequence g12a_init_regs[] = { { .reg = HHI_MPLL_CNTL0, .def = 0x00000543 }, }; +static int meson_g12a_dvfs_setup_common(struct platform_device *pdev, + struct clk_hw **hws) +{ + const char *notifier_clk_name; + struct clk *notifier_clk; + struct clk_hw *xtal; + int ret; + + xtal = clk_hw_get_parent_by_index(hws[CLKID_CPU_CLK_DYN1_SEL], 0); + + /* Setup clock notifier for cpu_clk_postmux0 */ + g12a_cpu_clk_postmux0_nb_data.xtal = xtal; + notifier_clk_name = clk_hw_get_name(&g12a_cpu_clk_postmux0.hw); + notifier_clk = __clk_lookup(notifier_clk_name); + ret = clk_notifier_register(notifier_clk, + &g12a_cpu_clk_postmux0_nb_data.nb); + if (ret) { + dev_err(&pdev->dev, "failed to register the cpu_clk_postmux0 notifier\n"); + return ret; + } + + /* Setup clock notifier for cpu_clk_dyn mux */ + notifier_clk_name = clk_hw_get_name(&g12a_cpu_clk_dyn.hw); + notifier_clk = __clk_lookup(notifier_clk_name); + ret = clk_notifier_register(notifier_clk, &g12a_cpu_clk_mux_nb); + if (ret) { + dev_err(&pdev->dev, "failed to register the cpu_clk_dyn notifier\n"); + return ret; + } + + return 0; +} + +static int meson_g12b_dvfs_setup(struct platform_device *pdev) +{ + struct clk_hw **hws = g12b_hw_onecell_data.hws; + const char *notifier_clk_name; + struct clk *notifier_clk; + struct clk_hw *xtal; + int ret; + + ret = meson_g12a_dvfs_setup_common(pdev, hws); + if (ret) + return ret; + + xtal = clk_hw_get_parent_by_index(hws[CLKID_CPU_CLK_DYN1_SEL], 0); + + /* Setup clock notifier for cpu_clk mux */ + notifier_clk_name = clk_hw_get_name(&g12b_cpu_clk.hw); + notifier_clk = __clk_lookup(notifier_clk_name); + ret = clk_notifier_register(notifier_clk, &g12a_cpu_clk_mux_nb); + if (ret) { + dev_err(&pdev->dev, "failed to register the cpu_clk notifier\n"); + return ret; + } + + /* Setup clock notifier for sys1_pll */ + notifier_clk_name = clk_hw_get_name(&g12b_sys1_pll.hw); + notifier_clk = __clk_lookup(notifier_clk_name); + ret = clk_notifier_register(notifier_clk, + &g12b_cpu_clk_sys1_pll_nb_data.nb); + if (ret) { + dev_err(&pdev->dev, "failed to register the sys1_pll notifier\n"); + return ret; + } + + /* Add notifiers for the second CPU cluster */ + + /* Setup clock notifier for cpub_clk_postmux0 */ + g12b_cpub_clk_postmux0_nb_data.xtal = xtal; + notifier_clk_name = clk_hw_get_name(&g12b_cpub_clk_postmux0.hw); + notifier_clk = __clk_lookup(notifier_clk_name); + ret = clk_notifier_register(notifier_clk, + &g12b_cpub_clk_postmux0_nb_data.nb); + if (ret) { + dev_err(&pdev->dev, "failed to register the cpub_clk_postmux0 notifier\n"); + return ret; + } + + /* Setup clock notifier for cpub_clk_dyn mux */ + notifier_clk_name = clk_hw_get_name(&g12b_cpub_clk_dyn.hw); + notifier_clk = __clk_lookup(notifier_clk_name); + ret = clk_notifier_register(notifier_clk, &g12a_cpu_clk_mux_nb); + if (ret) { + dev_err(&pdev->dev, "failed to register the cpub_clk_dyn notifier\n"); + return ret; + } + + /* Setup clock notifier for cpub_clk mux */ + notifier_clk_name = clk_hw_get_name(&g12b_cpub_clk.hw); + notifier_clk = __clk_lookup(notifier_clk_name); + ret = clk_notifier_register(notifier_clk, &g12a_cpu_clk_mux_nb); + if (ret) { + dev_err(&pdev->dev, "failed to register the cpub_clk notifier\n"); + return ret; + } + + /* Setup clock notifier for sys_pll */ + notifier_clk_name = clk_hw_get_name(&g12a_sys_pll.hw); + notifier_clk = __clk_lookup(notifier_clk_name); + ret = clk_notifier_register(notifier_clk, + &g12b_cpub_clk_sys_pll_nb_data.nb); + if (ret) { + dev_err(&pdev->dev, "failed to register the sys_pll notifier\n"); + return ret; + } + + return 0; +} + + +static int meson_g12a_dvfs_setup(struct platform_device *pdev) +{ + struct clk_hw **hws = g12a_hw_onecell_data.hws; + const char *notifier_clk_name; + struct clk *notifier_clk; + int ret; + + ret = meson_g12a_dvfs_setup_common(pdev, hws); + if (ret) + return ret; + + /* Setup clock notifier for cpu_clk mux */ + notifier_clk_name = clk_hw_get_name(&g12a_cpu_clk.hw); + notifier_clk = __clk_lookup(notifier_clk_name); + ret = clk_notifier_register(notifier_clk, &g12a_cpu_clk_mux_nb); + if (ret) { + dev_err(&pdev->dev, "failed to register the cpu_clk notifier\n"); + return ret; + } + + /* Setup clock notifier for sys_pll */ + notifier_clk_name = clk_hw_get_name(&g12a_sys_pll.hw); + notifier_clk = __clk_lookup(notifier_clk_name); + ret = clk_notifier_register(notifier_clk, &g12a_sys_pll_nb_data.nb); + if (ret) { + dev_err(&pdev->dev, "failed to register the sys_pll notifier\n"); + return ret; + } + + return 0; +} + static const struct meson_eeclkc_data g12a_clkc_data = { .regmap_clks = g12a_clk_regmaps, .regmap_clk_num = ARRAY_SIZE(g12a_clk_regmaps), .hw_onecell_data = &g12a_hw_onecell_data, .init_regs = g12a_init_regs, .init_count = ARRAY_SIZE(g12a_init_regs), + .setup = meson_g12a_dvfs_setup, }; static const struct meson_eeclkc_data g12b_clkc_data = { .regmap_clks = g12a_clk_regmaps, .regmap_clk_num = ARRAY_SIZE(g12a_clk_regmaps), - .hw_onecell_data = &g12b_hw_onecell_data + .hw_onecell_data = &g12b_hw_onecell_data, + .setup = meson_g12b_dvfs_setup, }; static const struct of_device_id clkc_match_table[] = { From patchwork Thu Jun 20 15:00:07 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neil Armstrong X-Patchwork-Id: 11007067 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 6CD1B924 for ; Thu, 20 Jun 2019 15:04:39 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 5DAD6287E5 for ; Thu, 20 Jun 2019 15:04:39 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 51FFF20502; Thu, 20 Jun 2019 15:04:39 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 04BA1287E5 for ; Thu, 20 Jun 2019 15:04:39 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=DA2oyoFthscE1fBV3TiRY0HofNMTqEHYptBTmy+KpNI=; b=HegsD2IEAnqet8 +1EhsECvzMLDVEqBwyIKvIbT7CUBLhjicIr+FjKwaXm8E8P5fjm9cCfX+qab20cyhwdDANHBiiLO2 PhSBTtf8duyHW49qxufFEUU5GrBgQHxME6/2LCL3qWpizA4DFDjocnt5bN6VbMog1DnpO+2UlfiQd nwtBVx0d3jJnGtmOIpoQO5l0I/IiLOG+OHdtukdZs3kJPx1gxnDnU/dhy5FnoEhK8OfqEKdKeq3/v nEhSCIp0Z9j5+ujhOWV9lmAANOBGktrNuOdk+XMXySalevA0/ztVelVkceYfR/OJQM14yWMZKn+QF nfykS6thkh4kHKwdtSpw==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92 #3 (Red Hat Linux)) id 1hdycA-0006OT-DS; Thu, 20 Jun 2019 15:04:38 +0000 Received: from mail-wr1-x441.google.com ([2a00:1450:4864:20::441]) by bombadil.infradead.org with esmtps (Exim 4.92 #3 (Red Hat Linux)) id 1hdyYA-0003Fo-Pu for linux-amlogic@lists.infradead.org; Thu, 20 Jun 2019 15:00:35 +0000 Received: by mail-wr1-x441.google.com with SMTP id k11so3410338wrl.1 for ; Thu, 20 Jun 2019 08:00:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=lvCQg8fkf4AhMPMA11E/TDsr9RLDhACmfamGvoLo6Us=; b=ZkNBuemC27/s9vbgndDsGwjRRSiLq96YdfPINqqKzDjQn90Qcm8t0Lj58ZfQBZYKGg 8bcR/XvPsILe892VTo0OmoSCiekCJCX3TlbRmHEHJ3vzE9+sGXw+vnKAhBs45P2SI07v e3Oxz+tucuq69krMLV2LUbPRErpWXYbw1Js/nnOYU/94RZS05BAgy3h/bPO6/zfrOwZ4 F7pNiAUgM8QtuJCVp8ilAjUhGe61FLORLA8seVVdFd2cslK6440TD2MBCqoSVTL6xu0X wVzWvyWRK4E0sVAODLvJRbX8E+NbHm9dcASo78JP08wjbXVEPa1TxBSF3Hg3xqEq4xUN RHHA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=lvCQg8fkf4AhMPMA11E/TDsr9RLDhACmfamGvoLo6Us=; b=AbNrh59W8pwGgrh8c3a1bBJQQ6dDWiUcV6kDjhWy7RVihXuAK574R0qyJV0N1TWbUw /qhlWugJ6YRFJY/+55JSLusBANrQ1BOYilIhwwXdKxVQkp3LocAsferhFHrLwpNMVJWj u8VLVf7SxGXQ+kJY3K2d4fQVBfSNZuOVE9VgGLE297Bzc2LrARoIaZlifdqkIdf2/Pdh 09//pbe5UM+YnNODXdHiDhhEouV9uBjSK3OQVZ7b3GcrIQ+Nwh8j0sh1M7qICgdpn+6N rIo9vm2K6sCg6Vmo07S+WAySqDbEqnsaDH3hbtoKen+fxuMfs980r7JxsPUEDmmXxaL/ bq+g== X-Gm-Message-State: APjAAAWZ/FRsTJUAY/5fH2evHHdmYnmOB/oqqL4qbX4BH8//5DlZCqrL Fr9PqiE0qTAtm2zQ3qqW44Kicg== X-Google-Smtp-Source: APXvYqzLYovsxFjf46DbcbhAjqfq5ncPgOBrMCKwL4HgOuGrU6Zszy7/dmR3PIOLGHWu/FGiIBljIQ== X-Received: by 2002:adf:df10:: with SMTP id y16mr4435320wrl.302.1561042829338; Thu, 20 Jun 2019 08:00:29 -0700 (PDT) Received: from bender.baylibre.local (lmontsouris-657-1-212-31.w90-63.abo.wanadoo.fr. [90.63.244.31]) by smtp.gmail.com with ESMTPSA id o126sm6802520wmo.1.2019.06.20.08.00.28 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 20 Jun 2019 08:00:28 -0700 (PDT) From: Neil Armstrong To: jbrunet@baylibre.com, khilman@baylibre.com Subject: [RFC/RFT 08/14] clk: meson: g12a: expose CPUB clock ID for G12B Date: Thu, 20 Jun 2019 17:00:07 +0200 Message-Id: <20190620150013.13462-9-narmstrong@baylibre.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190620150013.13462-1-narmstrong@baylibre.com> References: <20190620150013.13462-1-narmstrong@baylibre.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190620_080030_891945_24C39E89 X-CRM114-Status: UNSURE ( 9.39 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-amlogic@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Neil Armstrong , martin.blumenstingl@googlemail.com, linux-kernel@vger.kernel.org, linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org Sender: "linux-amlogic" Errors-To: linux-amlogic-bounces+patchwork-linux-amlogic=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Expose the CPUB clock id to add DVFS to the second CPU cluster of the Amlogic G12B SoC. Signed-off-by: Neil Armstrong --- include/dt-bindings/clock/g12a-clkc.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/dt-bindings/clock/g12a-clkc.h b/include/dt-bindings/clock/g12a-clkc.h index b6b127e45634..8ccc29ac7a72 100644 --- a/include/dt-bindings/clock/g12a-clkc.h +++ b/include/dt-bindings/clock/g12a-clkc.h @@ -137,5 +137,6 @@ #define CLKID_VDEC_HEVC 207 #define CLKID_VDEC_HEVCF 210 #define CLKID_TS 212 +#define CLKID_CPUB_CLK 224 #endif /* __G12A_CLKC_H */ From patchwork Thu Jun 20 15:00:08 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neil Armstrong X-Patchwork-Id: 11007091 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 0E07214E5 for ; Thu, 20 Jun 2019 15:06:42 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id E43DD2870C for ; Thu, 20 Jun 2019 15:06:41 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id D7240287B5; Thu, 20 Jun 2019 15:06:41 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id E49272870C for ; Thu, 20 Jun 2019 15:06:36 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=O+L4A75dyC62CEMupc1FWNppeTIqSk6t3Ymo2CCs634=; b=oDviHdO0ssbfQn DGoIY803GBg/79ACqPHf3xhcPY8+bRvKpy//j8JasMKnPy04JQV/mi4eYS3hgxs6M3PI8P8r3bu0K dDrABelSLFRmH5Y86XVk2V3AsswqSFRWh1cSRup74Ff92oKMqeat6yMf6sEhFTsqQ6nZrE177G3yP 4i3LpaAmGin7DwPkmqtVBss4MMFnfyD8fgBlMjzMLHqtu+o/pNBXpkD7g2mSuCpMFouuEPcZuTSr2 xqoDefyiFdvHrdxzhhmkkTO58OrAk45T4mwEFgPvjowERxq9BeGHQeNeUDcBHfWGvydKEfXVd49BV atMOQwCaWygqAXkCsB0g==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92 #3 (Red Hat Linux)) id 1hdye3-0000m8-DG; Thu, 20 Jun 2019 15:06:35 +0000 Received: from mail-wr1-x442.google.com ([2a00:1450:4864:20::442]) by bombadil.infradead.org with esmtps (Exim 4.92 #3 (Red Hat Linux)) id 1hdyYD-0003Hl-GD for linux-amlogic@lists.infradead.org; Thu, 20 Jun 2019 15:00:46 +0000 Received: by mail-wr1-x442.google.com with SMTP id f9so3341480wre.12 for ; Thu, 20 Jun 2019 08:00:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=eQkY2dGFw4JhflCUeezs1wtLLvO0l7bkLcOQTL5Omig=; b=yfiZKq2E9uHSYg4WDPputcHmuE9dxgOyXHJj2na1XBNzsZ0Q4SIKhuh9nuymJ/fGdE G0dPWI2Pb574doml/D+exoDqEuHzdCpjduWGDqbjRVEkTqvxOF+B585ANneWZychYfjf 6uXazixCtY6gAJDkT9Myfg25oHcLeDL/Oy+KS1iV+34qm+r39pbR8fXhA1Gn4vV1YwKH xWOKpeLOUEg+tiYj0+UZ1Ly8E3Wus01TiSQXJ1E2NycMJi8zCO/jv8dYdI89VyUNlMkx RM5yujf3fimYpWyc4NUQ30kyJ1bWTuEIEJwfdxzBHIWveW1J9pQzJfnF3bw0OPoHqBJz nIIw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=eQkY2dGFw4JhflCUeezs1wtLLvO0l7bkLcOQTL5Omig=; b=oHtmj0YJS2ulR7wryMWLdUNIZsdI+Mzuy/3sns3Sov35127pUSulyEIsAf1c8QRvV2 dfzaPFX9PU5k4NaBt21Y2eEeEzRYubiFb/+1uz3kkiYtTw4D35MgS5FEWm2q7RlVBYN1 lDwEBsqfP8VgDnZH1/0K703npqSDNmt5aMKdaUUik/aOfoUq3HG+bBhB+OA/POIeXJYr HQkurs2WnnKmgZa2JUsdQLz8rIYduWphx8DJwSDfeLOj5Yj6ZEeCbo/q/FaCzvM6vypV YOv0ZyJ/6vkG3DTFST5dcXVIT+UCKD8qUvOeeRF3fFernvwx8n4UFYmMKWQF/MCLrp5M QJSw== X-Gm-Message-State: APjAAAXTTTPY3Kx1TvMpYK/n7z8XJfxfVl+lxBlX4K6HolyfGF1dytg4 FwIKEbaiksI2n1D3PspCnhqSOA== X-Google-Smtp-Source: APXvYqxBQcMGZDhDOZ8Z5c3oXJmO2eLPnLUEUHJ+ChiQ2bewk5P0lpSuBPm4iPy136eC1yKOd0ChcQ== X-Received: by 2002:a05:6000:11cc:: with SMTP id i12mr34772232wrx.243.1561042830684; Thu, 20 Jun 2019 08:00:30 -0700 (PDT) Received: from bender.baylibre.local (lmontsouris-657-1-212-31.w90-63.abo.wanadoo.fr. [90.63.244.31]) by smtp.gmail.com with ESMTPSA id o126sm6802520wmo.1.2019.06.20.08.00.29 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 20 Jun 2019 08:00:30 -0700 (PDT) From: Neil Armstrong To: jbrunet@baylibre.com, khilman@baylibre.com Subject: [RFC/RFT 09/14] arm64: dts: move common G12A & G12B modes to meson-g12-common.dtsi Date: Thu, 20 Jun 2019 17:00:08 +0200 Message-Id: <20190620150013.13462-10-narmstrong@baylibre.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190620150013.13462-1-narmstrong@baylibre.com> References: <20190620150013.13462-1-narmstrong@baylibre.com> MIME-Version: 1.0 X-BeenThere: linux-amlogic@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Neil Armstrong , martin.blumenstingl@googlemail.com, linux-kernel@vger.kernel.org, linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org Sender: "linux-amlogic" Errors-To: linux-amlogic-bounces+patchwork-linux-amlogic=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP To simplify the representation of differences betweem the G12A and G12B SoCs, move the common nodes into a meson-g12-common.dtsi file and express the CPU nodes and differences in meson-g12a.dtsi and meson-g12b.dtsi. This separation will help for DVFS and future Amlogic SM1 Family support. Signed-off-by: Neil Armstrong --- .../boot/dts/amlogic/meson-g12-common.dtsi | 2456 +++++++++++++++++ arch/arm64/boot/dts/amlogic/meson-g12a.dtsi | 2452 +--------------- arch/arm64/boot/dts/amlogic/meson-g12b.dtsi | 26 +- 3 files changed, 2483 insertions(+), 2451 deletions(-) create mode 100644 arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi diff --git a/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi new file mode 100644 index 000000000000..2baa04303762 --- /dev/null +++ b/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi @@ -0,0 +1,2456 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2018 Amlogic, Inc. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/ { + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + tdmif_a: audio-controller-0 { + compatible = "amlogic,axg-tdm-iface"; + #sound-dai-cells = <0>; + sound-name-prefix = "TDM_A"; + clocks = <&clkc_audio AUD_CLKID_MST_A_MCLK>, + <&clkc_audio AUD_CLKID_MST_A_SCLK>, + <&clkc_audio AUD_CLKID_MST_A_LRCLK>; + clock-names = "mclk", "sclk", "lrclk"; + status = "disabled"; + }; + + tdmif_b: audio-controller-1 { + compatible = "amlogic,axg-tdm-iface"; + #sound-dai-cells = <0>; + sound-name-prefix = "TDM_B"; + clocks = <&clkc_audio AUD_CLKID_MST_B_MCLK>, + <&clkc_audio AUD_CLKID_MST_B_SCLK>, + <&clkc_audio AUD_CLKID_MST_B_LRCLK>; + clock-names = "mclk", "sclk", "lrclk"; + status = "disabled"; + }; + + tdmif_c: audio-controller-2 { + compatible = "amlogic,axg-tdm-iface"; + #sound-dai-cells = <0>; + sound-name-prefix = "TDM_C"; + clocks = <&clkc_audio AUD_CLKID_MST_C_MCLK>, + <&clkc_audio AUD_CLKID_MST_C_SCLK>, + <&clkc_audio AUD_CLKID_MST_C_LRCLK>; + clock-names = "mclk", "sclk", "lrclk"; + status = "disabled"; + }; + + efuse: efuse { + compatible = "amlogic,meson-gxbb-efuse"; + clocks = <&clkc CLKID_EFUSE>; + #address-cells = <1>; + #size-cells = <1>; + read-only; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* 3 MiB reserved for ARM Trusted Firmware (BL31) */ + secmon_reserved: secmon@5000000 { + reg = <0x0 0x05000000 0x0 0x300000>; + no-map; + }; + + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x0 0x38000000>; + alignment = <0x0 0x400000>; + linux,cma-default; + }; + }; + + sm: secure-monitor { + compatible = "amlogic,meson-gxbb-sm"; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + ethmac: ethernet@ff3f0000 { + compatible = "amlogic,meson-axg-dwmac", + "snps,dwmac-3.70a", + "snps,dwmac"; + reg = <0x0 0xff3f0000 0x0 0x10000 + 0x0 0xff634540 0x0 0x8>; + interrupts = ; + interrupt-names = "macirq"; + clocks = <&clkc CLKID_ETH>, + <&clkc CLKID_FCLK_DIV2>, + <&clkc CLKID_MPLL2>; + clock-names = "stmmaceth", "clkin0", "clkin1"; + status = "disabled"; + + mdio0: mdio { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + }; + }; + + apb: bus@ff600000 { + compatible = "simple-bus"; + reg = <0x0 0xff600000 0x0 0x200000>; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x0 0x0 0x0 0xff600000 0x0 0x200000>; + + hdmi_tx: hdmi-tx@0 { + compatible = "amlogic,meson-g12a-dw-hdmi"; + reg = <0x0 0x0 0x0 0x10000>; + interrupts = ; + resets = <&reset RESET_HDMITX_CAPB3>, + <&reset RESET_HDMITX_PHY>, + <&reset RESET_HDMITX>; + reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy"; + clocks = <&clkc CLKID_HDMI>, + <&clkc CLKID_HTX_PCLK>, + <&clkc CLKID_VPU_INTR>; + clock-names = "isfr", "iahb", "venci"; + #address-cells = <1>; + #size-cells = <0>; + #sound-dai-cells = <0>; + status = "disabled"; + + /* VPU VENC Input */ + hdmi_tx_venc_port: port@0 { + reg = <0>; + + hdmi_tx_in: endpoint { + remote-endpoint = <&hdmi_tx_out>; + }; + }; + + /* TMDS Output */ + hdmi_tx_tmds_port: port@1 { + reg = <1>; + }; + }; + + apb_efuse: bus@30000 { + compatible = "simple-bus"; + reg = <0x0 0x30000 0x0 0x2000>; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x0 0x0 0x0 0x30000 0x0 0x2000>; + + hwrng: rng@218 { + compatible = "amlogic,meson-rng"; + reg = <0x0 0x218 0x0 0x4>; + }; + }; + + periphs: bus@34400 { + compatible = "simple-bus"; + reg = <0x0 0x34400 0x0 0x400>; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x0 0x0 0x0 0x34400 0x0 0x400>; + + periphs_pinctrl: pinctrl@40 { + compatible = "amlogic,meson-g12a-periphs-pinctrl"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + gpio: bank@40 { + reg = <0x0 0x40 0x0 0x4c>, + <0x0 0xe8 0x0 0x18>, + <0x0 0x120 0x0 0x18>, + <0x0 0x2c0 0x0 0x40>, + <0x0 0x340 0x0 0x1c>; + reg-names = "gpio", + "pull", + "pull-enable", + "mux", + "ds"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&periphs_pinctrl 0 0 86>; + }; + + cec_ao_a_h_pins: cec_ao_a_h { + mux { + groups = "cec_ao_a_h"; + function = "cec_ao_a_h"; + bias-disable; + }; + }; + + cec_ao_b_h_pins: cec_ao_b_h { + mux { + groups = "cec_ao_b_h"; + function = "cec_ao_b_h"; + bias-disable; + }; + }; + + emmc_pins: emmc { + mux-0 { + groups = "emmc_nand_d0", + "emmc_nand_d1", + "emmc_nand_d2", + "emmc_nand_d3", + "emmc_nand_d4", + "emmc_nand_d5", + "emmc_nand_d6", + "emmc_nand_d7", + "emmc_cmd"; + function = "emmc"; + bias-pull-up; + drive-strength-microamp = <4000>; + }; + + mux-1 { + groups = "emmc_clk"; + function = "emmc"; + bias-disable; + drive-strength-microamp = <4000>; + }; + }; + + emmc_ds_pins: emmc-ds { + mux { + groups = "emmc_nand_ds"; + function = "emmc"; + bias-pull-down; + drive-strength-microamp = <4000>; + }; + }; + + emmc_clk_gate_pins: emmc_clk_gate { + mux { + groups = "BOOT_8"; + function = "gpio_periphs"; + bias-pull-down; + drive-strength-microamp = <4000>; + }; + }; + + hdmitx_ddc_pins: hdmitx_ddc { + mux { + groups = "hdmitx_sda", + "hdmitx_sck"; + function = "hdmitx"; + bias-disable; + drive-strength-microamp = <4000>; + }; + }; + + hdmitx_hpd_pins: hdmitx_hpd { + mux { + groups = "hdmitx_hpd_in"; + function = "hdmitx"; + bias-disable; + }; + }; + + + i2c0_sda_c_pins: i2c0-sda-c { + mux { + groups = "i2c0_sda_c"; + function = "i2c0"; + bias-disable; + drive-strength-microamp = <3000>; + + }; + }; + + i2c0_sck_c_pins: i2c0-sck-c { + mux { + groups = "i2c0_sck_c"; + function = "i2c0"; + bias-disable; + drive-strength-microamp = <3000>; + }; + }; + + i2c0_sda_z0_pins: i2c0-sda-z0 { + mux { + groups = "i2c0_sda_z0"; + function = "i2c0"; + bias-disable; + drive-strength-microamp = <3000>; + }; + }; + + i2c0_sck_z1_pins: i2c0-sck-z1 { + mux { + groups = "i2c0_sck_z1"; + function = "i2c0"; + bias-disable; + drive-strength-microamp = <3000>; + }; + }; + + i2c0_sda_z7_pins: i2c0-sda-z7 { + mux { + groups = "i2c0_sda_z7"; + function = "i2c0"; + bias-disable; + drive-strength-microamp = <3000>; + }; + }; + + i2c0_sda_z8_pins: i2c0-sda-z8 { + mux { + groups = "i2c0_sda_z8"; + function = "i2c0"; + bias-disable; + drive-strength-microamp = <3000>; + }; + }; + + i2c1_sda_x_pins: i2c1-sda-x { + mux { + groups = "i2c1_sda_x"; + function = "i2c1"; + bias-disable; + drive-strength-microamp = <3000>; + }; + }; + + i2c1_sck_x_pins: i2c1-sck-x { + mux { + groups = "i2c1_sck_x"; + function = "i2c1"; + bias-disable; + drive-strength-microamp = <3000>; + }; + }; + + i2c1_sda_h2_pins: i2c1-sda-h2 { + mux { + groups = "i2c1_sda_h2"; + function = "i2c1"; + bias-disable; + drive-strength-microamp = <3000>; + }; + }; + + i2c1_sck_h3_pins: i2c1-sck-h3 { + mux { + groups = "i2c1_sck_h3"; + function = "i2c1"; + bias-disable; + drive-strength-microamp = <3000>; + }; + }; + + i2c1_sda_h6_pins: i2c1-sda-h6 { + mux { + groups = "i2c1_sda_h6"; + function = "i2c1"; + bias-disable; + drive-strength-microamp = <3000>; + }; + }; + + i2c1_sck_h7_pins: i2c1-sck-h7 { + mux { + groups = "i2c1_sck_h7"; + function = "i2c1"; + bias-disable; + drive-strength-microamp = <3000>; + }; + }; + + i2c2_sda_x_pins: i2c2-sda-x { + mux { + groups = "i2c2_sda_x"; + function = "i2c2"; + bias-disable; + drive-strength-microamp = <3000>; + }; + }; + + i2c2_sck_x_pins: i2c2-sck-x { + mux { + groups = "i2c2_sck_x"; + function = "i2c2"; + bias-disable; + drive-strength-microamp = <3000>; + }; + }; + + i2c2_sda_z_pins: i2c2-sda-z { + mux { + groups = "i2c2_sda_z"; + function = "i2c2"; + bias-disable; + drive-strength-microamp = <3000>; + }; + }; + + i2c2_sck_z_pins: i2c2-sck-z { + mux { + groups = "i2c2_sck_z"; + function = "i2c2"; + bias-disable; + drive-strength-microamp = <3000>; + }; + }; + + i2c3_sda_h_pins: i2c3-sda-h { + mux { + groups = "i2c3_sda_h"; + function = "i2c3"; + bias-disable; + drive-strength-microamp = <3000>; + }; + }; + + i2c3_sck_h_pins: i2c3-sck-h { + mux { + groups = "i2c3_sck_h"; + function = "i2c3"; + bias-disable; + drive-strength-microamp = <3000>; + }; + }; + + i2c3_sda_a_pins: i2c3-sda-a { + mux { + groups = "i2c3_sda_a"; + function = "i2c3"; + bias-disable; + drive-strength-microamp = <3000>; + }; + }; + + i2c3_sck_a_pins: i2c3-sck-a { + mux { + groups = "i2c3_sck_a"; + function = "i2c3"; + bias-disable; + drive-strength-microamp = <3000>; + }; + }; + + mclk0_a_pins: mclk0-a { + mux { + groups = "mclk0_a"; + function = "mclk0"; + bias-disable; + drive-strength-microamp = <3000>; + }; + }; + + mclk1_a_pins: mclk1-a { + mux { + groups = "mclk1_a"; + function = "mclk1"; + bias-disable; + drive-strength-microamp = <3000>; + }; + }; + + mclk1_x_pins: mclk1-x { + mux { + groups = "mclk1_x"; + function = "mclk1"; + bias-disable; + drive-strength-microamp = <3000>; + }; + }; + + mclk1_z_pins: mclk1-z { + mux { + groups = "mclk1_z"; + function = "mclk1"; + bias-disable; + drive-strength-microamp = <3000>; + }; + }; + + pdm_din0_a_pins: pdm-din0-a { + mux { + groups = "pdm_din0_a"; + function = "pdm"; + bias-disable; + }; + }; + + pdm_din0_c_pins: pdm-din0-c { + mux { + groups = "pdm_din0_c"; + function = "pdm"; + bias-disable; + }; + }; + + pdm_din0_x_pins: pdm-din0-x { + mux { + groups = "pdm_din0_x"; + function = "pdm"; + bias-disable; + }; + }; + + pdm_din0_z_pins: pdm-din0-z { + mux { + groups = "pdm_din0_z"; + function = "pdm"; + bias-disable; + }; + }; + + pdm_din1_a_pins: pdm-din1-a { + mux { + groups = "pdm_din1_a"; + function = "pdm"; + bias-disable; + }; + }; + + pdm_din1_c_pins: pdm-din1-c { + mux { + groups = "pdm_din1_c"; + function = "pdm"; + bias-disable; + }; + }; + + pdm_din1_x_pins: pdm-din1-x { + mux { + groups = "pdm_din1_x"; + function = "pdm"; + bias-disable; + }; + }; + + pdm_din1_z_pins: pdm-din1-z { + mux { + groups = "pdm_din1_z"; + function = "pdm"; + bias-disable; + }; + }; + + pdm_din2_a_pins: pdm-din2-a { + mux { + groups = "pdm_din2_a"; + function = "pdm"; + bias-disable; + }; + }; + + pdm_din2_c_pins: pdm-din2-c { + mux { + groups = "pdm_din2_c"; + function = "pdm"; + bias-disable; + }; + }; + + pdm_din2_x_pins: pdm-din2-x { + mux { + groups = "pdm_din2_x"; + function = "pdm"; + bias-disable; + }; + }; + + pdm_din2_z_pins: pdm-din2-z { + mux { + groups = "pdm_din2_z"; + function = "pdm"; + bias-disable; + }; + }; + + pdm_din3_a_pins: pdm-din3-a { + mux { + groups = "pdm_din3_a"; + function = "pdm"; + bias-disable; + }; + }; + + pdm_din3_c_pins: pdm-din3-c { + mux { + groups = "pdm_din3_c"; + function = "pdm"; + bias-disable; + }; + }; + + pdm_din3_x_pins: pdm-din3-x { + mux { + groups = "pdm_din3_x"; + function = "pdm"; + bias-disable; + }; + }; + + pdm_din3_z_pins: pdm-din3-z { + mux { + groups = "pdm_din3_z"; + function = "pdm"; + bias-disable; + }; + }; + + pdm_dclk_a_pins: pdm-dclk-a { + mux { + groups = "pdm_dclk_a"; + function = "pdm"; + bias-disable; + drive-strength-microamp = <500>; + }; + }; + + pdm_dclk_c_pins: pdm-dclk-c { + mux { + groups = "pdm_dclk_c"; + function = "pdm"; + bias-disable; + drive-strength-microamp = <500>; + }; + }; + + pdm_dclk_x_pins: pdm-dclk-x { + mux { + groups = "pdm_dclk_x"; + function = "pdm"; + bias-disable; + drive-strength-microamp = <500>; + }; + }; + + pdm_dclk_z_pins: pdm-dclk-z { + mux { + groups = "pdm_dclk_z"; + function = "pdm"; + bias-disable; + drive-strength-microamp = <500>; + }; + }; + + pwm_a_pins: pwm-a { + mux { + groups = "pwm_a"; + function = "pwm_a"; + bias-disable; + }; + }; + + pwm_b_x7_pins: pwm-b-x7 { + mux { + groups = "pwm_b_x7"; + function = "pwm_b"; + bias-disable; + }; + }; + + pwm_b_x19_pins: pwm-b-x19 { + mux { + groups = "pwm_b_x19"; + function = "pwm_b"; + bias-disable; + }; + }; + + pwm_c_c_pins: pwm-c-c { + mux { + groups = "pwm_c_c"; + function = "pwm_c"; + bias-disable; + }; + }; + + pwm_c_x5_pins: pwm-c-x5 { + mux { + groups = "pwm_c_x5"; + function = "pwm_c"; + bias-disable; + }; + }; + + pwm_c_x8_pins: pwm-c-x8 { + mux { + groups = "pwm_c_x8"; + function = "pwm_c"; + bias-disable; + }; + }; + + pwm_d_x3_pins: pwm-d-x3 { + mux { + groups = "pwm_d_x3"; + function = "pwm_d"; + bias-disable; + }; + }; + + pwm_d_x6_pins: pwm-d-x6 { + mux { + groups = "pwm_d_x6"; + function = "pwm_d"; + bias-disable; + }; + }; + + pwm_e_pins: pwm-e { + mux { + groups = "pwm_e"; + function = "pwm_e"; + bias-disable; + }; + }; + + pwm_f_x_pins: pwm-f-x { + mux { + groups = "pwm_f_x"; + function = "pwm_f"; + bias-disable; + }; + }; + + pwm_f_h_pins: pwm-f-h { + mux { + groups = "pwm_f_h"; + function = "pwm_f"; + bias-disable; + }; + }; + + sdcard_c_pins: sdcard_c { + mux-0 { + groups = "sdcard_d0_c", + "sdcard_d1_c", + "sdcard_d2_c", + "sdcard_d3_c", + "sdcard_cmd_c"; + function = "sdcard"; + bias-pull-up; + drive-strength-microamp = <4000>; + }; + + mux-1 { + groups = "sdcard_clk_c"; + function = "sdcard"; + bias-disable; + drive-strength-microamp = <4000>; + }; + }; + + sdcard_clk_gate_c_pins: sdcard_clk_gate_c { + mux { + groups = "GPIOC_4"; + function = "gpio_periphs"; + bias-pull-down; + drive-strength-microamp = <4000>; + }; + }; + + sdcard_z_pins: sdcard_z { + mux-0 { + groups = "sdcard_d0_z", + "sdcard_d1_z", + "sdcard_d2_z", + "sdcard_d3_z", + "sdcard_cmd_z"; + function = "sdcard"; + bias-pull-up; + drive-strength-microamp = <4000>; + }; + + mux-1 { + groups = "sdcard_clk_z"; + function = "sdcard"; + bias-disable; + drive-strength-microamp = <4000>; + }; + }; + + sdcard_clk_gate_z_pins: sdcard_clk_gate_z { + mux { + groups = "GPIOZ_6"; + function = "gpio_periphs"; + bias-pull-down; + drive-strength-microamp = <4000>; + }; + }; + + spdif_in_a10_pins: spdif-in-a10 { + mux { + groups = "spdif_in_a10"; + function = "spdif_in"; + bias-disable; + }; + }; + + spdif_in_a12_pins: spdif-in-a12 { + mux { + groups = "spdif_in_a12"; + function = "spdif_in"; + bias-disable; + }; + }; + + spdif_in_h_pins: spdif-in-h { + mux { + groups = "spdif_in_h"; + function = "spdif_in"; + bias-disable; + }; + }; + + spdif_out_h_pins: spdif-out-h { + mux { + groups = "spdif_out_h"; + function = "spdif_out"; + drive-strength-microamp = <500>; + bias-disable; + }; + }; + + spdif_out_a11_pins: spdif-out-a11 { + mux { + groups = "spdif_out_a11"; + function = "spdif_out"; + drive-strength-microamp = <500>; + bias-disable; + }; + }; + + spdif_out_a13_pins: spdif-out-a13 { + mux { + groups = "spdif_out_a13"; + function = "spdif_out"; + drive-strength-microamp = <500>; + bias-disable; + }; + }; + + tdm_a_din0_pins: tdm-a-din0 { + mux { + groups = "tdm_a_din0"; + function = "tdm_a"; + bias-disable; + }; + }; + + + tdm_a_din1_pins: tdm-a-din1 { + mux { + groups = "tdm_a_din1"; + function = "tdm_a"; + bias-disable; + }; + }; + + tdm_a_dout0_pins: tdm-a-dout0 { + mux { + groups = "tdm_a_dout0"; + function = "tdm_a"; + bias-disable; + drive-strength-microamp = <3000>; + }; + }; + + tdm_a_dout1_pins: tdm-a-dout1 { + mux { + groups = "tdm_a_dout1"; + function = "tdm_a"; + bias-disable; + drive-strength-microamp = <3000>; + }; + }; + + tdm_a_fs_pins: tdm-a-fs { + mux { + groups = "tdm_a_fs"; + function = "tdm_a"; + bias-disable; + drive-strength-microamp = <3000>; + }; + }; + + tdm_a_sclk_pins: tdm-a-sclk { + mux { + groups = "tdm_a_sclk"; + function = "tdm_a"; + bias-disable; + drive-strength-microamp = <3000>; + }; + }; + + tdm_a_slv_fs_pins: tdm-a-slv-fs { + mux { + groups = "tdm_a_slv_fs"; + function = "tdm_a"; + bias-disable; + }; + }; + + + tdm_a_slv_sclk_pins: tdm-a-slv-sclk { + mux { + groups = "tdm_a_slv_sclk"; + function = "tdm_a"; + bias-disable; + }; + }; + + tdm_b_din0_pins: tdm-b-din0 { + mux { + groups = "tdm_b_din0"; + function = "tdm_b"; + bias-disable; + }; + }; + + tdm_b_din1_pins: tdm-b-din1 { + mux { + groups = "tdm_b_din1"; + function = "tdm_b"; + bias-disable; + }; + }; + + tdm_b_din2_pins: tdm-b-din2 { + mux { + groups = "tdm_b_din2"; + function = "tdm_b"; + bias-disable; + }; + }; + + tdm_b_din3_a_pins: tdm-b-din3-a { + mux { + groups = "tdm_b_din3_a"; + function = "tdm_b"; + bias-disable; + }; + }; + + tdm_b_din3_h_pins: tdm-b-din3-h { + mux { + groups = "tdm_b_din3_h"; + function = "tdm_b"; + bias-disable; + }; + }; + + tdm_b_dout0_pins: tdm-b-dout0 { + mux { + groups = "tdm_b_dout0"; + function = "tdm_b"; + bias-disable; + drive-strength-microamp = <3000>; + }; + }; + + tdm_b_dout1_pins: tdm-b-dout1 { + mux { + groups = "tdm_b_dout1"; + function = "tdm_b"; + bias-disable; + drive-strength-microamp = <3000>; + }; + }; + + tdm_b_dout2_pins: tdm-b-dout2 { + mux { + groups = "tdm_b_dout2"; + function = "tdm_b"; + bias-disable; + drive-strength-microamp = <3000>; + }; + }; + + tdm_b_dout3_a_pins: tdm-b-dout3-a { + mux { + groups = "tdm_b_dout3_a"; + function = "tdm_b"; + bias-disable; + drive-strength-microamp = <3000>; + }; + }; + + tdm_b_dout3_h_pins: tdm-b-dout3-h { + mux { + groups = "tdm_b_dout3_h"; + function = "tdm_b"; + bias-disable; + drive-strength-microamp = <3000>; + }; + }; + + tdm_b_fs_pins: tdm-b-fs { + mux { + groups = "tdm_b_fs"; + function = "tdm_b"; + bias-disable; + drive-strength-microamp = <3000>; + }; + }; + + tdm_b_sclk_pins: tdm-b-sclk { + mux { + groups = "tdm_b_sclk"; + function = "tdm_b"; + bias-disable; + drive-strength-microamp = <3000>; + }; + }; + + tdm_b_slv_fs_pins: tdm-b-slv-fs { + mux { + groups = "tdm_b_slv_fs"; + function = "tdm_b"; + bias-disable; + }; + }; + + tdm_b_slv_sclk_pins: tdm-b-slv-sclk { + mux { + groups = "tdm_b_slv_sclk"; + function = "tdm_b"; + bias-disable; + }; + }; + + tdm_c_din0_a_pins: tdm-c-din0-a { + mux { + groups = "tdm_c_din0_a"; + function = "tdm_c"; + bias-disable; + }; + }; + + tdm_c_din0_z_pins: tdm-c-din0-z { + mux { + groups = "tdm_c_din0_z"; + function = "tdm_c"; + bias-disable; + }; + }; + + tdm_c_din1_a_pins: tdm-c-din1-a { + mux { + groups = "tdm_c_din1_a"; + function = "tdm_c"; + bias-disable; + }; + }; + + tdm_c_din1_z_pins: tdm-c-din1-z { + mux { + groups = "tdm_c_din1_z"; + function = "tdm_c"; + bias-disable; + }; + }; + + tdm_c_din2_a_pins: tdm-c-din2-a { + mux { + groups = "tdm_c_din2_a"; + function = "tdm_c"; + bias-disable; + }; + }; + + eth_leds_pins: eth-leds { + mux { + groups = "eth_link_led", + "eth_act_led"; + function = "eth"; + bias-disable; + }; + }; + + eth_pins: eth { + mux { + groups = "eth_mdio", + "eth_mdc", + "eth_rgmii_rx_clk", + "eth_rx_dv", + "eth_rxd0", + "eth_rxd1", + "eth_txen", + "eth_txd0", + "eth_txd1"; + function = "eth"; + drive-strength-microamp = <4000>; + bias-disable; + }; + }; + + eth_rgmii_pins: eth-rgmii { + mux { + groups = "eth_rxd2_rgmii", + "eth_rxd3_rgmii", + "eth_rgmii_tx_clk", + "eth_txd2_rgmii", + "eth_txd3_rgmii"; + function = "eth"; + drive-strength-microamp = <4000>; + bias-disable; + }; + }; + + tdm_c_din2_z_pins: tdm-c-din2-z { + mux { + groups = "tdm_c_din2_z"; + function = "tdm_c"; + bias-disable; + }; + }; + + tdm_c_din3_a_pins: tdm-c-din3-a { + mux { + groups = "tdm_c_din3_a"; + function = "tdm_c"; + bias-disable; + }; + }; + + tdm_c_din3_z_pins: tdm-c-din3-z { + mux { + groups = "tdm_c_din3_z"; + function = "tdm_c"; + bias-disable; + }; + }; + + tdm_c_dout0_a_pins: tdm-c-dout0-a { + mux { + groups = "tdm_c_dout0_a"; + function = "tdm_c"; + bias-disable; + drive-strength-microamp = <3000>; + }; + }; + + tdm_c_dout0_z_pins: tdm-c-dout0-z { + mux { + groups = "tdm_c_dout0_z"; + function = "tdm_c"; + bias-disable; + drive-strength-microamp = <3000>; + }; + }; + + tdm_c_dout1_a_pins: tdm-c-dout1-a { + mux { + groups = "tdm_c_dout1_a"; + function = "tdm_c"; + bias-disable; + drive-strength-microamp = <3000>; + }; + }; + + tdm_c_dout1_z_pins: tdm-c-dout1-z { + mux { + groups = "tdm_c_dout1_z"; + function = "tdm_c"; + bias-disable; + drive-strength-microamp = <3000>; + }; + }; + + tdm_c_dout2_a_pins: tdm-c-dout2-a { + mux { + groups = "tdm_c_dout2_a"; + function = "tdm_c"; + bias-disable; + drive-strength-microamp = <3000>; + }; + }; + + tdm_c_dout2_z_pins: tdm-c-dout2-z { + mux { + groups = "tdm_c_dout2_z"; + function = "tdm_c"; + bias-disable; + drive-strength-microamp = <3000>; + }; + }; + + tdm_c_dout3_a_pins: tdm-c-dout3-a { + mux { + groups = "tdm_c_dout3_a"; + function = "tdm_c"; + bias-disable; + drive-strength-microamp = <3000>; + }; + }; + + tdm_c_dout3_z_pins: tdm-c-dout3-z { + mux { + groups = "tdm_c_dout3_z"; + function = "tdm_c"; + bias-disable; + drive-strength-microamp = <3000>; + }; + }; + + tdm_c_fs_a_pins: tdm-c-fs-a { + mux { + groups = "tdm_c_fs_a"; + function = "tdm_c"; + bias-disable; + drive-strength-microamp = <3000>; + }; + }; + + tdm_c_fs_z_pins: tdm-c-fs-z { + mux { + groups = "tdm_c_fs_z"; + function = "tdm_c"; + bias-disable; + drive-strength-microamp = <3000>; + }; + }; + + tdm_c_sclk_a_pins: tdm-c-sclk-a { + mux { + groups = "tdm_c_sclk_a"; + function = "tdm_c"; + bias-disable; + drive-strength-microamp = <3000>; + }; + }; + + tdm_c_sclk_z_pins: tdm-c-sclk-z { + mux { + groups = "tdm_c_sclk_z"; + function = "tdm_c"; + bias-disable; + drive-strength-microamp = <3000>; + }; + }; + + tdm_c_slv_fs_a_pins: tdm-c-slv-fs-a { + mux { + groups = "tdm_c_slv_fs_a"; + function = "tdm_c"; + bias-disable; + }; + }; + + tdm_c_slv_fs_z_pins: tdm-c-slv-fs-z { + mux { + groups = "tdm_c_slv_fs_z"; + function = "tdm_c"; + bias-disable; + }; + }; + + tdm_c_slv_sclk_a_pins: tdm-c-slv-sclk-a { + mux { + groups = "tdm_c_slv_sclk_a"; + function = "tdm_c"; + bias-disable; + }; + }; + + tdm_c_slv_sclk_z_pins: tdm-c-slv-sclk-z { + mux { + groups = "tdm_c_slv_sclk_z"; + function = "tdm_c"; + bias-disable; + }; + }; + + sdio_pins: sdio { + mux { + groups = "sdio_d0", + "sdio_d1", + "sdio_d2", + "sdio_d3", + "sdio_cmd", + "sdio_clk"; + function = "sdio"; + bias-disable; + drive-strength-microamp = <4000>; + }; + }; + + sdio_clk_gate_pins: sdio_clk_gate { + mux { + groups = "GPIOX_4"; + function = "gpio_periphs"; + bias-pull-down; + drive-strength-microamp = <4000>; + }; + }; + + + uart_a_pins: uart-a { + mux { + groups = "uart_a_tx", + "uart_a_rx"; + function = "uart_a"; + bias-disable; + }; + }; + + uart_a_cts_rts_pins: uart-a-cts-rts { + mux { + groups = "uart_a_cts", + "uart_a_rts"; + function = "uart_a"; + bias-disable; + }; + }; + + uart_b_pins: uart-b { + mux { + groups = "uart_b_tx", + "uart_b_rx"; + function = "uart_b"; + bias-disable; + }; + }; + + uart_c_pins: uart-c { + mux { + groups = "uart_c_tx", + "uart_c_rx"; + function = "uart_c"; + bias-disable; + }; + }; + + uart_c_cts_rts_pins: uart-c-cts-rts { + mux { + groups = "uart_c_cts", + "uart_c_rts"; + function = "uart_c"; + bias-disable; + }; + }; + }; + }; + + usb2_phy0: phy@36000 { + compatible = "amlogic,g12a-usb2-phy"; + reg = <0x0 0x36000 0x0 0x2000>; + clocks = <&xtal>; + clock-names = "xtal"; + resets = <&reset RESET_USB_PHY20>; + reset-names = "phy"; + #phy-cells = <0>; + }; + + dmc: bus@38000 { + compatible = "simple-bus"; + reg = <0x0 0x38000 0x0 0x400>; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x0 0x0 0x0 0x38000 0x0 0x400>; + + canvas: video-lut@48 { + compatible = "amlogic,canvas"; + reg = <0x0 0x48 0x0 0x14>; + }; + }; + + usb2_phy1: phy@3a000 { + compatible = "amlogic,g12a-usb2-phy"; + reg = <0x0 0x3a000 0x0 0x2000>; + clocks = <&xtal>; + clock-names = "xtal"; + resets = <&reset RESET_USB_PHY21>; + reset-names = "phy"; + #phy-cells = <0>; + }; + + hiu: bus@3c000 { + compatible = "simple-bus"; + reg = <0x0 0x3c000 0x0 0x1400>; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x0 0x0 0x0 0x3c000 0x0 0x1400>; + + hhi: system-controller@0 { + compatible = "amlogic,meson-gx-hhi-sysctrl", + "simple-mfd", "syscon"; + reg = <0 0 0 0x400>; + + clkc: clock-controller { + compatible = "amlogic,g12a-clkc"; + #clock-cells = <1>; + clocks = <&xtal>; + clock-names = "xtal"; + }; + }; + + mailbox: mailbox@404 { + compatible = "amlogic,meson-gx-mhu", + "amlogic,meson-gxbb-mhu"; + reg = <0 0x404 0 0x4c>; + interrupts = , + , + ; + clocks = <&clkc_AO CLKID_AO_MAILBOX>; + clock-names = "pclk"; + #mbox-cells = <1>; + }; + }; + + pdm: audio-controller@40000 { + compatible = "amlogic,g12a-pdm", + "amlogic,axg-pdm"; + reg = <0x0 0x40000 0x0 0x34>; + #sound-dai-cells = <0>; + sound-name-prefix = "PDM"; + clocks = <&clkc_audio AUD_CLKID_PDM>, + <&clkc_audio AUD_CLKID_PDM_DCLK>, + <&clkc_audio AUD_CLKID_PDM_SYSCLK>; + clock-names = "pclk", "dclk", "sysclk"; + status = "disabled"; + }; + + audio: bus@42000 { + compatible = "simple-bus"; + reg = <0x0 0x42000 0x0 0x2000>; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x0 0x0 0x0 0x42000 0x0 0x2000>; + + clkc_audio: clock-controller@0 { + status = "disabled"; + compatible = "amlogic,g12a-audio-clkc"; + reg = <0x0 0x0 0x0 0xb4>; + #clock-cells = <1>; + + clocks = <&clkc CLKID_AUDIO>, + <&clkc CLKID_MPLL0>, + <&clkc CLKID_MPLL1>, + <&clkc CLKID_MPLL2>, + <&clkc CLKID_MPLL3>, + <&clkc CLKID_HIFI_PLL>, + <&clkc CLKID_FCLK_DIV3>, + <&clkc CLKID_FCLK_DIV4>, + <&clkc CLKID_GP0_PLL>; + clock-names = "pclk", + "mst_in0", + "mst_in1", + "mst_in2", + "mst_in3", + "mst_in4", + "mst_in5", + "mst_in6", + "mst_in7"; + + resets = <&reset RESET_AUDIO>; + }; + + toddr_a: audio-controller@100 { + compatible = "amlogic,g12a-toddr", + "amlogic,axg-toddr"; + reg = <0x0 0x100 0x0 0x1c>; + #sound-dai-cells = <0>; + sound-name-prefix = "TODDR_A"; + interrupts = ; + clocks = <&clkc_audio AUD_CLKID_TODDR_A>; + resets = <&arb AXG_ARB_TODDR_A>; + status = "disabled"; + }; + + toddr_b: audio-controller@140 { + compatible = "amlogic,g12a-toddr", + "amlogic,axg-toddr"; + reg = <0x0 0x140 0x0 0x1c>; + #sound-dai-cells = <0>; + sound-name-prefix = "TODDR_B"; + interrupts = ; + clocks = <&clkc_audio AUD_CLKID_TODDR_B>; + resets = <&arb AXG_ARB_TODDR_B>; + status = "disabled"; + }; + + toddr_c: audio-controller@180 { + compatible = "amlogic,g12a-toddr", + "amlogic,axg-toddr"; + reg = <0x0 0x180 0x0 0x1c>; + #sound-dai-cells = <0>; + sound-name-prefix = "TODDR_C"; + interrupts = ; + clocks = <&clkc_audio AUD_CLKID_TODDR_C>; + resets = <&arb AXG_ARB_TODDR_C>; + status = "disabled"; + }; + + frddr_a: audio-controller@1c0 { + compatible = "amlogic,g12a-frddr", + "amlogic,axg-frddr"; + reg = <0x0 0x1c0 0x0 0x1c>; + #sound-dai-cells = <0>; + sound-name-prefix = "FRDDR_A"; + interrupts = ; + clocks = <&clkc_audio AUD_CLKID_FRDDR_A>; + resets = <&arb AXG_ARB_FRDDR_A>; + status = "disabled"; + }; + + frddr_b: audio-controller@200 { + compatible = "amlogic,g12a-frddr", + "amlogic,axg-frddr"; + reg = <0x0 0x200 0x0 0x1c>; + #sound-dai-cells = <0>; + sound-name-prefix = "FRDDR_B"; + interrupts = ; + clocks = <&clkc_audio AUD_CLKID_FRDDR_B>; + resets = <&arb AXG_ARB_FRDDR_B>; + status = "disabled"; + }; + + frddr_c: audio-controller@240 { + compatible = "amlogic,g12a-frddr", + "amlogic,axg-frddr"; + reg = <0x0 0x240 0x0 0x1c>; + #sound-dai-cells = <0>; + sound-name-prefix = "FRDDR_C"; + interrupts = ; + clocks = <&clkc_audio AUD_CLKID_FRDDR_C>; + resets = <&arb AXG_ARB_FRDDR_C>; + status = "disabled"; + }; + + arb: reset-controller@280 { + status = "disabled"; + compatible = "amlogic,meson-axg-audio-arb"; + reg = <0x0 0x280 0x0 0x4>; + #reset-cells = <1>; + clocks = <&clkc_audio AUD_CLKID_DDR_ARB>; + }; + + tdmin_a: audio-controller@300 { + compatible = "amlogic,g12a-tdmin", + "amlogic,axg-tdmin"; + reg = <0x0 0x300 0x0 0x40>; + sound-name-prefix = "TDMIN_A"; + clocks = <&clkc_audio AUD_CLKID_TDMIN_A>, + <&clkc_audio AUD_CLKID_TDMIN_A_SCLK>, + <&clkc_audio AUD_CLKID_TDMIN_A_SCLK_SEL>, + <&clkc_audio AUD_CLKID_TDMIN_A_LRCLK>, + <&clkc_audio AUD_CLKID_TDMIN_A_LRCLK>; + clock-names = "pclk", "sclk", "sclk_sel", + "lrclk", "lrclk_sel"; + status = "disabled"; + }; + + tdmin_b: audio-controller@340 { + compatible = "amlogic,g12a-tdmin", + "amlogic,axg-tdmin"; + reg = <0x0 0x340 0x0 0x40>; + sound-name-prefix = "TDMIN_B"; + clocks = <&clkc_audio AUD_CLKID_TDMIN_B>, + <&clkc_audio AUD_CLKID_TDMIN_B_SCLK>, + <&clkc_audio AUD_CLKID_TDMIN_B_SCLK_SEL>, + <&clkc_audio AUD_CLKID_TDMIN_B_LRCLK>, + <&clkc_audio AUD_CLKID_TDMIN_B_LRCLK>; + clock-names = "pclk", "sclk", "sclk_sel", + "lrclk", "lrclk_sel"; + status = "disabled"; + }; + + tdmin_c: audio-controller@380 { + compatible = "amlogic,g12a-tdmin", + "amlogic,axg-tdmin"; + reg = <0x0 0x380 0x0 0x40>; + sound-name-prefix = "TDMIN_C"; + clocks = <&clkc_audio AUD_CLKID_TDMIN_C>, + <&clkc_audio AUD_CLKID_TDMIN_C_SCLK>, + <&clkc_audio AUD_CLKID_TDMIN_C_SCLK_SEL>, + <&clkc_audio AUD_CLKID_TDMIN_C_LRCLK>, + <&clkc_audio AUD_CLKID_TDMIN_C_LRCLK>; + clock-names = "pclk", "sclk", "sclk_sel", + "lrclk", "lrclk_sel"; + status = "disabled"; + }; + + tdmin_lb: audio-controller@3c0 { + compatible = "amlogic,g12a-tdmin", + "amlogic,axg-tdmin"; + reg = <0x0 0x3c0 0x0 0x40>; + sound-name-prefix = "TDMIN_LB"; + clocks = <&clkc_audio AUD_CLKID_TDMIN_LB>, + <&clkc_audio AUD_CLKID_TDMIN_LB_SCLK>, + <&clkc_audio AUD_CLKID_TDMIN_LB_SCLK_SEL>, + <&clkc_audio AUD_CLKID_TDMIN_LB_LRCLK>, + <&clkc_audio AUD_CLKID_TDMIN_LB_LRCLK>; + clock-names = "pclk", "sclk", "sclk_sel", + "lrclk", "lrclk_sel"; + status = "disabled"; + }; + + spdifin: audio-controller@400 { + compatible = "amlogic,g12a-spdifin", + "amlogic,axg-spdifin"; + reg = <0x0 0x400 0x0 0x30>; + #sound-dai-cells = <0>; + sound-name-prefix = "SPDIFIN"; + interrupts = ; + clocks = <&clkc_audio AUD_CLKID_SPDIFIN>, + <&clkc_audio AUD_CLKID_SPDIFIN_CLK>; + clock-names = "pclk", "refclk"; + status = "disabled"; + }; + + spdifout: audio-controller@480 { + compatible = "amlogic,g12a-spdifout", + "amlogic,axg-spdifout"; + reg = <0x0 0x480 0x0 0x50>; + #sound-dai-cells = <0>; + sound-name-prefix = "SPDIFOUT"; + clocks = <&clkc_audio AUD_CLKID_SPDIFOUT>, + <&clkc_audio AUD_CLKID_SPDIFOUT_CLK>; + clock-names = "pclk", "mclk"; + status = "disabled"; + }; + + tdmout_a: audio-controller@500 { + compatible = "amlogic,g12a-tdmout"; + reg = <0x0 0x500 0x0 0x40>; + sound-name-prefix = "TDMOUT_A"; + clocks = <&clkc_audio AUD_CLKID_TDMOUT_A>, + <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK>, + <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK_SEL>, + <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>, + <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>; + clock-names = "pclk", "sclk", "sclk_sel", + "lrclk", "lrclk_sel"; + status = "disabled"; + }; + + tdmout_b: audio-controller@540 { + compatible = "amlogic,g12a-tdmout"; + reg = <0x0 0x540 0x0 0x40>; + sound-name-prefix = "TDMOUT_B"; + clocks = <&clkc_audio AUD_CLKID_TDMOUT_B>, + <&clkc_audio AUD_CLKID_TDMOUT_B_SCLK>, + <&clkc_audio AUD_CLKID_TDMOUT_B_SCLK_SEL>, + <&clkc_audio AUD_CLKID_TDMOUT_B_LRCLK>, + <&clkc_audio AUD_CLKID_TDMOUT_B_LRCLK>; + clock-names = "pclk", "sclk", "sclk_sel", + "lrclk", "lrclk_sel"; + status = "disabled"; + }; + + tdmout_c: audio-controller@580 { + compatible = "amlogic,g12a-tdmout"; + reg = <0x0 0x580 0x0 0x40>; + sound-name-prefix = "TDMOUT_C"; + clocks = <&clkc_audio AUD_CLKID_TDMOUT_C>, + <&clkc_audio AUD_CLKID_TDMOUT_C_SCLK>, + <&clkc_audio AUD_CLKID_TDMOUT_C_SCLK_SEL>, + <&clkc_audio AUD_CLKID_TDMOUT_C_LRCLK>, + <&clkc_audio AUD_CLKID_TDMOUT_C_LRCLK>; + clock-names = "pclk", "sclk", "sclk_sel", + "lrclk", "lrclk_sel"; + status = "disabled"; + }; + + spdifout_b: audio-controller@680 { + compatible = "amlogic,g12a-spdifout", + "amlogic,axg-spdifout"; + reg = <0x0 0x680 0x0 0x50>; + #sound-dai-cells = <0>; + sound-name-prefix = "SPDIFOUT_B"; + clocks = <&clkc_audio AUD_CLKID_SPDIFOUT_B>, + <&clkc_audio AUD_CLKID_SPDIFOUT_B_CLK>; + clock-names = "pclk", "mclk"; + status = "disabled"; + }; + + tohdmitx: audio-controller@744 { + compatible = "amlogic,g12a-tohdmitx"; + reg = <0x0 0x744 0x0 0x4>; + #sound-dai-cells = <1>; + sound-name-prefix = "TOHDMITX"; + status = "disabled"; + }; + }; + + usb3_pcie_phy: phy@46000 { + compatible = "amlogic,g12a-usb3-pcie-phy"; + reg = <0x0 0x46000 0x0 0x2000>; + clocks = <&clkc CLKID_PCIE_PLL>; + clock-names = "ref_clk"; + resets = <&reset RESET_PCIE_PHY>; + reset-names = "phy"; + assigned-clocks = <&clkc CLKID_PCIE_PLL>; + assigned-clock-rates = <100000000>; + #phy-cells = <1>; + }; + + eth_phy: mdio-multiplexer@4c000 { + compatible = "amlogic,g12a-mdio-mux"; + reg = <0x0 0x4c000 0x0 0xa4>; + clocks = <&clkc CLKID_ETH_PHY>, + <&xtal>, + <&clkc CLKID_MPLL_50M>; + clock-names = "pclk", "clkin0", "clkin1"; + mdio-parent-bus = <&mdio0>; + #address-cells = <1>; + #size-cells = <0>; + + ext_mdio: mdio@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + }; + + int_mdio: mdio@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + internal_ephy: ethernet_phy@8 { + compatible = "ethernet-phy-id0180.3301", + "ethernet-phy-ieee802.3-c22"; + interrupts = ; + reg = <8>; + max-speed = <100>; + }; + }; + }; + }; + + aobus: bus@ff800000 { + compatible = "simple-bus"; + reg = <0x0 0xff800000 0x0 0x100000>; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x0 0x0 0x0 0xff800000 0x0 0x100000>; + + rti: sys-ctrl@0 { + compatible = "amlogic,meson-gx-ao-sysctrl", + "simple-mfd", "syscon"; + reg = <0x0 0x0 0x0 0x100>; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x0 0x0 0x0 0x0 0x0 0x100>; + + clkc_AO: clock-controller { + compatible = "amlogic,meson-g12a-aoclkc"; + #clock-cells = <1>; + #reset-cells = <1>; + clocks = <&xtal>, <&clkc CLKID_CLK81>; + clock-names = "xtal", "mpeg-clk"; + }; + + pwrc_vpu: power-controller-vpu { + compatible = "amlogic,meson-g12a-pwrc-vpu"; + #power-domain-cells = <0>; + amlogic,hhi-sysctrl = <&hhi>; + resets = <&reset RESET_VIU>, + <&reset RESET_VENC>, + <&reset RESET_VCBUS>, + <&reset RESET_BT656>, + <&reset RESET_RDMA>, + <&reset RESET_VENCI>, + <&reset RESET_VENCP>, + <&reset RESET_VDAC>, + <&reset RESET_VDI6>, + <&reset RESET_VENCL>, + <&reset RESET_VID_LOCK>; + clocks = <&clkc CLKID_VPU>, + <&clkc CLKID_VAPB>; + clock-names = "vpu", "vapb"; + /* + * VPU clocking is provided by two identical clock paths + * VPU_0 and VPU_1 muxed to a single clock by a glitch + * free mux to safely change frequency while running. + * Same for VAPB but with a final gate after the glitch free mux. + */ + assigned-clocks = <&clkc CLKID_VPU_0_SEL>, + <&clkc CLKID_VPU_0>, + <&clkc CLKID_VPU>, /* Glitch free mux */ + <&clkc CLKID_VAPB_0_SEL>, + <&clkc CLKID_VAPB_0>, + <&clkc CLKID_VAPB_SEL>; /* Glitch free mux */ + assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>, + <0>, /* Do Nothing */ + <&clkc CLKID_VPU_0>, + <&clkc CLKID_FCLK_DIV4>, + <0>, /* Do Nothing */ + <&clkc CLKID_VAPB_0>; + assigned-clock-rates = <0>, /* Do Nothing */ + <666666666>, + <0>, /* Do Nothing */ + <0>, /* Do Nothing */ + <250000000>, + <0>; /* Do Nothing */ + }; + + ao_pinctrl: pinctrl@14 { + compatible = "amlogic,meson-g12a-aobus-pinctrl"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + gpio_ao: bank@14 { + reg = <0x0 0x14 0x0 0x8>, + <0x0 0x1c 0x0 0x8>, + <0x0 0x24 0x0 0x14>; + reg-names = "mux", + "ds", + "gpio"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&ao_pinctrl 0 0 15>; + }; + + i2c_ao_sck_pins: i2c_ao_sck_pins { + mux { + groups = "i2c_ao_sck"; + function = "i2c_ao"; + bias-disable; + drive-strength-microamp = <3000>; + }; + }; + + i2c_ao_sda_pins: i2c_ao_sda { + mux { + groups = "i2c_ao_sda"; + function = "i2c_ao"; + bias-disable; + drive-strength-microamp = <3000>; + }; + }; + + i2c_ao_sck_e_pins: i2c_ao_sck_e { + mux { + groups = "i2c_ao_sck_e"; + function = "i2c_ao"; + bias-disable; + drive-strength-microamp = <3000>; + }; + }; + + i2c_ao_sda_e_pins: i2c_ao_sda_e { + mux { + groups = "i2c_ao_sda_e"; + function = "i2c_ao"; + bias-disable; + drive-strength-microamp = <3000>; + }; + }; + + mclk0_ao_pins: mclk0-ao { + mux { + groups = "mclk0_ao"; + function = "mclk0_ao"; + bias-disable; + drive-strength-microamp = <3000>; + }; + }; + + tdm_ao_b_din0_pins: tdm-ao-b-din0 { + mux { + groups = "tdm_ao_b_din0"; + function = "tdm_ao_b"; + bias-disable; + }; + }; + + spdif_ao_out_pins: spdif-ao-out { + mux { + groups = "spdif_ao_out"; + function = "spdif_ao_out"; + drive-strength-microamp = <500>; + bias-disable; + }; + }; + + tdm_ao_b_din1_pins: tdm-ao-b-din1 { + mux { + groups = "tdm_ao_b_din1"; + function = "tdm_ao_b"; + bias-disable; + }; + }; + + tdm_ao_b_din2_pins: tdm-ao-b-din2 { + mux { + groups = "tdm_ao_b_din2"; + function = "tdm_ao_b"; + bias-disable; + }; + }; + + tdm_ao_b_dout0_pins: tdm-ao-b-dout0 { + mux { + groups = "tdm_ao_b_dout0"; + function = "tdm_ao_b"; + bias-disable; + drive-strength-microamp = <3000>; + }; + }; + + tdm_ao_b_dout1_pins: tdm-ao-b-dout1 { + mux { + groups = "tdm_ao_b_dout1"; + function = "tdm_ao_b"; + bias-disable; + drive-strength-microamp = <3000>; + }; + }; + + tdm_ao_b_dout2_pins: tdm-ao-b-dout2 { + mux { + groups = "tdm_ao_b_dout2"; + function = "tdm_ao_b"; + bias-disable; + drive-strength-microamp = <3000>; + }; + }; + + tdm_ao_b_fs_pins: tdm-ao-b-fs { + mux { + groups = "tdm_ao_b_fs"; + function = "tdm_ao_b"; + bias-disable; + drive-strength-microamp = <3000>; + }; + }; + + tdm_ao_b_sclk_pins: tdm-ao-b-sclk { + mux { + groups = "tdm_ao_b_sclk"; + function = "tdm_ao_b"; + bias-disable; + drive-strength-microamp = <3000>; + }; + }; + + tdm_ao_b_slv_fs_pins: tdm-ao-b-slv-fs { + mux { + groups = "tdm_ao_b_slv_fs"; + function = "tdm_ao_b"; + bias-disable; + }; + }; + + tdm_ao_b_slv_sclk_pins: tdm-ao-b-slv-sclk { + mux { + groups = "tdm_ao_b_slv_sclk"; + function = "tdm_ao_b"; + bias-disable; + }; + }; + + uart_ao_a_pins: uart-a-ao { + mux { + groups = "uart_ao_a_tx", + "uart_ao_a_rx"; + function = "uart_ao_a"; + bias-disable; + }; + }; + + uart_ao_a_cts_rts_pins: uart-ao-a-cts-rts { + mux { + groups = "uart_ao_a_cts", + "uart_ao_a_rts"; + function = "uart_ao_a"; + bias-disable; + }; + }; + + pwm_ao_a_pins: pwm-ao-a { + mux { + groups = "pwm_ao_a"; + function = "pwm_ao_a"; + bias-disable; + }; + }; + + pwm_ao_b_pins: pwm-ao-b { + mux { + groups = "pwm_ao_b"; + function = "pwm_ao_b"; + bias-disable; + }; + }; + + pwm_ao_c_4_pins: pwm-ao-c-4 { + mux { + groups = "pwm_ao_c_4"; + function = "pwm_ao_c"; + bias-disable; + }; + }; + + pwm_ao_c_6_pins: pwm-ao-c-6 { + mux { + groups = "pwm_ao_c_6"; + function = "pwm_ao_c"; + bias-disable; + }; + }; + + pwm_ao_d_5_pins: pwm-ao-d-5 { + mux { + groups = "pwm_ao_d_5"; + function = "pwm_ao_d"; + bias-disable; + }; + }; + + pwm_ao_d_10_pins: pwm-ao-d-10 { + mux { + groups = "pwm_ao_d_10"; + function = "pwm_ao_d"; + bias-disable; + }; + }; + + pwm_ao_d_e_pins: pwm-ao-d-e { + mux { + groups = "pwm_ao_d_e"; + function = "pwm_ao_d"; + }; + }; + + remote_input_ao_pins: remote-input-ao { + mux { + groups = "remote_ao_input"; + function = "remote_ao_input"; + bias-disable; + }; + }; + }; + }; + + cec_AO: cec@100 { + compatible = "amlogic,meson-gx-ao-cec"; + reg = <0x0 0x00100 0x0 0x14>; + interrupts = ; + clocks = <&clkc_AO CLKID_AO_CEC>; + clock-names = "core"; + status = "disabled"; + }; + + sec_AO: ao-secure@140 { + compatible = "amlogic,meson-gx-ao-secure", "syscon"; + reg = <0x0 0x140 0x0 0x140>; + amlogic,has-chip-id; + }; + + cecb_AO: cec@280 { + compatible = "amlogic,meson-g12a-ao-cec"; + reg = <0x0 0x00280 0x0 0x1c>; + interrupts = ; + clocks = <&clkc_AO CLKID_AO_CTS_OSCIN>; + clock-names = "oscin"; + status = "disabled"; + }; + + pwm_AO_cd: pwm@2000 { + compatible = "amlogic,meson-g12a-ao-pwm-cd"; + reg = <0x0 0x2000 0x0 0x20>; + #pwm-cells = <3>; + status = "disabled"; + }; + + uart_AO: serial@3000 { + compatible = "amlogic,meson-gx-uart", + "amlogic,meson-ao-uart"; + reg = <0x0 0x3000 0x0 0x18>; + interrupts = ; + clocks = <&xtal>, <&clkc_AO CLKID_AO_UART>, <&xtal>; + clock-names = "xtal", "pclk", "baud"; + reset = <&clkc_AO RESET_AO_UART>; + status = "disabled"; + }; + + uart_AO_B: serial@4000 { + compatible = "amlogic,meson-gx-uart", + "amlogic,meson-ao-uart"; + reg = <0x0 0x4000 0x0 0x18>; + interrupts = ; + clocks = <&xtal>, <&clkc_AO CLKID_AO_UART2>, <&xtal>; + clock-names = "xtal", "pclk", "baud"; + reset = <&clkc_AO RESET_AO_UART2>; + status = "disabled"; + }; + + i2c_AO: i2c@5000 { + compatible = "amlogic,meson-axg-i2c"; + status = "disabled"; + reg = <0x0 0x05000 0x0 0x20>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clkc CLKID_I2C>; + }; + + pwm_AO_ab: pwm@7000 { + compatible = "amlogic,meson-g12a-ao-pwm-ab"; + reg = <0x0 0x7000 0x0 0x20>; + #pwm-cells = <3>; + status = "disabled"; + }; + + ir: ir@8000 { + compatible = "amlogic,meson-gxbb-ir"; + reg = <0x0 0x8000 0x0 0x20>; + interrupts = ; + status = "disabled"; + }; + + saradc: adc@9000 { + compatible = "amlogic,meson-g12a-saradc", + "amlogic,meson-saradc"; + reg = <0x0 0x9000 0x0 0x48>; + #io-channel-cells = <1>; + interrupts = ; + clocks = <&xtal>, + <&clkc_AO CLKID_AO_SAR_ADC>, + <&clkc_AO CLKID_AO_SAR_ADC_CLK>, + <&clkc_AO CLKID_AO_SAR_ADC_SEL>; + clock-names = "clkin", "core", "adc_clk", "adc_sel"; + status = "disabled"; + }; + }; + + vdec: video-decoder@ff620000 { + compatible = "amlogic,g12a-vdec"; + reg = <0x0 0xff620000 0x0 0x10000>, + <0x0 0xffd0e180 0x0 0xe4>; + reg-names = "dos", "esparser"; + + interrupts = , + ; + interrupt-names = "vdec", "esparser"; + + amlogic,ao-sysctrl = <&rti>; + amlogic,canvas = <&canvas>; + + clocks = <&clkc CLKID_PARSER>, + <&clkc CLKID_DOS>, + <&clkc CLKID_VDEC_1>, + <&clkc CLKID_VDEC_HEVC>, + <&clkc CLKID_VDEC_HEVCF>; + clock-names = "dos_parser", "dos", "vdec_1", "vdec_hevc", "vdec_hevcf"; + resets = <&reset RESET_PARSER>; + reset-names = "esparser"; + }; + + vpu: vpu@ff900000 { + compatible = "amlogic,meson-g12a-vpu"; + reg = <0x0 0xff900000 0x0 0x100000>, + <0x0 0xff63c000 0x0 0x1000>; + reg-names = "vpu", "hhi"; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + amlogic,canvas = <&canvas>; + power-domains = <&pwrc_vpu>; + + /* CVBS VDAC output port */ + cvbs_vdac_port: port@0 { + reg = <0>; + }; + + /* HDMI-TX output port */ + hdmi_tx_port: port@1 { + reg = <1>; + + hdmi_tx_out: endpoint { + remote-endpoint = <&hdmi_tx_in>; + }; + }; + }; + + sram: sram@fffc0000 { + compatible = "mmio-sram"; + reg = <0x0 0xfffc0000 0x0 0x20000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x0 0xfffc0000 0x20000>; + + cpu_scp_lpri: scp-shmem@13000 { + compatible = "amlogic,meson-axg-scp-shmem"; + reg = <0x13000 0x400>; + }; + + cpu_scp_hpri: scp-shmem@13400 { + compatible = "amlogic,meson-axg-scp-shmem"; + reg = <0x13400 0x400>; + }; + }; + + gic: interrupt-controller@ffc01000 { + compatible = "arm,gic-400"; + reg = <0x0 0xffc01000 0 0x1000>, + <0x0 0xffc02000 0 0x2000>, + <0x0 0xffc04000 0 0x2000>, + <0x0 0xffc06000 0 0x2000>; + interrupt-controller; + interrupts = ; + #interrupt-cells = <3>; + #address-cells = <0>; + }; + + cbus: bus@ffd00000 { + compatible = "simple-bus"; + reg = <0x0 0xffd00000 0x0 0x100000>; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x100000>; + + reset: reset-controller@1004 { + compatible = "amlogic,meson-g12a-reset", + "amlogic,meson-axg-reset"; + reg = <0x0 0x1004 0x0 0x9c>; + #reset-cells = <1>; + }; + + pwm_ef: pwm@19000 { + compatible = "amlogic,meson-g12a-ee-pwm"; + reg = <0x0 0x19000 0x0 0x20>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm_cd: pwm@1a000 { + compatible = "amlogic,meson-g12a-ee-pwm"; + reg = <0x0 0x1a000 0x0 0x20>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm_ab: pwm@1b000 { + compatible = "amlogic,meson-g12a-ee-pwm"; + reg = <0x0 0x1b000 0x0 0x20>; + #pwm-cells = <3>; + status = "disabled"; + }; + + i2c3: i2c@1c000 { + compatible = "amlogic,meson-axg-i2c"; + status = "disabled"; + reg = <0x0 0x1c000 0x0 0x20>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clkc CLKID_I2C>; + }; + + i2c2: i2c@1d000 { + compatible = "amlogic,meson-axg-i2c"; + status = "disabled"; + reg = <0x0 0x1d000 0x0 0x20>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clkc CLKID_I2C>; + }; + + i2c1: i2c@1e000 { + compatible = "amlogic,meson-axg-i2c"; + status = "disabled"; + reg = <0x0 0x1e000 0x0 0x20>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clkc CLKID_I2C>; + }; + + i2c0: i2c@1f000 { + compatible = "amlogic,meson-axg-i2c"; + status = "disabled"; + reg = <0x0 0x1f000 0x0 0x20>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clkc CLKID_I2C>; + }; + + clk_msr: clock-measure@18000 { + compatible = "amlogic,meson-g12a-clk-measure"; + reg = <0x0 0x18000 0x0 0x10>; + }; + + uart_C: serial@22000 { + compatible = "amlogic,meson-gx-uart"; + reg = <0x0 0x22000 0x0 0x18>; + interrupts = ; + clocks = <&xtal>, <&clkc CLKID_UART2>, <&xtal>; + clock-names = "xtal", "pclk", "baud"; + status = "disabled"; + }; + + uart_B: serial@23000 { + compatible = "amlogic,meson-gx-uart"; + reg = <0x0 0x23000 0x0 0x18>; + interrupts = ; + clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>; + clock-names = "xtal", "pclk", "baud"; + status = "disabled"; + }; + + uart_A: serial@24000 { + compatible = "amlogic,meson-gx-uart"; + reg = <0x0 0x24000 0x0 0x18>; + interrupts = ; + clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>; + clock-names = "xtal", "pclk", "baud"; + status = "disabled"; + }; + }; + + sd_emmc_a: sd@ffe03000 { + compatible = "amlogic,meson-axg-mmc"; + reg = <0x0 0xffe03000 0x0 0x800>; + interrupts = ; + status = "disabled"; + clocks = <&clkc CLKID_SD_EMMC_A>, + <&clkc CLKID_SD_EMMC_A_CLK0>, + <&clkc CLKID_FCLK_DIV2>; + clock-names = "core", "clkin0", "clkin1"; + resets = <&reset RESET_SD_EMMC_A>; + }; + + sd_emmc_b: sd@ffe05000 { + compatible = "amlogic,meson-axg-mmc"; + reg = <0x0 0xffe05000 0x0 0x800>; + interrupts = ; + status = "disabled"; + clocks = <&clkc CLKID_SD_EMMC_B>, + <&clkc CLKID_SD_EMMC_B_CLK0>, + <&clkc CLKID_FCLK_DIV2>; + clock-names = "core", "clkin0", "clkin1"; + resets = <&reset RESET_SD_EMMC_B>; + }; + + sd_emmc_c: mmc@ffe07000 { + compatible = "amlogic,meson-axg-mmc"; + reg = <0x0 0xffe07000 0x0 0x800>; + interrupts = ; + status = "disabled"; + clocks = <&clkc CLKID_SD_EMMC_C>, + <&clkc CLKID_SD_EMMC_C_CLK0>, + <&clkc CLKID_FCLK_DIV2>; + clock-names = "core", "clkin0", "clkin1"; + resets = <&reset RESET_SD_EMMC_C>; + }; + + usb: usb@ffe09000 { + status = "disabled"; + compatible = "amlogic,meson-g12a-usb-ctrl"; + reg = <0x0 0xffe09000 0x0 0xa0>; + interrupts = ; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + clocks = <&clkc CLKID_USB>; + resets = <&reset RESET_USB>; + + dr_mode = "otg"; + + phys = <&usb2_phy0>, <&usb2_phy1>, + <&usb3_pcie_phy PHY_TYPE_USB3>; + phy-names = "usb2-phy0", "usb2-phy1", "usb3-phy0"; + + dwc2: usb@ff400000 { + compatible = "amlogic,meson-g12a-usb", "snps,dwc2"; + reg = <0x0 0xff400000 0x0 0x40000>; + interrupts = ; + clocks = <&clkc CLKID_USB1_DDR_BRIDGE>; + clock-names = "ddr"; + phys = <&usb2_phy1>; + dr_mode = "peripheral"; + g-rx-fifo-size = <192>; + g-np-tx-fifo-size = <128>; + g-tx-fifo-size = <128 128 16 16 16>; + }; + + dwc3: usb@ff500000 { + compatible = "snps,dwc3"; + reg = <0x0 0xff500000 0x0 0x100000>; + interrupts = ; + dr_mode = "host"; + snps,dis_u2_susphy_quirk; + snps,quirk-frame-length-adjustment; + }; + }; + + mali: gpu@ffe40000 { + compatible = "amlogic,meson-g12a-mali", "arm,mali-bifrost"; + reg = <0x0 0xffe40000 0x0 0x40000>; + interrupt-parent = <&gic>; + interrupts = , + , + ; + interrupt-names = "gpu", "mmu", "job"; + clocks = <&clkc CLKID_MALI>; + resets = <&reset RESET_DVALIN_CAPB3>, <&reset RESET_DVALIN>; + + /* + * Mali clocking is provided by two identical clock paths + * MALI_0 and MALI_1 muxed to a single clock by a glitch + * free mux to safely change frequency while running. + */ + assigned-clocks = <&clkc CLKID_MALI_0_SEL>, + <&clkc CLKID_MALI_0>, + <&clkc CLKID_MALI>; /* Glitch free mux */ + assigned-clock-parents = <&clkc CLKID_FCLK_DIV2P5>, + <0>, /* Do Nothing */ + <&clkc CLKID_MALI_0>; + assigned-clock-rates = <0>, /* Do Nothing */ + <800000000>, + <0>; /* Do Nothing */ + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + }; + + xtal: xtal-clk { + compatible = "fixed-clock"; + clock-frequency = <24000000>; + clock-output-names = "xtal"; + #clock-cells = <0>; + }; + +}; diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi index 58a6a9c4bcfc..ac15967bb7fa 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi @@ -3,57 +3,11 @@ * Copyright (c) 2018 Amlogic, Inc. All rights reserved. */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include +#include "meson-g12-common.dtsi" / { compatible = "amlogic,g12a"; - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - - tdmif_a: audio-controller-0 { - compatible = "amlogic,axg-tdm-iface"; - #sound-dai-cells = <0>; - sound-name-prefix = "TDM_A"; - clocks = <&clkc_audio AUD_CLKID_MST_A_MCLK>, - <&clkc_audio AUD_CLKID_MST_A_SCLK>, - <&clkc_audio AUD_CLKID_MST_A_LRCLK>; - clock-names = "mclk", "sclk", "lrclk"; - status = "disabled"; - }; - - tdmif_b: audio-controller-1 { - compatible = "amlogic,axg-tdm-iface"; - #sound-dai-cells = <0>; - sound-name-prefix = "TDM_B"; - clocks = <&clkc_audio AUD_CLKID_MST_B_MCLK>, - <&clkc_audio AUD_CLKID_MST_B_SCLK>, - <&clkc_audio AUD_CLKID_MST_B_LRCLK>; - clock-names = "mclk", "sclk", "lrclk"; - status = "disabled"; - }; - - tdmif_c: audio-controller-2 { - compatible = "amlogic,axg-tdm-iface"; - #sound-dai-cells = <0>; - sound-name-prefix = "TDM_C"; - clocks = <&clkc_audio AUD_CLKID_MST_C_MCLK>, - <&clkc_audio AUD_CLKID_MST_C_SCLK>, - <&clkc_audio AUD_CLKID_MST_C_LRCLK>; - clock-names = "mclk", "sclk", "lrclk"; - status = "disabled"; - }; - cpus { #address-cells = <0x2>; #size-cells = <0x0>; @@ -94,2406 +48,8 @@ compatible = "cache"; }; }; +}; - efuse: efuse { - compatible = "amlogic,meson-gxbb-efuse"; - clocks = <&clkc CLKID_EFUSE>; - #address-cells = <1>; - #size-cells = <1>; - read-only; - }; - - psci { - compatible = "arm,psci-1.0"; - method = "smc"; - }; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - /* 3 MiB reserved for ARM Trusted Firmware (BL31) */ - secmon_reserved: secmon@5000000 { - reg = <0x0 0x05000000 0x0 0x300000>; - no-map; - }; - - linux,cma { - compatible = "shared-dma-pool"; - reusable; - size = <0x0 0x38000000>; - alignment = <0x0 0x400000>; - linux,cma-default; - }; - }; - - sm: secure-monitor { - compatible = "amlogic,meson-gxbb-sm"; - }; - - soc { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - ethmac: ethernet@ff3f0000 { - compatible = "amlogic,meson-axg-dwmac", - "snps,dwmac-3.70a", - "snps,dwmac"; - reg = <0x0 0xff3f0000 0x0 0x10000 - 0x0 0xff634540 0x0 0x8>; - interrupts = ; - interrupt-names = "macirq"; - clocks = <&clkc CLKID_ETH>, - <&clkc CLKID_FCLK_DIV2>, - <&clkc CLKID_MPLL2>; - clock-names = "stmmaceth", "clkin0", "clkin1"; - status = "disabled"; - - mdio0: mdio { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,dwmac-mdio"; - }; - }; - - apb: bus@ff600000 { - compatible = "simple-bus"; - reg = <0x0 0xff600000 0x0 0x200000>; - #address-cells = <2>; - #size-cells = <2>; - ranges = <0x0 0x0 0x0 0xff600000 0x0 0x200000>; - - hdmi_tx: hdmi-tx@0 { - compatible = "amlogic,meson-g12a-dw-hdmi"; - reg = <0x0 0x0 0x0 0x10000>; - interrupts = ; - resets = <&reset RESET_HDMITX_CAPB3>, - <&reset RESET_HDMITX_PHY>, - <&reset RESET_HDMITX>; - reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy"; - clocks = <&clkc CLKID_HDMI>, - <&clkc CLKID_HTX_PCLK>, - <&clkc CLKID_VPU_INTR>; - clock-names = "isfr", "iahb", "venci"; - #address-cells = <1>; - #size-cells = <0>; - #sound-dai-cells = <0>; - status = "disabled"; - - /* VPU VENC Input */ - hdmi_tx_venc_port: port@0 { - reg = <0>; - - hdmi_tx_in: endpoint { - remote-endpoint = <&hdmi_tx_out>; - }; - }; - - /* TMDS Output */ - hdmi_tx_tmds_port: port@1 { - reg = <1>; - }; - }; - - apb_efuse: bus@30000 { - compatible = "simple-bus"; - reg = <0x0 0x30000 0x0 0x2000>; - #address-cells = <2>; - #size-cells = <2>; - ranges = <0x0 0x0 0x0 0x30000 0x0 0x2000>; - - hwrng: rng@218 { - compatible = "amlogic,meson-rng"; - reg = <0x0 0x218 0x0 0x4>; - }; - }; - - periphs: bus@34400 { - compatible = "simple-bus"; - reg = <0x0 0x34400 0x0 0x400>; - #address-cells = <2>; - #size-cells = <2>; - ranges = <0x0 0x0 0x0 0x34400 0x0 0x400>; - - periphs_pinctrl: pinctrl@40 { - compatible = "amlogic,meson-g12a-periphs-pinctrl"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - gpio: bank@40 { - reg = <0x0 0x40 0x0 0x4c>, - <0x0 0xe8 0x0 0x18>, - <0x0 0x120 0x0 0x18>, - <0x0 0x2c0 0x0 0x40>, - <0x0 0x340 0x0 0x1c>; - reg-names = "gpio", - "pull", - "pull-enable", - "mux", - "ds"; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&periphs_pinctrl 0 0 86>; - }; - - cec_ao_a_h_pins: cec_ao_a_h { - mux { - groups = "cec_ao_a_h"; - function = "cec_ao_a_h"; - bias-disable; - }; - }; - - cec_ao_b_h_pins: cec_ao_b_h { - mux { - groups = "cec_ao_b_h"; - function = "cec_ao_b_h"; - bias-disable; - }; - }; - - emmc_pins: emmc { - mux-0 { - groups = "emmc_nand_d0", - "emmc_nand_d1", - "emmc_nand_d2", - "emmc_nand_d3", - "emmc_nand_d4", - "emmc_nand_d5", - "emmc_nand_d6", - "emmc_nand_d7", - "emmc_cmd"; - function = "emmc"; - bias-pull-up; - drive-strength-microamp = <4000>; - }; - - mux-1 { - groups = "emmc_clk"; - function = "emmc"; - bias-disable; - drive-strength-microamp = <4000>; - }; - }; - - emmc_ds_pins: emmc-ds { - mux { - groups = "emmc_nand_ds"; - function = "emmc"; - bias-pull-down; - drive-strength-microamp = <4000>; - }; - }; - - emmc_clk_gate_pins: emmc_clk_gate { - mux { - groups = "BOOT_8"; - function = "gpio_periphs"; - bias-pull-down; - drive-strength-microamp = <4000>; - }; - }; - - hdmitx_ddc_pins: hdmitx_ddc { - mux { - groups = "hdmitx_sda", - "hdmitx_sck"; - function = "hdmitx"; - bias-disable; - drive-strength-microamp = <4000>; - }; - }; - - hdmitx_hpd_pins: hdmitx_hpd { - mux { - groups = "hdmitx_hpd_in"; - function = "hdmitx"; - bias-disable; - }; - }; - - - i2c0_sda_c_pins: i2c0-sda-c { - mux { - groups = "i2c0_sda_c"; - function = "i2c0"; - bias-disable; - drive-strength-microamp = <3000>; - - }; - }; - - i2c0_sck_c_pins: i2c0-sck-c { - mux { - groups = "i2c0_sck_c"; - function = "i2c0"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - i2c0_sda_z0_pins: i2c0-sda-z0 { - mux { - groups = "i2c0_sda_z0"; - function = "i2c0"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - i2c0_sck_z1_pins: i2c0-sck-z1 { - mux { - groups = "i2c0_sck_z1"; - function = "i2c0"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - i2c0_sda_z7_pins: i2c0-sda-z7 { - mux { - groups = "i2c0_sda_z7"; - function = "i2c0"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - i2c0_sda_z8_pins: i2c0-sda-z8 { - mux { - groups = "i2c0_sda_z8"; - function = "i2c0"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - i2c1_sda_x_pins: i2c1-sda-x { - mux { - groups = "i2c1_sda_x"; - function = "i2c1"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - i2c1_sck_x_pins: i2c1-sck-x { - mux { - groups = "i2c1_sck_x"; - function = "i2c1"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - i2c1_sda_h2_pins: i2c1-sda-h2 { - mux { - groups = "i2c1_sda_h2"; - function = "i2c1"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - i2c1_sck_h3_pins: i2c1-sck-h3 { - mux { - groups = "i2c1_sck_h3"; - function = "i2c1"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - i2c1_sda_h6_pins: i2c1-sda-h6 { - mux { - groups = "i2c1_sda_h6"; - function = "i2c1"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - i2c1_sck_h7_pins: i2c1-sck-h7 { - mux { - groups = "i2c1_sck_h7"; - function = "i2c1"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - i2c2_sda_x_pins: i2c2-sda-x { - mux { - groups = "i2c2_sda_x"; - function = "i2c2"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - i2c2_sck_x_pins: i2c2-sck-x { - mux { - groups = "i2c2_sck_x"; - function = "i2c2"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - i2c2_sda_z_pins: i2c2-sda-z { - mux { - groups = "i2c2_sda_z"; - function = "i2c2"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - i2c2_sck_z_pins: i2c2-sck-z { - mux { - groups = "i2c2_sck_z"; - function = "i2c2"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - i2c3_sda_h_pins: i2c3-sda-h { - mux { - groups = "i2c3_sda_h"; - function = "i2c3"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - i2c3_sck_h_pins: i2c3-sck-h { - mux { - groups = "i2c3_sck_h"; - function = "i2c3"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - i2c3_sda_a_pins: i2c3-sda-a { - mux { - groups = "i2c3_sda_a"; - function = "i2c3"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - i2c3_sck_a_pins: i2c3-sck-a { - mux { - groups = "i2c3_sck_a"; - function = "i2c3"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - mclk0_a_pins: mclk0-a { - mux { - groups = "mclk0_a"; - function = "mclk0"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - mclk1_a_pins: mclk1-a { - mux { - groups = "mclk1_a"; - function = "mclk1"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - mclk1_x_pins: mclk1-x { - mux { - groups = "mclk1_x"; - function = "mclk1"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - mclk1_z_pins: mclk1-z { - mux { - groups = "mclk1_z"; - function = "mclk1"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - pdm_din0_a_pins: pdm-din0-a { - mux { - groups = "pdm_din0_a"; - function = "pdm"; - bias-disable; - }; - }; - - pdm_din0_c_pins: pdm-din0-c { - mux { - groups = "pdm_din0_c"; - function = "pdm"; - bias-disable; - }; - }; - - pdm_din0_x_pins: pdm-din0-x { - mux { - groups = "pdm_din0_x"; - function = "pdm"; - bias-disable; - }; - }; - - pdm_din0_z_pins: pdm-din0-z { - mux { - groups = "pdm_din0_z"; - function = "pdm"; - bias-disable; - }; - }; - - pdm_din1_a_pins: pdm-din1-a { - mux { - groups = "pdm_din1_a"; - function = "pdm"; - bias-disable; - }; - }; - - pdm_din1_c_pins: pdm-din1-c { - mux { - groups = "pdm_din1_c"; - function = "pdm"; - bias-disable; - }; - }; - - pdm_din1_x_pins: pdm-din1-x { - mux { - groups = "pdm_din1_x"; - function = "pdm"; - bias-disable; - }; - }; - - pdm_din1_z_pins: pdm-din1-z { - mux { - groups = "pdm_din1_z"; - function = "pdm"; - bias-disable; - }; - }; - - pdm_din2_a_pins: pdm-din2-a { - mux { - groups = "pdm_din2_a"; - function = "pdm"; - bias-disable; - }; - }; - - pdm_din2_c_pins: pdm-din2-c { - mux { - groups = "pdm_din2_c"; - function = "pdm"; - bias-disable; - }; - }; - - pdm_din2_x_pins: pdm-din2-x { - mux { - groups = "pdm_din2_x"; - function = "pdm"; - bias-disable; - }; - }; - - pdm_din2_z_pins: pdm-din2-z { - mux { - groups = "pdm_din2_z"; - function = "pdm"; - bias-disable; - }; - }; - - pdm_din3_a_pins: pdm-din3-a { - mux { - groups = "pdm_din3_a"; - function = "pdm"; - bias-disable; - }; - }; - - pdm_din3_c_pins: pdm-din3-c { - mux { - groups = "pdm_din3_c"; - function = "pdm"; - bias-disable; - }; - }; - - pdm_din3_x_pins: pdm-din3-x { - mux { - groups = "pdm_din3_x"; - function = "pdm"; - bias-disable; - }; - }; - - pdm_din3_z_pins: pdm-din3-z { - mux { - groups = "pdm_din3_z"; - function = "pdm"; - bias-disable; - }; - }; - - pdm_dclk_a_pins: pdm-dclk-a { - mux { - groups = "pdm_dclk_a"; - function = "pdm"; - bias-disable; - drive-strength-microamp = <500>; - }; - }; - - pdm_dclk_c_pins: pdm-dclk-c { - mux { - groups = "pdm_dclk_c"; - function = "pdm"; - bias-disable; - drive-strength-microamp = <500>; - }; - }; - - pdm_dclk_x_pins: pdm-dclk-x { - mux { - groups = "pdm_dclk_x"; - function = "pdm"; - bias-disable; - drive-strength-microamp = <500>; - }; - }; - - pdm_dclk_z_pins: pdm-dclk-z { - mux { - groups = "pdm_dclk_z"; - function = "pdm"; - bias-disable; - drive-strength-microamp = <500>; - }; - }; - - pwm_a_pins: pwm-a { - mux { - groups = "pwm_a"; - function = "pwm_a"; - bias-disable; - }; - }; - - pwm_b_x7_pins: pwm-b-x7 { - mux { - groups = "pwm_b_x7"; - function = "pwm_b"; - bias-disable; - }; - }; - - pwm_b_x19_pins: pwm-b-x19 { - mux { - groups = "pwm_b_x19"; - function = "pwm_b"; - bias-disable; - }; - }; - - pwm_c_c_pins: pwm-c-c { - mux { - groups = "pwm_c_c"; - function = "pwm_c"; - bias-disable; - }; - }; - - pwm_c_x5_pins: pwm-c-x5 { - mux { - groups = "pwm_c_x5"; - function = "pwm_c"; - bias-disable; - }; - }; - - pwm_c_x8_pins: pwm-c-x8 { - mux { - groups = "pwm_c_x8"; - function = "pwm_c"; - bias-disable; - }; - }; - - pwm_d_x3_pins: pwm-d-x3 { - mux { - groups = "pwm_d_x3"; - function = "pwm_d"; - bias-disable; - }; - }; - - pwm_d_x6_pins: pwm-d-x6 { - mux { - groups = "pwm_d_x6"; - function = "pwm_d"; - bias-disable; - }; - }; - - pwm_e_pins: pwm-e { - mux { - groups = "pwm_e"; - function = "pwm_e"; - bias-disable; - }; - }; - - pwm_f_x_pins: pwm-f-x { - mux { - groups = "pwm_f_x"; - function = "pwm_f"; - bias-disable; - }; - }; - - pwm_f_h_pins: pwm-f-h { - mux { - groups = "pwm_f_h"; - function = "pwm_f"; - bias-disable; - }; - }; - - sdcard_c_pins: sdcard_c { - mux-0 { - groups = "sdcard_d0_c", - "sdcard_d1_c", - "sdcard_d2_c", - "sdcard_d3_c", - "sdcard_cmd_c"; - function = "sdcard"; - bias-pull-up; - drive-strength-microamp = <4000>; - }; - - mux-1 { - groups = "sdcard_clk_c"; - function = "sdcard"; - bias-disable; - drive-strength-microamp = <4000>; - }; - }; - - sdcard_clk_gate_c_pins: sdcard_clk_gate_c { - mux { - groups = "GPIOC_4"; - function = "gpio_periphs"; - bias-pull-down; - drive-strength-microamp = <4000>; - }; - }; - - sdcard_z_pins: sdcard_z { - mux-0 { - groups = "sdcard_d0_z", - "sdcard_d1_z", - "sdcard_d2_z", - "sdcard_d3_z", - "sdcard_cmd_z"; - function = "sdcard"; - bias-pull-up; - drive-strength-microamp = <4000>; - }; - - mux-1 { - groups = "sdcard_clk_z"; - function = "sdcard"; - bias-disable; - drive-strength-microamp = <4000>; - }; - }; - - sdcard_clk_gate_z_pins: sdcard_clk_gate_z { - mux { - groups = "GPIOZ_6"; - function = "gpio_periphs"; - bias-pull-down; - drive-strength-microamp = <4000>; - }; - }; - - sdio_pins: sdio { - mux { - groups = "sdio_d0", - "sdio_d1", - "sdio_d2", - "sdio_d3", - "sdio_clk", - "sdio_cmd"; - function = "sdio"; - bias-disable; - drive-strength-microamp = <4000>; - }; - }; - - sdio_clk_gate_pins: sdio_clk_gate { - mux { - groups = "GPIOX_4"; - function = "gpio_periphs"; - bias-pull-down; - drive-strength-microamp = <4000>; - }; - }; - - spdif_in_a10_pins: spdif-in-a10 { - mux { - groups = "spdif_in_a10"; - function = "spdif_in"; - bias-disable; - }; - }; - - spdif_in_a12_pins: spdif-in-a12 { - mux { - groups = "spdif_in_a12"; - function = "spdif_in"; - bias-disable; - }; - }; - - spdif_in_h_pins: spdif-in-h { - mux { - groups = "spdif_in_h"; - function = "spdif_in"; - bias-disable; - }; - }; - - spdif_out_h_pins: spdif-out-h { - mux { - groups = "spdif_out_h"; - function = "spdif_out"; - drive-strength-microamp = <500>; - bias-disable; - }; - }; - - spdif_out_a11_pins: spdif-out-a11 { - mux { - groups = "spdif_out_a11"; - function = "spdif_out"; - drive-strength-microamp = <500>; - bias-disable; - }; - }; - - spdif_out_a13_pins: spdif-out-a13 { - mux { - groups = "spdif_out_a13"; - function = "spdif_out"; - drive-strength-microamp = <500>; - bias-disable; - }; - }; - - tdm_a_din0_pins: tdm-a-din0 { - mux { - groups = "tdm_a_din0"; - function = "tdm_a"; - bias-disable; - }; - }; - - - tdm_a_din1_pins: tdm-a-din1 { - mux { - groups = "tdm_a_din1"; - function = "tdm_a"; - bias-disable; - }; - }; - - tdm_a_dout0_pins: tdm-a-dout0 { - mux { - groups = "tdm_a_dout0"; - function = "tdm_a"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - tdm_a_dout1_pins: tdm-a-dout1 { - mux { - groups = "tdm_a_dout1"; - function = "tdm_a"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - tdm_a_fs_pins: tdm-a-fs { - mux { - groups = "tdm_a_fs"; - function = "tdm_a"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - tdm_a_sclk_pins: tdm-a-sclk { - mux { - groups = "tdm_a_sclk"; - function = "tdm_a"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - tdm_a_slv_fs_pins: tdm-a-slv-fs { - mux { - groups = "tdm_a_slv_fs"; - function = "tdm_a"; - bias-disable; - }; - }; - - - tdm_a_slv_sclk_pins: tdm-a-slv-sclk { - mux { - groups = "tdm_a_slv_sclk"; - function = "tdm_a"; - bias-disable; - }; - }; - - tdm_b_din0_pins: tdm-b-din0 { - mux { - groups = "tdm_b_din0"; - function = "tdm_b"; - bias-disable; - }; - }; - - tdm_b_din1_pins: tdm-b-din1 { - mux { - groups = "tdm_b_din1"; - function = "tdm_b"; - bias-disable; - }; - }; - - tdm_b_din2_pins: tdm-b-din2 { - mux { - groups = "tdm_b_din2"; - function = "tdm_b"; - bias-disable; - }; - }; - - tdm_b_din3_a_pins: tdm-b-din3-a { - mux { - groups = "tdm_b_din3_a"; - function = "tdm_b"; - bias-disable; - }; - }; - - tdm_b_din3_h_pins: tdm-b-din3-h { - mux { - groups = "tdm_b_din3_h"; - function = "tdm_b"; - bias-disable; - }; - }; - - tdm_b_dout0_pins: tdm-b-dout0 { - mux { - groups = "tdm_b_dout0"; - function = "tdm_b"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - tdm_b_dout1_pins: tdm-b-dout1 { - mux { - groups = "tdm_b_dout1"; - function = "tdm_b"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - tdm_b_dout2_pins: tdm-b-dout2 { - mux { - groups = "tdm_b_dout2"; - function = "tdm_b"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - tdm_b_dout3_a_pins: tdm-b-dout3-a { - mux { - groups = "tdm_b_dout3_a"; - function = "tdm_b"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - tdm_b_dout3_h_pins: tdm-b-dout3-h { - mux { - groups = "tdm_b_dout3_h"; - function = "tdm_b"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - tdm_b_fs_pins: tdm-b-fs { - mux { - groups = "tdm_b_fs"; - function = "tdm_b"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - tdm_b_sclk_pins: tdm-b-sclk { - mux { - groups = "tdm_b_sclk"; - function = "tdm_b"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - tdm_b_slv_fs_pins: tdm-b-slv-fs { - mux { - groups = "tdm_b_slv_fs"; - function = "tdm_b"; - bias-disable; - }; - }; - - tdm_b_slv_sclk_pins: tdm-b-slv-sclk { - mux { - groups = "tdm_b_slv_sclk"; - function = "tdm_b"; - bias-disable; - }; - }; - - tdm_c_din0_a_pins: tdm-c-din0-a { - mux { - groups = "tdm_c_din0_a"; - function = "tdm_c"; - bias-disable; - }; - }; - - tdm_c_din0_z_pins: tdm-c-din0-z { - mux { - groups = "tdm_c_din0_z"; - function = "tdm_c"; - bias-disable; - }; - }; - - tdm_c_din1_a_pins: tdm-c-din1-a { - mux { - groups = "tdm_c_din1_a"; - function = "tdm_c"; - bias-disable; - }; - }; - - tdm_c_din1_z_pins: tdm-c-din1-z { - mux { - groups = "tdm_c_din1_z"; - function = "tdm_c"; - bias-disable; - }; - }; - - tdm_c_din2_a_pins: tdm-c-din2-a { - mux { - groups = "tdm_c_din2_a"; - function = "tdm_c"; - bias-disable; - }; - }; - - eth_leds_pins: eth-leds { - mux { - groups = "eth_link_led", - "eth_act_led"; - function = "eth"; - bias-disable; - }; - }; - - eth_pins: eth { - mux { - groups = "eth_mdio", - "eth_mdc", - "eth_rgmii_rx_clk", - "eth_rx_dv", - "eth_rxd0", - "eth_rxd1", - "eth_txen", - "eth_txd0", - "eth_txd1"; - function = "eth"; - drive-strength-microamp = <4000>; - bias-disable; - }; - }; - - eth_rgmii_pins: eth-rgmii { - mux { - groups = "eth_rxd2_rgmii", - "eth_rxd3_rgmii", - "eth_rgmii_tx_clk", - "eth_txd2_rgmii", - "eth_txd3_rgmii"; - function = "eth"; - drive-strength-microamp = <4000>; - bias-disable; - }; - }; - - tdm_c_din2_z_pins: tdm-c-din2-z { - mux { - groups = "tdm_c_din2_z"; - function = "tdm_c"; - bias-disable; - }; - }; - - tdm_c_din3_a_pins: tdm-c-din3-a { - mux { - groups = "tdm_c_din3_a"; - function = "tdm_c"; - bias-disable; - }; - }; - - tdm_c_din3_z_pins: tdm-c-din3-z { - mux { - groups = "tdm_c_din3_z"; - function = "tdm_c"; - bias-disable; - }; - }; - - tdm_c_dout0_a_pins: tdm-c-dout0-a { - mux { - groups = "tdm_c_dout0_a"; - function = "tdm_c"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - tdm_c_dout0_z_pins: tdm-c-dout0-z { - mux { - groups = "tdm_c_dout0_z"; - function = "tdm_c"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - tdm_c_dout1_a_pins: tdm-c-dout1-a { - mux { - groups = "tdm_c_dout1_a"; - function = "tdm_c"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - tdm_c_dout1_z_pins: tdm-c-dout1-z { - mux { - groups = "tdm_c_dout1_z"; - function = "tdm_c"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - tdm_c_dout2_a_pins: tdm-c-dout2-a { - mux { - groups = "tdm_c_dout2_a"; - function = "tdm_c"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - tdm_c_dout2_z_pins: tdm-c-dout2-z { - mux { - groups = "tdm_c_dout2_z"; - function = "tdm_c"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - tdm_c_dout3_a_pins: tdm-c-dout3-a { - mux { - groups = "tdm_c_dout3_a"; - function = "tdm_c"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - tdm_c_dout3_z_pins: tdm-c-dout3-z { - mux { - groups = "tdm_c_dout3_z"; - function = "tdm_c"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - tdm_c_fs_a_pins: tdm-c-fs-a { - mux { - groups = "tdm_c_fs_a"; - function = "tdm_c"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - tdm_c_fs_z_pins: tdm-c-fs-z { - mux { - groups = "tdm_c_fs_z"; - function = "tdm_c"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - tdm_c_sclk_a_pins: tdm-c-sclk-a { - mux { - groups = "tdm_c_sclk_a"; - function = "tdm_c"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - tdm_c_sclk_z_pins: tdm-c-sclk-z { - mux { - groups = "tdm_c_sclk_z"; - function = "tdm_c"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - tdm_c_slv_fs_a_pins: tdm-c-slv-fs-a { - mux { - groups = "tdm_c_slv_fs_a"; - function = "tdm_c"; - bias-disable; - }; - }; - - tdm_c_slv_fs_z_pins: tdm-c-slv-fs-z { - mux { - groups = "tdm_c_slv_fs_z"; - function = "tdm_c"; - bias-disable; - }; - }; - - tdm_c_slv_sclk_a_pins: tdm-c-slv-sclk-a { - mux { - groups = "tdm_c_slv_sclk_a"; - function = "tdm_c"; - bias-disable; - }; - }; - - tdm_c_slv_sclk_z_pins: tdm-c-slv-sclk-z { - mux { - groups = "tdm_c_slv_sclk_z"; - function = "tdm_c"; - bias-disable; - }; - }; - - uart_a_pins: uart-a { - mux { - groups = "uart_a_tx", - "uart_a_rx"; - function = "uart_a"; - bias-disable; - }; - }; - - uart_a_cts_rts_pins: uart-a-cts-rts { - mux { - groups = "uart_a_cts", - "uart_a_rts"; - function = "uart_a"; - bias-disable; - }; - }; - - uart_b_pins: uart-b { - mux { - groups = "uart_b_tx", - "uart_b_rx"; - function = "uart_b"; - bias-disable; - }; - }; - - uart_c_pins: uart-c { - mux { - groups = "uart_c_tx", - "uart_c_rx"; - function = "uart_c"; - bias-disable; - }; - }; - - uart_c_cts_rts_pins: uart-c-cts-rts { - mux { - groups = "uart_c_cts", - "uart_c_rts"; - function = "uart_c"; - bias-disable; - }; - }; - }; - }; - - usb2_phy0: phy@36000 { - compatible = "amlogic,g12a-usb2-phy"; - reg = <0x0 0x36000 0x0 0x2000>; - clocks = <&xtal>; - clock-names = "xtal"; - resets = <&reset RESET_USB_PHY20>; - reset-names = "phy"; - #phy-cells = <0>; - }; - - dmc: bus@38000 { - compatible = "simple-bus"; - reg = <0x0 0x38000 0x0 0x400>; - #address-cells = <2>; - #size-cells = <2>; - ranges = <0x0 0x0 0x0 0x38000 0x0 0x400>; - - canvas: video-lut@48 { - compatible = "amlogic,canvas"; - reg = <0x0 0x48 0x0 0x14>; - }; - }; - - usb2_phy1: phy@3a000 { - compatible = "amlogic,g12a-usb2-phy"; - reg = <0x0 0x3a000 0x0 0x2000>; - clocks = <&xtal>; - clock-names = "xtal"; - resets = <&reset RESET_USB_PHY21>; - reset-names = "phy"; - #phy-cells = <0>; - }; - - hiu: bus@3c000 { - compatible = "simple-bus"; - reg = <0x0 0x3c000 0x0 0x1400>; - #address-cells = <2>; - #size-cells = <2>; - ranges = <0x0 0x0 0x0 0x3c000 0x0 0x1400>; - - hhi: system-controller@0 { - compatible = "amlogic,meson-gx-hhi-sysctrl", - "simple-mfd", "syscon"; - reg = <0 0 0 0x400>; - - clkc: clock-controller { - compatible = "amlogic,g12a-clkc"; - #clock-cells = <1>; - clocks = <&xtal>; - clock-names = "xtal"; - }; - }; - - mailbox: mailbox@404 { - compatible = "amlogic,meson-gx-mhu", - "amlogic,meson-gxbb-mhu"; - reg = <0 0x404 0 0x4c>; - interrupts = , - , - ; - clocks = <&clkc_AO CLKID_AO_MAILBOX>; - clock-names = "pclk"; - #mbox-cells = <1>; - }; - }; - - pdm: audio-controller@40000 { - compatible = "amlogic,g12a-pdm", - "amlogic,axg-pdm"; - reg = <0x0 0x40000 0x0 0x34>; - #sound-dai-cells = <0>; - sound-name-prefix = "PDM"; - clocks = <&clkc_audio AUD_CLKID_PDM>, - <&clkc_audio AUD_CLKID_PDM_DCLK>, - <&clkc_audio AUD_CLKID_PDM_SYSCLK>; - clock-names = "pclk", "dclk", "sysclk"; - status = "disabled"; - }; - - audio: bus@42000 { - compatible = "simple-bus"; - reg = <0x0 0x42000 0x0 0x2000>; - #address-cells = <2>; - #size-cells = <2>; - ranges = <0x0 0x0 0x0 0x42000 0x0 0x2000>; - - clkc_audio: clock-controller@0 { - status = "disabled"; - compatible = "amlogic,g12a-audio-clkc"; - reg = <0x0 0x0 0x0 0xb4>; - #clock-cells = <1>; - - clocks = <&clkc CLKID_AUDIO>, - <&clkc CLKID_MPLL0>, - <&clkc CLKID_MPLL1>, - <&clkc CLKID_MPLL2>, - <&clkc CLKID_MPLL3>, - <&clkc CLKID_HIFI_PLL>, - <&clkc CLKID_FCLK_DIV3>, - <&clkc CLKID_FCLK_DIV4>, - <&clkc CLKID_GP0_PLL>; - clock-names = "pclk", - "mst_in0", - "mst_in1", - "mst_in2", - "mst_in3", - "mst_in4", - "mst_in5", - "mst_in6", - "mst_in7"; - - resets = <&reset RESET_AUDIO>; - }; - - toddr_a: audio-controller@100 { - compatible = "amlogic,g12a-toddr", - "amlogic,axg-toddr"; - reg = <0x0 0x100 0x0 0x1c>; - #sound-dai-cells = <0>; - sound-name-prefix = "TODDR_A"; - interrupts = ; - clocks = <&clkc_audio AUD_CLKID_TODDR_A>; - resets = <&arb AXG_ARB_TODDR_A>; - status = "disabled"; - }; - - toddr_b: audio-controller@140 { - compatible = "amlogic,g12a-toddr", - "amlogic,axg-toddr"; - reg = <0x0 0x140 0x0 0x1c>; - #sound-dai-cells = <0>; - sound-name-prefix = "TODDR_B"; - interrupts = ; - clocks = <&clkc_audio AUD_CLKID_TODDR_B>; - resets = <&arb AXG_ARB_TODDR_B>; - status = "disabled"; - }; - - toddr_c: audio-controller@180 { - compatible = "amlogic,g12a-toddr", - "amlogic,axg-toddr"; - reg = <0x0 0x180 0x0 0x1c>; - #sound-dai-cells = <0>; - sound-name-prefix = "TODDR_C"; - interrupts = ; - clocks = <&clkc_audio AUD_CLKID_TODDR_C>; - resets = <&arb AXG_ARB_TODDR_C>; - status = "disabled"; - }; - - frddr_a: audio-controller@1c0 { - compatible = "amlogic,g12a-frddr", - "amlogic,axg-frddr"; - reg = <0x0 0x1c0 0x0 0x1c>; - #sound-dai-cells = <0>; - sound-name-prefix = "FRDDR_A"; - interrupts = ; - clocks = <&clkc_audio AUD_CLKID_FRDDR_A>; - resets = <&arb AXG_ARB_FRDDR_A>; - status = "disabled"; - }; - - frddr_b: audio-controller@200 { - compatible = "amlogic,g12a-frddr", - "amlogic,axg-frddr"; - reg = <0x0 0x200 0x0 0x1c>; - #sound-dai-cells = <0>; - sound-name-prefix = "FRDDR_B"; - interrupts = ; - clocks = <&clkc_audio AUD_CLKID_FRDDR_B>; - resets = <&arb AXG_ARB_FRDDR_B>; - status = "disabled"; - }; - - frddr_c: audio-controller@240 { - compatible = "amlogic,g12a-frddr", - "amlogic,axg-frddr"; - reg = <0x0 0x240 0x0 0x1c>; - #sound-dai-cells = <0>; - sound-name-prefix = "FRDDR_C"; - interrupts = ; - clocks = <&clkc_audio AUD_CLKID_FRDDR_C>; - resets = <&arb AXG_ARB_FRDDR_C>; - status = "disabled"; - }; - - arb: reset-controller@280 { - status = "disabled"; - compatible = "amlogic,meson-axg-audio-arb"; - reg = <0x0 0x280 0x0 0x4>; - #reset-cells = <1>; - clocks = <&clkc_audio AUD_CLKID_DDR_ARB>; - }; - - tdmin_a: audio-controller@300 { - compatible = "amlogic,g12a-tdmin", - "amlogic,axg-tdmin"; - reg = <0x0 0x300 0x0 0x40>; - sound-name-prefix = "TDMIN_A"; - clocks = <&clkc_audio AUD_CLKID_TDMIN_A>, - <&clkc_audio AUD_CLKID_TDMIN_A_SCLK>, - <&clkc_audio AUD_CLKID_TDMIN_A_SCLK_SEL>, - <&clkc_audio AUD_CLKID_TDMIN_A_LRCLK>, - <&clkc_audio AUD_CLKID_TDMIN_A_LRCLK>; - clock-names = "pclk", "sclk", "sclk_sel", - "lrclk", "lrclk_sel"; - status = "disabled"; - }; - - tdmin_b: audio-controller@340 { - compatible = "amlogic,g12a-tdmin", - "amlogic,axg-tdmin"; - reg = <0x0 0x340 0x0 0x40>; - sound-name-prefix = "TDMIN_B"; - clocks = <&clkc_audio AUD_CLKID_TDMIN_B>, - <&clkc_audio AUD_CLKID_TDMIN_B_SCLK>, - <&clkc_audio AUD_CLKID_TDMIN_B_SCLK_SEL>, - <&clkc_audio AUD_CLKID_TDMIN_B_LRCLK>, - <&clkc_audio AUD_CLKID_TDMIN_B_LRCLK>; - clock-names = "pclk", "sclk", "sclk_sel", - "lrclk", "lrclk_sel"; - status = "disabled"; - }; - - tdmin_c: audio-controller@380 { - compatible = "amlogic,g12a-tdmin", - "amlogic,axg-tdmin"; - reg = <0x0 0x380 0x0 0x40>; - sound-name-prefix = "TDMIN_C"; - clocks = <&clkc_audio AUD_CLKID_TDMIN_C>, - <&clkc_audio AUD_CLKID_TDMIN_C_SCLK>, - <&clkc_audio AUD_CLKID_TDMIN_C_SCLK_SEL>, - <&clkc_audio AUD_CLKID_TDMIN_C_LRCLK>, - <&clkc_audio AUD_CLKID_TDMIN_C_LRCLK>; - clock-names = "pclk", "sclk", "sclk_sel", - "lrclk", "lrclk_sel"; - status = "disabled"; - }; - - tdmin_lb: audio-controller@3c0 { - compatible = "amlogic,g12a-tdmin", - "amlogic,axg-tdmin"; - reg = <0x0 0x3c0 0x0 0x40>; - sound-name-prefix = "TDMIN_LB"; - clocks = <&clkc_audio AUD_CLKID_TDMIN_LB>, - <&clkc_audio AUD_CLKID_TDMIN_LB_SCLK>, - <&clkc_audio AUD_CLKID_TDMIN_LB_SCLK_SEL>, - <&clkc_audio AUD_CLKID_TDMIN_LB_LRCLK>, - <&clkc_audio AUD_CLKID_TDMIN_LB_LRCLK>; - clock-names = "pclk", "sclk", "sclk_sel", - "lrclk", "lrclk_sel"; - status = "disabled"; - }; - - spdifin: audio-controller@400 { - compatible = "amlogic,g12a-spdifin", - "amlogic,axg-spdifin"; - reg = <0x0 0x400 0x0 0x30>; - #sound-dai-cells = <0>; - sound-name-prefix = "SPDIFIN"; - interrupts = ; - clocks = <&clkc_audio AUD_CLKID_SPDIFIN>, - <&clkc_audio AUD_CLKID_SPDIFIN_CLK>; - clock-names = "pclk", "refclk"; - status = "disabled"; - }; - - spdifout: audio-controller@480 { - compatible = "amlogic,g12a-spdifout", - "amlogic,axg-spdifout"; - reg = <0x0 0x480 0x0 0x50>; - #sound-dai-cells = <0>; - sound-name-prefix = "SPDIFOUT"; - clocks = <&clkc_audio AUD_CLKID_SPDIFOUT>, - <&clkc_audio AUD_CLKID_SPDIFOUT_CLK>; - clock-names = "pclk", "mclk"; - status = "disabled"; - }; - - tdmout_a: audio-controller@500 { - compatible = "amlogic,g12a-tdmout"; - reg = <0x0 0x500 0x0 0x40>; - sound-name-prefix = "TDMOUT_A"; - clocks = <&clkc_audio AUD_CLKID_TDMOUT_A>, - <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK>, - <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK_SEL>, - <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>, - <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>; - clock-names = "pclk", "sclk", "sclk_sel", - "lrclk", "lrclk_sel"; - status = "disabled"; - }; - - tdmout_b: audio-controller@540 { - compatible = "amlogic,g12a-tdmout"; - reg = <0x0 0x540 0x0 0x40>; - sound-name-prefix = "TDMOUT_B"; - clocks = <&clkc_audio AUD_CLKID_TDMOUT_B>, - <&clkc_audio AUD_CLKID_TDMOUT_B_SCLK>, - <&clkc_audio AUD_CLKID_TDMOUT_B_SCLK_SEL>, - <&clkc_audio AUD_CLKID_TDMOUT_B_LRCLK>, - <&clkc_audio AUD_CLKID_TDMOUT_B_LRCLK>; - clock-names = "pclk", "sclk", "sclk_sel", - "lrclk", "lrclk_sel"; - status = "disabled"; - }; - - tdmout_c: audio-controller@580 { - compatible = "amlogic,g12a-tdmout"; - reg = <0x0 0x580 0x0 0x40>; - sound-name-prefix = "TDMOUT_C"; - clocks = <&clkc_audio AUD_CLKID_TDMOUT_C>, - <&clkc_audio AUD_CLKID_TDMOUT_C_SCLK>, - <&clkc_audio AUD_CLKID_TDMOUT_C_SCLK_SEL>, - <&clkc_audio AUD_CLKID_TDMOUT_C_LRCLK>, - <&clkc_audio AUD_CLKID_TDMOUT_C_LRCLK>; - clock-names = "pclk", "sclk", "sclk_sel", - "lrclk", "lrclk_sel"; - status = "disabled"; - }; - - spdifout_b: audio-controller@680 { - compatible = "amlogic,g12a-spdifout", - "amlogic,axg-spdifout"; - reg = <0x0 0x680 0x0 0x50>; - #sound-dai-cells = <0>; - sound-name-prefix = "SPDIFOUT_B"; - clocks = <&clkc_audio AUD_CLKID_SPDIFOUT_B>, - <&clkc_audio AUD_CLKID_SPDIFOUT_B_CLK>; - clock-names = "pclk", "mclk"; - status = "disabled"; - }; - - tohdmitx: audio-controller@744 { - compatible = "amlogic,g12a-tohdmitx"; - reg = <0x0 0x744 0x0 0x4>; - #sound-dai-cells = <1>; - sound-name-prefix = "TOHDMITX"; - status = "disabled"; - }; - }; - - usb3_pcie_phy: phy@46000 { - compatible = "amlogic,g12a-usb3-pcie-phy"; - reg = <0x0 0x46000 0x0 0x2000>; - clocks = <&clkc CLKID_PCIE_PLL>; - clock-names = "ref_clk"; - resets = <&reset RESET_PCIE_PHY>; - reset-names = "phy"; - assigned-clocks = <&clkc CLKID_PCIE_PLL>; - assigned-clock-rates = <100000000>; - #phy-cells = <1>; - }; - - eth_phy: mdio-multiplexer@4c000 { - compatible = "amlogic,g12a-mdio-mux"; - reg = <0x0 0x4c000 0x0 0xa4>; - clocks = <&clkc CLKID_ETH_PHY>, - <&xtal>, - <&clkc CLKID_MPLL_50M>; - clock-names = "pclk", "clkin0", "clkin1"; - mdio-parent-bus = <&mdio0>; - #address-cells = <1>; - #size-cells = <0>; - - ext_mdio: mdio@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - }; - - int_mdio: mdio@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - - internal_ephy: ethernet_phy@8 { - compatible = "ethernet-phy-id0180.3301", - "ethernet-phy-ieee802.3-c22"; - interrupts = ; - reg = <8>; - max-speed = <100>; - }; - }; - }; - }; - - aobus: bus@ff800000 { - compatible = "simple-bus"; - reg = <0x0 0xff800000 0x0 0x100000>; - #address-cells = <2>; - #size-cells = <2>; - ranges = <0x0 0x0 0x0 0xff800000 0x0 0x100000>; - - rti: sys-ctrl@0 { - compatible = "amlogic,meson-gx-ao-sysctrl", - "simple-mfd", "syscon"; - reg = <0x0 0x0 0x0 0x100>; - #address-cells = <2>; - #size-cells = <2>; - ranges = <0x0 0x0 0x0 0x0 0x0 0x100>; - - clkc_AO: clock-controller { - compatible = "amlogic,meson-g12a-aoclkc"; - #clock-cells = <1>; - #reset-cells = <1>; - clocks = <&xtal>, <&clkc CLKID_CLK81>; - clock-names = "xtal", "mpeg-clk"; - }; - - pwrc_vpu: power-controller-vpu { - compatible = "amlogic,meson-g12a-pwrc-vpu"; - #power-domain-cells = <0>; - amlogic,hhi-sysctrl = <&hhi>; - resets = <&reset RESET_VIU>, - <&reset RESET_VENC>, - <&reset RESET_VCBUS>, - <&reset RESET_BT656>, - <&reset RESET_RDMA>, - <&reset RESET_VENCI>, - <&reset RESET_VENCP>, - <&reset RESET_VDAC>, - <&reset RESET_VDI6>, - <&reset RESET_VENCL>, - <&reset RESET_VID_LOCK>; - clocks = <&clkc CLKID_VPU>, - <&clkc CLKID_VAPB>; - clock-names = "vpu", "vapb"; - /* - * VPU clocking is provided by two identical clock paths - * VPU_0 and VPU_1 muxed to a single clock by a glitch - * free mux to safely change frequency while running. - * Same for VAPB but with a final gate after the glitch free mux. - */ - assigned-clocks = <&clkc CLKID_VPU_0_SEL>, - <&clkc CLKID_VPU_0>, - <&clkc CLKID_VPU>, /* Glitch free mux */ - <&clkc CLKID_VAPB_0_SEL>, - <&clkc CLKID_VAPB_0>, - <&clkc CLKID_VAPB_SEL>; /* Glitch free mux */ - assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>, - <0>, /* Do Nothing */ - <&clkc CLKID_VPU_0>, - <&clkc CLKID_FCLK_DIV4>, - <0>, /* Do Nothing */ - <&clkc CLKID_VAPB_0>; - assigned-clock-rates = <0>, /* Do Nothing */ - <666666666>, - <0>, /* Do Nothing */ - <0>, /* Do Nothing */ - <250000000>, - <0>; /* Do Nothing */ - }; - - ao_pinctrl: pinctrl@14 { - compatible = "amlogic,meson-g12a-aobus-pinctrl"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - gpio_ao: bank@14 { - reg = <0x0 0x14 0x0 0x8>, - <0x0 0x1c 0x0 0x8>, - <0x0 0x24 0x0 0x14>; - reg-names = "mux", - "ds", - "gpio"; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&ao_pinctrl 0 0 15>; - }; - - i2c_ao_sck_pins: i2c_ao_sck_pins { - mux { - groups = "i2c_ao_sck"; - function = "i2c_ao"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - i2c_ao_sda_pins: i2c_ao_sda { - mux { - groups = "i2c_ao_sda"; - function = "i2c_ao"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - i2c_ao_sck_e_pins: i2c_ao_sck_e { - mux { - groups = "i2c_ao_sck_e"; - function = "i2c_ao"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - i2c_ao_sda_e_pins: i2c_ao_sda_e { - mux { - groups = "i2c_ao_sda_e"; - function = "i2c_ao"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - mclk0_ao_pins: mclk0-ao { - mux { - groups = "mclk0_ao"; - function = "mclk0_ao"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - tdm_ao_b_din0_pins: tdm-ao-b-din0 { - mux { - groups = "tdm_ao_b_din0"; - function = "tdm_ao_b"; - bias-disable; - }; - }; - - spdif_ao_out_pins: spdif-ao-out { - mux { - groups = "spdif_ao_out"; - function = "spdif_ao_out"; - drive-strength-microamp = <500>; - bias-disable; - }; - }; - - tdm_ao_b_din1_pins: tdm-ao-b-din1 { - mux { - groups = "tdm_ao_b_din1"; - function = "tdm_ao_b"; - bias-disable; - }; - }; - - tdm_ao_b_din2_pins: tdm-ao-b-din2 { - mux { - groups = "tdm_ao_b_din2"; - function = "tdm_ao_b"; - bias-disable; - }; - }; - - tdm_ao_b_dout0_pins: tdm-ao-b-dout0 { - mux { - groups = "tdm_ao_b_dout0"; - function = "tdm_ao_b"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - tdm_ao_b_dout1_pins: tdm-ao-b-dout1 { - mux { - groups = "tdm_ao_b_dout1"; - function = "tdm_ao_b"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - tdm_ao_b_dout2_pins: tdm-ao-b-dout2 { - mux { - groups = "tdm_ao_b_dout2"; - function = "tdm_ao_b"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - tdm_ao_b_fs_pins: tdm-ao-b-fs { - mux { - groups = "tdm_ao_b_fs"; - function = "tdm_ao_b"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - tdm_ao_b_sclk_pins: tdm-ao-b-sclk { - mux { - groups = "tdm_ao_b_sclk"; - function = "tdm_ao_b"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - tdm_ao_b_slv_fs_pins: tdm-ao-b-slv-fs { - mux { - groups = "tdm_ao_b_slv_fs"; - function = "tdm_ao_b"; - bias-disable; - }; - }; - - tdm_ao_b_slv_sclk_pins: tdm-ao-b-slv-sclk { - mux { - groups = "tdm_ao_b_slv_sclk"; - function = "tdm_ao_b"; - bias-disable; - }; - }; - - uart_ao_a_pins: uart-a-ao { - mux { - groups = "uart_ao_a_tx", - "uart_ao_a_rx"; - function = "uart_ao_a"; - bias-disable; - }; - }; - - uart_ao_a_cts_rts_pins: uart-ao-a-cts-rts { - mux { - groups = "uart_ao_a_cts", - "uart_ao_a_rts"; - function = "uart_ao_a"; - bias-disable; - }; - }; - - pwm_ao_a_pins: pwm-ao-a { - mux { - groups = "pwm_ao_a"; - function = "pwm_ao_a"; - bias-disable; - }; - }; - - pwm_ao_b_pins: pwm-ao-b { - mux { - groups = "pwm_ao_b"; - function = "pwm_ao_b"; - bias-disable; - }; - }; - - pwm_ao_c_4_pins: pwm-ao-c-4 { - mux { - groups = "pwm_ao_c_4"; - function = "pwm_ao_c"; - bias-disable; - }; - }; - - pwm_ao_c_6_pins: pwm-ao-c-6 { - mux { - groups = "pwm_ao_c_6"; - function = "pwm_ao_c"; - bias-disable; - }; - }; - - pwm_ao_d_5_pins: pwm-ao-d-5 { - mux { - groups = "pwm_ao_d_5"; - function = "pwm_ao_d"; - bias-disable; - }; - }; - - pwm_ao_d_10_pins: pwm-ao-d-10 { - mux { - groups = "pwm_ao_d_10"; - function = "pwm_ao_d"; - bias-disable; - }; - }; - - pwm_ao_d_e_pins: pwm-ao-d-e { - mux { - groups = "pwm_ao_d_e"; - function = "pwm_ao_d"; - }; - }; - - remote_input_ao_pins: remote-input-ao { - mux { - groups = "remote_ao_input"; - function = "remote_ao_input"; - bias-disable; - }; - }; - }; - }; - - cec_AO: cec@100 { - compatible = "amlogic,meson-gx-ao-cec"; - reg = <0x0 0x00100 0x0 0x14>; - interrupts = ; - clocks = <&clkc_AO CLKID_AO_CEC>; - clock-names = "core"; - status = "disabled"; - }; - - sec_AO: ao-secure@140 { - compatible = "amlogic,meson-gx-ao-secure", "syscon"; - reg = <0x0 0x140 0x0 0x140>; - amlogic,has-chip-id; - }; - - cecb_AO: cec@280 { - compatible = "amlogic,meson-g12a-ao-cec"; - reg = <0x0 0x00280 0x0 0x1c>; - interrupts = ; - clocks = <&clkc_AO CLKID_AO_CTS_OSCIN>; - clock-names = "oscin"; - status = "disabled"; - }; - - pwm_AO_cd: pwm@2000 { - compatible = "amlogic,meson-g12a-ao-pwm-cd"; - reg = <0x0 0x2000 0x0 0x20>; - #pwm-cells = <3>; - status = "disabled"; - }; - - uart_AO: serial@3000 { - compatible = "amlogic,meson-gx-uart", - "amlogic,meson-ao-uart"; - reg = <0x0 0x3000 0x0 0x18>; - interrupts = ; - clocks = <&xtal>, <&clkc_AO CLKID_AO_UART>, <&xtal>; - clock-names = "xtal", "pclk", "baud"; - reset = <&clkc_AO RESET_AO_UART>; - status = "disabled"; - }; - - uart_AO_B: serial@4000 { - compatible = "amlogic,meson-gx-uart", - "amlogic,meson-ao-uart"; - reg = <0x0 0x4000 0x0 0x18>; - interrupts = ; - clocks = <&xtal>, <&clkc_AO CLKID_AO_UART2>, <&xtal>; - clock-names = "xtal", "pclk", "baud"; - reset = <&clkc_AO RESET_AO_UART2>; - status = "disabled"; - }; - - i2c_AO: i2c@5000 { - compatible = "amlogic,meson-axg-i2c"; - status = "disabled"; - reg = <0x0 0x05000 0x0 0x20>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&clkc CLKID_I2C>; - }; - - pwm_AO_ab: pwm@7000 { - compatible = "amlogic,meson-g12a-ao-pwm-ab"; - reg = <0x0 0x7000 0x0 0x20>; - #pwm-cells = <3>; - status = "disabled"; - }; - - ir: ir@8000 { - compatible = "amlogic,meson-gxbb-ir"; - reg = <0x0 0x8000 0x0 0x20>; - interrupts = ; - status = "disabled"; - }; - - saradc: adc@9000 { - compatible = "amlogic,meson-g12a-saradc", - "amlogic,meson-saradc"; - reg = <0x0 0x9000 0x0 0x48>; - #io-channel-cells = <1>; - interrupts = ; - clocks = <&xtal>, - <&clkc_AO CLKID_AO_SAR_ADC>, - <&clkc_AO CLKID_AO_SAR_ADC_CLK>, - <&clkc_AO CLKID_AO_SAR_ADC_SEL>; - clock-names = "clkin", "core", "adc_clk", "adc_sel"; - status = "disabled"; - }; - }; - - vdec: video-decoder@ff620000 { - compatible = "amlogic,g12a-vdec"; - reg = <0x0 0xff620000 0x0 0x10000>, - <0x0 0xffd0e180 0x0 0xe4>; - reg-names = "dos", "esparser"; - - interrupts = , - ; - interrupt-names = "vdec", "esparser"; - - amlogic,ao-sysctrl = <&rti>; - amlogic,canvas = <&canvas>; - - clocks = <&clkc CLKID_PARSER>, - <&clkc CLKID_DOS>, - <&clkc CLKID_VDEC_1>, - <&clkc CLKID_VDEC_HEVC>, - <&clkc CLKID_VDEC_HEVCF>; - clock-names = "dos_parser", "dos", "vdec_1", "vdec_hevc", "vdec_hevcf"; - resets = <&reset RESET_PARSER>; - reset-names = "esparser"; - }; - - vpu: vpu@ff900000 { - compatible = "amlogic,meson-g12a-vpu"; - reg = <0x0 0xff900000 0x0 0x100000>, - <0x0 0xff63c000 0x0 0x1000>; - reg-names = "vpu", "hhi"; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - amlogic,canvas = <&canvas>; - power-domains = <&pwrc_vpu>; - - /* CVBS VDAC output port */ - cvbs_vdac_port: port@0 { - reg = <0>; - }; - - /* HDMI-TX output port */ - hdmi_tx_port: port@1 { - reg = <1>; - - hdmi_tx_out: endpoint { - remote-endpoint = <&hdmi_tx_in>; - }; - }; - }; - - sram: sram@fffc0000 { - compatible = "mmio-sram"; - reg = <0x0 0xfffc0000 0x0 0x20000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x0 0xfffc0000 0x20000>; - - cpu_scp_lpri: scp-shmem@13000 { - compatible = "amlogic,meson-axg-scp-shmem"; - reg = <0x13000 0x400>; - }; - - cpu_scp_hpri: scp-shmem@13400 { - compatible = "amlogic,meson-axg-scp-shmem"; - reg = <0x13400 0x400>; - }; - }; - - gic: interrupt-controller@ffc01000 { - compatible = "arm,gic-400"; - reg = <0x0 0xffc01000 0 0x1000>, - <0x0 0xffc02000 0 0x2000>, - <0x0 0xffc04000 0 0x2000>, - <0x0 0xffc06000 0 0x2000>; - interrupt-controller; - interrupts = ; - #interrupt-cells = <3>; - #address-cells = <0>; - }; - - cbus: bus@ffd00000 { - compatible = "simple-bus"; - reg = <0x0 0xffd00000 0x0 0x100000>; - #address-cells = <2>; - #size-cells = <2>; - ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x100000>; - - reset: reset-controller@1004 { - compatible = "amlogic,meson-g12a-reset", - "amlogic,meson-axg-reset"; - reg = <0x0 0x1004 0x0 0x9c>; - #reset-cells = <1>; - }; - - pwm_ef: pwm@19000 { - compatible = "amlogic,meson-g12a-ee-pwm"; - reg = <0x0 0x19000 0x0 0x20>; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm_cd: pwm@1a000 { - compatible = "amlogic,meson-g12a-ee-pwm"; - reg = <0x0 0x1a000 0x0 0x20>; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm_ab: pwm@1b000 { - compatible = "amlogic,meson-g12a-ee-pwm"; - reg = <0x0 0x1b000 0x0 0x20>; - #pwm-cells = <3>; - status = "disabled"; - }; - - i2c3: i2c@1c000 { - compatible = "amlogic,meson-axg-i2c"; - status = "disabled"; - reg = <0x0 0x1c000 0x0 0x20>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&clkc CLKID_I2C>; - }; - - i2c2: i2c@1d000 { - compatible = "amlogic,meson-axg-i2c"; - status = "disabled"; - reg = <0x0 0x1d000 0x0 0x20>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&clkc CLKID_I2C>; - }; - - i2c1: i2c@1e000 { - compatible = "amlogic,meson-axg-i2c"; - status = "disabled"; - reg = <0x0 0x1e000 0x0 0x20>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&clkc CLKID_I2C>; - }; - - i2c0: i2c@1f000 { - compatible = "amlogic,meson-axg-i2c"; - status = "disabled"; - reg = <0x0 0x1f000 0x0 0x20>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&clkc CLKID_I2C>; - }; - - clk_msr: clock-measure@18000 { - compatible = "amlogic,meson-g12a-clk-measure"; - reg = <0x0 0x18000 0x0 0x10>; - }; - - uart_C: serial@22000 { - compatible = "amlogic,meson-gx-uart"; - reg = <0x0 0x22000 0x0 0x18>; - interrupts = ; - clocks = <&xtal>, <&clkc CLKID_UART2>, <&xtal>; - clock-names = "xtal", "pclk", "baud"; - status = "disabled"; - }; - - uart_B: serial@23000 { - compatible = "amlogic,meson-gx-uart"; - reg = <0x0 0x23000 0x0 0x18>; - interrupts = ; - clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>; - clock-names = "xtal", "pclk", "baud"; - status = "disabled"; - }; - - uart_A: serial@24000 { - compatible = "amlogic,meson-gx-uart"; - reg = <0x0 0x24000 0x0 0x18>; - interrupts = ; - clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>; - clock-names = "xtal", "pclk", "baud"; - status = "disabled"; - }; - }; - - sd_emmc_a: sd@ffe03000 { - compatible = "amlogic,meson-axg-mmc"; - reg = <0x0 0xffe03000 0x0 0x800>; - interrupts = ; - status = "disabled"; - clocks = <&clkc CLKID_SD_EMMC_A>, - <&clkc CLKID_SD_EMMC_A_CLK0>, - <&clkc CLKID_FCLK_DIV2>; - clock-names = "core", "clkin0", "clkin1"; - resets = <&reset RESET_SD_EMMC_A>; - amlogic,dram-access-quirk; - }; - - sd_emmc_b: sd@ffe05000 { - compatible = "amlogic,meson-axg-mmc"; - reg = <0x0 0xffe05000 0x0 0x800>; - interrupts = ; - status = "disabled"; - clocks = <&clkc CLKID_SD_EMMC_B>, - <&clkc CLKID_SD_EMMC_B_CLK0>, - <&clkc CLKID_FCLK_DIV2>; - clock-names = "core", "clkin0", "clkin1"; - resets = <&reset RESET_SD_EMMC_B>; - }; - - sd_emmc_c: mmc@ffe07000 { - compatible = "amlogic,meson-axg-mmc"; - reg = <0x0 0xffe07000 0x0 0x800>; - interrupts = ; - status = "disabled"; - clocks = <&clkc CLKID_SD_EMMC_C>, - <&clkc CLKID_SD_EMMC_C_CLK0>, - <&clkc CLKID_FCLK_DIV2>; - clock-names = "core", "clkin0", "clkin1"; - resets = <&reset RESET_SD_EMMC_C>; - }; - - usb: usb@ffe09000 { - status = "disabled"; - compatible = "amlogic,meson-g12a-usb-ctrl"; - reg = <0x0 0xffe09000 0x0 0xa0>; - interrupts = ; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - clocks = <&clkc CLKID_USB>; - resets = <&reset RESET_USB>; - - dr_mode = "otg"; - - phys = <&usb2_phy0>, <&usb2_phy1>, - <&usb3_pcie_phy PHY_TYPE_USB3>; - phy-names = "usb2-phy0", "usb2-phy1", "usb3-phy0"; - - dwc2: usb@ff400000 { - compatible = "amlogic,meson-g12a-usb", "snps,dwc2"; - reg = <0x0 0xff400000 0x0 0x40000>; - interrupts = ; - clocks = <&clkc CLKID_USB1_DDR_BRIDGE>; - clock-names = "ddr"; - phys = <&usb2_phy1>; - dr_mode = "peripheral"; - g-rx-fifo-size = <192>; - g-np-tx-fifo-size = <128>; - g-tx-fifo-size = <128 128 16 16 16>; - }; - - dwc3: usb@ff500000 { - compatible = "snps,dwc3"; - reg = <0x0 0xff500000 0x0 0x100000>; - interrupts = ; - dr_mode = "host"; - snps,dis_u2_susphy_quirk; - snps,quirk-frame-length-adjustment; - }; - }; - - mali: gpu@ffe40000 { - compatible = "amlogic,meson-g12a-mali", "arm,mali-bifrost"; - reg = <0x0 0xffe40000 0x0 0x40000>; - interrupt-parent = <&gic>; - interrupts = , - , - ; - interrupt-names = "gpu", "mmu", "job"; - clocks = <&clkc CLKID_MALI>; - resets = <&reset RESET_DVALIN_CAPB3>, <&reset RESET_DVALIN>; - - /* - * Mali clocking is provided by two identical clock paths - * MALI_0 and MALI_1 muxed to a single clock by a glitch - * free mux to safely change frequency while running. - */ - assigned-clocks = <&clkc CLKID_MALI_0_SEL>, - <&clkc CLKID_MALI_0>, - <&clkc CLKID_MALI>; /* Glitch free mux */ - assigned-clock-parents = <&clkc CLKID_FCLK_DIV2P5>, - <0>, /* Do Nothing */ - <&clkc CLKID_MALI_0>; - assigned-clock-rates = <0>, /* Do Nothing */ - <800000000>, - <0>; /* Do Nothing */ - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; - }; - - xtal: xtal-clk { - compatible = "fixed-clock"; - clock-frequency = <24000000>; - clock-output-names = "xtal"; - #clock-cells = <0>; - }; - +&sd_emmc_a { + amlogic,dram-access-quirk; }; diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12b.dtsi index 9e88e513b22d..ae63cd610892 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12b.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-g12b.dtsi @@ -4,12 +4,15 @@ * Author: Neil Armstrong */ -#include "meson-g12a.dtsi" +#include "meson-g12-common.dtsi" / { compatible = "amlogic,g12b"; cpus { + #address-cells = <0x2>; + #size-cells = <0x0>; + cpu-map { cluster0 { core0 { @@ -40,8 +43,21 @@ }; }; - /delete-node/ cpu@2; - /delete-node/ cpu@3; + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0 0x0>; + enable-method = "psci"; + next-level-cache = <&l2>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0 0x1>; + enable-method = "psci"; + next-level-cache = <&l2>; + }; cpu100: cpu@100 { device_type = "cpu"; @@ -74,6 +90,10 @@ enable-method = "psci"; next-level-cache = <&l2>; }; + + l2: l2-cache0 { + compatible = "cache"; + }; }; }; From patchwork Thu Jun 20 15:00:09 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neil Armstrong X-Patchwork-Id: 11007069 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 93108924 for ; Thu, 20 Jun 2019 15:04:43 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 833A72883C for ; Thu, 20 Jun 2019 15:04:43 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 72DD328837; Thu, 20 Jun 2019 15:04:43 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 2187D2885E for ; Thu, 20 Jun 2019 15:04:43 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=emDsahoQAxvR1NTgxIXrOBGhwTpOMn47FVvsj8mG680=; b=QvGYVKzBoj7OMO ZN/9j02oK7fp8Fxi8x1MMSOdqjKyrSfsmfQ3ZQDZow+hsR8iXLZGsI9JnD2SjlWMa3nCvc/jTdtem zq9uPNFTdu3DQXt0q02cpmpoZzw3uDDkJOFQeD0v9sX6VLL1L940e+2+qLtcSwP5FHfnveajMMjWw j7ayQ4oyrTXOjzBrdn7Qh4VCRjXjyIDnpvqAY/bpfxP1eaYO53bAGLWwABWVfSOox53np6oLbfDFt TOBg3p9m0Q7W8DELBPZpRz3SdyW48rKgNe2KKzTc2+K4Z2sjoP1MOfbh9VZv71EewXL6Niqgjw+ER L3eEFHRPiUvOqPoqssTQ==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92 #3 (Red Hat Linux)) id 1hdycE-0006SA-L3; Thu, 20 Jun 2019 15:04:42 +0000 Received: from mail-wm1-x344.google.com ([2a00:1450:4864:20::344]) by bombadil.infradead.org with esmtps (Exim 4.92 #3 (Red Hat Linux)) id 1hdyYD-0003Hk-55 for linux-amlogic@lists.infradead.org; Thu, 20 Jun 2019 15:00:35 +0000 Received: by mail-wm1-x344.google.com with SMTP id s3so3409576wms.2 for ; Thu, 20 Jun 2019 08:00:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=eF8xBGeTljvvRz8oIGPjn0ZgbNxxAvWP0tXIK0uht64=; b=G+jGjIMvhLDlHlsS6ZUQa62iQPcD1g9joTMkE88tdYoN0qASnjniGNFYJPZU+MLSCX H7EPMSh7fkUYj/ww1ZZ4miAqZl1duvLB+21CLWFEY9BOKNgXt9caf9pxRR0j94gTykle oZzT0WdZTg3PVn2yUYMarDfak4tAp1QeolW/5s6jNYm8aZxbPu/oQRZCVsjn8zZDkjR3 g9qrP/pXJWwTpDIiKG3L5k4I7FRfpiQ4v2MH31zO/f3/tgspZsezciharlR3DlUw9mXJ 0aaBOLMZUcIGomlBEMSR0QE/fZONdiICEkN1HZ0hE/PFo6spyeh0+0S+2jraLAi9vYs1 AMQA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=eF8xBGeTljvvRz8oIGPjn0ZgbNxxAvWP0tXIK0uht64=; b=TSSl6h8/sNG56grMQY2UX5temTEzJqmNAzcs4Lmq2xYo1M3eQ6p5jM8e6wf0XL+0O8 INqXWEMMqO0XUPjQXXV9FeOREqYW+XYEzIDHWRWLpruEO/HWRIFQK1OlQhSeVWlXf3HF T1Vhy41+xmDHGYdQuVTD44tJAEpEQ48feQ5I4ZmakL3p8DdqcsYuu/cQTp2frSdDqEmW ou7Pz3bEhcNCwlzyRPyjVoMGWy1PMvQDJe6/5q6zQacdda9vZ5fi+PMEkwJd3mutP2B1 F2dyrsIGhV8LPPf/c+FEJL7irzOey/h4KGDHWlVVwDaDt/RkveQ9OSzkNlhxW8vqEVLz FZdg== X-Gm-Message-State: APjAAAUM/RKk0s7hDY5T6PvTME3XLaIqWlpuW2pU+srH88Ku91bQQEjb /PTl8frdjr67zoB2MzwzdrIHTg== X-Google-Smtp-Source: APXvYqyB0M/8J7elbFZ7JqzPsyIKsmt8dD5yRCndjrBFTtmLDZMEgDCJQgbv0JCT6BR9I/9CVeq96w== X-Received: by 2002:a1c:1fc2:: with SMTP id f185mr56296wmf.154.1561042831759; Thu, 20 Jun 2019 08:00:31 -0700 (PDT) Received: from bender.baylibre.local (lmontsouris-657-1-212-31.w90-63.abo.wanadoo.fr. [90.63.244.31]) by smtp.gmail.com with ESMTPSA id o126sm6802520wmo.1.2019.06.20.08.00.30 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 20 Jun 2019 08:00:31 -0700 (PDT) From: Neil Armstrong To: jbrunet@baylibre.com, khilman@baylibre.com Subject: [RFC/RFT 10/14] arm64: dts: meson-g12-common: add pwm_a on GPIOE_2 pinmux Date: Thu, 20 Jun 2019 17:00:09 +0200 Message-Id: <20190620150013.13462-11-narmstrong@baylibre.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190620150013.13462-1-narmstrong@baylibre.com> References: <20190620150013.13462-1-narmstrong@baylibre.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190620_080033_212444_F3E288D1 X-CRM114-Status: UNSURE ( 9.36 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-amlogic@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Neil Armstrong , martin.blumenstingl@googlemail.com, linux-kernel@vger.kernel.org, linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org Sender: "linux-amlogic" Errors-To: linux-amlogic-bounces+patchwork-linux-amlogic=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Add the ao_pinctrl subnode for the pwm_a function on GPIOE_2. Signed-off-by: Neil Armstrong --- arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi index 2baa04303762..76484801478d 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi @@ -1984,6 +1984,14 @@ }; }; + pwm_a_e_pins: pwm-a-e { + mux { + groups = "pwm_a_e"; + function = "pwm_a_e"; + bias-disable; + }; + }; + pwm_ao_a_pins: pwm-ao-a { mux { groups = "pwm_ao_a"; From patchwork Thu Jun 20 15:00:10 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neil Armstrong X-Patchwork-Id: 11007073 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 17DAD14BB for ; Thu, 20 Jun 2019 15:05:08 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 06DE928846 for ; Thu, 20 Jun 2019 15:05:08 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id EF2E128837; Thu, 20 Jun 2019 15:05:07 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED autolearn=unavailable version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 5F47C2880C for ; Thu, 20 Jun 2019 15:05:07 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=r9cEOVreqdfcAksp1y5BY1dH+wRn6EOXnZA1/8bt+MM=; b=cJxSp9VQgkSXjV OZDoq/KWsUgRUJPIdk51/MZ+sp7Sz7watFYBybiXemWM6kD+d+VkLwetEzDqe4SR0gLM8T5+Z0Z/x azHNCjvVn6S/m9Aiz4uvJAwTMs9yMRyB7TWgZSw/Y3J4CFUl1tdbDv9BodNkTfFMzVNgDCUWaOA9L bDeHi47RgiYL6j1dlm1C7R33LDTOZT56kw5yWlp68LIIvzcc9FYUxIMnloSnNU7P6f5V0jMoT/eas 8CybcS8le8KgFB3CHpbFtKcAts71V7V3di4KpgUZwaCV+IFBIBZjidVyinrR8yHynMHJw5QX9g4fl ttnBQASMwGRSlh40F+aw==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92 #3 (Red Hat Linux)) id 1hdycb-0006tb-0F; Thu, 20 Jun 2019 15:05:05 +0000 Received: from mail-wr1-x430.google.com ([2a00:1450:4864:20::430]) by bombadil.infradead.org with esmtps (Exim 4.92 #3 (Red Hat Linux)) id 1hdyYE-0003IP-QA for linux-amlogic@lists.infradead.org; Thu, 20 Jun 2019 15:00:38 +0000 Received: by mail-wr1-x430.google.com with SMTP id p13so3355342wru.10 for ; Thu, 20 Jun 2019 08:00:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=C68d+qcYguHz3zXhv5eHfQ0ZAq7PycGdrc5Cah7BDk8=; b=q7N99tjjzhN3+LiLDy4XSG+Gx7+YBnKRo480RP/3ZjsunVDNZDHveRkH/fnqlxH7gD /1G4pCqT4MeJ18eq9ir+0HgAJR6JKyYdRD/DbF7xBlUXfI3t/UajywczG0oY1fICNK2H MrCPZmxutbZ6yCXVV7t3gsjA8tRtZzj4Y0ONAzVb4wRs4BMP/bReGXley9Sqo/XsjzoP 4wTPRi8VIIjf7kiySou96AwTW4CNtm3OWC3TSQj37L/SSNqyG/wYegbtv47GTVgBvlFT azXZdbCCDMP6bb1j/ehf5HawzD+uHHfihTOUcox/C/pq/+k783QM/nhqc9ytGfdacg8O MzVg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=C68d+qcYguHz3zXhv5eHfQ0ZAq7PycGdrc5Cah7BDk8=; b=ZIUt/+zAvgruchUNbk8ZRwezHULwxofb5HuIwN0uZQRT0zpFMKAvm68Ej+iUDtDbZ2 x0ADFFuUdIpoq2FCYkBg9uD1Ad87AqfYtvba1I+az6SoESTRlQ1Zmj0psBZLhJ+Sx9jp wiOPx/D6FvNq0xz+fXoChL4S3pUhqraBVE8IPpRSUa2Rtr/GAgI18wpNIM8KrwMIGK+a ts1bX/RZB1EbIorPWPflxExH1IaJf8hC7xSP7jjwWL2KnsS4UcroCZWC6emtCIqnIeMM EJgw7DccA2ONzAyEj+tkensoTvriG/qkulp/fGN84IMYBRyz78NznyAMqJ9Bqruv0I0n QuQQ== X-Gm-Message-State: APjAAAVDyM+O7EdpP2hz925uI/QYSdJCBUKH2eLMY/NLIAVs/t+neqQX zYdBvc2g6Ss7Jf6SdlJum8U+Ig== X-Google-Smtp-Source: APXvYqzErbqy4BohHinkppm/dPifMbl7dbPGdWxW8WZ7N66gJ3ZM2HTJNXQ2nC2N7QCBPq1HW1MRaA== X-Received: by 2002:adf:f6cb:: with SMTP id y11mr4725863wrp.245.1561042832953; Thu, 20 Jun 2019 08:00:32 -0700 (PDT) Received: from bender.baylibre.local (lmontsouris-657-1-212-31.w90-63.abo.wanadoo.fr. [90.63.244.31]) by smtp.gmail.com with ESMTPSA id o126sm6802520wmo.1.2019.06.20.08.00.31 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 20 Jun 2019 08:00:32 -0700 (PDT) From: Neil Armstrong To: jbrunet@baylibre.com, khilman@baylibre.com Subject: [RFC/RFT 11/14] arm64: dts: meson-g12a: add cpus OPP table Date: Thu, 20 Jun 2019 17:00:10 +0200 Message-Id: <20190620150013.13462-12-narmstrong@baylibre.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190620150013.13462-1-narmstrong@baylibre.com> References: <20190620150013.13462-1-narmstrong@baylibre.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190620_080034_895430_A748A9A5 X-CRM114-Status: GOOD ( 11.98 ) X-BeenThere: linux-amlogic@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Neil Armstrong , martin.blumenstingl@googlemail.com, linux-kernel@vger.kernel.org, linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org Sender: "linux-amlogic" Errors-To: linux-amlogic-bounces+patchwork-linux-amlogic=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Add the OPP table taken from the vendor u200 and u211 DTS. The Amlogic G12A SoC seems to available in 3 types : - low-speed: up to 1,8GHz - mid-speed: up to 1,908GHz - high-speed: up to 2.1GHz And the S905X2 opp voltages are slightly higher than the S905D2 OPP voltages for the low-speed table. This adds the conservative OPP table with the S905X2 higher voltages and the maximum low-speed OPP frequency. The values were tested to be stable on an Amlogic U200 Reference Board, SeiRobotics SEI510 and X96 Max Set-Top-Boxes running the arm64 cpuburn at [1] and cycling between all the possible cpufreq translations and checking the final frequency using the clock-measurer, script at [2]. [1] https://github.com/ssvb/cpuburn-arm/blob/master/cpuburn-a53.S [2] https://gist.github.com/superna9999/d4de964dbc0f84b7d527e1df2ddea25f Signed-off-by: Neil Armstrong --- arch/arm64/boot/dts/amlogic/meson-g12a.dtsi | 62 ++++++++++++++++++++- 1 file changed, 59 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi index ac15967bb7fa..ba9aab39fd95 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi @@ -48,8 +48,64 @@ compatible = "cache"; }; }; -}; -&sd_emmc_a { - amlogic,dram-access-quirk; + cpu_opp_table: opp-table { + compatible = "operating-points-v2"; + opp-shared; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + opp-microvolt = <731000>; + }; + + opp-250000000 { + opp-hz = /bits/ 64 <250000000>; + opp-microvolt = <731000>; + }; + + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + opp-microvolt = <731000>; + }; + + opp-667000000 { + opp-hz = /bits/ 64 <666666666>; + opp-microvolt = <731000>; + }; + + opp-1000000000 { + opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = <731000>; + }; + + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <731000>; + }; + + opp-1398000000 { + opp-hz = /bits/ 64 <1398000000>; + opp-microvolt = <761000>; + }; + + opp-1512000000 { + opp-hz = /bits/ 64 <1512000000>; + opp-microvolt = <791000>; + }; + + opp-1608000000 { + opp-hz = /bits/ 64 <1608000000>; + opp-microvolt = <831000>; + }; + + opp-1704000000 { + opp-hz = /bits/ 64 <1704000000>; + opp-microvolt = <861000>; + }; + + opp-1800000000 { + opp-hz = /bits/ 64 <1800000000>; + opp-microvolt = <981000>; + }; + }; }; From patchwork Thu Jun 20 15:00:11 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neil Armstrong X-Patchwork-Id: 11007083 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 7591514E5 for ; Thu, 20 Jun 2019 15:06:11 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 64CF528841 for ; Thu, 20 Jun 2019 15:06:11 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 5917528862; Thu, 20 Jun 2019 15:06:11 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED autolearn=unavailable version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id D494128841 for ; Thu, 20 Jun 2019 15:06:10 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=izJtiicVwu9EXKwbBpbugZO8Ap/rjU9anmSj7BDOLJc=; b=HI7ZG5cE02oato lHsxYZz0ooImC5C2xsMcD+A+e3wst4y/0OgunGmoYacw1J2S5WNpIURNGcMalDApoyoFY9OQ/W99Z xtYse1Qvs7FnXGY/WKwAaychTFh+YEiYoXN0BtRttb9PxAtIZa5OYNglBDCO+aVlonn0aoEKVYxd+ H1l3WdMaLSkxcsjSDZm5cR371jXdG3tC0LMfNldYclHAxXMVDbLK3j4IOuEJ3iYem4F4dQgcLgwka qglfwtRF8Rnf8OPc8zmtzXwivTIMo7YST3rl/40xepXPXq2XzXyQyZOkEpxk6gpqsOHn4J+PBbjYT F5ZBn2eUz5IYpvuCVBFw==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92 #3 (Red Hat Linux)) id 1hdyde-0000Pl-Bl; Thu, 20 Jun 2019 15:06:10 +0000 Received: from mail-wr1-x42e.google.com ([2a00:1450:4864:20::42e]) by bombadil.infradead.org with esmtps (Exim 4.92 #3 (Red Hat Linux)) id 1hdyYG-0003J1-1v for linux-amlogic@lists.infradead.org; Thu, 20 Jun 2019 15:00:41 +0000 Received: by mail-wr1-x42e.google.com with SMTP id v14so3392940wrr.4 for ; Thu, 20 Jun 2019 08:00:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=N2giQ2yIsAWn8MusPqgS1CP/DkqViRRuAeJS4LgppK4=; b=b+LXYfMJu8K3Irv+z9mH0+qqqhmw6l1ehg+Q35v6Z88zfJG1MOwscikQRxJh2njG4h WVzqtKd2aNO45HKxR7zXGNDOBYsvcURb2Un5PaXRJxB2sZI+M+6ns3+HXteJGNxoR4QD Igtbd+g2i4atWlx+tudsnSlm0177tLf1vM11HIZ5u1ymg8sRxUW8PdliGw6s62tFIm4m iG3L6EDDuwCh+LiAWnJqlJoO4pj8TdVbl4VWxYqLYTn60qxHgSrNlivcZf1nz1Xr/Uz3 OkSyYR+uuP8IQR1ixGDubknJlis/XNMdSD7/j0SVHd6+KD0/FJxAX0mXgvfKw/PW8+lW KNXA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=N2giQ2yIsAWn8MusPqgS1CP/DkqViRRuAeJS4LgppK4=; b=nxxkE4RiMTKyWMwI+57WMzao8AkyHMseHcAzcjQZjxWB/G/Rru3LUQZGZqwTRLSUFo IVf/ZFTEnwRPO5iPVv/A+qeibWw9OKc2Oj0MkGlI6Rbv2dxBQVQf5hGb8d+tHlEpllmv QWZDwgsIadvlyciL3B9oQDde9mgvFN1k1ICB2h8cPg5fTt8AGCqtPlZa7s8ZYzSxlmgN 2wkifGBat5LEnZ9+5y7IUO3LxkBxo6ggvxT7PrM8Qj6SD/0PP9ZD8BZ8z588DMUAUYtB 8b2DSD/KkIC+haU9G5guTWiTGItXI7glJ+BA78QsflO14kSEvIeZjY05Ae2Wxr83+wsA H8nQ== X-Gm-Message-State: APjAAAUrFD5r1lXixXLx7/eVS8cQpfinoo+3CBEGxEO3jbZ7exzw1zvI z152kL57iMq6Sp90DXsrENHiGQ== X-Google-Smtp-Source: APXvYqzhqvyJ4VQuHIxn4osbb6I0R4V3URcLiMgyiJwat+YLcIUOsZ5a2Urq9TgAy8NkI7wsnA/ceg== X-Received: by 2002:a5d:494d:: with SMTP id r13mr5374600wrs.152.1561042834101; Thu, 20 Jun 2019 08:00:34 -0700 (PDT) Received: from bender.baylibre.local (lmontsouris-657-1-212-31.w90-63.abo.wanadoo.fr. [90.63.244.31]) by smtp.gmail.com with ESMTPSA id o126sm6802520wmo.1.2019.06.20.08.00.32 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 20 Jun 2019 08:00:33 -0700 (PDT) From: Neil Armstrong To: jbrunet@baylibre.com, khilman@baylibre.com Subject: [RFC/RFT 12/14] arm64: dts: meson-g12a: enable DVFS on G12A boards Date: Thu, 20 Jun 2019 17:00:11 +0200 Message-Id: <20190620150013.13462-13-narmstrong@baylibre.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190620150013.13462-1-narmstrong@baylibre.com> References: <20190620150013.13462-1-narmstrong@baylibre.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190620_080036_152609_0618D2B7 X-CRM114-Status: GOOD ( 11.89 ) X-BeenThere: linux-amlogic@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Neil Armstrong , martin.blumenstingl@googlemail.com, linux-kernel@vger.kernel.org, linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org Sender: "linux-amlogic" Errors-To: linux-amlogic-bounces+patchwork-linux-amlogic=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Enable DVFS for the U200, SEI520 and X96-Max Amlogic G12A based board by setting the clock, OPP and supply for each CPU cores. The CPU cluster power supply can achieve 0.73V to 1.01V using a PWM output clocked at 800KHz with an inverse duty-cycle. DVFS has been tested by running the arm64 cpuburn at [1] and cycling between all the possible cpufreq translations and checking the final frequency using the clock-measurer, script at [2]. [1] https://github.com/ssvb/cpuburn-arm/blob/master/cpuburn-a53.S [2] https://gist.github.com/superna9999/d4de964dbc0f84b7d527e1df2ddea25f Signed-off-by: Neil Armstrong --- .../boot/dts/amlogic/meson-g12a-sei510.dts | 55 +++++++++++++++++++ .../boot/dts/amlogic/meson-g12a-u200.dts | 55 +++++++++++++++++++ .../boot/dts/amlogic/meson-g12a-x96-max.dts | 52 ++++++++++++++++++ 3 files changed, 162 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a-sei510.dts b/arch/arm64/boot/dts/amlogic/meson-g12a-sei510.dts index bd26b35102ff..be45437c51e1 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12a-sei510.dts +++ b/arch/arm64/boot/dts/amlogic/meson-g12a-sei510.dts @@ -129,6 +129,25 @@ enable-active-high; }; + vddcpu: regulator-vddcpu { + /* + * SY8120B1ABC DC/DC Regulator. + */ + compatible = "pwm-regulator"; + + regulator-name = "VDDCPU"; + regulator-min-microvolt = <721000>; + regulator-max-microvolt = <1022000>; + + vin-supply = <&dc_in>; + + pwms = <&pwm_AO_cd 1 1250 0>; + pwm-dutycycle-range = <100 0>; + + regulator-boot-on; + regulator-always-on; + }; + vddio_ao1v8: regulator-vddio_ao1v8 { compatible = "regulator-fixed"; regulator-name = "VDDIO_AO1V8"; @@ -297,6 +316,34 @@ status = "okay"; }; +&cpu0 { + cpu-supply = <&vddcpu>; + operating-points-v2 = <&cpu_opp_table>; + clocks = <&clkc CLKID_CPU_CLK>; + clock-latency = <50000>; +}; + +&cpu1 { + cpu-supply = <&vddcpu>; + operating-points-v2 = <&cpu_opp_table>; + clocks = <&clkc CLKID_CPU_CLK>; + clock-latency = <50000>; +}; + +&cpu2 { + cpu-supply = <&vddcpu>; + operating-points-v2 = <&cpu_opp_table>; + clocks = <&clkc CLKID_CPU_CLK>; + clock-latency = <50000>; +}; + +&cpu3 { + cpu-supply = <&vddcpu>; + operating-points-v2 = <&cpu_opp_table>; + clocks = <&clkc CLKID_CPU_CLK>; + clock-latency = <50000>; +}; + &cvbs_vdac_port { cvbs_vdac_out: endpoint { remote-endpoint = <&cvbs_connector_in>; @@ -339,6 +386,14 @@ pinctrl-names = "default"; }; +&pwm_AO_cd { + pinctrl-0 = <&pwm_ao_d_e_pins>; + pinctrl-names = "default"; + clocks = <&xtal>; + clock-names = "clkin1"; + status = "okay"; +}; + &pwm_ef { status = "okay"; pinctrl-0 = <&pwm_e_pins>; diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a-u200.dts b/arch/arm64/boot/dts/amlogic/meson-g12a-u200.dts index 332a4b27174b..b6bd96ee394a 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12a-u200.dts +++ b/arch/arm64/boot/dts/amlogic/meson-g12a-u200.dts @@ -136,6 +136,25 @@ regulator-always-on; }; + vddcpu: regulator-vddcpu { + /* + * MP8756GD Regulator. + */ + compatible = "pwm-regulator"; + + regulator-name = "VDDCPU"; + regulator-min-microvolt = <721000>; + regulator-max-microvolt = <1022000>; + + vin-supply = <&main_12v>; + + pwms = <&pwm_AO_cd 1 1250 0>; + pwm-dutycycle-range = <100 0>; + + regulator-boot-on; + regulator-always-on; + }; + sound { compatible = "amlogic,axg-sound-card"; model = "G12A-U200"; @@ -305,6 +324,34 @@ status = "okay"; }; +&cpu0 { + cpu-supply = <&vddcpu>; + operating-points-v2 = <&cpu_opp_table>; + clocks = <&clkc CLKID_CPU_CLK>; + clock-latency = <50000>; +}; + +&cpu1 { + cpu-supply = <&vddcpu>; + operating-points-v2 = <&cpu_opp_table>; + clocks = <&clkc CLKID_CPU_CLK>; + clock-latency = <50000>; +}; + +&cpu2 { + cpu-supply = <&vddcpu>; + operating-points-v2 = <&cpu_opp_table>; + clocks = <&clkc CLKID_CPU_CLK>; + clock-latency = <50000>; +}; + +&cpu3 { + cpu-supply = <&vddcpu>; + operating-points-v2 = <&cpu_opp_table>; + clocks = <&clkc CLKID_CPU_CLK>; + clock-latency = <50000>; +}; + &cvbs_vdac_port { cvbs_vdac_out: endpoint { remote-endpoint = <&cvbs_connector_in>; @@ -369,6 +416,14 @@ pinctrl-names = "default"; }; +&pwm_AO_cd { + pinctrl-0 = <&pwm_ao_d_e_pins>; + pinctrl-names = "default"; + clocks = <&xtal>; + clock-names = "clkin1"; + status = "okay"; +}; + /* SD card */ &sd_emmc_b { status = "okay"; diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a-x96-max.dts b/arch/arm64/boot/dts/amlogic/meson-g12a-x96-max.dts index d37868d21114..099ccf67547e 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12a-x96-max.dts +++ b/arch/arm64/boot/dts/amlogic/meson-g12a-x96-max.dts @@ -132,6 +132,22 @@ regulator-always-on; }; + vddcpu: regulator-vddcpu { + compatible = "pwm-regulator"; + + regulator-name = "VDDCPU"; + regulator-min-microvolt = <721000>; + regulator-max-microvolt = <1022000>; + + vin-supply = <&dc_in>; + + pwms = <&pwm_AO_cd 1 1250 0>; + pwm-dutycycle-range = <100 0>; + + regulator-boot-on; + regulator-always-on; + }; + sound { compatible = "amlogic,axg-sound-card"; model = "G12A-X96-MAX"; @@ -242,6 +258,34 @@ status = "okay"; }; +&cpu0 { + cpu-supply = <&vddcpu>; + operating-points-v2 = <&cpu_opp_table>; + clocks = <&clkc CLKID_CPU_CLK>; + clock-latency = <50000>; +}; + +&cpu1 { + cpu-supply = <&vddcpu>; + operating-points-v2 = <&cpu_opp_table>; + clocks = <&clkc CLKID_CPU_CLK>; + clock-latency = <50000>; +}; + +&cpu2 { + cpu-supply = <&vddcpu>; + operating-points-v2 = <&cpu_opp_table>; + clocks = <&clkc CLKID_CPU_CLK>; + clock-latency = <50000>; +}; + +&cpu3 { + cpu-supply = <&vddcpu>; + operating-points-v2 = <&cpu_opp_table>; + clocks = <&clkc CLKID_CPU_CLK>; + clock-latency = <50000>; +}; + &cvbs_vdac_port { cvbs_vdac_out: endpoint { remote-endpoint = <&cvbs_connector_in>; @@ -279,6 +323,14 @@ pinctrl-names = "default"; }; +&pwm_AO_cd { + pinctrl-0 = <&pwm_ao_d_e_pins>; + pinctrl-names = "default"; + clocks = <&xtal>; + clock-names = "clkin1"; + status = "okay"; +}; + &ext_mdio { external_phy: ethernet-phy@0 { /* Realtek RTL8211F (0x001cc916) */ From patchwork Thu Jun 20 15:00:12 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neil Armstrong X-Patchwork-Id: 11007079 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 96F5A924 for ; Thu, 20 Jun 2019 15:05:46 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 8794728870 for ; Thu, 20 Jun 2019 15:05:46 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 7B94C287E7; Thu, 20 Jun 2019 15:05:46 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED autolearn=unavailable version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 1DDF32886E for ; Thu, 20 Jun 2019 15:05:46 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=qQ9zcOIb07nj9oeYXRymPD9YmFuJiB38jBMcpCeUqQs=; b=SAZz/3BhvdMQ+W YuwJUDDk5uQhwnne7rtSgy3eJ+veQOSBjLZNMW4pf7CCRXjoFUTnypbeiim1jW7X/VEeJgvoitoql 2GLhRLZhqaIiF7CNkkV4oSb3H8Kb0cOcz2sv1zYP7q9VBrehkBD5/aM4wJwFqn+OiL/dTEQjwxUaU qDe0R24bmfzgBFSUZZn4bdVTfTMrUExkEKo7ZEWQJkal62h0j1TnJbX8gwphgMCexJRHkITapordh uNUQ7OoNKwHFPWYPQqYJgGzuRbZQLlerwsGmPNwpW6/ex1Uty+HeXZD5nDHhxq/iM2qrNpPFcDsOG U5usaFkQFrbLOJ+gc9BQ==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92 #3 (Red Hat Linux)) id 1hdydF-00005r-Ji; Thu, 20 Jun 2019 15:05:45 +0000 Received: from mail-wm1-x342.google.com ([2a00:1450:4864:20::342]) by bombadil.infradead.org with esmtps (Exim 4.92 #3 (Red Hat Linux)) id 1hdyYG-0003Jr-Nm for linux-amlogic@lists.infradead.org; Thu, 20 Jun 2019 15:00:41 +0000 Received: by mail-wm1-x342.google.com with SMTP id h19so7109365wme.0 for ; Thu, 20 Jun 2019 08:00:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Qes8sASy5sBJ+5Ve+lLAIoBLeN8x3Knt4kb//nQEub0=; b=bLp5L5v3QS5wFKBUizSp2SVDeh+p42Tp3wW6h23FY+eZOvz+3rFse3fX8nrHfAF0N0 3hXWdF6RHyDvszXQOhz1PMo4c402hmKDlOSgweCFFtwOfj8Rw8B6/5HwQSPcwg0+lqFq rsQdTMgAumuGjnkfbaxvq4jhiTZsoMAou1x9jQjN5jz73KLW48hwY3WfUh5Jjr/EsOeX qnrUxITzWZ6NTFXaPmOuxxWMd1Wun+GtMgtItKLdcITqUVGCH72DheIEtWzVQrsg2bQZ WJhPJdmCpOitD5eXOFNStzJ/GJzw4aVzHFbkYX1NYwVbV/jUYx0NvDC8NFdwzW2xMD85 g+dg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Qes8sASy5sBJ+5Ve+lLAIoBLeN8x3Knt4kb//nQEub0=; b=tsyNI4PhvDsu/j1ZRax5ZqEDLn9DuFh+SCPtICHn9Zja6XP8cYI8YGKRjvMFtRTMVl 6EbagCmBJdSGZ4ebJPwhLCFoaZlSAswY0b8B3+QHsBB0/uGY1ANyi/zxW70rvcfQNFds sdf5jzK+sWKQmepxfvHboAPlaSbAHPpgWkxaTD68/qSU9DwwYfALaDrNA7oRVT4HisQ3 dSBQ/Oclri9A1cTVDilkUyJ/G6zAhpKY5Uv0x62mtd2EML566ipVyG0mYZFiAeCuoBfz dwQf87q03+HzUUKW81fpSTr42o03PykO8M6u7+OssfxsInySzRRjq51rqnhoHSczWiBU bhAQ== X-Gm-Message-State: APjAAAUuZrD2TTV/sehnjhoJJHfT329tucwDo/dd/Dnh/3/7J+8XDnpL acW0wK6wyDDGrwR1TjEj6p7DZg== X-Google-Smtp-Source: APXvYqxYtPp/wFEGNPPmoWaruFCEPgqbTgh4Hr4WX99UR9HAxN54KL5cPBZrIVaCKfUePTpJArYSAQ== X-Received: by 2002:a1c:6c14:: with SMTP id h20mr58185wmc.168.1561042835265; Thu, 20 Jun 2019 08:00:35 -0700 (PDT) Received: from bender.baylibre.local (lmontsouris-657-1-212-31.w90-63.abo.wanadoo.fr. [90.63.244.31]) by smtp.gmail.com with ESMTPSA id o126sm6802520wmo.1.2019.06.20.08.00.34 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 20 Jun 2019 08:00:34 -0700 (PDT) From: Neil Armstrong To: jbrunet@baylibre.com, khilman@baylibre.com Subject: [RFC/RFT 13/14] arm64: dts: meson-g12b: add cpus OPP tables Date: Thu, 20 Jun 2019 17:00:12 +0200 Message-Id: <20190620150013.13462-14-narmstrong@baylibre.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190620150013.13462-1-narmstrong@baylibre.com> References: <20190620150013.13462-1-narmstrong@baylibre.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190620_080036_794732_D4F90679 X-CRM114-Status: GOOD ( 10.34 ) X-BeenThere: linux-amlogic@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Neil Armstrong , martin.blumenstingl@googlemail.com, linux-kernel@vger.kernel.org, linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org Sender: "linux-amlogic" Errors-To: linux-amlogic-bounces+patchwork-linux-amlogic=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Add the OPP table taken from the HardKernel Odroid-N2 DTS. The Amlogic G12B SoC seems to available in 2 types : - low-speed: Cortex-A73 Cluster up to 1,704GHz - high-speed: Cortex-A73 Cluster up to 2.208GHz The Cortex-A73 Cluster can be clocked up to 1,896GHz for both types. The Vendor Amlogic A311D OPP table are slighly different, with lower voltages than the HardKernel S922X tables but seems to be high-speed type. This adds the conservative OPP table with the S922X higher voltages and the maximum low-speed OPP frequency. The values were tested to be stable on an HardKernel Odroid-N2 board running the arm64 cpuburn at [1] and cycling between all the possible cpufreq translations for both clusters and checking the final frequency using the clock-measurer, script at [2]. [1] https://github.com/ssvb/cpuburn-arm/blob/master/cpuburn-a53.S [2] https://gist.github.com/superna9999/d4de964dbc0f84b7d527e1df2ddea25f Signed-off-by: Neil Armstrong --- arch/arm64/boot/dts/amlogic/meson-g12b.dtsi | 115 ++++++++++++++++++++ 1 file changed, 115 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12b.dtsi index ae63cd610892..334742de11a7 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12b.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-g12b.dtsi @@ -95,6 +95,121 @@ compatible = "cache"; }; }; + + cpu_opp_table_0: opp-table-0 { + compatible = "operating-points-v2"; + opp-shared; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + opp-microvolt = <731000>; + }; + + opp-250000000 { + opp-hz = /bits/ 64 <250000000>; + opp-microvolt = <731000>; + }; + + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + opp-microvolt = <731000>; + }; + + opp-666666666 { + opp-hz = /bits/ 64 <666666666>; + opp-microvolt = <731000>; + }; + + opp-1000000000 { + opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = <731000>; + }; + + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <731000>; + }; + + opp-1398000000 { + opp-hz = /bits/ 64 <1398000000>; + opp-microvolt = <761000>; + }; + + opp-1512000000 { + opp-hz = /bits/ 64 <1512000000>; + opp-microvolt = <791000>; + }; + + opp-1608000000 { + opp-hz = /bits/ 64 <1608000000>; + opp-microvolt = <831000>; + }; + + opp-1704000000 { + opp-hz = /bits/ 64 <1704000000>; + opp-microvolt = <861000>; + }; + + opp-1896000000 { + opp-hz = /bits/ 64 <1896000000>; + opp-microvolt = <981000>; + }; + }; + + cpub_opp_table_1: opp-table-1 { + compatible = "operating-points-v2"; + opp-shared; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + opp-microvolt = <751000>; + }; + + opp-250000000 { + opp-hz = /bits/ 64 <250000000>; + opp-microvolt = <751000>; + }; + + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + opp-microvolt = <751000>; + }; + + opp-666666666 { + opp-hz = /bits/ 64 <666666666>; + opp-microvolt = <751000>; + }; + + opp-1000000000 { + opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = <751000>; + }; + + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <771000>; + }; + + opp-1398000000 { + opp-hz = /bits/ 64 <1398000000>; + opp-microvolt = <791000>; + }; + + opp-1512000000 { + opp-hz = /bits/ 64 <1512000000>; + opp-microvolt = <821000>; + }; + + opp-1608000000 { + opp-hz = /bits/ 64 <1608000000>; + opp-microvolt = <861000>; + }; + + opp-1704000000 { + opp-hz = /bits/ 64 <1704000000>; + opp-microvolt = <891000>; + }; + }; }; &clkc { From patchwork Thu Jun 20 15:00:13 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neil Armstrong X-Patchwork-Id: 11007089 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 2EB6014E5 for ; Thu, 20 Jun 2019 15:06:33 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 1D641286EC for ; Thu, 20 Jun 2019 15:06:33 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 10D7A28779; Thu, 20 Jun 2019 15:06:33 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED autolearn=unavailable version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 968DD286EC for ; Thu, 20 Jun 2019 15:06:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=Z/Nnyw1n53NC3Q779/gfHZjt1o2WHmakpp4mctUmluU=; b=mgA3j+iuq1eLHL UlGD33B+kCMQkkeqzSqOhi0gTkDxUcgjf7ZLfpvOkG10LK/3cNG1zuadHIt43bMApLtU2GOlcF3z+ j3vOMH5ekbw2vlV1FX/hF///9ZvgV8Elcfb8cN4v95olMDK0neXtDGoz3R9TlWJRmPWgxKRkITEeg 7C0ll2HzYHTClyUnqdzqw/SgcsZnQ7AzWUzT5UQPEnIL5EFM+4sxMnHIiAe6ED6e5efX1VjqQxOUn IxPRDr8HLdk8UfmZ1IU96pLdemdYwUZELCENOH4gzvMIbNyYLS9Lk/Jrb3LKVZ8AwKcI48aFxyOKr QxD3kGCDL3sDJmMhSGiw==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92 #3 (Red Hat Linux)) id 1hdye0-0000is-50; Thu, 20 Jun 2019 15:06:32 +0000 Received: from mail-wr1-x442.google.com ([2a00:1450:4864:20::442]) by bombadil.infradead.org with esmtps (Exim 4.92 #3 (Red Hat Linux)) id 1hdyYI-0003L3-4g for linux-amlogic@lists.infradead.org; Thu, 20 Jun 2019 15:00:44 +0000 Received: by mail-wr1-x442.google.com with SMTP id r16so3351612wrl.11 for ; Thu, 20 Jun 2019 08:00:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=9RQ6YaugFGkpRgh3juxH1I5rV90U2Bkw0dj0SZEZKwc=; b=VdSslLtIXp8jR0pmF12UjHiRAZxnZj61IXQmVJgReoJLPHEfMYQY6/e2NGkRzRFu8D us6kk3w+O5Imf29ygHn0TnHf61CISxKiE7hCnSRJMcYTA8VPFszQYzTSRW1na1aZQhO6 +hTVcykF0PBuBlMzoCwEIZdMUUuXjc9UgHETxodcfV4oUi3rgg2GTHl7iS1ZazL2a++G pONuFmHIGIcHuL4GHYgFNKivOmsCsUNuedYxk2rzKekPImvLfygMg4aw5tEJADlFSJB4 r8XU9CosbiXJT4pqWs4DjxGjTEZ5ld4TXDNxUoJseuYRaM70tnf6wAKYmghLabwgnK0A IvbA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=9RQ6YaugFGkpRgh3juxH1I5rV90U2Bkw0dj0SZEZKwc=; b=tYcHmdCLEhBLjJukNqoW8TxStAGT9MrCq+Y7v161U3//sSuCt2evinnN/tLm8OzMkj /bj6kWNzW5Q2tXlNqx/VBBscOCruDs4NVsySJCMCQBuvitrKDu0IYGuMaHFFX7Ua6vKK QuEA+2MuTk2BXPRHSgdul7tAt8DfoeNGPcBtA4H/Qeat1fJeU6fHpvpX3viXehmmGXkm CmKQ0ZtxdwHkS3q/zr+Zo7yg8GGja5GNllXPLoN86ZdZpI/1upRHjOxlOhX0hEEqMg5d QiRitJ836st/vvKZltDwI5ltglrXwS2vdCLVFSASVkp71zrgi+50F8oYj7c2h7qW1QB/ wTmA== X-Gm-Message-State: APjAAAVuYJL9v4A1vX8pneYr6tbalUPpuUAogJfLsKGcDfZ6G3cYUKmy 7Qf8QD0SFv5IsP0+xP8Gxo6QEg== X-Google-Smtp-Source: APXvYqzFkcqp+IU136AcFO26klI3508FIczvmeG6WnfapKtGfZQW34ACEjuxr2v58Y3CPceRgYRm6w== X-Received: by 2002:adf:f812:: with SMTP id s18mr27170003wrp.32.1561042836447; Thu, 20 Jun 2019 08:00:36 -0700 (PDT) Received: from bender.baylibre.local (lmontsouris-657-1-212-31.w90-63.abo.wanadoo.fr. [90.63.244.31]) by smtp.gmail.com with ESMTPSA id o126sm6802520wmo.1.2019.06.20.08.00.35 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 20 Jun 2019 08:00:35 -0700 (PDT) From: Neil Armstrong To: jbrunet@baylibre.com, khilman@baylibre.com Subject: [RFC/RFT 14/14] arm64: dts: meson-g12b-odroid-n2: enable DVFS Date: Thu, 20 Jun 2019 17:00:13 +0200 Message-Id: <20190620150013.13462-15-narmstrong@baylibre.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190620150013.13462-1-narmstrong@baylibre.com> References: <20190620150013.13462-1-narmstrong@baylibre.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190620_080038_189760_242A827F X-CRM114-Status: GOOD ( 11.91 ) X-BeenThere: linux-amlogic@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Neil Armstrong , martin.blumenstingl@googlemail.com, linux-kernel@vger.kernel.org, linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org Sender: "linux-amlogic" Errors-To: linux-amlogic-bounces+patchwork-linux-amlogic=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Enable DVFS for the Odroid-N2 by setting the clock, OPP and supply for each cores of each CPU clusters. The first cluster uses the "VDDCPU_B" power supply, and the second cluster uses the "VDDCPU_A" power supply. Each power supply can achieve 0.73V to 1.01V using 2 distinct PWM outputs clocked at 800KHz with an inverse duty-cycle. DVFS has been tested by running the arm64 cpuburn at [1] and cycling between all the possible cpufreq translations of each cluster and checking the final frequency using the clock-measurer, script at [2]. [1] https://github.com/ssvb/cpuburn-arm/blob/master/cpuburn-a53.S [2] https://gist.github.com/superna9999/d4de964dbc0f84b7d527e1df2ddea25f Signed-off-by: Neil Armstrong --- .../boot/dts/amlogic/meson-g12b-odroid-n2.dts | 96 +++++++++++++++++++ 1 file changed, 96 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dts b/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dts index c3e0735e6d9f..0db1547bfb5a 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dts +++ b/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dts @@ -114,6 +114,44 @@ /* FIXME: actually controlled by VDDCPU_B_EN */ }; + vddcpu_a: regulator-vddcpu-a { + /* + * MP8756GD Regulator. + */ + compatible = "pwm-regulator"; + + regulator-name = "VDDCPU_A"; + regulator-min-microvolt = <721000>; + regulator-max-microvolt = <1022000>; + + vin-supply = <&main_12v>; + + pwms = <&pwm_ab 0 1250 0>; + pwm-dutycycle-range = <100 0>; + + regulator-boot-on; + regulator-always-on; + }; + + vddcpu_b: regulator-vddcpu-b { + /* + * Silergy SY8120B1ABC Regulator. + */ + compatible = "pwm-regulator"; + + regulator-name = "VDDCPU_B"; + regulator-min-microvolt = <721000>; + regulator-max-microvolt = <1022000>; + + vin-supply = <&main_12v>; + + pwms = <&pwm_AO_cd 1 1250 0>; + pwm-dutycycle-range = <100 0>; + + regulator-boot-on; + regulator-always-on; + }; + hub_5v: regulator-hub_5v { compatible = "regulator-fixed"; regulator-name = "HUB_5V"; @@ -245,6 +283,48 @@ status = "okay"; }; +&cpu0 { + cpu-supply = <&vddcpu_b>; + operating-points-v2 = <&cpu_opp_table_0>; + clocks = <&clkc CLKID_CPU_CLK>; + clock-latency = <50000>; +}; + +&cpu1 { + cpu-supply = <&vddcpu_b>; + operating-points-v2 = <&cpu_opp_table_0>; + clocks = <&clkc CLKID_CPU_CLK>; + clock-latency = <50000>; +}; + +&cpu100 { + cpu-supply = <&vddcpu_a>; + operating-points-v2 = <&cpub_opp_table_1>; + clocks = <&clkc CLKID_CPUB_CLK>; + clock-latency = <50000>; +}; + +&cpu101 { + cpu-supply = <&vddcpu_a>; + operating-points-v2 = <&cpub_opp_table_1>; + clocks = <&clkc CLKID_CPUB_CLK>; + clock-latency = <50000>; +}; + +&cpu102 { + cpu-supply = <&vddcpu_a>; + operating-points-v2 = <&cpub_opp_table_1>; + clocks = <&clkc CLKID_CPUB_CLK>; + clock-latency = <50000>; +}; + +&cpu103 { + cpu-supply = <&vddcpu_a>; + operating-points-v2 = <&cpub_opp_table_1>; + clocks = <&clkc CLKID_CPUB_CLK>; + clock-latency = <50000>; +}; + &ext_mdio { external_phy: ethernet-phy@0 { /* Realtek RTL8211F (0x001cc916) */ @@ -308,6 +388,22 @@ pinctrl-names = "default"; }; +&pwm_ab { + pinctrl-0 = <&pwm_a_e_pins>; + pinctrl-names = "default"; + clocks = <&xtal>; + clock-names = "clkin0"; + status = "okay"; +}; + +&pwm_AO_cd { + pinctrl-0 = <&pwm_ao_d_e_pins>; + pinctrl-names = "default"; + clocks = <&xtal>; + clock-names = "clkin1"; + status = "okay"; +}; + /* SD card */ &sd_emmc_b { status = "okay";