From patchwork Sat Jun 22 16:51:41 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vidya Sagar X-Patchwork-Id: 11011351 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 1553B1986 for ; Sat, 22 Jun 2019 16:51:54 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id EC9E528B77 for ; Sat, 22 Jun 2019 16:51:53 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id DF4BE28B7A; Sat, 22 Jun 2019 16:51:53 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 6BFA228B77 for ; Sat, 22 Jun 2019 16:51:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726355AbfFVQvw (ORCPT ); Sat, 22 Jun 2019 12:51:52 -0400 Received: from hqemgate15.nvidia.com ([216.228.121.64]:17134 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726353AbfFVQvw (ORCPT ); Sat, 22 Jun 2019 12:51:52 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Sat, 22 Jun 2019 09:51:53 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Sat, 22 Jun 2019 09:51:51 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Sat, 22 Jun 2019 09:51:51 -0700 Received: from HQMAIL105.nvidia.com (172.20.187.12) by HQMAIL104.nvidia.com (172.18.146.11) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Sat, 22 Jun 2019 16:51:50 +0000 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Sat, 22 Jun 2019 16:51:50 +0000 Received: from vidyas-desktop.nvidia.com (Not Verified[10.24.37.38]) by hqnvemgw01.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Sat, 22 Jun 2019 09:51:50 -0700 From: Vidya Sagar To: , , , , , , CC: , , , , , Subject: [PATCH V7 1/3] PCI: dwc: Add API support to de-initialize host Date: Sat, 22 Jun 2019 22:21:41 +0530 Message-ID: <20190622165143.11906-1-vidyas@nvidia.com> X-Mailer: git-send-email 2.17.1 X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1561222313; bh=kHzOZ0ioktzRy5B/z8d32g38iVfdRdG4Wj2O9cc1+GE=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: X-NVConfidentiality:MIME-Version:Content-Type; b=nYMdTrRp5GvL4l0CxWhqGkVdMSxUSWt6LmMWtx359BuKSLKtSp0dYu/TcsdRQ1NLL 6fPZJfXr7NlX4QD9r1TfBG+EtJvidJ+xyITK+vtMhtc8bmIf1C63e3enhaJ13WSsoT psVQnZeREfpXLHdtnpSFvXySI/lgPTinWNvRchUL788PD1IFtYZEECpLwySuT9/oUF QT6bGfSnE/u6RKc5yckGgTcGHFNqWjpTbSwGieKdWQ7Me8MCGK2tbl3V6GqA+YytlN kx0WGkx+gDc3P61KGhZKaDhqzkOfy1/JW+DbwtiE1R1Gm1BXuXu7u5pFeHNcL+gyJo 9lKoKLe43AUXA== Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add an API to group all the tasks to be done to de-initialize host which can then be called by any DesignWare core based driver implementations while adding .remove() support in their respective drivers. Signed-off-by: Vidya Sagar Acked-by: Gustavo Pimentel --- Changes from v6: * None Changes from v5: * None Changes from v4: * None Changes from v3: * Added check if (pci_msi_enabled() && !pp->ops->msi_host_init) before calling dw_pcie_free_msi() API to mimic init path Changes from v2: * Rebased on top of linux-next top of the tree branch Changes from v1: * s/Designware/DesignWare drivers/pci/controller/dwc/pcie-designware-host.c | 8 ++++++++ drivers/pci/controller/dwc/pcie-designware.h | 5 +++++ 2 files changed, 13 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c index 77db32529319..d069e4290180 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -496,6 +496,14 @@ int dw_pcie_host_init(struct pcie_port *pp) return ret; } +void dw_pcie_host_deinit(struct pcie_port *pp) +{ + pci_stop_root_bus(pp->root_bus); + pci_remove_root_bus(pp->root_bus); + if (pci_msi_enabled() && !pp->ops->msi_host_init) + dw_pcie_free_msi(pp); +} + static int dw_pcie_access_other_conf(struct pcie_port *pp, struct pci_bus *bus, u32 devfn, int where, int size, u32 *val, bool write) diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h index b8993f2b78df..14762e262758 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -351,6 +351,7 @@ void dw_pcie_msi_init(struct pcie_port *pp); void dw_pcie_free_msi(struct pcie_port *pp); void dw_pcie_setup_rc(struct pcie_port *pp); int dw_pcie_host_init(struct pcie_port *pp); +void dw_pcie_host_deinit(struct pcie_port *pp); int dw_pcie_allocate_domains(struct pcie_port *pp); #else static inline irqreturn_t dw_handle_msi_irq(struct pcie_port *pp) @@ -375,6 +376,10 @@ static inline int dw_pcie_host_init(struct pcie_port *pp) return 0; } +static inline void dw_pcie_host_deinit(struct pcie_port *pp) +{ +} + static inline int dw_pcie_allocate_domains(struct pcie_port *pp) { return 0; From patchwork Sat Jun 22 16:51:42 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vidya Sagar X-Patchwork-Id: 11011353 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 69170924 for ; Sat, 22 Jun 2019 16:52:07 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 57EA228B77 for ; Sat, 22 Jun 2019 16:52:07 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 496BE28B7A; Sat, 22 Jun 2019 16:52:07 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 7DC6228B77 for ; Sat, 22 Jun 2019 16:52:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726388AbfFVQwF (ORCPT ); Sat, 22 Jun 2019 12:52:05 -0400 Received: from hqemgate16.nvidia.com ([216.228.121.65]:14062 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726353AbfFVQwF (ORCPT ); Sat, 22 Jun 2019 12:52:05 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Sat, 22 Jun 2019 09:52:02 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Sat, 22 Jun 2019 09:52:02 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Sat, 22 Jun 2019 09:52:02 -0700 Received: from HQMAIL110.nvidia.com (172.18.146.15) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Sat, 22 Jun 2019 16:52:02 +0000 Received: from HQMAIL106.nvidia.com (172.18.146.12) by hqmail110.nvidia.com (172.18.146.15) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Sat, 22 Jun 2019 16:52:02 +0000 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by HQMAIL106.nvidia.com (172.18.146.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Sat, 22 Jun 2019 16:52:01 +0000 Received: from vidyas-desktop.nvidia.com (Not Verified[10.24.37.38]) by hqnvemgw01.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Sat, 22 Jun 2019 09:52:01 -0700 From: Vidya Sagar To: , , , , , , CC: , , , , , Subject: [PATCH V7 2/3] PCI: dwc: Cleanup DBI,ATU read and write APIs Date: Sat, 22 Jun 2019 22:21:42 +0530 Message-ID: <20190622165143.11906-2-vidyas@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190622165143.11906-1-vidyas@nvidia.com> References: <20190622165143.11906-1-vidyas@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1561222322; bh=W7I7ouiyukhr6b9yR8Z0JGvbioUALPNni9aEdee2yB0=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=CLlQVZMxnsBIqgif0KhphggLlem6bGWfpNDMbSex7uf/wDYy3khn7N4W+e8g33/Kg +dt2RFGvPakOfns8g/QP4/qhFQZeNmOdP+oXh8v8ZabOhstOFQerV9fAvfx3+S3iQf ZL1Oqbs4qyH/vz1Nu8Z2+iWvzpEnm3c7axk1QxGqQXZF2Rh8f8/PVztU2cfkDSm5Ef h4jH6E4b6qsd+D9wzNIvz+/LtVZaSw9GtU8gK7bRbzMs8zigz+cyPxl0cwM3N13BZr PJdDyDADCAEf04/Y2UNk/IgFotg8QSjMnEcF9CFI+mNlxcHnzgUe0RBbN3YJgMCGHi NVSue8/lD2p/g== Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Cleanup DBI read and write APIs by removing "__" (underscore) from their names as there are no no-underscore versions and the underscore versions are already doing what no-underscore versions typically do. It also removes passing dbi/dbi2 base address as one of the arguments as the same can be derived with in read and write APIs. Since dw_pcie_{readl/writel}_dbi() APIs can't be used for ATU read/write as ATU base address could be different from DBI base address, this patch attempts to implement ATU read/write APIs using ATU base address without using dw_pcie_{readl/writel}_dbi() APIs. Signed-off-by: Vidya Sagar --- Changes from v6: * Modified ATU read/write APIs to use implementation specific DBI read/write APIs if present. Changes from v5: * Removed passing base address as one of the arguments as the same can be derived within the API itself. * Modified ATU read/write APIs to call dw_pcie_{write/read}() API Changes from v4: * This is a new patch in this series drivers/pci/controller/dwc/pcie-designware.c | 28 +++++------ drivers/pci/controller/dwc/pcie-designware.h | 51 +++++++++++++------- 2 files changed, 45 insertions(+), 34 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c index 9d7c51c32b3b..0b383feb13de 100644 --- a/drivers/pci/controller/dwc/pcie-designware.c +++ b/drivers/pci/controller/dwc/pcie-designware.c @@ -52,64 +52,60 @@ int dw_pcie_write(void __iomem *addr, int size, u32 val) return PCIBIOS_SUCCESSFUL; } -u32 __dw_pcie_read_dbi(struct dw_pcie *pci, void __iomem *base, u32 reg, - size_t size) +u32 dw_pcie_read_dbi(struct dw_pcie *pci, u32 reg, size_t size) { int ret; u32 val; if (pci->ops->read_dbi) - return pci->ops->read_dbi(pci, base, reg, size); + return pci->ops->read_dbi(pci, pci->dbi_base, reg, size); - ret = dw_pcie_read(base + reg, size, &val); + ret = dw_pcie_read(pci->dbi_base + reg, size, &val); if (ret) dev_err(pci->dev, "Read DBI address failed\n"); return val; } -void __dw_pcie_write_dbi(struct dw_pcie *pci, void __iomem *base, u32 reg, - size_t size, u32 val) +void dw_pcie_write_dbi(struct dw_pcie *pci, u32 reg, size_t size, u32 val) { int ret; if (pci->ops->write_dbi) { - pci->ops->write_dbi(pci, base, reg, size, val); + pci->ops->write_dbi(pci, pci->dbi_base, reg, size, val); return; } - ret = dw_pcie_write(base + reg, size, val); + ret = dw_pcie_write(pci->dbi_base + reg, size, val); if (ret) dev_err(pci->dev, "Write DBI address failed\n"); } -u32 __dw_pcie_read_dbi2(struct dw_pcie *pci, void __iomem *base, u32 reg, - size_t size) +u32 dw_pcie_read_dbi2(struct dw_pcie *pci, u32 reg, size_t size) { int ret; u32 val; if (pci->ops->read_dbi2) - return pci->ops->read_dbi2(pci, base, reg, size); + return pci->ops->read_dbi2(pci, pci->dbi_base2, reg, size); - ret = dw_pcie_read(base + reg, size, &val); + ret = dw_pcie_read(pci->dbi_base2 + reg, size, &val); if (ret) dev_err(pci->dev, "read DBI address failed\n"); return val; } -void __dw_pcie_write_dbi2(struct dw_pcie *pci, void __iomem *base, u32 reg, - size_t size, u32 val) +void dw_pcie_write_dbi2(struct dw_pcie *pci, u32 reg, size_t size, u32 val) { int ret; if (pci->ops->write_dbi2) { - pci->ops->write_dbi2(pci, base, reg, size, val); + pci->ops->write_dbi2(pci, pci->dbi_base2, reg, size, val); return; } - ret = dw_pcie_write(base + reg, size, val); + ret = dw_pcie_write(pci->dbi_base2 + reg, size, val); if (ret) dev_err(pci->dev, "write DBI address failed\n"); } diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h index 14762e262758..657e25e2c789 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -254,14 +254,10 @@ struct dw_pcie { int dw_pcie_read(void __iomem *addr, int size, u32 *val); int dw_pcie_write(void __iomem *addr, int size, u32 val); -u32 __dw_pcie_read_dbi(struct dw_pcie *pci, void __iomem *base, u32 reg, - size_t size); -void __dw_pcie_write_dbi(struct dw_pcie *pci, void __iomem *base, u32 reg, - size_t size, u32 val); -u32 __dw_pcie_read_dbi2(struct dw_pcie *pci, void __iomem *base, u32 reg, - size_t size); -void __dw_pcie_write_dbi2(struct dw_pcie *pci, void __iomem *base, u32 reg, - size_t size, u32 val); +u32 dw_pcie_read_dbi(struct dw_pcie *pci, u32 reg, size_t size); +void dw_pcie_write_dbi(struct dw_pcie *pci, u32 reg, size_t size, u32 val); +u32 dw_pcie_read_dbi2(struct dw_pcie *pci, u32 reg, size_t size); +void dw_pcie_write_dbi2(struct dw_pcie *pci, u32 reg, size_t size, u32 val); int dw_pcie_link_up(struct dw_pcie *pci); int dw_pcie_wait_for_link(struct dw_pcie *pci); void dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index, @@ -275,52 +271,71 @@ void dw_pcie_setup(struct dw_pcie *pci); static inline void dw_pcie_writel_dbi(struct dw_pcie *pci, u32 reg, u32 val) { - __dw_pcie_write_dbi(pci, pci->dbi_base, reg, 0x4, val); + dw_pcie_write_dbi(pci, reg, 0x4, val); } static inline u32 dw_pcie_readl_dbi(struct dw_pcie *pci, u32 reg) { - return __dw_pcie_read_dbi(pci, pci->dbi_base, reg, 0x4); + return dw_pcie_read_dbi(pci, reg, 0x4); } static inline void dw_pcie_writew_dbi(struct dw_pcie *pci, u32 reg, u16 val) { - __dw_pcie_write_dbi(pci, pci->dbi_base, reg, 0x2, val); + dw_pcie_write_dbi(pci, reg, 0x2, val); } static inline u16 dw_pcie_readw_dbi(struct dw_pcie *pci, u32 reg) { - return __dw_pcie_read_dbi(pci, pci->dbi_base, reg, 0x2); + return dw_pcie_read_dbi(pci, reg, 0x2); } static inline void dw_pcie_writeb_dbi(struct dw_pcie *pci, u32 reg, u8 val) { - __dw_pcie_write_dbi(pci, pci->dbi_base, reg, 0x1, val); + dw_pcie_write_dbi(pci, reg, 0x1, val); } static inline u8 dw_pcie_readb_dbi(struct dw_pcie *pci, u32 reg) { - return __dw_pcie_read_dbi(pci, pci->dbi_base, reg, 0x1); + return dw_pcie_read_dbi(pci, reg, 0x1); } static inline void dw_pcie_writel_dbi2(struct dw_pcie *pci, u32 reg, u32 val) { - __dw_pcie_write_dbi2(pci, pci->dbi_base2, reg, 0x4, val); + dw_pcie_write_dbi2(pci, reg, 0x4, val); } static inline u32 dw_pcie_readl_dbi2(struct dw_pcie *pci, u32 reg) { - return __dw_pcie_read_dbi2(pci, pci->dbi_base2, reg, 0x4); + return dw_pcie_read_dbi2(pci, reg, 0x4); } static inline void dw_pcie_writel_atu(struct dw_pcie *pci, u32 reg, u32 val) { - __dw_pcie_write_dbi(pci, pci->atu_base, reg, 0x4, val); + int ret; + + if (pci->ops->write_dbi) { + pci->ops->write_dbi(pci, pci->atu_base, reg, 0x4, val); + return; + } + + ret = dw_pcie_write(pci->atu_base + reg, 0x4, val); + if (ret) + dev_err(pci->dev, "Write ATU address failed\n"); } static inline u32 dw_pcie_readl_atu(struct dw_pcie *pci, u32 reg) { - return __dw_pcie_read_dbi(pci, pci->atu_base, reg, 0x4); + int ret; + u32 val; + + if (pci->ops->read_dbi) + return pci->ops->read_dbi(pci, pci->atu_base, reg, 0x4); + + ret = dw_pcie_read(pci->atu_base + reg, 0x4, &val); + if (ret) + dev_err(pci->dev, "Read ATU address failed\n"); + + return val; } static inline void dw_pcie_dbi_ro_wr_en(struct dw_pcie *pci) From patchwork Sat Jun 22 16:51:43 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vidya Sagar X-Patchwork-Id: 11011355 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 7892413AF for ; Sat, 22 Jun 2019 16:52:18 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 683B628B77 for ; Sat, 22 Jun 2019 16:52:18 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 5C13E28B7A; Sat, 22 Jun 2019 16:52:18 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id E28D028B77 for ; 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Sat, 22 Jun 2019 16:52:14 +0000 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Sat, 22 Jun 2019 16:52:14 +0000 Received: from vidyas-desktop.nvidia.com (Not Verified[10.24.37.38]) by hqnvemgw01.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Sat, 22 Jun 2019 09:52:13 -0700 From: Vidya Sagar To: , , , , , , CC: , , , , , Subject: [PATCH V7 3/3] PCI: dwc: Export APIs to support .remove() implementation Date: Sat, 22 Jun 2019 22:21:43 +0530 Message-ID: <20190622165143.11906-3-vidyas@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190622165143.11906-1-vidyas@nvidia.com> References: <20190622165143.11906-1-vidyas@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1561222333; bh=ltyT8sOHqbA8vvFvGDceEuW+3PZIHktZsi/WtHYMyM8=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=csZUPnq40Ga442aOZgn4cdAmLqiG0tRbJ3tirJCewE+U/uD1YBHgrzLHRkkHdKcuE WHg1u2ye24Z4j3+mlJiO2nU7KJX7RwbnhK1O9RL2b0bdRCsD1NKvVzxTeTFVxCFPXf XQaavMSiuSQXyhdilhE97Vc4IPUcon/lMVhLXVIMt5nqkjiF5Wps5VX90F/QRZglOz TV+MgSrWal6jbpKlBoJO2FKoK92/7BlZg/TSr/HWEHhMdLVv2wq8Wi0Z64kSdU5IlX Ozc5NbFA3zmwZoZByAlLccYQfQuj++XX0GmWfvzxmKQ4I0cL2U72KcOXrHcq24xpK6 JWU1WlWEcepHw== Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Export all configuration space access APIs and also other APIs to support host controller drivers of DesignWare core based implementations while adding support for .remove() hook to build their respective drivers as modules Signed-off-by: Vidya Sagar Acked-by: Gustavo Pimentel --- Changes from v6: * None Changes from v5: * None Changes from v4: * Removed __ (underscore) from dw_pcie_{write/read}_dbi API names Changes from v3: * Exported only __dw_pcie_{read/write}_dbi() APIs instead of dw_pcie_read{l/w/b}_dbi & dw_pcie_write{l/w/b}_dbi APIs. Changes from v2: * Rebased on top of linux-next top of the tree branch Changes from v1: * s/Designware/DesignWare drivers/pci/controller/dwc/pcie-designware-host.c | 4 ++++ drivers/pci/controller/dwc/pcie-designware.c | 4 ++++ 2 files changed, 8 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c index d069e4290180..f93252d0da5b 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -311,6 +311,7 @@ void dw_pcie_msi_init(struct pcie_port *pp) dw_pcie_wr_own_conf(pp, PCIE_MSI_ADDR_HI, 4, upper_32_bits(msi_target)); } +EXPORT_SYMBOL_GPL(dw_pcie_msi_init); int dw_pcie_host_init(struct pcie_port *pp) { @@ -495,6 +496,7 @@ int dw_pcie_host_init(struct pcie_port *pp) dw_pcie_free_msi(pp); return ret; } +EXPORT_SYMBOL_GPL(dw_pcie_host_init); void dw_pcie_host_deinit(struct pcie_port *pp) { @@ -503,6 +505,7 @@ void dw_pcie_host_deinit(struct pcie_port *pp) if (pci_msi_enabled() && !pp->ops->msi_host_init) dw_pcie_free_msi(pp); } +EXPORT_SYMBOL_GPL(dw_pcie_host_deinit); static int dw_pcie_access_other_conf(struct pcie_port *pp, struct pci_bus *bus, u32 devfn, int where, int size, u32 *val, @@ -695,3 +698,4 @@ void dw_pcie_setup_rc(struct pcie_port *pp) val |= PORT_LOGIC_SPEED_CHANGE; dw_pcie_wr_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, val); } +EXPORT_SYMBOL_GPL(dw_pcie_setup_rc); diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c index 0b383feb13de..dc9cdcd72ffc 100644 --- a/drivers/pci/controller/dwc/pcie-designware.c +++ b/drivers/pci/controller/dwc/pcie-designware.c @@ -34,6 +34,7 @@ int dw_pcie_read(void __iomem *addr, int size, u32 *val) return PCIBIOS_SUCCESSFUL; } +EXPORT_SYMBOL_GPL(dw_pcie_read); int dw_pcie_write(void __iomem *addr, int size, u32 val) { @@ -51,6 +52,7 @@ int dw_pcie_write(void __iomem *addr, int size, u32 val) return PCIBIOS_SUCCESSFUL; } +EXPORT_SYMBOL_GPL(dw_pcie_write); u32 dw_pcie_read_dbi(struct dw_pcie *pci, u32 reg, size_t size) { @@ -66,6 +68,7 @@ u32 dw_pcie_read_dbi(struct dw_pcie *pci, u32 reg, size_t size) return val; } +EXPORT_SYMBOL_GPL(dw_pcie_read_dbi); void dw_pcie_write_dbi(struct dw_pcie *pci, u32 reg, size_t size, u32 val) { @@ -80,6 +83,7 @@ void dw_pcie_write_dbi(struct dw_pcie *pci, u32 reg, size_t size, u32 val) if (ret) dev_err(pci->dev, "Write DBI address failed\n"); } +EXPORT_SYMBOL_GPL(dw_pcie_write_dbi); u32 dw_pcie_read_dbi2(struct dw_pcie *pci, u32 reg, size_t size) {