From patchwork Mon Jun 24 21:08:43 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Navare, Manasi" X-Patchwork-Id: 11014155 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 7DCF9112C for ; Mon, 24 Jun 2019 21:07:12 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 6E9B228917 for ; Mon, 24 Jun 2019 21:07:12 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 633C928949; Mon, 24 Jun 2019 21:07:12 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 0544528917 for ; Mon, 24 Jun 2019 21:07:11 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 8484A89DE6; Mon, 24 Jun 2019 21:07:10 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTPS id A95F989DAB for ; Mon, 24 Jun 2019 21:07:09 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga102.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 24 Jun 2019 14:07:09 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.63,413,1557212400"; d="scan'208";a="163740795" Received: from labuser-z97x-ud5h.jf.intel.com ([10.54.75.49]) by orsmga003.jf.intel.com with ESMTP; 24 Jun 2019 14:07:08 -0700 From: Manasi Navare To: intel-gfx@lists.freedesktop.org Date: Mon, 24 Jun 2019 14:08:43 -0700 Message-Id: <20190624210850.17223-2-manasi.d.navare@intel.com> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20190624210850.17223-1-manasi.d.navare@intel.com> References: <20190624210850.17223-1-manasi.d.navare@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v3 1/8] drm/i915/display: Rename update_crtcs() to commit_modeset_enables() X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jani Nikula Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP This patch has no functional changes. This just renames the update_crtcs() hooks to commit_modeset_enables() to match the drm_atomic helper naming conventions. Suggested-by: Daniel Vetter Cc: Ville Syrjälä Cc: Maarten Lankhorst Cc: Matt Roper Cc: Jani Nikula Signed-off-by: Manasi Navare Reviewed-by: Madhumitha Tolakanahalli Pradeep < --- drivers/gpu/drm/i915/display/intel_display.c | 10 +++++----- drivers/gpu/drm/i915/i915_drv.h | 2 +- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 73fe1bcfcd99..71e86e2f0f90 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -13613,7 +13613,7 @@ static void intel_update_crtc(struct drm_crtc *crtc, intel_finish_crtc_commit(to_intel_atomic_state(state), intel_crtc); } -static void intel_update_crtcs(struct drm_atomic_state *state) +static void intel_commit_modeset_enables(struct drm_atomic_state *state) { struct drm_crtc *crtc; struct drm_crtc_state *old_crtc_state, *new_crtc_state; @@ -13628,7 +13628,7 @@ static void intel_update_crtcs(struct drm_atomic_state *state) } } -static void skl_update_crtcs(struct drm_atomic_state *state) +static void skl_commit_modeset_enables(struct drm_atomic_state *state) { struct drm_i915_private *dev_priv = to_i915(state->dev); struct intel_atomic_state *intel_state = to_intel_atomic_state(state); @@ -13868,7 +13868,7 @@ static void intel_atomic_commit_tail(struct drm_atomic_state *state) } /* Now enable the clocks, plane, pipe, and connectors that we set up. */ - dev_priv->display.update_crtcs(state); + dev_priv->display.commit_modeset_enables(state); if (intel_state->modeset) intel_set_cdclk_post_plane_update(dev_priv, @@ -15719,9 +15719,9 @@ void intel_init_display_hooks(struct drm_i915_private *dev_priv) } if (INTEL_GEN(dev_priv) >= 9) - dev_priv->display.update_crtcs = skl_update_crtcs; + dev_priv->display.commit_modeset_enables = skl_commit_modeset_enables; else - dev_priv->display.update_crtcs = intel_update_crtcs; + dev_priv->display.commit_modeset_enables = intel_commit_modeset_enables; } static i915_reg_t i915_vgacntrl_reg(struct drm_i915_private *dev_priv) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 62e7c5e8aee5..075d7eb3c3f2 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -310,7 +310,7 @@ struct drm_i915_display_funcs { struct drm_atomic_state *old_state); void (*crtc_disable)(struct intel_crtc_state *old_crtc_state, struct drm_atomic_state *old_state); - void (*update_crtcs)(struct drm_atomic_state *state); + void (*commit_modeset_enables)(struct drm_atomic_state *state); void (*audio_codec_enable)(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state, const struct drm_connector_state *conn_state); From patchwork Mon Jun 24 21:08:44 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Navare, Manasi" X-Patchwork-Id: 11014157 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 74D4D112C for ; Mon, 24 Jun 2019 21:07:13 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 6594F28917 for ; Mon, 24 Jun 2019 21:07:13 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 59E7A28949; Mon, 24 Jun 2019 21:07:13 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id D7E8728917 for ; Mon, 24 Jun 2019 21:07:12 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id C30BD89D6C; Mon, 24 Jun 2019 21:07:10 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTPS id C352F89D6C for ; Mon, 24 Jun 2019 21:07:09 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga102.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 24 Jun 2019 14:07:09 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.63,413,1557212400"; d="scan'208";a="163740798" Received: from labuser-z97x-ud5h.jf.intel.com ([10.54.75.49]) by orsmga003.jf.intel.com with ESMTP; 24 Jun 2019 14:07:08 -0700 From: Manasi Navare To: intel-gfx@lists.freedesktop.org Date: Mon, 24 Jun 2019 14:08:44 -0700 Message-Id: <20190624210850.17223-3-manasi.d.navare@intel.com> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20190624210850.17223-1-manasi.d.navare@intel.com> References: <20190624210850.17223-1-manasi.d.navare@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v3 2/8] drm/i915/display: Move the commit_tail() disable sequence to commit_modeset_disables() hook X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jani Nikula Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP Create a new hook commit_modeset_disables() consistent with the naming in drm atomic helpers and similar to the commit_modeset_enables() hook. This helps better organize the disable sequence in atomic_commit_tail() and move that to this disable hook. No functional change Suggested-by: Daniel Vetter Cc: Ville Syrjälä Cc: Maarten Lankhorst Cc: Matt Roper Cc: Jani Nikula Signed-off-by: Manasi Navare --- drivers/gpu/drm/i915/display/intel_display.c | 105 +++++++++++-------- drivers/gpu/drm/i915/i915_drv.h | 1 + 2 files changed, 64 insertions(+), 42 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 71e86e2f0f90..c34118998ace 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -13613,6 +13613,58 @@ static void intel_update_crtc(struct drm_crtc *crtc, intel_finish_crtc_commit(to_intel_atomic_state(state), intel_crtc); } +static void intel_commit_modeset_disables(struct drm_atomic_state *state) +{ + struct drm_device *dev = state->dev; + struct intel_atomic_state *intel_state = to_intel_atomic_state(state); + struct drm_i915_private *dev_priv = to_i915(dev); + struct drm_crtc_state *old_crtc_state, *new_crtc_state; + struct intel_crtc_state *new_intel_crtc_state, *old_intel_crtc_state; + struct drm_crtc *crtc; + struct intel_crtc *intel_crtc; + int i; + + for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { + old_intel_crtc_state = to_intel_crtc_state(old_crtc_state); + new_intel_crtc_state = to_intel_crtc_state(new_crtc_state); + intel_crtc = to_intel_crtc(crtc); + + if (!needs_modeset(new_crtc_state)) + continue; + + intel_pre_plane_update(old_intel_crtc_state, new_intel_crtc_state); + + if (old_crtc_state->active) { + intel_crtc_disable_planes(intel_state, intel_crtc); + + /* + * We need to disable pipe CRC before disabling the pipe, + * or we race against vblank off. + */ + intel_crtc_disable_pipe_crc(intel_crtc); + + dev_priv->display.crtc_disable(old_intel_crtc_state, state); + intel_crtc->active = false; + intel_fbc_disable(intel_crtc); + intel_disable_shared_dpll(old_intel_crtc_state); + + /* + * Underruns don't always raise interrupts, + * so check manually. + */ + intel_check_cpu_fifo_underruns(dev_priv); + intel_check_pch_fifo_underruns(dev_priv); + + /* FIXME unify this for all platforms */ + if (!new_crtc_state->active && + !HAS_GMCH(dev_priv) && + dev_priv->display.initial_watermarks) + dev_priv->display.initial_watermarks(intel_state, + new_intel_crtc_state); + } + } +} + static void intel_commit_modeset_enables(struct drm_atomic_state *state) { struct drm_crtc *crtc; @@ -13769,7 +13821,7 @@ static void intel_atomic_commit_tail(struct drm_atomic_state *state) struct intel_atomic_state *intel_state = to_intel_atomic_state(state); struct drm_i915_private *dev_priv = to_i915(dev); struct drm_crtc_state *old_crtc_state, *new_crtc_state; - struct intel_crtc_state *new_intel_crtc_state, *old_intel_crtc_state; + struct intel_crtc_state *new_intel_crtc_state; struct drm_crtc *crtc; struct intel_crtc *intel_crtc; u64 put_domains[I915_MAX_PIPES] = {}; @@ -13778,58 +13830,24 @@ static void intel_atomic_commit_tail(struct drm_atomic_state *state) intel_atomic_commit_fence_wait(intel_state); - drm_atomic_helper_wait_for_dependencies(state); - - if (intel_state->modeset) - wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET); - for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { - old_intel_crtc_state = to_intel_crtc_state(old_crtc_state); new_intel_crtc_state = to_intel_crtc_state(new_crtc_state); intel_crtc = to_intel_crtc(crtc); if (needs_modeset(new_crtc_state) || - to_intel_crtc_state(new_crtc_state)->update_pipe) { - + new_intel_crtc_state->update_pipe) { put_domains[intel_crtc->pipe] = modeset_get_crtc_power_domains(crtc, - new_intel_crtc_state); + new_intel_crtc_state); } + } - if (!needs_modeset(new_crtc_state)) - continue; - - intel_pre_plane_update(old_intel_crtc_state, new_intel_crtc_state); - - if (old_crtc_state->active) { - intel_crtc_disable_planes(intel_state, intel_crtc); - - /* - * We need to disable pipe CRC before disabling the pipe, - * or we race against vblank off. - */ - intel_crtc_disable_pipe_crc(intel_crtc); - - dev_priv->display.crtc_disable(old_intel_crtc_state, state); - intel_crtc->active = false; - intel_fbc_disable(intel_crtc); - intel_disable_shared_dpll(old_intel_crtc_state); + drm_atomic_helper_wait_for_dependencies(state); - /* - * Underruns don't always raise - * interrupts, so check manually. - */ - intel_check_cpu_fifo_underruns(dev_priv); - intel_check_pch_fifo_underruns(dev_priv); + if (intel_state->modeset) + wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET); - /* FIXME unify this for all platforms */ - if (!new_crtc_state->active && - !HAS_GMCH(dev_priv) && - dev_priv->display.initial_watermarks) - dev_priv->display.initial_watermarks(intel_state, - new_intel_crtc_state); - } - } + dev_priv->display.commit_modeset_disables(state); /* FIXME: Eventually get rid of our intel_crtc->config pointer */ for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) @@ -15722,6 +15740,9 @@ void intel_init_display_hooks(struct drm_i915_private *dev_priv) dev_priv->display.commit_modeset_enables = skl_commit_modeset_enables; else dev_priv->display.commit_modeset_enables = intel_commit_modeset_enables; + + dev_priv->display.commit_modeset_disables = intel_commit_modeset_disables; + } static i915_reg_t i915_vgacntrl_reg(struct drm_i915_private *dev_priv) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 075d7eb3c3f2..edb6b431f90c 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -311,6 +311,7 @@ struct drm_i915_display_funcs { void (*crtc_disable)(struct intel_crtc_state *old_crtc_state, struct drm_atomic_state *old_state); void (*commit_modeset_enables)(struct drm_atomic_state *state); + void (*commit_modeset_disables)(struct drm_atomic_state *state); void (*audio_codec_enable)(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state, const struct drm_connector_state *conn_state); From patchwork Mon Jun 24 21:08:45 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Navare, Manasi" X-Patchwork-Id: 11014161 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id E818A112C for ; Mon, 24 Jun 2019 21:07:22 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id D898F28949 for ; Mon, 24 Jun 2019 21:07:22 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id CCB3828998; Mon, 24 Jun 2019 21:07:22 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 49C0628949 for ; Mon, 24 Jun 2019 21:07:22 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id A7DEB89DE3; Mon, 24 Jun 2019 21:07:21 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTPS id DBB4D89DE1 for ; Mon, 24 Jun 2019 21:07:09 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga102.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 24 Jun 2019 14:07:09 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.63,413,1557212400"; d="scan'208";a="163740801" Received: from labuser-z97x-ud5h.jf.intel.com ([10.54.75.49]) by orsmga003.jf.intel.com with ESMTP; 24 Jun 2019 14:07:08 -0700 From: Manasi Navare To: intel-gfx@lists.freedesktop.org Date: Mon, 24 Jun 2019 14:08:45 -0700 Message-Id: <20190624210850.17223-4-manasi.d.navare@intel.com> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20190624210850.17223-1-manasi.d.navare@intel.com> References: <20190624210850.17223-1-manasi.d.navare@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v3 3/8] drm/i915/display/icl: Save Master transcoder in slave's crtc_state for Transcoder Port Sync X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Daniel Vetter Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP In case of tiled displays when the two tiles are sent across two CRTCs over two separate DP SST connectors, we need a mechanism to synchronize the two CRTCs and their corresponding transcoders. So use the master-slave mode where there is one master corresponding to last horizontal and vertical tile that needs to be genlocked with all other slave tiles. This patch identifies saves the master transcoder in all the slave CRTC states. This is needed to select the master CRTC/transcoder while configuring transcoder port sync for the corresponding slaves. v3: * Use master_tramscoder instead of master_crtc for valid HW state readouts (Ville) v2: * Move this to intel_mode_set_pipe_config(Jani N, Ville) * Use slave_bitmask to save associated slaves in master crtc state (Ville) Cc: Daniel Vetter Cc: Ville Syrjälä Cc: Maarten Lankhorst Cc: Matt Roper Signed-off-by: Manasi Navare --- drivers/gpu/drm/i915/display/intel_display.c | 102 +++++++++++++++++++ drivers/gpu/drm/i915/display/intel_display.h | 1 + drivers/gpu/drm/i915/intel_drv.h | 6 ++ 3 files changed, 109 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index c34118998ace..367c7fb2be88 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -11600,6 +11600,91 @@ static bool c8_planes_changed(const struct intel_crtc_state *new_crtc_state) return !old_crtc_state->c8_planes != !new_crtc_state->c8_planes; } +static int icl_add_sync_mode_crtcs(struct drm_crtc *crtc, + struct intel_crtc_state *crtc_state, + struct drm_atomic_state *state) +{ + struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev); + struct drm_connector *master_connector, *connector; + struct drm_connector_state *connector_state; + struct drm_connector_list_iter conn_iter; + struct drm_crtc *master_crtc = NULL; + struct drm_crtc_state *master_crtc_state; + struct intel_crtc_state *master_pipe_config; + int i, tile_group_id; + + if (INTEL_GEN(dev_priv) < 11) + return 0; + + /* + * In case of tiled displays there could be one or more slaves but there is + * only one master. Lets make the CRTC used by the connector corresponding + * to the last horizonal and last vertical tile a master/genlock CRTC. + * All the other CRTCs corresponding to other tiles of the same Tile group + * are the slave CRTCs and hold a pointer to their genlock CRTC. + */ + for_each_new_connector_in_state(state, connector, connector_state, i) { + if (connector_state->crtc != crtc) + continue; + if (!connector->has_tile) + continue; + if (crtc_state->base.mode.hdisplay != connector->tile_h_size || + crtc_state->base.mode.vdisplay != connector->tile_v_size) + return 0; + if (connector->tile_h_loc == connector->num_h_tile - 1 && + connector->tile_v_loc == connector->num_v_tile - 1) + continue; + crtc_state->sync_mode_slaves_mask = 0; + tile_group_id = connector->tile_group->id; + drm_connector_list_iter_begin(&dev_priv->drm, &conn_iter); + drm_for_each_connector_iter(master_connector, &conn_iter) { + struct drm_connector_state *master_conn_state = NULL; + + if (!master_connector->has_tile) + continue; + if (master_connector->tile_h_loc != master_connector->num_h_tile - 1 || + master_connector->tile_v_loc != master_connector->num_v_tile - 1) + continue; + if (master_connector->tile_group->id != tile_group_id) + continue; + + master_conn_state = drm_atomic_get_connector_state(state, + master_connector); + if (IS_ERR(master_conn_state)) { + drm_connector_list_iter_end(&conn_iter); + return PTR_ERR(master_conn_state); + } + if (master_conn_state->crtc) { + master_crtc = master_conn_state->crtc; + break; + } + } + drm_connector_list_iter_end(&conn_iter); + + if (!master_crtc) { + DRM_DEBUG_KMS("Could not find Master CRTC for Slave CRTC %d\n", + connector_state->crtc->base.id); + return -EINVAL; + } + + master_crtc_state = drm_atomic_get_crtc_state(state, + master_crtc); + if (IS_ERR(master_crtc_state)) + return PTR_ERR(master_crtc_state); + + master_pipe_config = to_intel_crtc_state(master_crtc_state); + crtc_state->master_transcoder = master_pipe_config->cpu_transcoder; + master_pipe_config->sync_mode_slaves_mask |= + BIT(crtc_state->cpu_transcoder); + DRM_DEBUG_KMS("Master Transcoder = %s added for Slave CRTC = %d, slave transcoder bitmask = %d\n", + transcoder_name(crtc_state->master_transcoder), + crtc_state->base.crtc->base.id, + master_pipe_config->sync_mode_slaves_mask); + } + + return 0; +} + static int intel_crtc_atomic_check(struct drm_crtc *crtc, struct drm_crtc_state *crtc_state) { @@ -12094,6 +12179,9 @@ clear_intel_crtc_state(struct intel_crtc_state *crtc_state) if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) saved_state->wm = crtc_state->wm; + if (INTEL_GEN(dev_priv) >= 11) + saved_state->sync_mode_slaves_mask = + crtc_state->sync_mode_slaves_mask; /* Keep base drm_crtc_state intact, only clear our extended struct */ BUILD_BUG_ON(offsetof(struct intel_crtc_state, base)); @@ -12187,6 +12275,15 @@ intel_modeset_pipe_config(struct intel_crtc_state *pipe_config) drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode, CRTC_STEREO_DOUBLE); + /* Set the crtc_state defaults for trans_port_sync */ + pipe_config->master_transcoder = INVALID_TRANSCODER; + ret = icl_add_sync_mode_crtcs(crtc, pipe_config, state); + if (ret) { + DRM_DEBUG_KMS("Cannot assign Sync Mode CRTCs: %d\n", + ret); + return ret; + } + /* Pass our mode to the connectors and the CRTC to give them a chance to * adjust it according to limitations or connector properties, and also * a chance to reject the mode entirely. @@ -12676,6 +12773,11 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config, PIPE_CONF_CHECK_INFOFRAME(hdmi); PIPE_CONF_CHECK_INFOFRAME(drm); + if (INTEL_GEN(dev_priv) >= 11) { + PIPE_CONF_CHECK_I(sync_mode_slaves_mask); + PIPE_CONF_CHECK_I(master_transcoder); + } + #undef PIPE_CONF_CHECK_X #undef PIPE_CONF_CHECK_I #undef PIPE_CONF_CHECK_BOOL diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h index ee6b8194a459..40054fbec82c 100644 --- a/drivers/gpu/drm/i915/display/intel_display.h +++ b/drivers/gpu/drm/i915/display/intel_display.h @@ -66,6 +66,7 @@ enum pipe { #define pipe_name(p) ((p) + 'A') enum transcoder { + INVALID_TRANSCODER = -1, /* * The following transcoders have a 1:1 transcoder -> pipe mapping, * keep their values fixed: the code assumes that TRANSCODER_A=0, the diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index 1d58f7ec5d84..6e42cf31e5ce 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -946,6 +946,12 @@ struct intel_crtc_state { /* Forward Error correction State */ bool fec_enable; + + /* Pointer to master transcoder in case of tiled displays */ + enum transcoder master_transcoder; + + /* Bitmask to indicate slaves attached */ + u8 sync_mode_slaves_mask; }; struct intel_crtc { From patchwork Mon Jun 24 21:08:46 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Navare, Manasi" X-Patchwork-Id: 11014163 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 8AEA5186E for ; Mon, 24 Jun 2019 21:07:23 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 7C88628949 for ; Mon, 24 Jun 2019 21:07:23 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 70E0D28998; Mon, 24 Jun 2019 21:07:23 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 128D728949 for ; Mon, 24 Jun 2019 21:07:23 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id D0E2A89DE5; Mon, 24 Jun 2019 21:07:21 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTPS id 02EC489D6C for ; Mon, 24 Jun 2019 21:07:09 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga102.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 24 Jun 2019 14:07:09 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.63,413,1557212400"; d="scan'208";a="163740804" Received: from labuser-z97x-ud5h.jf.intel.com ([10.54.75.49]) by orsmga003.jf.intel.com with ESMTP; 24 Jun 2019 14:07:08 -0700 From: Manasi Navare To: intel-gfx@lists.freedesktop.org Date: Mon, 24 Jun 2019 14:08:46 -0700 Message-Id: <20190624210850.17223-5-manasi.d.navare@intel.com> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20190624210850.17223-1-manasi.d.navare@intel.com> References: <20190624210850.17223-1-manasi.d.navare@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v3 4/8] drm/i915/display/icl: Enable TRANSCODER PORT SYNC for tiled displays across separate ports X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jani Nikula , Daniel Vetter Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP In case of tiled displays where different tiles are displayed across different ports, we need to synchronize the transcoders involved. This patch implements the transcoder port sync feature for synchronizing one master transcoder with one or more slave transcoders. This is only enbaled in slave transcoder and the master transcoder is unaware that it is operating in this mode. This has been tested with tiled display connected to ICL. v3: * Check of DP_MST moved to atomic_check (Maarten) v2: * Do not use RMW, just write to the register in commit (Jani N) Cc: Daniel Vetter Cc: Ville Syrjälä Cc: Maarten Lankhorst Cc: Matt Roper Cc: Jani Nikula Signed-off-by: Manasi Navare --- drivers/gpu/drm/i915/display/intel_display.c | 44 ++++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 367c7fb2be88..f359a6212574 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -4366,6 +4366,47 @@ static void icl_set_pipe_chicken(struct intel_crtc *crtc) I915_WRITE(PIPE_CHICKEN(pipe), tmp); } +static void icl_enable_trans_port_sync(struct intel_atomic_state *old_intel_state, + const struct intel_crtc_state *crtc_state) +{ + struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); + u32 trans_ddi_func_ctl2_val; + u8 master_select; + + /* + * Configure the master select and enable Transcoder Port Sync for + * Slave CRTCs transcoder. + */ + if (crtc_state->master_transcoder == INVALID_TRANSCODER) + return; + + switch (crtc_state->master_transcoder) { + case TRANSCODER_A: + master_select = 1; + break; + case TRANSCODER_B: + master_select = 2; + break; + case TRANSCODER_C: + master_select = 3; + break; + case TRANSCODER_EDP: + default: + master_select = 0; + break; + } + /* Set the master select bits for Tranascoder Port Sync */ + trans_ddi_func_ctl2_val = (PORT_SYNC_MODE_MASTER_SELECT(master_select) & + PORT_SYNC_MODE_MASTER_SELECT_MASK) << + PORT_SYNC_MODE_MASTER_SELECT_SHIFT; + /* Enable Transcoder Port Sync */ + trans_ddi_func_ctl2_val |= PORT_SYNC_MODE_ENABLE; + + I915_WRITE(TRANS_DDI_FUNC_CTL2(crtc_state->cpu_transcoder), + trans_ddi_func_ctl2_val); +} + static void intel_update_pipe_config(const struct intel_crtc_state *old_crtc_state, const struct intel_crtc_state *new_crtc_state) { @@ -6344,6 +6385,9 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config, if (!transcoder_is_dsi(cpu_transcoder)) intel_set_pipe_timings(pipe_config); + if (INTEL_GEN(dev_priv) >= 11) + icl_enable_trans_port_sync(old_intel_state, pipe_config); + intel_set_pipe_src_size(pipe_config); if (cpu_transcoder != TRANSCODER_EDP && From patchwork Mon Jun 24 21:08:47 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Navare, Manasi" X-Patchwork-Id: 11014165 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id A362676 for ; Mon, 24 Jun 2019 21:07:24 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 94F4828990 for ; Mon, 24 Jun 2019 21:07:24 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 895F4289B0; Mon, 24 Jun 2019 21:07:24 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 3C61C28990 for ; Mon, 24 Jun 2019 21:07:24 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 0ABA989DEA; Mon, 24 Jun 2019 21:07:22 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTPS id 1FC1C89DE1 for ; Mon, 24 Jun 2019 21:07:10 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga102.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 24 Jun 2019 14:07:09 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.63,413,1557212400"; d="scan'208";a="163740806" Received: from labuser-z97x-ud5h.jf.intel.com ([10.54.75.49]) by orsmga003.jf.intel.com with ESMTP; 24 Jun 2019 14:07:08 -0700 From: Manasi Navare To: intel-gfx@lists.freedesktop.org Date: Mon, 24 Jun 2019 14:08:47 -0700 Message-Id: <20190624210850.17223-6-manasi.d.navare@intel.com> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20190624210850.17223-1-manasi.d.navare@intel.com> References: <20190624210850.17223-1-manasi.d.navare@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v3 5/8] drm/i915/display/icl: HW state readout for transcoder port sync config X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jani Nikula Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP After the state is committed, we readout the HW registers and compare the HW state with the SW state that we just committed. For Transcdoer port sync, we add master_transcoder and the salves bitmask to the crtc_state, hence we need to read those during the HW state readout to avoid pipe state mismatch. Cc: Ville Syrjälä Cc: Maarten Lankhorst Cc: Matt Roper Cc: Jani Nikula Signed-off-by: Manasi Navare --- drivers/gpu/drm/i915/display/intel_display.c | 44 ++++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index f359a6212574..7156b1b4c6c5 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -10271,6 +10271,47 @@ static void haswell_get_ddi_port_state(struct intel_crtc *crtc, } } +static void icelake_get_trans_port_sync_config(struct intel_crtc *crtc, + struct intel_crtc_state *pipe_config) +{ + struct drm_device *dev = crtc->base.dev; + struct drm_i915_private *dev_priv = to_i915(dev); + u32 trans_port_sync, transcoders, master_select; + enum transcoder cpu_transcoder; + + trans_port_sync = I915_READ(TRANS_DDI_FUNC_CTL2(pipe_config->cpu_transcoder)); + if (trans_port_sync & PORT_SYNC_MODE_ENABLE) { + master_select = trans_port_sync & + PORT_SYNC_MODE_MASTER_SELECT_MASK; + switch (master_select) { + case 1: + pipe_config->master_transcoder = TRANSCODER_A; + break; + case 2: + pipe_config->master_transcoder = TRANSCODER_B; + break; + case 3: + pipe_config->master_transcoder = TRANSCODER_C; + break; + default: + pipe_config->master_transcoder = TRANSCODER_EDP; + break; + } + } else + pipe_config->master_transcoder = INVALID_TRANSCODER; + + transcoders = BIT(TRANSCODER_EDP) | + BIT(TRANSCODER_A) | + BIT(TRANSCODER_B) | + BIT(TRANSCODER_C); + for_each_cpu_transcoder_masked(dev_priv, cpu_transcoder, transcoders) { + trans_port_sync = I915_READ(TRANS_DDI_FUNC_CTL2(cpu_transcoder)); + + if (trans_port_sync & PORT_SYNC_MODE_ENABLE) + pipe_config->sync_mode_slaves_mask |= BIT(cpu_transcoder); + } +} + static bool haswell_get_pipe_config(struct intel_crtc *crtc, struct intel_crtc_state *pipe_config) { @@ -10367,6 +10408,9 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc, pipe_config->pixel_multiplier = 1; } + if (INTEL_GEN(dev_priv) >= 11) + icelake_get_trans_port_sync_config(crtc, pipe_config); + out: for_each_power_domain(power_domain, power_domain_mask) intel_display_power_put(dev_priv, From patchwork Mon Jun 24 21:08:48 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Navare, Manasi" X-Patchwork-Id: 11014167 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id BC0A276 for ; Mon, 24 Jun 2019 21:07:25 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id AC66728925 for ; Mon, 24 Jun 2019 21:07:25 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id A106528998; Mon, 24 Jun 2019 21:07:25 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id E29DF28917 for ; Mon, 24 Jun 2019 21:07:24 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 3F89D89DED; Mon, 24 Jun 2019 21:07:22 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTPS id 3A60F89D6C for ; Mon, 24 Jun 2019 21:07:10 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga102.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 24 Jun 2019 14:07:09 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.63,413,1557212400"; d="scan'208";a="163740810" Received: from labuser-z97x-ud5h.jf.intel.com ([10.54.75.49]) by orsmga003.jf.intel.com with ESMTP; 24 Jun 2019 14:07:08 -0700 From: Manasi Navare To: intel-gfx@lists.freedesktop.org Date: Mon, 24 Jun 2019 14:08:48 -0700 Message-Id: <20190624210850.17223-7-manasi.d.navare@intel.com> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20190624210850.17223-1-manasi.d.navare@intel.com> References: <20190624210850.17223-1-manasi.d.navare@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v3 6/8] drm/i915/display/icl: Enable master-slaves in trans port sync mode in correct order X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Daniel Vetter Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP As per the display enable sequence, we need to follow the enable sequence for slaves first with DP_TP_CTL set to Idle and configure the transcoder port sync register to select the corersponding master, then follow the enable sequence for master leaving DP_TP_CTL to idle. At this point the transcoder port sync mode is configured and enabled and the Vblanks of both ports are synchronized so then set DP_TP_CTL for the slave and master to Normal and do post crtc enable updates. v2: * Create a icl_update_crtcs hook (Maarten, Danvet) * This sequence only for CRTCs in trans port sync mode (Maarten) Cc: Daniel Vetter Cc: Ville Syrjälä Cc: Maarten Lankhorst Cc: Matt Roper Signed-off-by: Manasi Navare --- drivers/gpu/drm/i915/display/intel_ddi.c | 3 +- drivers/gpu/drm/i915/display/intel_display.c | 217 ++++++++++++++++++- drivers/gpu/drm/i915/display/intel_display.h | 4 + 3 files changed, 221 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index 7925a176f900..bceb7e4b1877 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -3154,7 +3154,8 @@ static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder, true); intel_dp_sink_set_fec_ready(intel_dp, crtc_state); intel_dp_start_link_train(intel_dp); - if (port != PORT_A || INTEL_GEN(dev_priv) >= 9) + if ((port != PORT_A || INTEL_GEN(dev_priv) >= 9) && + !is_trans_port_sync_mode(crtc_state)) intel_dp_stop_link_train(intel_dp); intel_ddi_enable_fec(encoder, crtc_state); diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 7156b1b4c6c5..f88d3a929e36 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -520,6 +520,26 @@ needs_modeset(const struct drm_crtc_state *state) return drm_atomic_crtc_needs_modeset(state); } +bool +is_trans_port_sync_mode(const struct intel_crtc_state *state) +{ + return (state->master_transcoder != INVALID_TRANSCODER || + state->sync_mode_slaves_mask); +} + +static bool +is_trans_port_sync_slave(const struct intel_crtc_state *state) +{ + return state->master_transcoder != INVALID_TRANSCODER; +} + +static bool +is_trans_port_sync_master(const struct intel_crtc_state *state) +{ + return (state->master_transcoder == INVALID_TRANSCODER && + state->sync_mode_slaves_mask); +} + /* * Platform specific helpers to calculate the port PLL loopback- (clock.m), * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast @@ -13944,9 +13964,200 @@ static void skl_commit_modeset_enables(struct drm_atomic_state *state) progress = true; } } while (progress); +} +static void icl_commit_modeset_enables(struct drm_atomic_state *state) +{ + struct drm_i915_private *dev_priv = to_i915(state->dev); + struct intel_atomic_state *intel_state = to_intel_atomic_state(state); + struct drm_crtc *crtc; + struct intel_crtc *intel_crtc; + struct drm_crtc_state *old_crtc_state, *new_crtc_state; + struct intel_crtc_state *cstate; + unsigned int updated = 0; + bool progress; + enum pipe pipe; + int i; + u8 hw_enabled_slices = dev_priv->wm.skl_hw.ddb.enabled_slices; + u8 required_slices = intel_state->wm_results.ddb.enabled_slices; + struct skl_ddb_entry entries[I915_MAX_PIPES] = {}; + + for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) + /* ignore allocations for crtc's that have been turned off. */ + if (new_crtc_state->active) + entries[i] = to_intel_crtc_state(old_crtc_state)->wm.skl.ddb; + + /* If 2nd DBuf slice required, enable it here */ + if (required_slices > hw_enabled_slices) + icl_dbuf_slices_update(dev_priv, required_slices); + + /* + * Whenever the number of active pipes changes, we need to make sure we + * update the pipes in the right order so that their ddb allocations + * never overlap with eachother inbetween CRTC updates. Otherwise we'll + * cause pipe underruns and other bad stuff. + */ + do { + progress = false; + + for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { + bool vbl_wait = false; + unsigned int cmask = drm_crtc_mask(crtc); + bool modeset = needs_modeset(new_crtc_state); + + intel_crtc = to_intel_crtc(crtc); + cstate = to_intel_crtc_state(new_crtc_state); + pipe = intel_crtc->pipe; + + if (updated & cmask || !cstate->base.active) + continue; + + if (modeset && is_trans_port_sync_mode(cstate)) { + DRM_DEBUG_KMS("Pushing the Sync Mode CRTC %d %s that needs update to separate loop\n", + intel_crtc->base.base.id, intel_crtc->base.name); + continue; + } + + if (skl_ddb_allocation_overlaps(&cstate->wm.skl.ddb, + entries, + INTEL_INFO(dev_priv)->num_pipes, i)) + continue; + + updated |= cmask; + entries[i] = cstate->wm.skl.ddb; + + /* + * If this is an already active pipe, it's DDB changed, + * and this isn't the last pipe that needs updating + * then we need to wait for a vblank to pass for the + * new ddb allocation to take effect. + */ + if (!skl_ddb_entry_equal(&cstate->wm.skl.ddb, + &to_intel_crtc_state(old_crtc_state)->wm.skl.ddb) && + !new_crtc_state->active_changed && + intel_state->wm_results.dirty_pipes != updated) + vbl_wait = true; + + intel_update_crtc(crtc, state, old_crtc_state, + new_crtc_state); + + if (vbl_wait) + intel_wait_for_vblank(dev_priv, pipe); + + progress = true; + } + } while (progress); + + /* Separate loop for updating Slave CRTCs that need modeset. + * We need to loop through all slaves of tiled display first and + * follow enable sequence with DP_TP_CTL left Idle until the master + * is ready. + */ + for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { + bool modeset = needs_modeset(new_crtc_state); + struct intel_crtc_state *pipe_config = + to_intel_crtc_state(new_crtc_state); + + intel_crtc = to_intel_crtc(crtc); + + if (!pipe_config->base.active || !modeset || + !is_trans_port_sync_slave(pipe_config)) + continue; + + update_scanline_offset(pipe_config); + dev_priv->display.crtc_enable(pipe_config, state); + intel_crtc_enable_pipe_crc(intel_crtc); + } + /* Now do the display enable sequence for master CRTC */ + for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { + bool modeset = needs_modeset(new_crtc_state); + struct intel_crtc_state *pipe_config = + to_intel_crtc_state(new_crtc_state); + + intel_crtc = to_intel_crtc(crtc); + + if (!pipe_config->base.active || !modeset || + !is_trans_port_sync_master(pipe_config)) + continue; + + update_scanline_offset(pipe_config); + dev_priv->display.crtc_enable(pipe_config, state); + intel_crtc_enable_pipe_crc(intel_crtc); + } + /* Set Slave's DP_TP_CTL to Normal */ + for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { + int j; + struct drm_connector_state *conn_state; + struct drm_connector *conn; + bool modeset = needs_modeset(new_crtc_state); + struct intel_dp *intel_dp; + struct intel_crtc_state *pipe_config = + to_intel_crtc_state(new_crtc_state); + + intel_crtc = to_intel_crtc(crtc); + + if (!pipe_config->base.active || !modeset || + !is_trans_port_sync_slave(pipe_config)) + continue; + + for_each_new_connector_in_state(state, conn, conn_state, j) { + if (conn_state->crtc == crtc) + break; + } + intel_dp = enc_to_intel_dp(&intel_attached_encoder(conn)->base); + intel_dp_stop_link_train(intel_dp); + } + /* Set Master's DP_TP_CTL to Normal */ + for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { + int j; + struct drm_connector_state *conn_state; + struct drm_connector *conn; + bool modeset = needs_modeset(new_crtc_state); + struct intel_dp *intel_dp; + struct intel_crtc_state *pipe_config = + to_intel_crtc_state(new_crtc_state); + + intel_crtc = to_intel_crtc(crtc); + + if (!pipe_config->base.active || !modeset || + !is_trans_port_sync_master(pipe_config)) + continue; + + /* Wait for 200us before setting the master DP_TP_TCL to Normal */ + usleep_range(200, 400); + for_each_new_connector_in_state(state, conn, conn_state, j) { + if (conn_state->crtc == crtc) + break; + } + intel_dp = enc_to_intel_dp(&intel_attached_encoder(conn)->base); + intel_dp_stop_link_train(intel_dp); + } + /* Now do the post crtc enable for all master and slaves */ + for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { + bool modeset = needs_modeset(new_crtc_state); + struct intel_plane_state *new_plane_state; + struct intel_crtc_state *pipe_config = to_intel_crtc_state(new_crtc_state); + + intel_crtc = to_intel_crtc(crtc); + + if (!pipe_config->base.active || !modeset || + !is_trans_port_sync_mode(pipe_config)) + continue; + + new_plane_state = + intel_atomic_get_new_plane_state(to_intel_atomic_state(state), + to_intel_plane(crtc->primary)); + if (pipe_config->update_pipe && !pipe_config->enable_fbc) + intel_fbc_disable(intel_crtc); + else if (new_plane_state) + intel_fbc_enable(intel_crtc, pipe_config, new_plane_state); + + intel_begin_crtc_commit(to_intel_atomic_state(state), intel_crtc); + skl_update_planes_on_crtc(to_intel_atomic_state(state), intel_crtc); + intel_finish_crtc_commit(to_intel_atomic_state(state), intel_crtc); + } /* If 2nd DBuf slice is no more required disable it */ - if (INTEL_GEN(dev_priv) >= 11 && required_slices < hw_enabled_slices) + if (required_slices < hw_enabled_slices) icl_dbuf_slices_update(dev_priv, required_slices); } @@ -15926,7 +16137,9 @@ void intel_init_display_hooks(struct drm_i915_private *dev_priv) dev_priv->display.fdi_link_train = hsw_fdi_link_train; } - if (INTEL_GEN(dev_priv) >= 9) + if (INTEL_GEN(dev_priv) >= 11) + dev_priv->display.commit_modeset_enables = icl_commit_modeset_enables; + else if (INTEL_GEN(dev_priv) >= 9) dev_priv->display.commit_modeset_enables = skl_commit_modeset_enables; else dev_priv->display.commit_modeset_enables = intel_commit_modeset_enables; diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h index 40054fbec82c..29f6c4c91d53 100644 --- a/drivers/gpu/drm/i915/display/intel_display.h +++ b/drivers/gpu/drm/i915/display/intel_display.h @@ -28,8 +28,11 @@ #include #include +#include "intel_dp_link_training.h" + struct drm_i915_private; struct intel_plane_state; +struct intel_crtc_state; enum i915_gpio { GPIOA, @@ -358,5 +361,6 @@ void lpt_disable_clkout_dp(struct drm_i915_private *dev_priv); u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv, u32 pixel_format, u64 modifier); bool intel_plane_can_remap(const struct intel_plane_state *plane_state); +bool is_trans_port_sync_mode(const struct intel_crtc_state *state); #endif From patchwork Mon Jun 24 21:08:49 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Navare, Manasi" X-Patchwork-Id: 11014159 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 35C2D76 for ; Mon, 24 Jun 2019 21:07:19 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 2711E28949 for ; Mon, 24 Jun 2019 21:07:19 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 1A87928998; Mon, 24 Jun 2019 21:07:19 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id B98A228949 for ; Mon, 24 Jun 2019 21:07:18 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 4FA3189DE1; Mon, 24 Jun 2019 21:07:18 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTPS id 5A60C89DE3 for ; Mon, 24 Jun 2019 21:07:10 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga102.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 24 Jun 2019 14:07:10 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.63,413,1557212400"; d="scan'208";a="163740812" Received: from labuser-z97x-ud5h.jf.intel.com ([10.54.75.49]) by orsmga003.jf.intel.com with ESMTP; 24 Jun 2019 14:07:08 -0700 From: Manasi Navare To: intel-gfx@lists.freedesktop.org Date: Mon, 24 Jun 2019 14:08:49 -0700 Message-Id: <20190624210850.17223-8-manasi.d.navare@intel.com> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20190624210850.17223-1-manasi.d.navare@intel.com> References: <20190624210850.17223-1-manasi.d.navare@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v3 7/8] drm/i915/display/icl: Disable transcoder port sync as part of crtc_disable() sequence X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jani Nikula Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP This clears the transcoder port sync bits of the TRANS_DDI_FUNC_CTL2 register during crtc_disable(). Cc: Ville Syrjälä Cc: Maarten Lankhorst Cc: Matt Roper Cc: Jani Nikula Signed-off-by: Manasi Navare --- drivers/gpu/drm/i915/display/intel_display.c | 44 ++++++++++++++++---- 1 file changed, 35 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index f88d3a929e36..0a0d97ef03d6 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -4427,6 +4427,26 @@ static void icl_enable_trans_port_sync(struct intel_atomic_state *old_intel_stat trans_ddi_func_ctl2_val); } +static void icl_disable_transcoder_port_sync(const struct intel_crtc_state *old_crtc_state) +{ + struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc); + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); + i915_reg_t reg; + u32 trans_ddi_func_ctl2_val; + + if (old_crtc_state->master_transcoder == INVALID_TRANSCODER) + return; + + DRM_DEBUG_KMS("Disabling Transcoder Port Sync on Slave Transcoder %s\n", + transcoder_name(old_crtc_state->cpu_transcoder)); + + reg = TRANS_DDI_FUNC_CTL2(old_crtc_state->cpu_transcoder); + trans_ddi_func_ctl2_val = I915_READ(reg); + trans_ddi_func_ctl2_val &= ~(PORT_SYNC_MODE_ENABLE | + PORT_SYNC_MODE_MASTER_SELECT_MASK); + I915_WRITE(reg, trans_ddi_func_ctl2_val); +} + static void intel_update_pipe_config(const struct intel_crtc_state *old_crtc_state, const struct intel_crtc_state *new_crtc_state) { @@ -6586,6 +6606,9 @@ static void haswell_crtc_disable(struct intel_crtc_state *old_crtc_state, if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DP_MST)) intel_ddi_set_vc_payload_alloc(old_crtc_state, false); + if (INTEL_GEN(dev_priv) >= 11) + icl_disable_transcoder_port_sync(old_crtc_state); + if (!transcoder_is_dsi(cpu_transcoder)) intel_ddi_disable_transcoder_func(old_crtc_state); @@ -10317,18 +10340,21 @@ static void icelake_get_trans_port_sync_config(struct intel_crtc *crtc, pipe_config->master_transcoder = TRANSCODER_EDP; break; } - } else + + pipe_config->sync_mode_slaves_mask = 0; + } else { pipe_config->master_transcoder = INVALID_TRANSCODER; - transcoders = BIT(TRANSCODER_EDP) | - BIT(TRANSCODER_A) | - BIT(TRANSCODER_B) | - BIT(TRANSCODER_C); - for_each_cpu_transcoder_masked(dev_priv, cpu_transcoder, transcoders) { - trans_port_sync = I915_READ(TRANS_DDI_FUNC_CTL2(cpu_transcoder)); + transcoders = BIT(TRANSCODER_EDP) | + BIT(TRANSCODER_A) | + BIT(TRANSCODER_B) | + BIT(TRANSCODER_C); + for_each_cpu_transcoder_masked(dev_priv, cpu_transcoder, transcoders) { + trans_port_sync = I915_READ(TRANS_DDI_FUNC_CTL2(cpu_transcoder)); - if (trans_port_sync & PORT_SYNC_MODE_ENABLE) - pipe_config->sync_mode_slaves_mask |= BIT(cpu_transcoder); + if (trans_port_sync & PORT_SYNC_MODE_ENABLE) + pipe_config->sync_mode_slaves_mask |= BIT(cpu_transcoder); + } } } From patchwork Mon Jun 24 21:08:50 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Navare, Manasi" X-Patchwork-Id: 11014169 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 33263186E for ; Mon, 24 Jun 2019 21:07:26 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 24CBE28917 for ; Mon, 24 Jun 2019 21:07:26 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 19AA428949; Mon, 24 Jun 2019 21:07:26 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id A508128917 for ; Mon, 24 Jun 2019 21:07:25 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 98B9A89DFB; Mon, 24 Jun 2019 21:07:22 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTPS id 7FADA89DE5 for ; Mon, 24 Jun 2019 21:07:10 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga102.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 24 Jun 2019 14:07:10 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.63,413,1557212400"; d="scan'208";a="163740815" Received: from labuser-z97x-ud5h.jf.intel.com ([10.54.75.49]) by orsmga003.jf.intel.com with ESMTP; 24 Jun 2019 14:07:09 -0700 From: Manasi Navare To: intel-gfx@lists.freedesktop.org Date: Mon, 24 Jun 2019 14:08:50 -0700 Message-Id: <20190624210850.17223-9-manasi.d.navare@intel.com> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20190624210850.17223-1-manasi.d.navare@intel.com> References: <20190624210850.17223-1-manasi.d.navare@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v3 8/8] drm/i915/display/icl: In port sync mode disable slaves first then masters X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jani Nikula Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP In the transcoder port sync mode, the slave transcoders mask their vblanks until master transcoder's vblank so while disabling them, make sure slaves are disabled first and then the masters. Cc: Ville Syrjälä Cc: Maarten Lankhorst Cc: Matt Roper Cc: Jani Nikula Signed-off-by: Manasi Navare --- drivers/gpu/drm/i915/display/intel_display.c | 117 ++++++++++++++++++- 1 file changed, 111 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 0a0d97ef03d6..85746a26d0e0 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -13901,6 +13901,106 @@ static void intel_commit_modeset_disables(struct drm_atomic_state *state) } } +static void icl_commit_modeset_disables(struct drm_atomic_state *state) +{ + struct drm_device *dev = state->dev; + struct intel_atomic_state *intel_state = to_intel_atomic_state(state); + struct drm_i915_private *dev_priv = to_i915(dev); + struct drm_crtc_state *old_crtc_state, *new_crtc_state; + struct intel_crtc_state *new_intel_crtc_state, *old_intel_crtc_state; + struct drm_crtc *crtc; + struct intel_crtc *intel_crtc; + int i; + + /* + * Disable all the Port Sync Slaves first + */ + for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { + old_intel_crtc_state = to_intel_crtc_state(old_crtc_state); + new_intel_crtc_state = to_intel_crtc_state(new_crtc_state); + intel_crtc = to_intel_crtc(crtc); + + if (!needs_modeset(new_crtc_state) || + !is_trans_port_sync_slave(old_intel_crtc_state)) + continue; + + intel_pre_plane_update(old_intel_crtc_state, new_intel_crtc_state); + + if (old_crtc_state->active) { + intel_crtc_disable_planes(intel_state, intel_crtc); + + /* + * We need to disable pipe CRC before disabling the pipe, + * or we race against vblank off. + */ + intel_crtc_disable_pipe_crc(intel_crtc); + + dev_priv->display.crtc_disable(old_intel_crtc_state, state); + intel_crtc->active = false; + intel_fbc_disable(intel_crtc); + intel_disable_shared_dpll(old_intel_crtc_state); + + /* + * Underruns don't always raise interrupts, + * so check manually. + */ + intel_check_cpu_fifo_underruns(dev_priv); + intel_check_pch_fifo_underruns(dev_priv); + + /* FIXME unify this for all platforms */ + if (!new_crtc_state->active && + !HAS_GMCH(dev_priv) && + dev_priv->display.initial_watermarks) + dev_priv->display.initial_watermarks(intel_state, + new_intel_crtc_state); + } + } + + /* + * Disable rest of the CRTCs other than slaves + */ + for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { + old_intel_crtc_state = to_intel_crtc_state(old_crtc_state); + new_intel_crtc_state = to_intel_crtc_state(new_crtc_state); + intel_crtc = to_intel_crtc(crtc); + + if (!needs_modeset(new_crtc_state) || + is_trans_port_sync_slave(old_intel_crtc_state)) + continue; + + intel_pre_plane_update(old_intel_crtc_state, new_intel_crtc_state); + + if (old_crtc_state->active) { + intel_crtc_disable_planes(intel_state, intel_crtc); + + /* + * We need to disable pipe CRC before disabling the pipe, + * or we race against vblank off. + */ + intel_crtc_disable_pipe_crc(intel_crtc); + + dev_priv->display.crtc_disable(old_intel_crtc_state, state); + intel_crtc->active = false; + intel_fbc_disable(intel_crtc); + intel_disable_shared_dpll(old_intel_crtc_state); + + /* + * Underruns don't always raise interrupts, + * so check manually. + */ + intel_check_cpu_fifo_underruns(dev_priv); + intel_check_pch_fifo_underruns(dev_priv); + + /* FIXME unify this for all platforms */ + if (!new_crtc_state->active && + !HAS_GMCH(dev_priv) && + dev_priv->display.initial_watermarks) + dev_priv->display.initial_watermarks(intel_state, + new_intel_crtc_state); + } + } +} + static void intel_commit_modeset_enables(struct drm_atomic_state *state) { struct drm_crtc *crtc; @@ -14257,6 +14357,11 @@ static void intel_atomic_commit_tail(struct drm_atomic_state *state) intel_atomic_commit_fence_wait(intel_state); + drm_atomic_helper_wait_for_dependencies(state); + + if (intel_state->modeset) + wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET); + for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { new_intel_crtc_state = to_intel_crtc_state(new_crtc_state); intel_crtc = to_intel_crtc(crtc); @@ -14269,11 +14374,6 @@ static void intel_atomic_commit_tail(struct drm_atomic_state *state) } } - drm_atomic_helper_wait_for_dependencies(state); - - if (intel_state->modeset) - wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET); - dev_priv->display.commit_modeset_disables(state); /* FIXME: Eventually get rid of our intel_crtc->config pointer */ @@ -16170,7 +16270,12 @@ void intel_init_display_hooks(struct drm_i915_private *dev_priv) else dev_priv->display.commit_modeset_enables = intel_commit_modeset_enables; - dev_priv->display.commit_modeset_disables = intel_commit_modeset_disables; + if (INTEL_GEN(dev_priv) >= 11) + dev_priv->display.commit_modeset_disables = + icl_commit_modeset_disables; + else + dev_priv->display.commit_modeset_disables = + intel_commit_modeset_disables; }