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Date: Mon, 24 Jun 2019 15:38:19 -0700 Message-Id: <20190624223819.14320-1-atish.patra@wdc.com> X-Mailer: git-send-email 2.21.0 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190624_153854_400844_F55F12CA X-CRM114-Status: UNSURE ( 8.59 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , devicetree@vger.kernel.org, Albert Ou , Anup Patel , Palmer Dabbelt , Atish Patra , Yash Shah , Rob Herring , Paul Walmsley , linux-riscv@lists.infradead.org Sender: "linux-riscv" Errors-To: linux-riscv-bounces+patchwork-linux-riscv=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Currently, there is no CPU topology defined for RISC-V. The following series adds topology support in RISC-V. http://lists.infradead.org/pipermail/linux-riscv/2019-June/005072.html Add a DT node for unleashed that describes the CPU topology present in HiFive Unleashed. Signed-off-by: Atish Patra Reviewed-by: Palmer Dabbelt --- arch/riscv/boot/dts/sifive/fu540-c000.dtsi | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi index 83f40b00ab63..907564f4f07a 100644 --- a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi +++ b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi @@ -22,6 +22,24 @@ #address-cells = <1>; #size-cells = <0>; timebase-frequency = <1000000>; + + cpu-map { + cluster0 { + core0 { + cpu = <&cpu1>; + }; + core1 { + cpu = <&cpu2>; + }; + core2 { + cpu = <&cpu3>; + }; + core3 { + cpu = <&cpu4>; + }; + }; + }; + cpu0: cpu@0 { compatible = "sifive,e51", "sifive,rocket0", "riscv"; device_type = "cpu";