From patchwork Thu Jun 27 04:44:42 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sai Prakash Ranjan X-Patchwork-Id: 11018713 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 1B28114C0 for ; Thu, 27 Jun 2019 04:45:08 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 09094289FB for ; Thu, 27 Jun 2019 04:45:08 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id F10D928A19; Thu, 27 Jun 2019 04:45:07 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.7 required=2.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 5A69F289FB for ; Thu, 27 Jun 2019 04:45:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727017AbfF0EpG (ORCPT ); Thu, 27 Jun 2019 00:45:06 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:41640 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725385AbfF0EpG (ORCPT ); Thu, 27 Jun 2019 00:45:06 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 2B6E760767; Thu, 27 Jun 2019 04:45:05 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1561610705; bh=YS6o769+NUXJLCLSg99xSxR1Jeof3nDcPuh33f70AFc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=cZPNq+RCBv8XaY4er9sSYa4wK/CsKnmkt1jBm3TBET6QkcMwgCvumhLhLF/Gq2yU8 g83z3rvNquEojpE0HC0Zzk8DfGtqRXT4JUk54NPV0DvyryNmG/74nWsCbaEyYusRNs tfbgBm7obHc0Wx94Eesn+5EdzbNmdBkr1V9Ye7l0= Received: from blr-ubuntu-311.qualcomm.com (blr-bdr-fw-01_globalnat_allzones-outside.qualcomm.com [103.229.18.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: saiprakash.ranjan@codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 1D3ED60ADE; Thu, 27 Jun 2019 04:44:59 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1561610703; bh=YS6o769+NUXJLCLSg99xSxR1Jeof3nDcPuh33f70AFc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=XjGF5xszH+AjtNIA603kW8HPS4l/wXdvy6UIVTYNa3F8tLFpOSgRRwSMdZwMPkAy2 w62FKofse5h8zJD5ahRc09ED+rIHds+NZ9NYVfyeruvUCVBI/bRWTHlOTmXpgDNq6z QsJX6YmvaUOTQxI9zY2gN3gSLaSIL33giSHQ8iGw= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 1D3ED60ADE Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=saiprakash.ranjan@codeaurora.org From: Sai Prakash Ranjan To: Mathieu Poirier , Suzuki K Poulose , Rob Herring , devicetree@vger.kernel.org, Leo Yan , Alexander Shishkin , David Brown , Mark Rutland Cc: Rajendra Nayak , Vivek Gautam , Sibi Sankar , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, Sai Prakash Ranjan Subject: [RESEND PATCHv4 1/1] coresight: Do not default to CPU0 for missing CPU phandle Date: Thu, 27 Jun 2019 10:14:42 +0530 Message-Id: <0a20cf9eb34b14a191381af98af1694bbc222734.1561610498.git.saiprakash.ranjan@codeaurora.org> X-Mailer: git-send-email 2.22.0 In-Reply-To: References: MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Coresight platform support assumes that a missing "cpu" phandle defaults to CPU0. This could be problematic and unnecessarily binds components to CPU0, where they may not be. Let us make the DT binding rules a bit stricter by not defaulting to CPU0 for missing "cpu" affinity information. Also in coresight etm and cpu-debug drivers, abort the probe for such cases. Signed-off-by: Sai Prakash Ranjan Reviewed-by: Suzuki K Poulose --- .../bindings/arm/coresight-cpu-debug.txt | 4 ++-- .../devicetree/bindings/arm/coresight.txt | 8 +++++--- .../hwtracing/coresight/coresight-cpu-debug.c | 3 +++ drivers/hwtracing/coresight/coresight-etm3x.c | 3 +++ drivers/hwtracing/coresight/coresight-etm4x.c | 3 +++ .../hwtracing/coresight/coresight-platform.c | 20 +++++++++---------- 6 files changed, 26 insertions(+), 15 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/coresight-cpu-debug.txt b/Documentation/devicetree/bindings/arm/coresight-cpu-debug.txt index 298291211ea4..f1de3247c1b7 100644 --- a/Documentation/devicetree/bindings/arm/coresight-cpu-debug.txt +++ b/Documentation/devicetree/bindings/arm/coresight-cpu-debug.txt @@ -26,8 +26,8 @@ Required properties: processor core is clocked by the internal CPU clock, so it is enabled with CPU clock by default. -- cpu : the CPU phandle the debug module is affined to. When omitted - the module is considered to belong to CPU0. +- cpu : the CPU phandle the debug module is affined to. Do not assume it + to default to CPU0 if omitted. Optional properties: diff --git a/Documentation/devicetree/bindings/arm/coresight.txt b/Documentation/devicetree/bindings/arm/coresight.txt index 8a88ddebc1a2..fcc3bacfd8bc 100644 --- a/Documentation/devicetree/bindings/arm/coresight.txt +++ b/Documentation/devicetree/bindings/arm/coresight.txt @@ -59,6 +59,11 @@ its hardware characteristcs. * port or ports: see "Graph bindings for Coresight" below. +* Additional required property for Embedded Trace Macrocell (version 3.x and + version 4.x): + * cpu: the cpu phandle this ETM/PTM is affined to. Do not + assume it to default to CPU0 if omitted. + * Additional required properties for System Trace Macrocells (STM): * reg: along with the physical base address and length of the register set as described above, another entry is required to describe the @@ -87,9 +92,6 @@ its hardware characteristcs. * arm,cp14: must be present if the system accesses ETM/PTM management registers via co-processor 14. - * cpu: the cpu phandle this ETM/PTM is affined to. When omitted the - source is considered to belong to CPU0. - * Optional property for TMC: * arm,buffer-size: size of contiguous buffer space for TMC ETR diff --git a/drivers/hwtracing/coresight/coresight-cpu-debug.c b/drivers/hwtracing/coresight/coresight-cpu-debug.c index 07a1367c733f..58bfd6319f65 100644 --- a/drivers/hwtracing/coresight/coresight-cpu-debug.c +++ b/drivers/hwtracing/coresight/coresight-cpu-debug.c @@ -579,6 +579,9 @@ static int debug_probe(struct amba_device *adev, const struct amba_id *id) return -ENOMEM; drvdata->cpu = coresight_get_cpu(dev); + if (drvdata->cpu < 0) + return drvdata->cpu; + if (per_cpu(debug_drvdata, drvdata->cpu)) { dev_err(dev, "CPU%d drvdata has already been initialized\n", drvdata->cpu); diff --git a/drivers/hwtracing/coresight/coresight-etm3x.c b/drivers/hwtracing/coresight/coresight-etm3x.c index 225c2982e4fe..e2cb6873c3f2 100644 --- a/drivers/hwtracing/coresight/coresight-etm3x.c +++ b/drivers/hwtracing/coresight/coresight-etm3x.c @@ -816,6 +816,9 @@ static int etm_probe(struct amba_device *adev, const struct amba_id *id) } drvdata->cpu = coresight_get_cpu(dev); + if (drvdata->cpu < 0) + return drvdata->cpu; + desc.name = devm_kasprintf(dev, GFP_KERNEL, "etm%d", drvdata->cpu); if (!desc.name) return -ENOMEM; diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c b/drivers/hwtracing/coresight/coresight-etm4x.c index 7fe266194ab5..7bcac8896fc1 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.c +++ b/drivers/hwtracing/coresight/coresight-etm4x.c @@ -1101,6 +1101,9 @@ static int etm4_probe(struct amba_device *adev, const struct amba_id *id) spin_lock_init(&drvdata->spinlock); drvdata->cpu = coresight_get_cpu(dev); + if (drvdata->cpu < 0) + return drvdata->cpu; + desc.name = devm_kasprintf(dev, GFP_KERNEL, "etm%d", drvdata->cpu); if (!desc.name) return -ENOMEM; diff --git a/drivers/hwtracing/coresight/coresight-platform.c b/drivers/hwtracing/coresight/coresight-platform.c index 3c5ceda8db24..cf580ffbc27c 100644 --- a/drivers/hwtracing/coresight/coresight-platform.c +++ b/drivers/hwtracing/coresight/coresight-platform.c @@ -159,16 +159,16 @@ static int of_coresight_get_cpu(struct device *dev) struct device_node *dn; if (!dev->of_node) - return 0; + return -ENODEV; + dn = of_parse_phandle(dev->of_node, "cpu", 0); - /* Affinity defaults to CPU0 */ if (!dn) - return 0; + return -ENODEV; + cpu = of_cpu_node_to_id(dn); of_node_put(dn); - /* Affinity to CPU0 if no cpu nodes are found */ - return (cpu < 0) ? 0 : cpu; + return cpu; } /* @@ -310,7 +310,7 @@ of_get_coresight_platform_data(struct device *dev, static inline int of_coresight_get_cpu(struct device *dev) { - return 0; + return -ENODEV; } #endif @@ -734,14 +734,14 @@ static int acpi_coresight_get_cpu(struct device *dev) struct acpi_device *adev = ACPI_COMPANION(dev); if (!adev) - return 0; + return -ENODEV; status = acpi_get_parent(adev->handle, &cpu_handle); if (ACPI_FAILURE(status)) - return 0; + return -ENODEV; cpu = acpi_handle_to_logical_cpuid(cpu_handle); if (cpu >= nr_cpu_ids) - return 0; + return -ENODEV; return cpu; } @@ -769,7 +769,7 @@ acpi_get_coresight_platform_data(struct device *dev, static inline int acpi_coresight_get_cpu(struct device *dev) { - return 0; + return -ENODEV; } #endif