From patchwork Thu Jun 27 13:34:21 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sibi Sankar X-Patchwork-Id: 11019725 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 8981F13B4 for ; Thu, 27 Jun 2019 13:34:44 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 7A60326C9B for ; Thu, 27 Jun 2019 13:34:44 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 77EDE28B3D; Thu, 27 Jun 2019 13:34:44 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.7 required=2.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id C6463288C4 for ; Thu, 27 Jun 2019 13:34:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726841AbfF0Nen (ORCPT ); Thu, 27 Jun 2019 09:34:43 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:37228 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726370AbfF0Nen (ORCPT ); Thu, 27 Jun 2019 09:34:43 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 5415C607CA; Thu, 27 Jun 2019 13:34:42 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1561642482; bh=sNGHRg/AVqvcuTMuiO6jtsnX89/WYPc7sjQ6Yr/5IKE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ZUuCCPGw9JYEnIf5r5uZ6Ml24cepvZKH7TEkucJs1K18mzh+U/8A6s+2duGLLWMri k1HearZJT1LRD9CXYp3eU1VZqo1xRmZ6PVbQWS9AvyFUh0DPF0Pj59VZyjw8C3duCT RsaWZo0gmP7J5UFZcBRBoTAJgSCzP1lxJ8Lut2Rk= Received: from blr-ubuntu-87.qualcomm.com (blr-bdr-fw-01_globalnat_allzones-outside.qualcomm.com [103.229.18.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: sibis@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 7FE5660A33; Thu, 27 Jun 2019 13:34:37 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1561642481; bh=sNGHRg/AVqvcuTMuiO6jtsnX89/WYPc7sjQ6Yr/5IKE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=eYD501kMzkX4BCy96Ew+uubjgWIYzLGl5EemTcDgTLvPhhWWmScA0/Rqvkw37gRtv WdsP1jPSr78oHs2AnlWC+Wm2eXkD0MpD022/iCIdfdZTkWfjC0B1UJ9sDlnEKkcY3t zzlGe43dO43hxM57Ete04ly9v8xcPODoUYKGHzVg= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 7FE5660A33 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=sibis@codeaurora.org From: Sibi Sankar To: viresh.kumar@linaro.org, nm@ti.com, sboyd@kernel.org, georgi.djakov@linaro.org Cc: agross@kernel.org, david.brown@linaro.org, robh+dt@kernel.org, mark.rutland@arm.com, rjw@rjwysocki.net, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, saravanak@google.com, Sibi Sankar Subject: [PATCH RFC 1/4] OPP: Add and export helper to update voltage Date: Thu, 27 Jun 2019 19:04:21 +0530 Message-Id: <20190627133424.4980-2-sibis@codeaurora.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190627133424.4980-1-sibis@codeaurora.org> References: <20190627133424.4980-1-sibis@codeaurora.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add and export 'dev_pm_opp_update_voltage' to find and update voltage of an opp for a given frequency. This will be useful to update the opps with voltages read back from firmware. Signed-off-by: Sibi Sankar --- drivers/opp/core.c | 52 ++++++++++++++++++++++++++++++++++++++++++ include/linux/pm_opp.h | 10 ++++++++ 2 files changed, 62 insertions(+) diff --git a/drivers/opp/core.c b/drivers/opp/core.c index 68551d6366e6b..c85c04dc2c7de 100644 --- a/drivers/opp/core.c +++ b/drivers/opp/core.c @@ -2197,6 +2197,58 @@ int dev_pm_opp_disable(struct device *dev, unsigned long freq) } EXPORT_SYMBOL_GPL(dev_pm_opp_disable); +/** + * dev_pm_opp_update_voltage() - Find and update voltage + * @dev: device for which we do this operation + * @freq: OPP frequency to update voltage + * @u_volt: voltage requested for this opp + * + * Find and update voltage of a disabled opp corresponding to the given + * frequency. This is useful only for devices with single power supply. + * + * Return: 0 if no modification was done OR modification was + * successful or a negative error value. + */ +int dev_pm_opp_update_voltage(struct device *dev, unsigned long freq, + unsigned long u_volt) +{ + struct dev_pm_opp *opp = ERR_PTR(-ENODEV); + struct opp_table *opp_table; + unsigned long tol; + int ret = 0; + + opp = dev_pm_opp_find_freq_exact(dev, freq, false); + if (IS_ERR(opp)) + return PTR_ERR(opp); + + /* Find the opp_table */ + opp_table = _find_opp_table(dev); + if (IS_ERR(opp_table)) { + ret = PTR_ERR(opp_table); + dev_err(dev, "%s: OPP table not found (%d)\n", __func__, ret); + goto put_opp; + } + + mutex_lock(&opp_table->lock); + + /* update only if the opp is disabled */ + if (opp->available) + goto unlock; + + tol = u_volt * opp_table->voltage_tolerance_v1 / 100; + opp->supplies[0].u_volt_min = u_volt - tol; + opp->supplies[0].u_volt = u_volt; + opp->supplies[0].u_volt_min = u_volt + tol; + +unlock: + mutex_unlock(&opp_table->lock); + dev_pm_opp_put_opp_table(opp_table); +put_opp: + dev_pm_opp_put(opp); + return ret; +} +EXPORT_SYMBOL_GPL(dev_pm_opp_update_voltage); + /** * dev_pm_opp_register_notifier() - Register OPP notifier for the device * @dev: Device for which notifier needs to be registered diff --git a/include/linux/pm_opp.h b/include/linux/pm_opp.h index 87fa09d93d8c2..a17c462974851 100644 --- a/include/linux/pm_opp.h +++ b/include/linux/pm_opp.h @@ -130,6 +130,9 @@ int dev_pm_opp_enable(struct device *dev, unsigned long freq); int dev_pm_opp_disable(struct device *dev, unsigned long freq); +int dev_pm_opp_update_voltage(struct device *dev, unsigned long freq, + unsigned long u_volt); + int dev_pm_opp_register_notifier(struct device *dev, struct notifier_block *nb); int dev_pm_opp_unregister_notifier(struct device *dev, struct notifier_block *nb); @@ -261,6 +264,13 @@ static inline int dev_pm_opp_disable(struct device *dev, unsigned long freq) return 0; } +static inline int dev_pm_opp_update_voltage(struct device *dev, + unsigned long freq, + unsigned long u_volt) +{ + return 0; +} + static inline int dev_pm_opp_register_notifier(struct device *dev, struct notifier_block *nb) { return -ENOTSUPP; From patchwork Thu Jun 27 13:34:22 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sibi Sankar X-Patchwork-Id: 11019737 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 497781708 for ; Thu, 27 Jun 2019 13:35:08 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 39C2C28738 for ; Thu, 27 Jun 2019 13:35:08 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 2B7F028B45; Thu, 27 Jun 2019 13:35:08 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.7 required=2.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id C550428738 for ; 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Thu, 27 Jun 2019 13:34:41 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1561642485; bh=3W21pQMFNZFtYVC6GlWd+gVxHXzD/QUiLxcs6mipQqU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=n/ziMy77wzDA1k2VuMRaSUiLXp/tZilMDVQe9oYy8VY5CrhLJfXPc1NZnBpvvT5IX ZdIfvdeQ9xiWFY0EI703Od/CizMUljxE3E1X/QRHQE2y7L2IOsaqeuy7EJyqNYrGbj Qa92WpLcvYgditEMgvayLGbi6/PwUtkyy6qfOEdM= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org CCF6460C8B Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=sibis@codeaurora.org From: Sibi Sankar To: viresh.kumar@linaro.org, nm@ti.com, sboyd@kernel.org, georgi.djakov@linaro.org Cc: agross@kernel.org, david.brown@linaro.org, robh+dt@kernel.org, mark.rutland@arm.com, rjw@rjwysocki.net, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, saravanak@google.com, Sibi Sankar Subject: [PATCH RFC 2/4] OPP: Add and export helper to set bandwidth Date: Thu, 27 Jun 2019 19:04:22 +0530 Message-Id: <20190627133424.4980-3-sibis@codeaurora.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190627133424.4980-1-sibis@codeaurora.org> References: <20190627133424.4980-1-sibis@codeaurora.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add and export 'dev_pm_opp_set_bw' to set the bandwidth levels associated with an OPP for a given frequency. Signed-off-by: Sibi Sankar --- drivers/opp/core.c | 46 ++++++++++++++++++++++++++++++++++++++++++ include/linux/pm_opp.h | 6 ++++++ 2 files changed, 52 insertions(+) diff --git a/drivers/opp/core.c b/drivers/opp/core.c index c85c04dc2c7de..78f42960860d1 100644 --- a/drivers/opp/core.c +++ b/drivers/opp/core.c @@ -746,6 +746,52 @@ static int _set_required_opps(struct device *dev, return ret; } +/** + * dev_pm_opp_set_bw() - Configures OPP bandwidth levels + * @dev: device for which we do this operation + * @freq: bandwidth values to set with matching 'freq' + * + * This configures the bandwidth to the levels specified + * by the OPP corresponding to the given frequency. + * + * Return: 0 on success or a negative error value. + */ +int dev_pm_opp_set_bw(struct device *dev, unsigned long freq) +{ + struct opp_table *opp_table; + struct dev_pm_opp *opp; + int ret = 0; + int i; + + opp = dev_pm_opp_find_freq_exact(dev, freq, true); + if (IS_ERR(opp)) + return PTR_ERR(opp); + + opp_table = _find_opp_table(dev); + if (IS_ERR(opp_table)) { + dev_err(dev, "%s: device opp table doesn't exist\n", __func__); + ret = PTR_ERR(opp_table); + goto put_opp; + } + + if (IS_ERR_OR_NULL(opp_table->paths)) { + ret = -ENODEV; + goto put_opp_table; + } + + for (i = 0; i < opp_table->path_count; i++) { + ret = icc_set_bw(opp_table->paths[i], opp->bandwidth[i].avg, + opp->bandwidth[i].peak); + } + +put_opp_table: + dev_pm_opp_put_opp_table(opp_table); +put_opp: + dev_pm_opp_put(opp); + return ret; +} +EXPORT_SYMBOL_GPL(dev_pm_opp_set_bw); + /** * dev_pm_opp_set_rate() - Configure new OPP based on frequency * @dev: device for which we do this operation diff --git a/include/linux/pm_opp.h b/include/linux/pm_opp.h index a17c462974851..1cdc2d0a2b20e 100644 --- a/include/linux/pm_opp.h +++ b/include/linux/pm_opp.h @@ -152,6 +152,7 @@ struct opp_table *dev_pm_opp_attach_genpd(struct device *dev, const char **names void dev_pm_opp_detach_genpd(struct opp_table *opp_table); int dev_pm_opp_xlate_performance_state(struct opp_table *src_table, struct opp_table *dst_table, unsigned int pstate); int dev_pm_opp_set_rate(struct device *dev, unsigned long target_freq); +int dev_pm_opp_set_bw(struct device *dev, unsigned long freq); int dev_pm_opp_set_sharing_cpus(struct device *cpu_dev, const struct cpumask *cpumask); int dev_pm_opp_get_sharing_cpus(struct device *cpu_dev, struct cpumask *cpumask); void dev_pm_opp_remove_table(struct device *dev); @@ -336,6 +337,11 @@ static inline int dev_pm_opp_set_rate(struct device *dev, unsigned long target_f return -ENOTSUPP; } +static inline int dev_pm_opp_set_bw(struct device *dev, unsigned long freq) +{ + return -ENOTSUPP; +} + static inline int dev_pm_opp_set_sharing_cpus(struct device *cpu_dev, const struct cpumask *cpumask) { return -ENOTSUPP; From patchwork Thu Jun 27 13:34:23 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sibi Sankar X-Patchwork-Id: 11019733 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 0E91F1708 for ; Thu, 27 Jun 2019 13:35:07 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 01A9C28995 for ; Thu, 27 Jun 2019 13:35:07 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id E96AC28B4C; Thu, 27 Jun 2019 13:35:06 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.7 required=2.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 73BEC28995 for ; Thu, 27 Jun 2019 13:35:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727026AbfF0Ne4 (ORCPT ); Thu, 27 Jun 2019 09:34:56 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:37908 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726786AbfF0New (ORCPT ); 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h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=MfL9qh11hclbeBBKYns3z3SqVR3XNzITO9pvnOCCGEDndlK8hK/jgS3C4I2jRjRkG DSSp3qCdkw3Nxr3wJFo5zq6OGS4+iMjV2oj4LCADnLkwK0W2R54RAdnMqgmq5XUv9e eFLluiIi2XK4Ei/VrxhNwHoLiADobc44JGWM1EVA= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 2A8A360E59 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=sibis@codeaurora.org From: Sibi Sankar To: viresh.kumar@linaro.org, nm@ti.com, sboyd@kernel.org, georgi.djakov@linaro.org Cc: agross@kernel.org, david.brown@linaro.org, robh+dt@kernel.org, mark.rutland@arm.com, rjw@rjwysocki.net, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, saravanak@google.com, Sibi Sankar Subject: [PATCH RFC 3/4] cpufreq: qcom: Update the bandwidth levels on frequency change Date: Thu, 27 Jun 2019 19:04:23 +0530 Message-Id: <20190627133424.4980-4-sibis@codeaurora.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190627133424.4980-1-sibis@codeaurora.org> References: <20190627133424.4980-1-sibis@codeaurora.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add support to parse and update optional OPP tables attached to the cpu nodes when the OPP bandwidth values are populated to enable scaling of DDR/L3 bandwidth levels with frequency change. Signed-off-by: Sibi Sankar --- drivers/cpufreq/qcom-cpufreq-hw.c | 77 ++++++++++++++++++++++++++++++- 1 file changed, 75 insertions(+), 2 deletions(-) diff --git a/drivers/cpufreq/qcom-cpufreq-hw.c b/drivers/cpufreq/qcom-cpufreq-hw.c index 4b0b50403901b..eacc75fac9b00 100644 --- a/drivers/cpufreq/qcom-cpufreq-hw.c +++ b/drivers/cpufreq/qcom-cpufreq-hw.c @@ -6,6 +6,7 @@ #include #include #include +#include #include #include #include @@ -30,13 +31,41 @@ static unsigned long cpu_hw_rate, xo_rate; static struct platform_device *global_pdev; +static int qcom_cpufreq_set_bw(struct cpufreq_policy *policy, + unsigned long freq_khz) +{ + struct device *dev; + + dev = get_cpu_device(policy->cpu); + if (!dev) + return -ENODEV; + + return dev_pm_opp_set_bw(dev, freq_khz * 1000); +} + +static int qcom_cpufreq_update_opp(struct device *cpu_dev, + unsigned long freq_khz, + unsigned long volt) +{ + unsigned long freq_hz = freq_khz * 1000; + + if (dev_pm_opp_update_voltage(cpu_dev, freq_hz, volt)) + return dev_pm_opp_add(cpu_dev, freq_hz, volt); + + /* Enable the opp after voltage update*/ + return dev_pm_opp_enable(cpu_dev, freq_hz); +} + static int qcom_cpufreq_hw_target_index(struct cpufreq_policy *policy, unsigned int index) { void __iomem *perf_state_reg = policy->driver_data; + u32 freq = policy->freq_table[index].frequency; writel_relaxed(index, perf_state_reg); + qcom_cpufreq_set_bw(policy, freq); + return 0; } @@ -79,13 +108,29 @@ static int qcom_cpufreq_hw_read_lut(struct device *cpu_dev, { u32 data, src, lval, i, core_count, prev_cc = 0, prev_freq = 0, freq; u32 volt; + u64 rate; unsigned int max_cores = cpumask_weight(policy->cpus); struct cpufreq_frequency_table *table; + struct device_node *opp_table_np, *np; + int ret; table = kcalloc(LUT_MAX_ENTRIES + 1, sizeof(*table), GFP_KERNEL); if (!table) return -ENOMEM; + ret = dev_pm_opp_of_add_table(cpu_dev); + if (!ret) { + /* Disable all opps and cross-validate against LUT */ + opp_table_np = dev_pm_opp_of_get_opp_desc_node(cpu_dev); + for_each_available_child_of_node(opp_table_np, np) { + ret = of_property_read_u64(np, "opp-hz", &rate); + dev_pm_opp_disable(cpu_dev, rate); + } + of_node_put(opp_table_np); + } else { + dev_err(cpu_dev, "Couldn't add OPP table from dt\n"); + } + for (i = 0; i < LUT_MAX_ENTRIES; i++) { data = readl_relaxed(base + REG_FREQ_LUT + i * LUT_ROW_SIZE); @@ -104,7 +149,7 @@ static int qcom_cpufreq_hw_read_lut(struct device *cpu_dev, if (freq != prev_freq && core_count == max_cores) { table[i].frequency = freq; - dev_pm_opp_add(cpu_dev, freq * 1000, volt); + qcom_cpufreq_update_opp(cpu_dev, freq, volt); dev_dbg(cpu_dev, "index=%d freq=%d, core_count %d\n", i, freq, core_count); } else { @@ -125,7 +170,8 @@ static int qcom_cpufreq_hw_read_lut(struct device *cpu_dev, if (prev_cc != max_cores) { prev->frequency = prev_freq; prev->flags = CPUFREQ_BOOST_FREQ; - dev_pm_opp_add(cpu_dev, prev_freq * 1000, volt); + qcom_cpufreq_update_opp(cpu_dev, prev_freq, + volt); } break; @@ -168,6 +214,7 @@ static void qcom_get_related_cpus(int index, struct cpumask *m) static int qcom_cpufreq_hw_cpu_init(struct cpufreq_policy *policy) { struct device *dev = &global_pdev->dev; + struct opp_table *opp_table = NULL; struct of_phandle_args args; struct device_node *cpu_np; struct device *cpu_dev; @@ -202,6 +249,8 @@ static int qcom_cpufreq_hw_cpu_init(struct cpufreq_policy *policy) if (!base) return -ENOMEM; + opp_table = dev_pm_opp_set_paths(cpu_dev); + /* HW should be in enabled state to proceed */ if (!(readl_relaxed(base + REG_ENABLE) & 0x1)) { dev_err(dev, "Domain-%d cpufreq hardware not enabled\n", index); @@ -237,6 +286,8 @@ static int qcom_cpufreq_hw_cpu_init(struct cpufreq_policy *policy) return 0; error: + if (opp_table) + dev_pm_opp_put_paths(opp_table); devm_iounmap(dev, base); return ret; } @@ -275,6 +326,8 @@ static struct cpufreq_driver cpufreq_qcom_hw_driver = { static int qcom_cpufreq_hw_driver_probe(struct platform_device *pdev) { + struct opp_table *opp_table = NULL; + struct device *cpu_dev; struct clk *clk; int ret; @@ -294,6 +347,26 @@ static int qcom_cpufreq_hw_driver_probe(struct platform_device *pdev) global_pdev = pdev; + /* Check for optional interconnect paths on CPU0 */ + cpu_dev = get_cpu_device(0); + if (!cpu_dev) { + dev_err(&pdev->dev, "failed to get cpu0 device\n"); + return -ENODEV; + } + + opp_table = dev_pm_opp_set_paths(cpu_dev); + if (IS_ERR(opp_table)) { + ret = PTR_ERR(opp_table); + if (ret == -EPROBE_DEFER) { + dev_dbg(&pdev->dev, "defer icc set paths: %d\n", ret); + return ret; + } + dev_err(&pdev->dev, "set paths failed ddr/l3 scaling off: %d\n", + ret); + } else { + dev_pm_opp_put_paths(opp_table); + } + ret = cpufreq_register_driver(&cpufreq_qcom_hw_driver); if (ret) dev_err(&pdev->dev, "CPUFreq HW driver failed to register\n"); From patchwork Thu Jun 27 13:34:24 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sibi Sankar X-Patchwork-Id: 11019727 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 548FD13B4 for ; Thu, 27 Jun 2019 13:35:05 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 3F02528738 for ; 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dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=sibis@codeaurora.org From: Sibi Sankar To: viresh.kumar@linaro.org, nm@ti.com, sboyd@kernel.org, georgi.djakov@linaro.org Cc: agross@kernel.org, david.brown@linaro.org, robh+dt@kernel.org, mark.rutland@arm.com, rjw@rjwysocki.net, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, saravanak@google.com, Sibi Sankar Subject: [PATCH RFC 4/4] arm64: dts: qcom: sdm845: Add cpu OPP tables Date: Thu, 27 Jun 2019 19:04:24 +0530 Message-Id: <20190627133424.4980-5-sibis@codeaurora.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190627133424.4980-1-sibis@codeaurora.org> References: <20190627133424.4980-1-sibis@codeaurora.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add OPP tables for the cpu nodes. Signed-off-by: Sibi Sankar --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 343 +++++++++++++++++++++++++++ 1 file changed, 343 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 471cbb7d9bc39..8cabbb274d3e7 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -197,6 +197,10 @@ qcom,freq-domain = <&cpufreq_hw 0>; #cooling-cells = <2>; next-level-cache = <&L2_0>; + operating-points-v2 = <&cpu0_opp_table>; + /* path between CPU and DDR memory and CPU and L3 */ + interconnects = <&rsc_hlos MASTER_APPSS_PROC &rsc_hlos SLAVE_EBI1>, + <&rsc_hlos MASTER_APPSS_PROC &osm_l3 SLAVE_OSM_L3>; L2_0: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>; @@ -218,6 +222,10 @@ qcom,freq-domain = <&cpufreq_hw 0>; #cooling-cells = <2>; next-level-cache = <&L2_100>; + operating-points-v2 = <&cpu0_opp_table>; + /* path between CPU and DDR memory and CPU and L3 */ + interconnects = <&rsc_hlos MASTER_APPSS_PROC &rsc_hlos SLAVE_EBI1>, + <&rsc_hlos MASTER_APPSS_PROC &osm_l3 SLAVE_OSM_L3>; L2_100: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>; @@ -236,6 +244,10 @@ qcom,freq-domain = <&cpufreq_hw 0>; #cooling-cells = <2>; next-level-cache = <&L2_200>; + operating-points-v2 = <&cpu0_opp_table>; + /* path between CPU and DDR memory and CPU and L3 */ + interconnects = <&rsc_hlos MASTER_APPSS_PROC &rsc_hlos SLAVE_EBI1>, + <&rsc_hlos MASTER_APPSS_PROC &osm_l3 SLAVE_OSM_L3>; L2_200: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>; @@ -254,6 +266,10 @@ qcom,freq-domain = <&cpufreq_hw 0>; #cooling-cells = <2>; next-level-cache = <&L2_300>; + operating-points-v2 = <&cpu0_opp_table>; + /* path between CPU and DDR memory and CPU and L3 */ + interconnects = <&rsc_hlos MASTER_APPSS_PROC &rsc_hlos SLAVE_EBI1>, + <&rsc_hlos MASTER_APPSS_PROC &osm_l3 SLAVE_OSM_L3>; L2_300: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>; @@ -272,6 +288,10 @@ qcom,freq-domain = <&cpufreq_hw 1>; #cooling-cells = <2>; next-level-cache = <&L2_400>; + operating-points-v2 = <&cpu4_opp_table>; + /* path between CPU and DDR memory and CPU and L3 */ + interconnects = <&rsc_hlos MASTER_APPSS_PROC &rsc_hlos SLAVE_EBI1>, + <&rsc_hlos MASTER_APPSS_PROC &osm_l3 SLAVE_OSM_L3>; L2_400: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>; @@ -290,6 +310,10 @@ qcom,freq-domain = <&cpufreq_hw 1>; #cooling-cells = <2>; next-level-cache = <&L2_500>; + operating-points-v2 = <&cpu4_opp_table>; + /* path between CPU and DDR memory and CPU and L3 */ + interconnects = <&rsc_hlos MASTER_APPSS_PROC &rsc_hlos SLAVE_EBI1>, + <&rsc_hlos MASTER_APPSS_PROC &osm_l3 SLAVE_OSM_L3>; L2_500: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>; @@ -308,6 +332,10 @@ qcom,freq-domain = <&cpufreq_hw 1>; #cooling-cells = <2>; next-level-cache = <&L2_600>; + operating-points-v2 = <&cpu4_opp_table>; + /* path between CPU and DDR memory and CPU and L3 */ + interconnects = <&rsc_hlos MASTER_APPSS_PROC &rsc_hlos SLAVE_EBI1>, + <&rsc_hlos MASTER_APPSS_PROC &osm_l3 SLAVE_OSM_L3>; L2_600: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>; @@ -326,6 +354,10 @@ qcom,freq-domain = <&cpufreq_hw 1>; #cooling-cells = <2>; next-level-cache = <&L2_700>; + operating-points-v2 = <&cpu4_opp_table>; + /* path between CPU and DDR memory and CPU and L3 */ + interconnects = <&rsc_hlos MASTER_APPSS_PROC &rsc_hlos SLAVE_EBI1>, + <&rsc_hlos MASTER_APPSS_PROC &osm_l3 SLAVE_OSM_L3>; L2_700: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>; @@ -423,6 +455,317 @@ }; }; + cpu0_opp_table: cpu0_opp_table { + compatible = "operating-points-v2"; + opp-shared; + + cpu0_opp1: opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + /* CPU<->DDR bandwidth: 0 MB/s average, 762 MB/s peak */ + /* CPU<->L3 bandwidth: 0 MB/s average, 4577 MB/s peak */ + bandwidth-MBps = <0 762>, <0 4577>; + }; + + cpu0_opp2: opp-403200000 { + opp-hz = /bits/ 64 <403200000>; + /* CPU<->DDR bandwidth: 0 MB/s average, 762 MB/s peak */ + /* CPU<->L3 bandwidth: 0 MB/s average, 4577 MB/s peak */ + bandwidth-MBps = <0 762>, <0 4577>; + }; + + cpu0_opp3: opp-480000000 { + opp-hz = /bits/ 64 <480000000>; + /* CPU<->DDR bandwidth: 0 MB/s average, 762 MB/s peak */ + /* CPU<->L3 bandwidth: 0 MB/s average, 6152 MB/s peak */ + bandwidth-MBps = <0 762>, <0 6152>; + }; + + cpu0_opp4: opp-576000000 { + opp-hz = /bits/ 64 <576000000>; + /* CPU<->DDR bandwidth: 0 MB/s average, 762 MB/s peak */ + /* CPU<->L3 bandwidth: 0 MB/s average, 6152 MB/s peak */ + bandwidth-MBps = <0 762>, <0 6152>; + }; + + cpu0_opp5: opp-652800000 { + opp-hz = /bits/ 64 <652800000>; + /* CPU<->DDR bandwidth: 0 MB/s average, 762 MB/s peak */ + /* CPU<->L3 bandwidth: 0 MB/s average, 7324 MB/s peak */ + bandwidth-MBps = <0 762>, <0 7324>; + }; + + cpu0_opp6: opp-748800000 { + opp-hz = /bits/ 64 <748800000>; + /* CPU<->DDR bandwidth: 0 MB/s average, 1720 MB/s peak */ + /* CPU<->L3 bandwidth: 0 MB/s average, 8789 MB/s peak */ + bandwidth-MBps = <0 1720>, <0 8789>; + }; + + cpu0_opp7: opp-825600000 { + opp-hz = /bits/ 64 <825600000>; + /* CPU<->DDR bandwidth: 0 MB/s average, 1720 MB/s peak */ + /* CPU<->L3 bandwidth: 0 MB/s average, 8789 MB/s peak */ + bandwidth-MBps = <0 1720>, <0 8789>; + }; + + cpu0_opp8: opp-902400000 { + opp-hz = /bits/ 64 <902400000>; + /* CPU<->DDR bandwidth: 0 MB/s average, 1720 MB/s peak */ + /* CPU<->L3 bandwidth: 0 MB/s average, 9960 MB/s peak */ + bandwidth-MBps = <0 1720>, <0 9960>; + }; + + cpu0_opp9: opp-979200000 { + opp-hz = /bits/ 64 <979200000>; + /* CPU<->DDR bandwidth: 0 MB/s average, 1720 MB/s peak */ + /* CPU<->L3 bandwidth: 0 MB/s average, 11425 MB/s peak */ + bandwidth-MBps = <0 1720>, <0 11425>; + }; + + cpu0_opp10: opp-1056000000 { + opp-hz = /bits/ 64 <1056000000>; + /* CPU<->DDR bandwidth: 0 MB/s average, 1720 MB/s peak */ + /* CPU<->L3 bandwidth: 0 MB/s average, 11425 MB/s peak */ + bandwidth-MBps = <0 1720>, <0 11425>; + }; + + cpu0_opp11: opp-1132800000 { + opp-hz = /bits/ 64 <1132800000>; + /* CPU<->DDR bandwidth: 0 MB/s average, 2086 MB/s peak */ + /* CPU<->L3 bandwidth: 0 MB/s average, 12890 MB/s peak */ + bandwidth-MBps = <0 2086>, <0 12890>; + }; + + cpu0_opp12: opp-1228800000 { + opp-hz = /bits/ 64 <1228800000>; + /* CPU<->DDR bandwidth: 0 MB/s average, 2086 MB/s peak */ + /* CPU<->L3 bandwidth: 0 MB/s average, 14355 MB/s peak */ + bandwidth-MBps = <0 2086>, <0 14355>; + }; + + cpu0_opp13: opp-1324800000 { + opp-hz = /bits/ 64 <1324800000>; + /* CPU<->DDR bandwidth: 0 MB/s average, 2086 MB/s peak */ + /* CPU<->L3 bandwidth: 0 MB/s average, 15820 MB/s peak */ + bandwidth-MBps = <0 2086>, <0 15820>; + }; + + cpu0_opp14: opp-1420800000 { + opp-hz = /bits/ 64 <1420800000>; + /* CPU<->DDR bandwidth: 0 MB/s average, 2086 MB/s peak */ + /* CPU<->L3 bandwidth: 0 MB/s average, 17285 MB/s peak */ + bandwidth-MBps = <0 2086>, <0 17285>; + }; + + cpu0_opp15: opp-1516800000 { + opp-hz = /bits/ 64 <1516800000>; + /* CPU<->DDR bandwidth: 0 MB/s average, 2597 MB/s peak */ + /* CPU<->L3 bandwidth: 0 MB/s average, 18457 MB/s peak */ + bandwidth-MBps = <0 2597>, <0 18457>; + }; + + cpu0_opp16: opp-1612800000 { + opp-hz = /bits/ 64 <1612800000>; + /* CPU<->DDR bandwidth: 0 MB/s average, 3879 MB/s peak */ + /* CPU<->L3 bandwidth: 0 MB/s average, 18457 MB/s peak */ + bandwidth-MBps = <0 3879>, <0 18457>; + }; + + cpu0_opp17: opp-1689600000 { + opp-hz = /bits/ 64 <1689600000>; + /* CPU<->DDR bandwidth: 0 MB/s average, 3879 MB/s peak */ + /* CPU<->L3 bandwidth: 0 MB/s average, 19921 MB/s peak */ + bandwidth-MBps = <0 3879>, <0 19921>; + }; + + cpu0_opp18: opp-1766400000 { + opp-hz = /bits/ 64 <1766400000>; + /* CPU<->DDR bandwidth: 0 MB/s average, 3879 MB/s peak */ + /* CPU<->L3 bandwidth: 0 MB/s average, 21386 MB/s peak */ + bandwidth-MBps = <0 3879>, <0 21386>; + }; + }; + + cpu4_opp_table: cpu4_opp_table { + compatible = "operating-points-v2"; + opp-shared; + + cpu4_opp1: opp-825600000 { + opp-hz = /bits/ 64 <825600000>; + /* CPU<->DDR bandwidth: 0 MB/s average, 1144 MB/s peak */ + /* CPU<->L3 bandwidth: 0 MB/s average, 8789 MB/s peak */ + bandwidth-MBps = <0 1144>, <0 8789>; + }; + + cpu4_opp2: opp-902400000 { + opp-hz = /bits/ 64 <902400000>; + /* CPU<->DDR bandwidth: 0 MB/s average, 1144 MB/s peak */ + /* CPU<->L3 bandwidth: 0 MB/s average, 8789 MB/s peak */ + bandwidth-MBps = <0 1144>, <0 8789>; + }; + + cpu4_opp3: opp-979200000 { + opp-hz = /bits/ 64 <979200000>; + /* CPU<->DDR bandwidth: 0 MB/s average, 1144 MB/s peak */ + /* CPU<->L3 bandwidth: 0 MB/s average, 8789 MB/s peak */ + bandwidth-MBps = <0 1144>, <0 8789>; + }; + + cpu4_opp4: opp-1056000000 { + opp-hz = /bits/ 64 <1056000000>; + /* CPU<->DDR bandwidth: 0 MB/s average, 2929 MB/s peak */ + /* CPU<->L3 bandwidth: 0 MB/s average, 11425 MB/s peak */ + bandwidth-MBps = <0 2929>, <0 11425>; + }; + + cpu4_opp5: opp-1209600000 { + opp-hz = /bits/ 64 <1209600000>; + /* CPU<->DDR bandwidth: 0 MB/s average, 3879 MB/s peak */ + /* CPU<->L3 bandwidth: 0 MB/s average, 11425 MB/s peak */ + bandwidth-MBps = <0 3879>, <0 11425>; + }; + + cpu4_opp6: opp-1286400000 { + opp-hz = /bits/ 64 <1286400000>; + /* CPU<->DDR bandwidth: 0 MB/s average, 3879 MB/s peak */ + /* CPU<->L3 bandwidth: 0 MB/s average, 11425 MB/s peak */ + bandwidth-MBps = <0 3879>, <0 11425>; + }; + + cpu4_opp7: opp-1363200000 { + opp-hz = /bits/ 64 <1363200000>; + /* CPU<->DDR bandwidth: 0 MB/s average, 3879 MB/s peak */ + /* CPU<->L3 bandwidth: 0 MB/s average, 14355 MB/s peak */ + bandwidth-MBps = <0 3879>, <0 14355>; + }; + + cpu4_opp8: opp-1459200000 { + opp-hz = /bits/ 64 <1459200000>; + /* CPU<->DDR bandwidth: 0 MB/s average, 3879 MB/s peak */ + /* CPU<->L3 bandwidth: 0 MB/s average, 14355 MB/s peak */ + bandwidth-MBps = <0 3879>, <0 14355>; + }; + + cpu4_opp9: opp-1536000000 { + opp-hz = /bits/ 64 <1536000000>; + /* CPU<->DDR bandwidth: 0 MB/s average, 3879 MB/s peak */ + /* CPU<->L3 bandwidth: 0 MB/s average, 14355 MB/s peak */ + bandwidth-MBps = <0 3879>, <0 14355>; + }; + + cpu4_opp10: opp-1612800000 { + opp-hz = /bits/ 64 <1612800000>; + /* CPU<->DDR bandwidth: 0 MB/s average, 4943 MB/s peak */ + /* CPU<->L3 bandwidth: 0 MB/s average, 14355 MB/s peak */ + bandwidth-MBps = <0 4943>, <0 14355>; + }; + + cpu4_opp11: opp-1689600000 { + opp-hz = /bits/ 64 <1689600000>; + /* CPU<->DDR bandwidth: 0 MB/s average, 4943 MB/s peak */ + /* CPU<->L3 bandwidth: 0 MB/s average, 18457 MB/s peak */ + bandwidth-MBps = <0 4943>, <0 18457>; + }; + + cpu4_opp12: opp-1766400000 { + opp-hz = /bits/ 64 <1766400000>; + /* CPU<->DDR bandwidth: 0 MB/s average, 5931 MB/s peak */ + /* CPU<->L3 bandwidth: 0 MB/s average, 18457 MB/s peak */ + bandwidth-MBps = <0 5931>, <0 18457>; + }; + + cpu4_opp13: opp-1843200000 { + opp-hz = /bits/ 64 <1843200000>; + /* CPU<->DDR bandwidth: 0 MB/s average, 5931 MB/s peak */ + /* CPU<->L3 bandwidth: 0 MB/s average, 18457 MB/s peak */ + bandwidth-MBps = <0 5931>, <0 18457>; + }; + + cpu4_opp14: opp-1920000000 { + opp-hz = /bits/ 64 <1920000000>; + /* CPU<->DDR bandwidth: 0 MB/s average, 5931 MB/s peak */ + /* CPU<->L3 bandwidth: 0 MB/s average, 18457 MB/s peak */ + bandwidth-MBps = <0 5931>, <0 18457>; + }; + + cpu4_opp15: opp-1996800000 { + opp-hz = /bits/ 64 <1996800000>; + /* CPU<->DDR bandwidth: 0 MB/s average, 6881 MB/s peak */ + /* CPU<->L3 bandwidth: 0 MB/s average, 19921 MB/s peak */ + bandwidth-MBps = <0 6881>, <0 19921>; + }; + + cpu4_opp16: opp-2092800000 { + opp-hz = /bits/ 64 <2092800000>; + /* CPU<->DDR bandwidth: 0 MB/s average, 6881 MB/s peak */ + /* CPU<->L3 bandwidth: 0 MB/s average, 19921 MB/s peak */ + bandwidth-MBps = <0 6881>, <0 19921>; + }; + + cpu4_opp17: opp-2169600000 { + opp-hz = /bits/ 64 <2169600000>; + /* CPU<->DDR bandwidth: 0 MB/s average, 6881 MB/s peak */ + /* CPU<->L3 bandwidth: 0 MB/s average, 19921 MB/s peak */ + bandwidth-MBps = <0 6881>, <0 19921>; + }; + + cpu4_opp18: opp-2246400000 { + opp-hz = /bits/ 64 <2246400000>; + /* CPU<->DDR bandwidth: 0 MB/s average, 6881 MB/s peak */ + /* CPU<->L3 bandwidth: 0 MB/s average, 19921 MB/s peak */ + bandwidth-MBps = <0 6881>, <0 19921>; + }; + + cpu4_opp19: opp-2323200000 { + opp-hz = /bits/ 64 <2323200000>; + /* CPU<->DDR bandwidth: 0 MB/s average, 6881 MB/s peak */ + /* CPU<->L3 bandwidth: 0 MB/s average, 19921 MB/s peak */ + bandwidth-MBps = <0 6881>, <0 19921>; + }; + + cpu4_opp20: opp-2400000000 { + opp-hz = /bits/ 64 <2400000000>; + /* CPU<->DDR bandwidth: 0 MB/s average, 6881 MB/s peak */ + /* CPU<->L3 bandwidth: 0 MB/s average, 21386 MB/s peak */ + bandwidth-MBps = <0 6881>, <0 21386>; + }; + + cpu4_opp21: opp-2476800000 { + opp-hz = /bits/ 64 <2476800000>; + /* CPU<->DDR bandwidth: 0 MB/s average, 6881 MB/s peak */ + /* CPU<->L3 bandwidth: 0 MB/s average, 21386 MB/s peak */ + bandwidth-MBps = <0 6881>, <0 21386>; + }; + + cpu4_opp22: opp-2553600000 { + opp-hz = /bits/ 64 <2553600000>; + /* CPU<->DDR bandwidth: 0 MB/s average, 6881 MB/s peak */ + /* CPU<->L3 bandwidth: 0 MB/s average, 21386 MB/s peak */ + bandwidth-MBps = <0 6881>, <0 21386>; + }; + + cpu4_opp23: opp-2649600000 { + opp-hz = /bits/ 64 <2649600000>; + /* CPU<->DDR bandwidth: 0 MB/s average, 6881 MB/s peak */ + /* CPU<->L3 bandwidth: 0 MB/s average, 21386 MB/s peak */ + bandwidth-MBps = <0 6881>, <0 21386>; + }; + + cpu4_opp24: opp-2745600000 { + opp-hz = /bits/ 64 <2745600000>; + /* CPU<->DDR bandwidth: 0 MB/s average, 6881 MB/s peak */ + /* CPU<->L3 bandwidth: 0 MB/s average, 22558 MB/s peak */ + bandwidth-MBps = <0 6881>, <0 22558>; + }; + + cpu4_opp25: opp-2803200000 { + opp-hz = /bits/ 64 <2803200000>; + /* CPU<->DDR bandwidth: 0 MB/s average, 6881 MB/s peak */ + /* CPU<->L3 bandwidth: 0 MB/s average, 22558 MB/s peak */ + bandwidth-MBps = <0 6881>, <0 22558>; + }; + }; + pmu { compatible = "arm,armv8-pmuv3"; interrupts = ;