From patchwork Sun Jun 30 15:01:39 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rob Clark X-Patchwork-Id: 11024425 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 90071138B for ; Sun, 30 Jun 2019 15:02:48 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 806CE284FC for ; Sun, 30 Jun 2019 15:02:48 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 7371F2862A; Sun, 30 Jun 2019 15:02:48 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FROM,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id A16EE284FC for ; Sun, 30 Jun 2019 15:02:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726557AbfF3PCq (ORCPT ); Sun, 30 Jun 2019 11:02:46 -0400 Received: from mail-qk1-f193.google.com ([209.85.222.193]:43414 "EHLO mail-qk1-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726500AbfF3PCq (ORCPT ); Sun, 30 Jun 2019 11:02:46 -0400 Received: by mail-qk1-f193.google.com with SMTP id m14so9019448qka.10; Sun, 30 Jun 2019 08:02:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=dc1ZOlpC7lAGBUCKs27bntMMiI+Lv0N6AfkWh/PXjOk=; b=fRHGr0NQRl6QvXdXDos0N3g4OnlcsrnOQydwKjK+U2IPKj0928RwVCgGi3IQaSs4qH zPnvOEb3KyEDJP8ctxwqL1pH2KxsDKBww8OhmSBtRf+rpS26HQHOvzUQjiLg5OAAGRwm XsG82J9zo8YnkJJxcZe1VI4GIepME7KctKg0TBO+EcFT8kGbfyb56T2bEiM1s2hUtJA6 qoD6XoT0J+kRNHp6YEtaXh7s2UVAXQ/bw9CfgufMCSHubvoFK2EuVBjtwZfdPSLiMwTZ aNkMziMnF4hCh4P+zLJcg+c8dKBysA4k/3VaxQrBB1kZMKecjWDZBRh48zPPkqdxlmZn e0vg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=dc1ZOlpC7lAGBUCKs27bntMMiI+Lv0N6AfkWh/PXjOk=; b=tmXw4pwLCcluUAXI/onrQySsT4VxF06JvA7q53NGm8Wg9BGfgJLH+94bAYweYujYc6 Tx3mkK4735S+Mj40iS0YYQUXZ0FcAZNOxesztaLQGUFm2hvGj/olqE8K0qxym6XtnMee gZJQRAT9eYNQ9OCFRsbT3MCODG2yYJiVSkimPE9XPbFijZSeMhHoRqw3sZ0ICXJWtgM0 0/h0AE0T136Q3Q2hGx9ZUIKtrPbYUgFnLS3qS5tZzE/E2Jp8dszn3c7UBnC2qI6XEVzw wwjZqmePOTevpM0HwEwVtnHuFM8vNV8v+1bnaGTAJvsZ3b1kF6YQUtCzydkL4v3LA17f FI/g== X-Gm-Message-State: APjAAAVaa8rb6Yv2Ea5wFsVJKtd2to/6O/k8U31Cr8n/I8Y9g4C9AJkB ZVs/K3MQQVkRowN5oVNZS04= X-Google-Smtp-Source: APXvYqyb4A8fxnJFGSVk29kqD4iLsI5nw1fUR6ng/0RGFELkKo5n83itxm+NC7Wif+yG0dLGI4k+bA== X-Received: by 2002:a37:795:: with SMTP id 143mr17084419qkh.140.1561906964588; Sun, 30 Jun 2019 08:02:44 -0700 (PDT) Received: from localhost ([2601:184:4780:7861:5010:5849:d76d:b714]) by smtp.gmail.com with ESMTPSA id s11sm4077384qte.49.2019.06.30.08.02.43 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Sun, 30 Jun 2019 08:02:44 -0700 (PDT) From: Rob Clark To: dri-devel@lists.freedesktop.org, linux-arm-msm@vger.kernel.org Cc: freedreno@lists.freedesktop.org, aarch64-laptops@lists.linaro.org, linux-clk@vger.kernel.org, linux-pm@vger.kernel.org, Rob Clark , Michael Turquette , Stephen Boyd , Andy Gross , linux-kernel@vger.kernel.org Subject: [PATCH 1/5] clk: inherit clocks enabled by bootloader Date: Sun, 30 Jun 2019 08:01:39 -0700 Message-Id: <20190630150230.7878-2-robdclark@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190630150230.7878-1-robdclark@gmail.com> References: <20190630150230.7878-1-robdclark@gmail.com> MIME-Version: 1.0 Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Rob Clark The goal here is to support inheriting a display setup by bootloader, although there may also be some non-display related use-cases. Rough idea is to add a flag for clks and power domains that might already be enabled when kernel starts, and which should not be disabled at late_initcall if the kernel thinks they are "unused". If bootloader is enabling display, and kernel is using efifb before real display driver is loaded (potentially from kernel module after userspace starts, in a typical distro kernel), we don't want to kill the clocks and power domains that are used by the display before userspace starts. Signed-off-by: Rob Clark Reviewed-by: Jeffrey Hugo --- drivers/clk/clk.c | 48 ++++++++++++++++++++++++++++++++ drivers/clk/qcom/common.c | 25 +++++++++++++++++ drivers/clk/qcom/dispcc-sdm845.c | 22 ++++++++------- drivers/clk/qcom/gcc-sdm845.c | 3 +- include/linux/clk-provider.h | 10 +++++++ 5 files changed, 97 insertions(+), 11 deletions(-) diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c index aa51756fd4d6..14460e87f508 100644 --- a/drivers/clk/clk.c +++ b/drivers/clk/clk.c @@ -66,6 +66,7 @@ struct clk_core { unsigned long flags; bool orphan; bool rpm_enabled; + bool inherit_enabled; /* clock was enabled by bootloader */ unsigned int enable_count; unsigned int prepare_count; unsigned int protect_count; @@ -1166,6 +1167,9 @@ static void clk_unprepare_unused_subtree(struct clk_core *core) hlist_for_each_entry(child, &core->children, child_node) clk_unprepare_unused_subtree(child); + if (core->inherit_enabled) + return; + if (core->prepare_count) return; @@ -1197,6 +1201,9 @@ static void clk_disable_unused_subtree(struct clk_core *core) hlist_for_each_entry(child, &core->children, child_node) clk_disable_unused_subtree(child); + if (core->inherit_enabled) + return; + if (core->flags & CLK_OPS_PARENT_ENABLE) clk_core_prepare_enable(core->parent); @@ -1270,6 +1277,45 @@ static int clk_disable_unused(void) } late_initcall_sync(clk_disable_unused); +/* Ignore CLK_INHERIT_BOOTLOADER clocks enabled by bootloader. This + * gives a debug knob to disable inheriting clks from bootloader, so + * that drivers that used to work, when loaded as a module, thanks + * to disabling "unused" clocks at late_initcall(), can continue to + * work. + * + * The proper solution is to fix the drivers. + */ +static bool clk_ignore_inherited; +static int __init clk_ignore_inherited_setup(char *__unused) +{ + clk_ignore_inherited = true; + return 1; +} +__setup("clk_ignore_inherited", clk_ignore_inherited_setup); + +/* clock and it's parents are already prepared/enabled from bootloader, + * so simply record the fact. + */ +static void __clk_inherit_enabled(struct clk_core *core) +{ + unsigned long parent_rate = 0; + core->inherit_enabled = true; + if (core->parent) { + __clk_inherit_enabled(core->parent); + parent_rate = core->parent->rate; + } + if (core->ops->recalc_rate) + core->rate = core->ops->recalc_rate(core->hw, parent_rate); +} + +void clk_inherit_enabled(struct clk *clk) +{ + if (clk_ignore_inherited) + return; + __clk_inherit_enabled(clk->core); +} +EXPORT_SYMBOL_GPL(clk_inherit_enabled); + static int clk_core_determine_round_nolock(struct clk_core *core, struct clk_rate_request *req) { @@ -3302,6 +3348,8 @@ static int __clk_core_init(struct clk_core *core) * are enabled during init but might not have a parent yet. */ if (parent) { + if (orphan->inherit_enabled) + __clk_inherit_enabled(parent); /* update the clk tree topology */ __clk_set_parent_before(orphan, parent); __clk_set_parent_after(orphan, parent, NULL); diff --git a/drivers/clk/qcom/common.c b/drivers/clk/qcom/common.c index a6b2f86112d8..0d542eeef9aa 100644 --- a/drivers/clk/qcom/common.c +++ b/drivers/clk/qcom/common.c @@ -290,6 +290,31 @@ int qcom_cc_really_probe(struct platform_device *pdev, if (ret) return ret; + /* + * Check which of clocks that we inherit state from bootloader + * are enabled, and fixup enable/prepare state (as well as that + * of it's parents). + */ + for (i = 0; i < num_clks; i++) { + struct clk_hw *hw; + + if (!rclks[i]) + continue; + + hw = &rclks[i]->hw; + + if (!(hw->init->flags & CLK_INHERIT_BOOTLOADER)) + continue; + + if (!clk_is_enabled_regmap(hw)) + continue; + + dev_dbg(dev, "%s is enabled from bootloader!\n", + hw->init->name); + + clk_inherit_enabled(hw->clk); + } + return 0; } EXPORT_SYMBOL_GPL(qcom_cc_really_probe); diff --git a/drivers/clk/qcom/dispcc-sdm845.c b/drivers/clk/qcom/dispcc-sdm845.c index 0cc4909b5dbe..40d7e0ab4340 100644 --- a/drivers/clk/qcom/dispcc-sdm845.c +++ b/drivers/clk/qcom/dispcc-sdm845.c @@ -263,6 +263,7 @@ static struct clk_branch disp_cc_mdss_ahb_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_ahb_clk", + .flags = CLK_INHERIT_BOOTLOADER, .ops = &clk_branch2_ops, }, }, @@ -276,6 +277,7 @@ static struct clk_branch disp_cc_mdss_axi_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_axi_clk", + .flags = CLK_INHERIT_BOOTLOADER, .ops = &clk_branch2_ops, }, }, @@ -294,7 +296,7 @@ static struct clk_branch disp_cc_mdss_byte0_clk = { "disp_cc_mdss_byte0_clk_src", }, .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, + .flags = CLK_SET_RATE_PARENT | CLK_INHERIT_BOOTLOADER, .ops = &clk_branch2_ops, }, }, @@ -330,7 +332,7 @@ static struct clk_branch disp_cc_mdss_byte0_intf_clk = { "disp_cc_mdss_byte0_div_clk_src", }, .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, + .flags = CLK_SET_RATE_PARENT | CLK_INHERIT_BOOTLOADER, .ops = &clk_branch2_ops, }, }, @@ -349,7 +351,7 @@ static struct clk_branch disp_cc_mdss_byte1_clk = { "disp_cc_mdss_byte1_clk_src", }, .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, + .flags = CLK_SET_RATE_PARENT | CLK_INHERIT_BOOTLOADER, .ops = &clk_branch2_ops, }, }, @@ -385,7 +387,7 @@ static struct clk_branch disp_cc_mdss_byte1_intf_clk = { "disp_cc_mdss_byte1_div_clk_src", }, .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, + .flags = CLK_SET_RATE_PARENT | CLK_INHERIT_BOOTLOADER, .ops = &clk_branch2_ops, }, }, @@ -403,7 +405,7 @@ static struct clk_branch disp_cc_mdss_esc0_clk = { "disp_cc_mdss_esc0_clk_src", }, .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, + .flags = CLK_SET_RATE_PARENT | CLK_INHERIT_BOOTLOADER, .ops = &clk_branch2_ops, }, }, @@ -421,7 +423,7 @@ static struct clk_branch disp_cc_mdss_esc1_clk = { "disp_cc_mdss_esc1_clk_src", }, .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, + .flags = CLK_SET_RATE_PARENT | CLK_INHERIT_BOOTLOADER, .ops = &clk_branch2_ops, }, }, @@ -439,7 +441,7 @@ static struct clk_branch disp_cc_mdss_mdp_clk = { "disp_cc_mdss_mdp_clk_src", }, .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, + .flags = CLK_SET_RATE_PARENT | CLK_INHERIT_BOOTLOADER, .ops = &clk_branch2_ops, }, }, @@ -475,7 +477,7 @@ static struct clk_branch disp_cc_mdss_pclk0_clk = { "disp_cc_mdss_pclk0_clk_src", }, .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, + .flags = CLK_SET_RATE_PARENT | CLK_INHERIT_BOOTLOADER, .ops = &clk_branch2_ops, }, }, @@ -494,7 +496,7 @@ static struct clk_branch disp_cc_mdss_pclk1_clk = { "disp_cc_mdss_pclk1_clk_src", }, .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, + .flags = CLK_SET_RATE_PARENT | CLK_INHERIT_BOOTLOADER, .ops = &clk_branch2_ops, }, }, @@ -561,7 +563,7 @@ static struct clk_branch disp_cc_mdss_vsync_clk = { "disp_cc_mdss_vsync_clk_src", }, .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, + .flags = CLK_SET_RATE_PARENT | CLK_INHERIT_BOOTLOADER, .ops = &clk_branch2_ops, }, }, diff --git a/drivers/clk/qcom/gcc-sdm845.c b/drivers/clk/qcom/gcc-sdm845.c index 7131dcf9b060..fe2498be7bc7 100644 --- a/drivers/clk/qcom/gcc-sdm845.c +++ b/drivers/clk/qcom/gcc-sdm845.c @@ -1314,7 +1314,7 @@ static struct clk_branch gcc_disp_ahb_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_disp_ahb_clk", - .flags = CLK_IS_CRITICAL, + .flags = CLK_IS_CRITICAL | CLK_INHERIT_BOOTLOADER, .ops = &clk_branch2_ops, }, }, @@ -1328,6 +1328,7 @@ static struct clk_branch gcc_disp_axi_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_disp_axi_clk", + .flags = CLK_INHERIT_BOOTLOADER, .ops = &clk_branch2_ops, }, }, diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h index bb6118f79784..41b951c8b92b 100644 --- a/include/linux/clk-provider.h +++ b/include/linux/clk-provider.h @@ -34,6 +34,7 @@ #define CLK_OPS_PARENT_ENABLE BIT(12) /* duty cycle call may be forwarded to the parent clock */ #define CLK_DUTY_CYCLE_PARENT BIT(13) +#define CLK_INHERIT_BOOTLOADER BIT(14) /* clk may be enabled from bootloader */ struct clk; struct clk_hw; @@ -349,6 +350,15 @@ void clk_hw_unregister_fixed_rate(struct clk_hw *hw); void of_fixed_clk_setup(struct device_node *np); +/** + * clk_inherit_enabled - update the enable/prepare count of a clock and it's + * parents for clock enabled by bootloader. + * + * Intended to be used by clock drivers to inform the clk core of a clock + * that is already running. + */ +void clk_inherit_enabled(struct clk *clk); + /** * struct clk_gate - gating clock * From patchwork Sun Jun 30 15:01:40 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rob Clark X-Patchwork-Id: 11024439 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 81B9C138B for ; Sun, 30 Jun 2019 15:02:57 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 76AF6284FC for ; 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Sun, 30 Jun 2019 08:02:50 -0700 (PDT) Received: from localhost ([2601:184:4780:7861:5010:5849:d76d:b714]) by smtp.gmail.com with ESMTPSA id q36sm4115062qtc.12.2019.06.30.08.02.50 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Sun, 30 Jun 2019 08:02:50 -0700 (PDT) From: Rob Clark To: dri-devel@lists.freedesktop.org, linux-arm-msm@vger.kernel.org Cc: freedreno@lists.freedesktop.org, aarch64-laptops@lists.linaro.org, linux-clk@vger.kernel.org, linux-pm@vger.kernel.org, Rob Clark , "Rafael J. Wysocki" , Kevin Hilman , Ulf Hansson , Len Brown , Pavel Machek , Greg Kroah-Hartman , Andy Gross , Michael Turquette , Stephen Boyd , linux-kernel@vger.kernel.org Subject: [PATCH 2/5] genpd/gdsc: inherit display powerdomain from bootloader Date: Sun, 30 Jun 2019 08:01:40 -0700 Message-Id: <20190630150230.7878-3-robdclark@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190630150230.7878-1-robdclark@gmail.com> References: <20190630150230.7878-1-robdclark@gmail.com> MIME-Version: 1.0 Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Rob Clark Mark power domains that may be enabled by bootloader, and which should not be disabled until a driver takes them over. This keeps efifb alive until the real driver can be probed. In a distro kernel, the driver will most likely built as a module, and not probed until we get to userspace (after late_initcall) Signed-off-by: Rob Clark Reviewed-by: Jeffrey Hugo --- drivers/base/power/domain.c | 10 ++++++++++ drivers/clk/qcom/dispcc-sdm845.c | 2 +- drivers/clk/qcom/gdsc.c | 5 +++++ drivers/clk/qcom/gdsc.h | 1 + include/linux/pm_domain.h | 4 ++++ 5 files changed, 21 insertions(+), 1 deletion(-) diff --git a/drivers/base/power/domain.c b/drivers/base/power/domain.c index 33c30c1e6a30..513a8655fbd7 100644 --- a/drivers/base/power/domain.c +++ b/drivers/base/power/domain.c @@ -537,6 +537,16 @@ static int genpd_power_off(struct generic_pm_domain *genpd, bool one_dev_on, not_suspended++; } + /* + * If the power domain is enabled by the bootloader (for example + * display enabled by bootloader), but no devices attached yet + * (perhaps because driver built as kernel module), then do not + * suspend. + */ + if ((genpd->flags & GENPD_FLAG_INHERIT_BL) && + list_empty(&genpd->dev_list)) + not_suspended++; + if (not_suspended > 1 || (not_suspended == 1 && !one_dev_on)) return -EBUSY; diff --git a/drivers/clk/qcom/dispcc-sdm845.c b/drivers/clk/qcom/dispcc-sdm845.c index 40d7e0ab4340..1d9365ac2315 100644 --- a/drivers/clk/qcom/dispcc-sdm845.c +++ b/drivers/clk/qcom/dispcc-sdm845.c @@ -575,7 +575,7 @@ static struct gdsc mdss_gdsc = { .name = "mdss_gdsc", }, .pwrsts = PWRSTS_OFF_ON, - .flags = HW_CTRL | POLL_CFG_GDSCR, + .flags = HW_CTRL | POLL_CFG_GDSCR | INHERIT_BL, }; static struct clk_regmap *disp_cc_sdm845_clocks[] = { diff --git a/drivers/clk/qcom/gdsc.c b/drivers/clk/qcom/gdsc.c index a250f59708d8..4639fbeb9a7f 100644 --- a/drivers/clk/qcom/gdsc.c +++ b/drivers/clk/qcom/gdsc.c @@ -331,6 +331,11 @@ static int gdsc_init(struct gdsc *sc) if ((sc->flags & VOTABLE) && on) gdsc_enable(&sc->pd); + if ((sc->flags & INHERIT_BL) && on) { + pr_debug("gdsc: %s is enabled from bootloader!\n", sc->pd.name); + sc->pd.flags |= GENPD_FLAG_INHERIT_BL; + } + /* If ALWAYS_ON GDSCs are not ON, turn them ON */ if (sc->flags & ALWAYS_ON) { if (!on) diff --git a/drivers/clk/qcom/gdsc.h b/drivers/clk/qcom/gdsc.h index 64cdc8cf0d4d..c6fe56247399 100644 --- a/drivers/clk/qcom/gdsc.h +++ b/drivers/clk/qcom/gdsc.h @@ -49,6 +49,7 @@ struct gdsc { #define AON_RESET BIT(4) #define POLL_CFG_GDSCR BIT(5) #define ALWAYS_ON BIT(6) +#define INHERIT_BL BIT(7) struct reset_controller_dev *rcdev; unsigned int *resets; unsigned int reset_count; diff --git a/include/linux/pm_domain.h b/include/linux/pm_domain.h index 91d9bf497071..5e421afcf6f3 100644 --- a/include/linux/pm_domain.h +++ b/include/linux/pm_domain.h @@ -55,6 +55,9 @@ * * GENPD_FLAG_RPM_ALWAYS_ON: Instructs genpd to always keep the PM domain * powered on except for system suspend. + * + * GENPD_FLAG_INHERIT_BL: The bootloader has already enabled this power + * domain. */ #define GENPD_FLAG_PM_CLK (1U << 0) #define GENPD_FLAG_IRQ_SAFE (1U << 1) @@ -62,6 +65,7 @@ #define GENPD_FLAG_ACTIVE_WAKEUP (1U << 3) #define GENPD_FLAG_CPU_DOMAIN (1U << 4) #define GENPD_FLAG_RPM_ALWAYS_ON (1U << 5) +#define GENPD_FLAG_INHERIT_BL (1U << 6) enum gpd_status { GPD_STATE_ACTIVE = 0, /* PM domain is active */ From patchwork Sun Jun 30 15:01:41 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rob Clark X-Patchwork-Id: 11024447 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 996C5174A for ; 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Sun, 30 Jun 2019 08:03:02 -0700 (PDT) Received: from localhost ([2601:184:4780:7861:5010:5849:d76d:b714]) by smtp.gmail.com with ESMTPSA id w62sm3820792qkd.30.2019.06.30.08.03.01 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Sun, 30 Jun 2019 08:03:01 -0700 (PDT) From: Rob Clark To: dri-devel@lists.freedesktop.org, linux-arm-msm@vger.kernel.org Cc: freedreno@lists.freedesktop.org, aarch64-laptops@lists.linaro.org, linux-clk@vger.kernel.org, linux-pm@vger.kernel.org, Rob Clark , Rob Clark , Sean Paul , David Airlie , Daniel Vetter , Chandan Uddaraju , Archit Taneja , Sibi Sankar , Laurent Pinchart , Thomas Gleixner , Greg Kroah-Hartman , Allison Randal , Jordan Crouse , Abhinav Kumar , linux-kernel@vger.kernel.org Subject: [PATCH 3/5] drm/msm/dsi: split clk rate setting and enable Date: Sun, 30 Jun 2019 08:01:41 -0700 Message-Id: <20190630150230.7878-4-robdclark@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190630150230.7878-1-robdclark@gmail.com> References: <20190630150230.7878-1-robdclark@gmail.com> MIME-Version: 1.0 Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Rob Clark Prep work for the following patch. Signed-off-by: Rob Clark Reviewed-by: Jeffrey Hugo --- drivers/gpu/drm/msm/dsi/dsi.h | 2 ++ drivers/gpu/drm/msm/dsi/dsi_cfg.c | 3 +++ drivers/gpu/drm/msm/dsi/dsi_cfg.h | 1 + drivers/gpu/drm/msm/dsi/dsi_host.c | 38 ++++++++++++++++++++++-------- 4 files changed, 34 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/msm/dsi/dsi.h b/drivers/gpu/drm/msm/dsi/dsi.h index 4dd2a9a79257..c4e3c4cf96c5 100644 --- a/drivers/gpu/drm/msm/dsi/dsi.h +++ b/drivers/gpu/drm/msm/dsi/dsi.h @@ -178,6 +178,8 @@ int msm_dsi_host_modeset_init(struct mipi_dsi_host *host, int msm_dsi_host_init(struct msm_dsi *msm_dsi); int msm_dsi_runtime_suspend(struct device *dev); int msm_dsi_runtime_resume(struct device *dev); +int dsi_link_clk_set_rate_6g(struct msm_dsi_host *msm_host); +int dsi_link_clk_set_rate_v2(struct msm_dsi_host *msm_host); int dsi_link_clk_enable_6g(struct msm_dsi_host *msm_host); int dsi_link_clk_enable_v2(struct msm_dsi_host *msm_host); void dsi_link_clk_disable_6g(struct msm_dsi_host *msm_host); diff --git a/drivers/gpu/drm/msm/dsi/dsi_cfg.c b/drivers/gpu/drm/msm/dsi/dsi_cfg.c index 9ddf16380289..35e272c27780 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_cfg.c +++ b/drivers/gpu/drm/msm/dsi/dsi_cfg.c @@ -129,6 +129,7 @@ static const struct msm_dsi_config sdm845_dsi_cfg = { }; const static struct msm_dsi_host_cfg_ops msm_dsi_v2_host_ops = { + .link_clk_set_rate = dsi_link_clk_set_rate_v2, .link_clk_enable = dsi_link_clk_enable_v2, .link_clk_disable = dsi_link_clk_disable_v2, .clk_init_ver = dsi_clk_init_v2, @@ -140,6 +141,7 @@ const static struct msm_dsi_host_cfg_ops msm_dsi_v2_host_ops = { }; const static struct msm_dsi_host_cfg_ops msm_dsi_6g_host_ops = { + .link_clk_set_rate = dsi_link_clk_set_rate_6g, .link_clk_enable = dsi_link_clk_enable_6g, .link_clk_disable = dsi_link_clk_disable_6g, .clk_init_ver = NULL, @@ -151,6 +153,7 @@ const static struct msm_dsi_host_cfg_ops msm_dsi_6g_host_ops = { }; const static struct msm_dsi_host_cfg_ops msm_dsi_6g_v2_host_ops = { + .link_clk_set_rate = dsi_link_clk_set_rate_6g, .link_clk_enable = dsi_link_clk_enable_6g, .link_clk_disable = dsi_link_clk_disable_6g, .clk_init_ver = dsi_clk_init_6g_v2, diff --git a/drivers/gpu/drm/msm/dsi/dsi_cfg.h b/drivers/gpu/drm/msm/dsi/dsi_cfg.h index a6a3d2bad263..7c1bc174537d 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_cfg.h +++ b/drivers/gpu/drm/msm/dsi/dsi_cfg.h @@ -33,6 +33,7 @@ struct msm_dsi_config { }; struct msm_dsi_host_cfg_ops { + int (*link_clk_set_rate)(struct msm_dsi_host *msm_host); int (*link_clk_enable)(struct msm_dsi_host *msm_host); void (*link_clk_disable)(struct msm_dsi_host *msm_host); int (*clk_init_ver)(struct msm_dsi_host *msm_host); diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c index d03212ef4853..87119d0afb91 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_host.c +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c @@ -503,7 +503,7 @@ int msm_dsi_runtime_resume(struct device *dev) return dsi_bus_clk_enable(msm_host); } -int dsi_link_clk_enable_6g(struct msm_dsi_host *msm_host) +int dsi_link_clk_set_rate_6g(struct msm_dsi_host *msm_host) { int ret; @@ -513,13 +513,13 @@ int dsi_link_clk_enable_6g(struct msm_dsi_host *msm_host) ret = clk_set_rate(msm_host->byte_clk, msm_host->byte_clk_rate); if (ret) { pr_err("%s: Failed to set rate byte clk, %d\n", __func__, ret); - goto error; + return ret; } ret = clk_set_rate(msm_host->pixel_clk, msm_host->pixel_clk_rate); if (ret) { pr_err("%s: Failed to set rate pixel clk, %d\n", __func__, ret); - goto error; + return ret; } if (msm_host->byte_intf_clk) { @@ -528,10 +528,18 @@ int dsi_link_clk_enable_6g(struct msm_dsi_host *msm_host) if (ret) { pr_err("%s: Failed to set rate byte intf clk, %d\n", __func__, ret); - goto error; + return ret; } } + return 0; +} + + +int dsi_link_clk_enable_6g(struct msm_dsi_host *msm_host) +{ + int ret; + ret = clk_prepare_enable(msm_host->esc_clk); if (ret) { pr_err("%s: Failed to enable dsi esc clk\n", __func__); @@ -571,7 +579,7 @@ int dsi_link_clk_enable_6g(struct msm_dsi_host *msm_host) return ret; } -int dsi_link_clk_enable_v2(struct msm_dsi_host *msm_host) +int dsi_link_clk_set_rate_v2(struct msm_dsi_host *msm_host) { int ret; @@ -582,27 +590,34 @@ int dsi_link_clk_enable_v2(struct msm_dsi_host *msm_host) ret = clk_set_rate(msm_host->byte_clk, msm_host->byte_clk_rate); if (ret) { pr_err("%s: Failed to set rate byte clk, %d\n", __func__, ret); - goto error; + return ret; } ret = clk_set_rate(msm_host->esc_clk, msm_host->esc_clk_rate); if (ret) { pr_err("%s: Failed to set rate esc clk, %d\n", __func__, ret); - goto error; + return ret; } ret = clk_set_rate(msm_host->src_clk, msm_host->src_clk_rate); if (ret) { pr_err("%s: Failed to set rate src clk, %d\n", __func__, ret); - goto error; + return ret; } ret = clk_set_rate(msm_host->pixel_clk, msm_host->pixel_clk_rate); if (ret) { pr_err("%s: Failed to set rate pixel clk, %d\n", __func__, ret); - goto error; + return ret; } + return 0; +} + +int dsi_link_clk_enable_v2(struct msm_dsi_host *msm_host) +{ + int ret; + ret = clk_prepare_enable(msm_host->byte_clk); if (ret) { pr_err("%s: Failed to enable dsi byte clk\n", __func__); @@ -1997,6 +2012,7 @@ int msm_dsi_host_xfer_prepare(struct mipi_dsi_host *host, * mdp clock need to be enabled to receive dsi interrupt */ pm_runtime_get_sync(&msm_host->pdev->dev); + cfg_hnd->ops->link_clk_set_rate(msm_host); cfg_hnd->ops->link_clk_enable(msm_host); /* TODO: vote for bus bandwidth */ @@ -2345,7 +2361,9 @@ int msm_dsi_host_power_on(struct mipi_dsi_host *host, } pm_runtime_get_sync(&msm_host->pdev->dev); - ret = cfg_hnd->ops->link_clk_enable(msm_host); + ret = cfg_hnd->ops->link_clk_set_rate(msm_host); + if (!ret) + ret = cfg_hnd->ops->link_clk_enable(msm_host); if (ret) { pr_err("%s: failed to enable link clocks. ret=%d\n", __func__, ret); From patchwork Sun Jun 30 15:01:42 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rob Clark X-Patchwork-Id: 11024455 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 83C68138B for ; Sun, 30 Jun 2019 15:03:17 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 79343284FC for ; Sun, 30 Jun 2019 15:03:17 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 6DC32285A9; Sun, 30 Jun 2019 15:03:17 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FROM,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 0B6CF284FC for ; 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Sun, 30 Jun 2019 08:03:10 -0700 (PDT) From: Rob Clark To: dri-devel@lists.freedesktop.org, linux-arm-msm@vger.kernel.org Cc: freedreno@lists.freedesktop.org, aarch64-laptops@lists.linaro.org, linux-clk@vger.kernel.org, linux-pm@vger.kernel.org, Rob Clark , Rob Clark , Sean Paul , David Airlie , Daniel Vetter , Jordan Crouse , Abhinav Kumar , Sibi Sankar , Mamta Shukla , Chandan Uddaraju , Archit Taneja , Rajesh Yadav , linux-kernel@vger.kernel.org Subject: [PATCH 4/5] drm/msm/dsi: get the clocks into OFF state at init Date: Sun, 30 Jun 2019 08:01:42 -0700 Message-Id: <20190630150230.7878-5-robdclark@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190630150230.7878-1-robdclark@gmail.com> References: <20190630150230.7878-1-robdclark@gmail.com> MIME-Version: 1.0 Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Rob Clark Do an extra enable/disable cycle at init, to get the clks into disabled state in case bootloader left them enabled. In case they were already enabled, the clk_prepare_enable() has no real effect, other than getting the enable_count/prepare_count into the right state so that we can disable clocks in the correct order. This way we avoid having stuck clocks when we later want to do a modeset and set the clock rates. Signed-off-by: Rob Clark --- drivers/gpu/drm/msm/dsi/dsi_host.c | 18 +++++++++++++++--- drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c | 1 + 2 files changed, 16 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c index 87119d0afb91..d6e81f330db4 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_host.c +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c @@ -215,8 +215,6 @@ static const struct msm_dsi_cfg_handler *dsi_get_config( goto put_gdsc; } - pm_runtime_get_sync(dev); - ret = regulator_enable(gdsc_reg); if (ret) { pr_err("%s: unable to enable gdsc\n", __func__); @@ -243,7 +241,6 @@ static const struct msm_dsi_cfg_handler *dsi_get_config( clk_disable_unprepare(ahb_clk); disable_gdsc: regulator_disable(gdsc_reg); - pm_runtime_put_sync(dev); put_gdsc: regulator_put(gdsc_reg); exit: @@ -390,6 +387,8 @@ static int dsi_clk_init(struct msm_dsi_host *msm_host) __func__, cfg->bus_clk_names[i], ret); goto exit; } + + clk_prepare_enable(msm_host->bus_clks[i]); } /* get link and source clocks */ @@ -436,6 +435,16 @@ static int dsi_clk_init(struct msm_dsi_host *msm_host) if (cfg_hnd->ops->clk_init_ver) ret = cfg_hnd->ops->clk_init_ver(msm_host); + + /* + * Do an extra enable/disable sequence initially to ensure the + * clocks are actually off, if left enabled by bootloader.. + */ + ret = cfg_hnd->ops->link_clk_enable(msm_host); + if (!ret) + cfg_hnd->ops->link_clk_disable(msm_host); + ret = 0; + exit: return ret; } @@ -1855,6 +1864,7 @@ int msm_dsi_host_init(struct msm_dsi *msm_dsi) } pm_runtime_enable(&pdev->dev); + pm_runtime_get_sync(&pdev->dev); msm_host->cfg_hnd = dsi_get_config(msm_host); if (!msm_host->cfg_hnd) { @@ -1885,6 +1895,8 @@ int msm_dsi_host_init(struct msm_dsi *msm_dsi) goto fail; } + pm_runtime_put_sync(&pdev->dev); + msm_host->rx_buf = devm_kzalloc(&pdev->dev, SZ_4K, GFP_KERNEL); if (!msm_host->rx_buf) { ret = -ENOMEM; diff --git a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c index aabab6311043..d0172d8db882 100644 --- a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c +++ b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c @@ -354,6 +354,7 @@ static int dsi_pll_10nm_lock_status(struct dsi_pll_10nm *pll) if (rc) pr_err("DSI PLL(%d) lock failed, status=0x%08x\n", pll->id, status); +rc = 0; // HACK, this will fail if PLL already running.. return rc; } From patchwork Sun Jun 30 15:01:43 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rob Clark X-Patchwork-Id: 11024461 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 2E313138B for ; Sun, 30 Jun 2019 15:03:21 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 22ACD2851B for ; Sun, 30 Jun 2019 15:03:21 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 16EAB28553; Sun, 30 Jun 2019 15:03:21 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FROM,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id BD0D0284FC for ; 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Sun, 30 Jun 2019 08:03:14 -0700 (PDT) From: Rob Clark To: dri-devel@lists.freedesktop.org, linux-arm-msm@vger.kernel.org Cc: freedreno@lists.freedesktop.org, aarch64-laptops@lists.linaro.org, linux-clk@vger.kernel.org, linux-pm@vger.kernel.org, Rob Clark , Andrzej Hajda , Laurent Pinchart , David Airlie , Daniel Vetter , linux-kernel@vger.kernel.org Subject: [PATCH 5/5] drm/bridge: ti-sn65dsi86: support booloader enabled display Date: Sun, 30 Jun 2019 08:01:43 -0700 Message-Id: <20190630150230.7878-6-robdclark@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190630150230.7878-1-robdclark@gmail.com> References: <20190630150230.7878-1-robdclark@gmail.com> MIME-Version: 1.0 Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Rob Clark Request the enable gpio ASIS to avoid disabling bridge during probe, if already enabled. And if already enabled, defer enabling runpm until attach to avoid cutting off the power to the bridge. Once we get to attach, we know panel and drm driver are probed successfully, so at this point it i s safe to enable runpm and reset the bridge. If we do it earlier, we kill efifb (in the case that panel or drm driver do not probe successfully, giving the user no way to see what is going on. Signed-off-by: Rob Clark --- drivers/gpu/drm/bridge/ti-sn65dsi86.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/bridge/ti-sn65dsi86.c b/drivers/gpu/drm/bridge/ti-sn65dsi86.c index 7a046bcdd81b..8bdc33576992 100644 --- a/drivers/gpu/drm/bridge/ti-sn65dsi86.c +++ b/drivers/gpu/drm/bridge/ti-sn65dsi86.c @@ -257,6 +257,12 @@ static int ti_sn_bridge_attach(struct drm_bridge *bridge) .node = NULL, }; + if (gpiod_get_value(pdata->enable_gpio)) { + pm_runtime_enable(pdata->dev); + ti_sn_bridge_resume(pdata->dev); + ti_sn_bridge_suspend(pdata->dev); + } + ret = drm_connector_init(bridge->dev, &pdata->connector, &ti_sn_bridge_connector_funcs, DRM_MODE_CONNECTOR_eDP); @@ -813,7 +819,7 @@ static int ti_sn_bridge_probe(struct i2c_client *client, dev_set_drvdata(&client->dev, pdata); pdata->enable_gpio = devm_gpiod_get(pdata->dev, "enable", - GPIOD_OUT_LOW); + GPIOD_ASIS); if (IS_ERR(pdata->enable_gpio)) { DRM_ERROR("failed to get enable gpio from DT\n"); ret = PTR_ERR(pdata->enable_gpio); @@ -843,7 +849,9 @@ static int ti_sn_bridge_probe(struct i2c_client *client, if (ret) return ret; - pm_runtime_enable(pdata->dev); + if (!gpiod_get_value(pdata->enable_gpio)) { + pm_runtime_enable(pdata->dev); + } i2c_set_clientdata(client, pdata);