From patchwork Mon Jul 1 10:46:55 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neil Armstrong X-Patchwork-Id: 11025507 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 5B5FE112C for ; Mon, 1 Jul 2019 10:47:59 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 4DE6C1FFC8 for ; Mon, 1 Jul 2019 10:47:59 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 4258D2864F; Mon, 1 Jul 2019 10:47:59 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id A6BA61FFC8 for ; Mon, 1 Jul 2019 10:47:58 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=sGaT02RkTY93P/3Q365Xo6xPZlq4T+cVHiGjCez1Da0=; b=Ph+NIq+kFrtyMQ W+I5n7H2wxCHNElTJ4xwtZkVaZPbjVk18GWZOr9eQXrfZN0OXMghyfbXnE6kW/NBdpj0ErvdjesH1 GrGK/X5lhQTr3ltLZ2r7lkNaohiXVL6bMG3C3f7uXh1/BB9ATssiQEywIbEkFYyB3fxX0atzPX77f T55gD1fuLXyxAaC8EhI5QvhV0mKAAhLkUnS4vgDxUKETQ3RmSNEnmfMQ7MZcxQTqRLZoQwCZjwkO4 CfNqr1l+kJVChthRQcDBfZfwAQ6RFmXrM0KPD7KWSqaszQ9svjboDlJnpxJutDc6KGsKqDX1eTOvd XpXtr1NLQJj7sCUkqklg==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92 #3 (Red Hat Linux)) id 1hhtqg-0006uI-UX; Mon, 01 Jul 2019 10:47:51 +0000 Received: from mail-wm1-x342.google.com ([2a00:1450:4864:20::342]) by bombadil.infradead.org with esmtps (Exim 4.92 #3 (Red Hat Linux)) id 1hhtqI-0006YN-L6 for linux-arm-kernel@lists.infradead.org; Mon, 01 Jul 2019 10:47:28 +0000 Received: by mail-wm1-x342.google.com with SMTP id u8so15369105wmm.1 for ; Mon, 01 Jul 2019 03:47:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=wfgjAQ3M5HY2NtkjVQDzRJpLev5yRfzCJhptr2owUzY=; b=zPBzDYcjDqHiHXy9jMFQwxCKaAAzbtCKZS+bwK61KcgKKpDtVjmshT4h915qhXcnxN GvwfCIK4DBZEZ4s2JPKlmLDWsh/l7icG41GIM20ZorILqhFXmjfYjLllTB8xnsfodCps Zt+QSHs1sZfGVGgZZgtsDLCQcMfhzB1vBZArWhJ6b3MIfCOM38RuEI6qunfj61p08z17 x0U0vbKHjuPy4nXo3/46YLS53egemjbBMuCI4TRDKO/+a6HKHDCsWM05WohCj+QuxeRj 3bDhWP5je88qRmMmnqCYb1z3f8ld5CRz3z04Rx50kwxO3V4eR8c42qaac+j76eVocv7Z QwQg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=wfgjAQ3M5HY2NtkjVQDzRJpLev5yRfzCJhptr2owUzY=; b=NJggKXXwYi/wObs3D1chZbuUxdRgD1b7tSM6x/4ne6BBFf5G0Syg1P8I1vnrkF+HQB eH9zyfYJZxv5Aye8aVk3FUEosNAru4cfsYloWXh23s3DnbLKDUtxeLa69j5mF+hR/M8O 4pX6wRGMWFnrTZ11Ep/1EJnHkVqY6gkIABVTicUkLBJl5Ngnt1uItzLswCqRy5+NyOkM q2OdQwcX2SMzM7CXDegRWqjwuqNpb5ZYV9eQB7Cqv9Ajt3YVQbHOM/VLWG9FXYDjxD+j O3fDSui0nft3Kig1iFy4QKCvWXLWbGnFl/SNk6whvxGHv+bzqvX3HYK2xP2yC2hkjFP2 xNMg== X-Gm-Message-State: APjAAAVlIaQxIeaGRgejpMIVvKaQWaSdEdFYbPlpjeLs0Lq7lHf1vjCu 5hV7KYg14Y+8NWwWFOtd+52J/A== X-Google-Smtp-Source: APXvYqzrQnQF/+v+bIQvryP/j5lpMQ4UpR0oBp9qdOxkvujlAZoajK57bDQABJ8zj0Dn/XghUa8Djw== X-Received: by 2002:a05:600c:1150:: with SMTP id z16mr16105586wmz.168.1561978044919; Mon, 01 Jul 2019 03:47:24 -0700 (PDT) Received: from localhost.localdomain (176-150-251-154.abo.bbox.fr. [176.150.251.154]) by smtp.gmail.com with ESMTPSA id d24sm11658802wra.43.2019.07.01.03.47.24 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 01 Jul 2019 03:47:24 -0700 (PDT) From: Neil Armstrong To: jbrunet@baylibre.com, khilman@baylibre.com Subject: [RFC 01/11] soc: amlogic: meson-gx-socinfo: Add SM1 and S905X3 IDs Date: Mon, 1 Jul 2019 12:46:55 +0200 Message-Id: <20190701104705.18271-2-narmstrong@baylibre.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190701104705.18271-1-narmstrong@baylibre.com> References: <20190701104705.18271-1-narmstrong@baylibre.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190701_034726_689517_42C6B83F X-CRM114-Status: GOOD ( 10.33 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Neil Armstrong Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Add the SoC IDs for the S905X3 Amlogic SM1 SoC. Signed-off-by: Neil Armstrong Reviewed-by: Jerome Brunet Reviewed-by: Martin Blumenstingl --- drivers/soc/amlogic/meson-gx-socinfo.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/soc/amlogic/meson-gx-socinfo.c b/drivers/soc/amlogic/meson-gx-socinfo.c index bca34954518e..eb81d391b620 100644 --- a/drivers/soc/amlogic/meson-gx-socinfo.c +++ b/drivers/soc/amlogic/meson-gx-socinfo.c @@ -39,6 +39,7 @@ static const struct meson_gx_soc_id { { "TXHD", 0x27 }, { "G12A", 0x28 }, { "G12B", 0x29 }, + { "SM1", 0x2b }, }; static const struct meson_gx_package_id { @@ -65,6 +66,7 @@ static const struct meson_gx_package_id { { "S905D2", 0x28, 0x10, 0xf0 }, { "S905X2", 0x28, 0x40, 0xf0 }, { "S922X", 0x29, 0x40, 0xf0 }, + { "S905X3", 0x2b, 0x50, 0xf0 }, }; static inline unsigned int socinfo_to_major(u32 socinfo) From patchwork Mon Jul 1 10:46:56 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neil Armstrong X-Patchwork-Id: 11025515 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id ECF15138D for ; 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[176.150.251.154]) by smtp.gmail.com with ESMTPSA id d24sm11658802wra.43.2019.07.01.03.47.24 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 01 Jul 2019 03:47:25 -0700 (PDT) From: Neil Armstrong To: jbrunet@baylibre.com, khilman@baylibre.com, devicetree@vger.kernel.org Subject: [RFC 02/11] dt-bindings: power: amlogic, meson-gx-pwrc: Add SM1 bindings Date: Mon, 1 Jul 2019 12:46:56 +0200 Message-Id: <20190701104705.18271-3-narmstrong@baylibre.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190701104705.18271-1-narmstrong@baylibre.com> References: <20190701104705.18271-1-narmstrong@baylibre.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190701_034727_765113_82038DA1 X-CRM114-Status: GOOD ( 13.72 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Neil Armstrong Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Add bindings for the Amlogic SM1 Power control: - the VPU power control compatible - the general-purpose power controller, controlling the USB, PCIe, NNA and GE2D power domains. Signed-off-by: Neil Armstrong --- .../bindings/power/amlogic,meson-gx-pwrc.txt | 35 +++++++++++++++++++ include/dt-bindings/power/meson-sm1-power.h | 15 ++++++++ 2 files changed, 50 insertions(+) create mode 100644 include/dt-bindings/power/meson-sm1-power.h diff --git a/Documentation/devicetree/bindings/power/amlogic,meson-gx-pwrc.txt b/Documentation/devicetree/bindings/power/amlogic,meson-gx-pwrc.txt index 0fdc3dd1125e..f0a1e20555bf 100644 --- a/Documentation/devicetree/bindings/power/amlogic,meson-gx-pwrc.txt +++ b/Documentation/devicetree/bindings/power/amlogic,meson-gx-pwrc.txt @@ -19,6 +19,7 @@ Required properties: - compatible: should be one of the following : - "amlogic,meson-gx-pwrc-vpu" for the Meson GX SoCs - "amlogic,meson-g12a-pwrc-vpu" for the Meson G12A SoCs + - "amlogic,meson-sm1-pwrc-vpu" for the Meson SM1 SoCs - #power-domain-cells: should be 0 - amlogic,hhi-sysctrl: phandle to the HHI sysctrl node - resets: phandles to the reset lines needed for this power demain sequence @@ -60,4 +61,38 @@ ao_sysctrl: sys-ctrl@0 { }; }; +General Purpose Power Controller +-------------------------------- +The Amlogic SM1 SoCs embeds a General Purpose Power Controller used +to control the power domain for, at least, the USB PHYs and PCIe +peripherals. + + +Device Tree Bindings: +--------------------- + +Required properties: +- compatible: should be one of the following : + - "amlogic,meson-sm1-pwrc" for the Meson SM1 SoCs +- #power-domain-cells: should be 0 +- amlogic,hhi-sysctrl: phandle to the HHI sysctrl node + +Parent node should have the following properties : +- compatible: "amlogic,meson-gx-ao-sysctrl", "syscon", "simple-mfd" +- reg: base address and size of the AO system control register space. + + +Example: +------- + +ao_sysctrl: sys-ctrl@0 { + compatible = "amlogic,meson-gx-ao-sysctrl", "syscon", "simple-mfd"; + reg = <0x0 0x0 0x0 0x100>; + + pwrc: power-controller { + compatible = "amlogic,meson-sm1-pwrc"; + #power-domain-cells = <1>; + amlogic,hhi-sysctrl = <&hhi>; + }; +}; diff --git a/include/dt-bindings/power/meson-sm1-power.h b/include/dt-bindings/power/meson-sm1-power.h new file mode 100644 index 000000000000..30e17e4a478e --- /dev/null +++ b/include/dt-bindings/power/meson-sm1-power.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */ +/* + * Copyright (c) 2019 BayLibre, SAS + * Author: Neil Armstrong + */ + +#ifndef _DT_BINDINGS_MESON_SM1_POWER_H +#define _DT_BINDINGS_MESON_SM1_POWER_H + +#define PWRC_SM1_NNA_ID 0 +#define PWRC_SM1_USB_ID 1 +#define PWRC_SM1_PCIE_ID 2 +#define PWRC_SM1_GE2D_ID 3 + +#endif From patchwork Mon Jul 1 10:46:57 2019 Content-Type: text/plain; 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[176.150.251.154]) by smtp.gmail.com with ESMTPSA id d24sm11658802wra.43.2019.07.01.03.47.25 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 01 Jul 2019 03:47:26 -0700 (PDT) From: Neil Armstrong To: jbrunet@baylibre.com, khilman@baylibre.com Subject: [RFC 03/11] soc: amlogic: gx-pwrc-vpu: add SM1 support Date: Mon, 1 Jul 2019 12:46:57 +0200 Message-Id: <20190701104705.18271-4-narmstrong@baylibre.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190701104705.18271-1-narmstrong@baylibre.com> References: <20190701104705.18271-1-narmstrong@baylibre.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190701_034728_784936_8C09635A X-CRM114-Status: GOOD ( 15.41 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Neil Armstrong Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Add support for the Amlogic SM1 SoCs VPU Power Domain control, it uses a different register for Isolation and a supplementaty register for the domain memories power control. Signed-off-by: Neil Armstrong --- drivers/soc/amlogic/meson-gx-pwrc-vpu.c | 120 ++++++++++++++++++++++++ 1 file changed, 120 insertions(+) diff --git a/drivers/soc/amlogic/meson-gx-pwrc-vpu.c b/drivers/soc/amlogic/meson-gx-pwrc-vpu.c index 511b6856225d..fabb2868d09b 100644 --- a/drivers/soc/amlogic/meson-gx-pwrc-vpu.c +++ b/drivers/soc/amlogic/meson-gx-pwrc-vpu.c @@ -18,6 +18,7 @@ /* AO Offsets */ #define AO_RTI_GEN_PWR_SLEEP0 (0x3a << 2) +#define AO_RTI_GEN_PWR_ISO0 (0x3b << 2) #define GEN_PWR_VPU_HDMI BIT(8) #define GEN_PWR_VPU_HDMI_ISO BIT(9) @@ -28,6 +29,8 @@ #define HHI_VPU_MEM_PD_REG0 (0x41 << 2) #define HHI_VPU_MEM_PD_REG1 (0x42 << 2) #define HHI_VPU_MEM_PD_REG2 (0x4d << 2) +#define HHI_VPU_MEM_PD_REG3 (0x43 << 2) +#define HHI_VPU_MEM_PD_REG4 (0x44 << 2) struct meson_gx_pwrc_vpu { struct generic_pm_domain genpd; @@ -125,6 +128,53 @@ static int meson_g12a_pwrc_vpu_power_off(struct generic_pm_domain *genpd) return 0; } +static int meson_sm1_pwrc_vpu_power_off(struct generic_pm_domain *genpd) +{ + struct meson_gx_pwrc_vpu *pd = genpd_to_pd(genpd); + int i; + + regmap_update_bits(pd->regmap_ao, AO_RTI_GEN_PWR_ISO0, + GEN_PWR_VPU_HDMI, GEN_PWR_VPU_HDMI); + udelay(20); + + /* Power Down Memories */ + for (i = 0; i < 32; i += 2) { + regmap_update_bits(pd->regmap_hhi, HHI_VPU_MEM_PD_REG0, + 0x3 << i, 0x3 << i); + udelay(5); + } + for (i = 0; i < 32; i += 2) { + regmap_update_bits(pd->regmap_hhi, HHI_VPU_MEM_PD_REG1, + 0x3 << i, 0x3 << i); + udelay(5); + } + for (i = 0; i < 32; i += 2) { + regmap_update_bits(pd->regmap_hhi, HHI_VPU_MEM_PD_REG2, + 0x3 << i, 0x3 << i); + udelay(5); + } + regmap_update_bits(pd->regmap_hhi, HHI_VPU_MEM_PD_REG4, + 0x3 << 4, 0x3 << 4); + regmap_update_bits(pd->regmap_hhi, HHI_VPU_MEM_PD_REG4, + 0x7, 0x7); + for (i = 8; i < 16; i++) { + regmap_update_bits(pd->regmap_hhi, HHI_MEM_PD_REG0, + BIT(i), BIT(i)); + udelay(5); + } + udelay(20); + + regmap_update_bits(pd->regmap_ao, AO_RTI_GEN_PWR_SLEEP0, + GEN_PWR_VPU_HDMI, GEN_PWR_VPU_HDMI); + + msleep(20); + + clk_disable_unprepare(pd->vpu_clk); + clk_disable_unprepare(pd->vapb_clk); + + return 0; +} + static int meson_gx_pwrc_vpu_setup_clk(struct meson_gx_pwrc_vpu *pd) { int ret; @@ -242,6 +292,64 @@ static int meson_g12a_pwrc_vpu_power_on(struct generic_pm_domain *genpd) return 0; } +static int meson_sm1_pwrc_vpu_power_on(struct generic_pm_domain *genpd) +{ + struct meson_gx_pwrc_vpu *pd = genpd_to_pd(genpd); + int ret; + int i; + + regmap_update_bits(pd->regmap_ao, AO_RTI_GEN_PWR_SLEEP0, + GEN_PWR_VPU_HDMI, 0); + udelay(20); + + /* Power Up Memories */ + for (i = 0; i < 32; i += 2) { + regmap_update_bits(pd->regmap_hhi, HHI_VPU_MEM_PD_REG0, + 0x3 << i, 0); + udelay(5); + } + + for (i = 0; i < 32; i += 2) { + regmap_update_bits(pd->regmap_hhi, HHI_VPU_MEM_PD_REG1, + 0x3 << i, 0); + udelay(5); + } + + for (i = 0; i < 32; i += 2) { + regmap_update_bits(pd->regmap_hhi, HHI_VPU_MEM_PD_REG2, + 0x3 << i, 0); + udelay(5); + } + + regmap_update_bits(pd->regmap_hhi, HHI_VPU_MEM_PD_REG4, 0x3 << 4, 0); + + regmap_update_bits(pd->regmap_hhi, HHI_VPU_MEM_PD_REG4, 0x7, 0); + + for (i = 8; i < 16; i++) { + regmap_update_bits(pd->regmap_hhi, HHI_MEM_PD_REG0, + BIT(i), 0); + udelay(5); + } + udelay(20); + + ret = reset_control_assert(pd->rstc); + if (ret) + return ret; + + regmap_update_bits(pd->regmap_ao, AO_RTI_GEN_PWR_ISO0, + GEN_PWR_VPU_HDMI, 0); + + ret = reset_control_deassert(pd->rstc); + if (ret) + return ret; + + ret = meson_gx_pwrc_vpu_setup_clk(pd); + if (ret) + return ret; + + return 0; +} + static bool meson_gx_pwrc_vpu_get_power(struct meson_gx_pwrc_vpu *pd) { u32 reg; @@ -267,6 +375,14 @@ static struct meson_gx_pwrc_vpu vpu_hdmi_pd_g12a = { }, }; +static struct meson_gx_pwrc_vpu vpu_hdmi_pd_sm1 = { + .genpd = { + .name = "vpu_hdmi", + .power_off = meson_sm1_pwrc_vpu_power_off, + .power_on = meson_sm1_pwrc_vpu_power_on, + }, +}; + static int meson_gx_pwrc_vpu_probe(struct platform_device *pdev) { const struct meson_gx_pwrc_vpu *vpu_pd_match; @@ -362,6 +478,10 @@ static const struct of_device_id meson_gx_pwrc_vpu_match_table[] = { .compatible = "amlogic,meson-g12a-pwrc-vpu", .data = &vpu_hdmi_pd_g12a }, + { + .compatible = "amlogic,meson-sm1-pwrc-vpu", + .data = &vpu_hdmi_pd_sm1 + }, { /* sentinel */ } }; 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[176.150.251.154]) by smtp.gmail.com with ESMTPSA id d24sm11658802wra.43.2019.07.01.03.47.27 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 01 Jul 2019 03:47:27 -0700 (PDT) From: Neil Armstrong To: jbrunet@baylibre.com, khilman@baylibre.com Subject: [RFC 04/11] soc: amlogic: Add support for SM1 power controller Date: Mon, 1 Jul 2019 12:46:58 +0200 Message-Id: <20190701104705.18271-5-narmstrong@baylibre.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190701104705.18271-1-narmstrong@baylibre.com> References: <20190701104705.18271-1-narmstrong@baylibre.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190701_034730_020413_D12AD921 X-CRM114-Status: GOOD ( 17.07 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Neil Armstrong Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Add support for the General Purpose Amlogic SM1 Power controller, dedicated to the PCIe, USB, NNA and GE2D Power Domains. Signed-off-by: Neil Armstrong --- drivers/soc/amlogic/Kconfig | 11 ++ drivers/soc/amlogic/Makefile | 1 + drivers/soc/amlogic/meson-sm1-pwrc.c | 245 +++++++++++++++++++++++++++ 3 files changed, 257 insertions(+) create mode 100644 drivers/soc/amlogic/meson-sm1-pwrc.c diff --git a/drivers/soc/amlogic/Kconfig b/drivers/soc/amlogic/Kconfig index 5501ad5650b2..596f1afef1a7 100644 --- a/drivers/soc/amlogic/Kconfig +++ b/drivers/soc/amlogic/Kconfig @@ -36,6 +36,17 @@ config MESON_GX_PM_DOMAINS Say yes to expose Amlogic Meson GX Power Domains as Generic Power Domains. +config MESON_SM1_PM_DOMAINS + bool "Amlogic Meson SM1 Power Domains driver" + depends on ARCH_MESON || COMPILE_TEST + depends on PM && OF + default ARCH_MESON + select PM_GENERIC_DOMAINS + select PM_GENERIC_DOMAINS_OF + help + Say yes to expose Amlogic Meson SM1 Power Domains as + Generic Power Domains. + config MESON_MX_SOCINFO bool "Amlogic Meson MX SoC Information driver" depends on ARCH_MESON || COMPILE_TEST diff --git a/drivers/soc/amlogic/Makefile b/drivers/soc/amlogic/Makefile index bf2d109f61e9..f99935499ee6 100644 --- a/drivers/soc/amlogic/Makefile +++ b/drivers/soc/amlogic/Makefile @@ -3,3 +3,4 @@ obj-$(CONFIG_MESON_CLK_MEASURE) += meson-clk-measure.o obj-$(CONFIG_MESON_GX_SOCINFO) += meson-gx-socinfo.o obj-$(CONFIG_MESON_GX_PM_DOMAINS) += meson-gx-pwrc-vpu.o obj-$(CONFIG_MESON_MX_SOCINFO) += meson-mx-socinfo.o +obj-$(CONFIG_MESON_SM1_PM_DOMAINS) += meson-sm1-pwrc.o diff --git a/drivers/soc/amlogic/meson-sm1-pwrc.c b/drivers/soc/amlogic/meson-sm1-pwrc.c new file mode 100644 index 000000000000..9ece1d06f417 --- /dev/null +++ b/drivers/soc/amlogic/meson-sm1-pwrc.c @@ -0,0 +1,245 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2017 BayLibre, SAS + * Author: Neil Armstrong + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +/* AO Offsets */ + +#define AO_RTI_GEN_PWR_SLEEP0 (0x3a << 2) +#define AO_RTI_GEN_PWR_ISO0 (0x3b << 2) + +/* HHI Offsets */ + +#define HHI_MEM_PD_REG0 (0x40 << 2) +#define HHI_NANOQ_MEM_PD_REG0 (0x46 << 2) +#define HHI_NANOQ_MEM_PD_REG1 (0x47 << 2) + +struct meson_sm1_pwrc; + +struct meson_sm1_pwrc_mem_domain { + unsigned int reg; + unsigned int mask; +}; + +struct meson_sm1_pwrc_domain_desc { + char *name; + unsigned int sleep_reg; + unsigned int sleep_bit; + unsigned int iso_reg; + unsigned int iso_bit; + unsigned int mem_pd_count; + struct meson_sm1_pwrc_mem_domain *mem_pd; +}; + +struct meson_sm1_pwrc_domain_data { + unsigned int count; + struct meson_sm1_pwrc_domain_desc *domains; +}; + +static struct meson_sm1_pwrc_mem_domain sm1_pwrc_mem_nna[] = { + { HHI_NANOQ_MEM_PD_REG0, 0xff }, + { HHI_NANOQ_MEM_PD_REG1, 0xff }, +}; + +static struct meson_sm1_pwrc_mem_domain sm1_pwrc_mem_usb[] = { + { HHI_MEM_PD_REG0, GENMASK(31, 30) }, +}; + +static struct meson_sm1_pwrc_mem_domain sm1_pwrc_mem_pcie[] = { + { HHI_MEM_PD_REG0, GENMASK(29, 26) }, +}; + +static struct meson_sm1_pwrc_mem_domain sm1_pwrc_mem_ge2d[] = { + { HHI_MEM_PD_REG0, GENMASK(25, 18) }, +}; + +#define SM1_PD(__name, __bit, __mem) \ + { \ + .name = __name, \ + .sleep_reg = AO_RTI_GEN_PWR_SLEEP0, \ + .sleep_bit = __bit, \ + .iso_reg = AO_RTI_GEN_PWR_ISO0, \ + .iso_bit = __bit, \ + .mem_pd_count = ARRAY_SIZE(__mem), \ + .mem_pd = __mem, \ + } + +static struct meson_sm1_pwrc_domain_desc sm1_pwrc_domains[] = { + [PWRC_SM1_NNA_ID] = SM1_PD("NNA", 16, sm1_pwrc_mem_nna), + [PWRC_SM1_USB_ID] = SM1_PD("USB", 17, sm1_pwrc_mem_usb), + [PWRC_SM1_PCIE_ID] = SM1_PD("PCI", 18, sm1_pwrc_mem_pcie), + [PWRC_SM1_GE2D_ID] = SM1_PD("GE2D", 19, sm1_pwrc_mem_ge2d), +}; + +struct meson_sm1_pwrc_domain { + struct generic_pm_domain base; + bool enabled; + struct meson_sm1_pwrc *pwrc; + struct meson_sm1_pwrc_domain_desc desc; +}; + +struct meson_sm1_pwrc { + struct regmap *regmap_ao; + struct regmap *regmap_hhi; + struct meson_sm1_pwrc_domain *domains; + struct genpd_onecell_data xlate; +}; + +static int meson_sm1_pwrc_off(struct generic_pm_domain *domain) +{ + struct meson_sm1_pwrc_domain *pwrc_domain = + container_of(domain, struct meson_sm1_pwrc_domain, base); + int i; + + regmap_update_bits(pwrc_domain->pwrc->regmap_ao, + pwrc_domain->desc.sleep_reg, + pwrc_domain->desc.sleep_bit, + pwrc_domain->desc.sleep_bit); + udelay(20); + + for (i = 0 ; i < pwrc_domain->desc.mem_pd_count ; ++i) + regmap_update_bits(pwrc_domain->pwrc->regmap_hhi, + pwrc_domain->desc.mem_pd[i].reg, + pwrc_domain->desc.mem_pd[i].mask, + pwrc_domain->desc.mem_pd[i].mask); + + udelay(20); + + regmap_update_bits(pwrc_domain->pwrc->regmap_ao, + pwrc_domain->desc.iso_reg, + pwrc_domain->desc.iso_bit, + pwrc_domain->desc.iso_bit); + + return 0; +} + +static int meson_sm1_pwrc_on(struct generic_pm_domain *domain) +{ + struct meson_sm1_pwrc_domain *pwrc_domain = + container_of(domain, struct meson_sm1_pwrc_domain, base); + int i; + + regmap_update_bits(pwrc_domain->pwrc->regmap_ao, + pwrc_domain->desc.sleep_reg, + pwrc_domain->desc.sleep_bit, 0); + udelay(20); + + for (i = 0 ; i < pwrc_domain->desc.mem_pd_count ; ++i) + regmap_update_bits(pwrc_domain->pwrc->regmap_hhi, + pwrc_domain->desc.mem_pd[i].reg, + pwrc_domain->desc.mem_pd[i].mask, 0); + + udelay(20); + + regmap_update_bits(pwrc_domain->pwrc->regmap_ao, + pwrc_domain->desc.iso_reg, + pwrc_domain->desc.iso_bit, 0); + + return 0; +} + +static int meson_sm1_pwrc_probe(struct platform_device *pdev) +{ + const struct meson_sm1_pwrc_domain_data *match; + struct regmap *regmap_ao, *regmap_hhi; + struct meson_sm1_pwrc *sm1_pwrc; + int i; + + match = of_device_get_match_data(&pdev->dev); + if (!match) { + dev_err(&pdev->dev, "failed to get match data\n"); + return -ENODEV; + } + + sm1_pwrc = devm_kzalloc(&pdev->dev, sizeof(*sm1_pwrc), GFP_KERNEL); + if (!sm1_pwrc) + return -ENOMEM; + + sm1_pwrc->xlate.domains = + devm_kcalloc(&pdev->dev, + match->count, + sizeof(*sm1_pwrc->xlate.domains), + GFP_KERNEL); + if (!sm1_pwrc->xlate.domains) + return -ENOMEM; + + sm1_pwrc->domains = + devm_kcalloc(&pdev->dev, + match->count, + sizeof(*sm1_pwrc->domains), + GFP_KERNEL); + if (!sm1_pwrc->domains) + return -ENOMEM; + + sm1_pwrc->xlate.num_domains = match->count; + + regmap_ao = syscon_node_to_regmap(of_get_parent(pdev->dev.of_node)); + if (IS_ERR(regmap_ao)) { + dev_err(&pdev->dev, "failed to get regmap\n"); + return PTR_ERR(regmap_ao); + } + + regmap_hhi = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, + "amlogic,hhi-sysctrl"); + if (IS_ERR(regmap_hhi)) { + dev_err(&pdev->dev, "failed to get HHI regmap\n"); + return PTR_ERR(regmap_hhi); + } + + sm1_pwrc->regmap_ao = regmap_ao; + sm1_pwrc->regmap_hhi = regmap_hhi; + + platform_set_drvdata(pdev, sm1_pwrc); + + for (i = 0 ; i < match->count ; ++i) { + struct meson_sm1_pwrc_domain *dom = &sm1_pwrc->domains[i]; + + dom->pwrc = sm1_pwrc; + + memcpy(&dom->desc, &match->domains[i], sizeof(dom->desc)); + + dom->base.name = dom->desc.name; + dom->base.power_on = meson_sm1_pwrc_on; + dom->base.power_off = meson_sm1_pwrc_off; + + pm_genpd_init(&dom->base, NULL, true); + + sm1_pwrc->xlate.domains[i] = &dom->base; + } + + of_genpd_add_provider_onecell(pdev->dev.of_node, &sm1_pwrc->xlate); + + return 0; +} + +static struct meson_sm1_pwrc_domain_data meson_sm1_pwrc_data = { + .count = ARRAY_SIZE(sm1_pwrc_domains), + .domains = sm1_pwrc_domains, +}; + +static const struct of_device_id meson_sm1_pwrc_match_table[] = { + { + .compatible = "amlogic,meson-sm1-pwrc", + .data = &meson_sm1_pwrc_data, + }, + { /* sentinel */ } +}; + +static struct platform_driver meson_sm1_pwrc_driver = { + .probe = meson_sm1_pwrc_probe, + .driver = { + .name = "meson_sm1_pwrc", + .of_match_table = meson_sm1_pwrc_match_table, + }, +}; +builtin_platform_driver(meson_sm1_pwrc_driver); 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[176.150.251.154]) by smtp.gmail.com with ESMTPSA id d24sm11658802wra.43.2019.07.01.03.47.28 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 01 Jul 2019 03:47:28 -0700 (PDT) From: Neil Armstrong To: jbrunet@baylibre.com, khilman@baylibre.com, devicetree@vger.kernel.org Subject: [RFC 05/11] dt-bindings: soc: amlogic: clk-measure: Add SM1 compatible Date: Mon, 1 Jul 2019 12:46:59 +0200 Message-Id: <20190701104705.18271-6-narmstrong@baylibre.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190701104705.18271-1-narmstrong@baylibre.com> References: <20190701104705.18271-1-narmstrong@baylibre.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190701_034731_180520_BDC1FABC X-CRM114-Status: GOOD ( 10.89 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Neil Armstrong Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Add the Amlogic SM1 Compatible for the clk-measurer IP. Signed-off-by: Neil Armstrong Reviewed-by: Martin Blumenstingl Reviewed-by: Rob Herring --- Documentation/devicetree/bindings/soc/amlogic/clk-measure.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/soc/amlogic/clk-measure.txt b/Documentation/devicetree/bindings/soc/amlogic/clk-measure.txt index 6bf6b43f8dd8..3dd563cec794 100644 --- a/Documentation/devicetree/bindings/soc/amlogic/clk-measure.txt +++ b/Documentation/devicetree/bindings/soc/amlogic/clk-measure.txt @@ -11,6 +11,7 @@ Required properties: "amlogic,meson8b-clk-measure" for Meson8b SoCs "amlogic,meson-axg-clk-measure" for AXG SoCs "amlogic,meson-g12a-clk-measure" for G12a SoCs + "amlogic,meson-sm1-clk-measure" for SM1 SoCs - reg: base address and size of the Clock Measurer register space. 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[176.150.251.154]) by smtp.gmail.com with ESMTPSA id d24sm11658802wra.43.2019.07.01.03.47.29 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 01 Jul 2019 03:47:29 -0700 (PDT) From: Neil Armstrong To: jbrunet@baylibre.com, khilman@baylibre.com Subject: [RFC 06/11] soc: amlogic: clk-measure: Add support for SM1 Date: Mon, 1 Jul 2019 12:47:00 +0200 Message-Id: <20190701104705.18271-7-narmstrong@baylibre.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190701104705.18271-1-narmstrong@baylibre.com> References: <20190701104705.18271-1-narmstrong@baylibre.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190701_034732_059244_58FE74D3 X-CRM114-Status: GOOD ( 11.55 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Neil Armstrong Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Add the clk-measurer clocks IDs for the Amlogic SM1 SoC family. Signed-off-by: Neil Armstrong --- drivers/soc/amlogic/meson-clk-measure.c | 134 ++++++++++++++++++++++++ 1 file changed, 134 insertions(+) diff --git a/drivers/soc/amlogic/meson-clk-measure.c b/drivers/soc/amlogic/meson-clk-measure.c index f09b404b39d3..e32e97613000 100644 --- a/drivers/soc/amlogic/meson-clk-measure.c +++ b/drivers/soc/amlogic/meson-clk-measure.c @@ -357,6 +357,136 @@ static struct meson_msr_id clk_msr_g12a[CLK_MSR_MAX] = { CLK_MSR_ID(122, "audio_pdm_dclk"), }; +static struct meson_msr_id clk_msr_sm1[CLK_MSR_MAX] = { + CLK_MSR_ID(0, "ring_osc_out_ee_0"), + CLK_MSR_ID(1, "ring_osc_out_ee_1"), + CLK_MSR_ID(2, "ring_osc_out_ee_2"), + CLK_MSR_ID(3, "ring_osc_out_ee_3"), + CLK_MSR_ID(4, "gp0_pll"), + CLK_MSR_ID(5, "gp1_pll"), + CLK_MSR_ID(6, "enci"), + CLK_MSR_ID(7, "clk81"), + CLK_MSR_ID(8, "encp"), + CLK_MSR_ID(9, "encl"), + CLK_MSR_ID(10, "vdac"), + CLK_MSR_ID(11, "eth_tx"), + CLK_MSR_ID(12, "hifi_pll"), + CLK_MSR_ID(13, "mod_tcon"), + CLK_MSR_ID(14, "fec_0"), + CLK_MSR_ID(15, "fec_1"), + CLK_MSR_ID(16, "fec_2"), + CLK_MSR_ID(17, "sys_pll_div16"), + CLK_MSR_ID(18, "sys_cpu_div16"), + CLK_MSR_ID(19, "lcd_an_ph2"), + CLK_MSR_ID(20, "rtc_osc_out"), + CLK_MSR_ID(21, "lcd_an_ph3"), + CLK_MSR_ID(22, "eth_phy_ref"), + CLK_MSR_ID(23, "mpll_50m"), + CLK_MSR_ID(24, "eth_125m"), + CLK_MSR_ID(25, "eth_rmii"), + CLK_MSR_ID(26, "sc_int"), + CLK_MSR_ID(27, "in_mac"), + CLK_MSR_ID(28, "sar_adc"), + CLK_MSR_ID(29, "pcie_inp"), + CLK_MSR_ID(30, "pcie_inn"), + CLK_MSR_ID(31, "mpll_test_out"), + CLK_MSR_ID(32, "vdec"), + CLK_MSR_ID(34, "eth_mpll_50m"), + CLK_MSR_ID(35, "mali"), + CLK_MSR_ID(36, "hdmi_tx_pixel"), + CLK_MSR_ID(37, "cdac"), + CLK_MSR_ID(38, "vdin_meas"), + CLK_MSR_ID(39, "bt656"), + CLK_MSR_ID(40, "arm_ring_osc_out_4"), + CLK_MSR_ID(41, "eth_rx_or_rmii"), + CLK_MSR_ID(42, "mp0_out"), + CLK_MSR_ID(43, "fclk_div5"), + CLK_MSR_ID(44, "pwm_b"), + CLK_MSR_ID(45, "pwm_a"), + CLK_MSR_ID(46, "vpu"), + CLK_MSR_ID(47, "ddr_dpll_pt"), + CLK_MSR_ID(48, "mp1_out"), + CLK_MSR_ID(49, "mp2_out"), + CLK_MSR_ID(50, "mp3_out"), + CLK_MSR_ID(51, "sd_emmc_c"), + CLK_MSR_ID(52, "sd_emmc_b"), + CLK_MSR_ID(53, "sd_emmc_a"), + CLK_MSR_ID(54, "vpu_clkc"), + CLK_MSR_ID(55, "vid_pll_div_out"), + CLK_MSR_ID(56, "wave420l_a"), + CLK_MSR_ID(57, "wave420l_c"), + CLK_MSR_ID(58, "wave420l_b"), + CLK_MSR_ID(59, "hcodec"), + CLK_MSR_ID(40, "arm_ring_osc_out_5"), + CLK_MSR_ID(61, "gpio_msr"), + CLK_MSR_ID(62, "hevcb"), + CLK_MSR_ID(63, "dsi_meas"), + CLK_MSR_ID(64, "spicc_1"), + CLK_MSR_ID(65, "spicc_0"), + CLK_MSR_ID(66, "vid_lock"), + CLK_MSR_ID(67, "dsi_phy"), + CLK_MSR_ID(68, "hdcp22_esm"), + CLK_MSR_ID(69, "hdcp22_skp"), + CLK_MSR_ID(70, "pwm_f"), + CLK_MSR_ID(71, "pwm_e"), + CLK_MSR_ID(72, "pwm_d"), + CLK_MSR_ID(73, "pwm_c"), + CLK_MSR_ID(74, "arm_ring_osc_out_6"), + CLK_MSR_ID(75, "hevcf"), + CLK_MSR_ID(74, "arm_ring_osc_out_7"), + CLK_MSR_ID(77, "rng_ring_osc_0"), + CLK_MSR_ID(78, "rng_ring_osc_1"), + CLK_MSR_ID(79, "rng_ring_osc_2"), + CLK_MSR_ID(80, "rng_ring_osc_3"), + CLK_MSR_ID(81, "vapb"), + CLK_MSR_ID(82, "ge2d"), + CLK_MSR_ID(83, "co_rx"), + CLK_MSR_ID(84, "co_tx"), + CLK_MSR_ID(85, "arm_ring_osc_out_8"), + CLK_MSR_ID(86, "arm_ring_osc_out_9"), + CLK_MSR_ID(87, "mipi_dsi_phy"), + CLK_MSR_ID(88, "cis2_adapt"), + CLK_MSR_ID(89, "hdmi_todig"), + CLK_MSR_ID(90, "hdmitx_sys"), + CLK_MSR_ID(91, "nna_core"), + CLK_MSR_ID(92, "nna_axi"), + CLK_MSR_ID(93, "vad"), + CLK_MSR_ID(94, "eth_phy_rx"), + CLK_MSR_ID(95, "eth_phy_pll"), + CLK_MSR_ID(96, "vpu_b"), + CLK_MSR_ID(97, "cpu_b_tmp"), + CLK_MSR_ID(98, "ts"), + CLK_MSR_ID(99, "arm_ring_osc_out_10"), + CLK_MSR_ID(100, "arm_ring_osc_out_11"), + CLK_MSR_ID(101, "arm_ring_osc_out_12"), + CLK_MSR_ID(102, "arm_ring_osc_out_13"), + CLK_MSR_ID(103, "arm_ring_osc_out_14"), + CLK_MSR_ID(104, "arm_ring_osc_out_15"), + CLK_MSR_ID(105, "arm_ring_osc_out_16"), + CLK_MSR_ID(106, "ephy_test"), + CLK_MSR_ID(107, "au_dac_g128x"), + CLK_MSR_ID(108, "audio_locker_out"), + CLK_MSR_ID(109, "audio_locker_in"), + CLK_MSR_ID(110, "audio_tdmout_c_sclk"), + CLK_MSR_ID(111, "audio_tdmout_b_sclk"), + CLK_MSR_ID(112, "audio_tdmout_a_sclk"), + CLK_MSR_ID(113, "audio_tdmin_lb_sclk"), + CLK_MSR_ID(114, "audio_tdmin_c_sclk"), + CLK_MSR_ID(115, "audio_tdmin_b_sclk"), + CLK_MSR_ID(116, "audio_tdmin_a_sclk"), + CLK_MSR_ID(117, "audio_resample"), + CLK_MSR_ID(118, "audio_pdm_sys"), + CLK_MSR_ID(119, "audio_spdifout_b"), + CLK_MSR_ID(120, "audio_spdifout"), + CLK_MSR_ID(121, "audio_spdifin"), + CLK_MSR_ID(122, "audio_pdm_dclk"), + CLK_MSR_ID(123, "audio_resampled"), + CLK_MSR_ID(124, "earcrx_pll"), + CLK_MSR_ID(125, "earcrx_pll_test"), + CLK_MSR_ID(126, "csi_phy0"), + CLK_MSR_ID(127, "csi2_data"), +}; + static int meson_measure_id(struct meson_msr_id *clk_msr_id, unsigned int duration) { @@ -545,6 +675,10 @@ static const struct of_device_id meson_msr_match_table[] = { .compatible = "amlogic,meson-g12a-clk-measure", .data = (void *)clk_msr_g12a, }, + { + .compatible = "amlogic,meson-sm1-clk-measure", + .data = (void *)clk_msr_sm1, + }, { /* sentinel */ } }; From patchwork Mon Jul 1 10:47:01 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neil Armstrong X-Patchwork-Id: 11025533 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 211AF112C for ; Mon, 1 Jul 2019 10:49:50 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 138D51FFC8 for ; Mon, 1 Jul 2019 10:49:50 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 07A7C28647; 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[176.150.251.154]) by smtp.gmail.com with ESMTPSA id d24sm11658802wra.43.2019.07.01.03.47.30 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 01 Jul 2019 03:47:30 -0700 (PDT) From: Neil Armstrong To: jbrunet@baylibre.com, khilman@baylibre.com, linux-media@vger.kernel.org, devicetree@vger.kernel.org Subject: [RFC 07/11] dt-bindings: media: meson-ao-cec: add SM1 compatible Date: Mon, 1 Jul 2019 12:47:01 +0200 Message-Id: <20190701104705.18271-8-narmstrong@baylibre.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190701104705.18271-1-narmstrong@baylibre.com> References: <20190701104705.18271-1-narmstrong@baylibre.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190701_034733_130503_0D1E66BC X-CRM114-Status: GOOD ( 11.11 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Neil Armstrong Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Add AO-CEC compatible string for the Amlogic SM1 SoC family, a derivate of the G12A AO-CECB controller. Signed-off-by: Neil Armstrong Reviewed-by: Rob Herring --- Documentation/devicetree/bindings/media/meson-ao-cec.txt | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/media/meson-ao-cec.txt b/Documentation/devicetree/bindings/media/meson-ao-cec.txt index c67fc41d4aa2..ad92ee41c0dd 100644 --- a/Documentation/devicetree/bindings/media/meson-ao-cec.txt +++ b/Documentation/devicetree/bindings/media/meson-ao-cec.txt @@ -5,10 +5,12 @@ to handle communication between HDMI connected devices over the CEC bus. Required properties: - compatible : value should be following depending on the SoC : - For GXBB, GXL, GXM and G12A (AO_CEC_A module) : + For GXBB, GXL, GXM, G12A and SM1 (AO_CEC_A module) : "amlogic,meson-gx-ao-cec" For G12A (AO_CEC_B module) : "amlogic,meson-g12a-ao-cec" + For SM1 (AO_CEC_B module) : + "amlogic,meson-sm1-ao-cec" - reg : Physical base address of the IP registers and length of memory mapped region. @@ -16,9 +18,9 @@ Required properties: - interrupts : AO-CEC interrupt number to the CPU. - clocks : from common clock binding: handle to AO-CEC clock. - clock-names : from common clock binding, must contain : - For GXBB, GXL, GXM and G12A (AO_CEC_A module) : + For GXBB, GXL, GXM, G12A and SM1 (AO_CEC_A module) : - "core" - For G12A (AO_CEC_B module) : + For G12A, SM1 (AO_CEC_B module) : - "oscin" corresponding to entry in the clocks property. - hdmi-phandle: phandle to the HDMI controller From patchwork Mon Jul 1 10:47:02 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neil Armstrong X-Patchwork-Id: 11025541 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id E7395138D for ; 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[176.150.251.154]) by smtp.gmail.com with ESMTPSA id d24sm11658802wra.43.2019.07.01.03.47.31 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 01 Jul 2019 03:47:31 -0700 (PDT) From: Neil Armstrong To: jbrunet@baylibre.com, khilman@baylibre.com, linux-media@vger.kernel.org Subject: [RFC 08/11] media: platform: meson-ao-cec-g12a: add support for SM1 Date: Mon, 1 Jul 2019 12:47:02 +0200 Message-Id: <20190701104705.18271-9-narmstrong@baylibre.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190701104705.18271-1-narmstrong@baylibre.com> References: <20190701104705.18271-1-narmstrong@baylibre.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190701_034734_950069_141FDFE4 X-CRM114-Status: GOOD ( 15.27 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Neil Armstrong Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Add support for the Amlogic SM1 SoC Family to the G12A AO-CECB derivative. It only adds a single init register. Signed-off-by: Neil Armstrong --- drivers/media/platform/meson/ao-cec-g12a.c | 37 +++++++++++++++++++++- 1 file changed, 36 insertions(+), 1 deletion(-) diff --git a/drivers/media/platform/meson/ao-cec-g12a.c b/drivers/media/platform/meson/ao-cec-g12a.c index 3620a1e310f5..1c696a126ee8 100644 --- a/drivers/media/platform/meson/ao-cec-g12a.c +++ b/drivers/media/platform/meson/ao-cec-g12a.c @@ -121,6 +121,9 @@ #define CECB_CTRL_TYPE_NEXT 2 #define CECB_CTRL2 0x01 + +#define CECB_CTRL2_RISE_DEL_MAX GENMASK(4, 0) + #define CECB_INTR_MASK 0x02 #define CECB_LADD_LOW 0x05 #define CECB_LADD_HIGH 0x06 @@ -165,6 +168,11 @@ #define CECB_WAKEUPCTRL 0x31 +struct meson_ao_cec_g12a_data { + /* Setup the internal CECB_CTRL2 register */ + bool ctrl2_setup; +}; + struct meson_ao_cec_g12a_device { struct platform_device *pdev; struct regmap *regmap; @@ -175,6 +183,7 @@ struct meson_ao_cec_g12a_device { struct cec_msg rx_msg; struct clk *oscin; struct clk *core; + const struct meson_ao_cec_g12a_data *data; }; static const struct regmap_config meson_ao_cec_g12a_regmap_conf = { @@ -620,6 +629,10 @@ static int meson_ao_cec_g12a_adap_enable(struct cec_adapter *adap, bool enable) regmap_update_bits(ao_cec->regmap, CECB_GEN_CNTL_REG, CECB_GEN_CNTL_RESET, 0); + if (ao_cec->data->ctrl2_setup) + regmap_write(ao_cec->regmap_cec, CECB_CTRL2, + FIELD_PREP(CECB_CTRL2_RISE_DEL_MAX, 2)); + meson_ao_cec_g12a_irq_setup(ao_cec, true); return 0; @@ -639,6 +652,7 @@ static int meson_ao_cec_g12a_probe(struct platform_device *pdev) void __iomem *base; int ret, irq; + hdmi_dev = cec_notifier_parse_hdmi_phandle(&pdev->dev); if (IS_ERR(hdmi_dev)) return PTR_ERR(hdmi_dev); @@ -647,6 +661,12 @@ static int meson_ao_cec_g12a_probe(struct platform_device *pdev) if (!ao_cec) return -ENOMEM; + ao_cec->data = of_device_get_match_data(&pdev->dev); + if (!ao_cec->data) { + dev_err(&pdev->dev, "failed to get match data\n"); + return -ENODEV; + } + spin_lock_init(&ao_cec->cec_reg_lock); ao_cec->pdev = pdev; @@ -757,8 +777,23 @@ static int meson_ao_cec_g12a_remove(struct platform_device *pdev) return 0; } +static const struct meson_ao_cec_g12a_data ao_cec_g12a_data = { + .ctrl2_setup = false, +}; + +static const struct meson_ao_cec_g12a_data ao_cec_sm1_data = { + .ctrl2_setup = true, +}; + static const struct of_device_id meson_ao_cec_g12a_of_match[] = { - { .compatible = "amlogic,meson-g12a-ao-cec", }, + { + .compatible = "amlogic,meson-g12a-ao-cec", + .data = &ao_cec_g12a_data, + }, + { + .compatible = "amlogic,meson-sm1-ao-cec", + .data = &ao_cec_sm1_data, + }, { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, meson_ao_cec_g12a_of_match); From patchwork Mon Jul 1 10:47:03 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neil Armstrong X-Patchwork-Id: 11025543 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 0C485112C for ; Mon, 1 Jul 2019 10:50:40 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id EF96526255 for ; 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[176.150.251.154]) by smtp.gmail.com with ESMTPSA id d24sm11658802wra.43.2019.07.01.03.47.32 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 01 Jul 2019 03:47:33 -0700 (PDT) From: Neil Armstrong To: jbrunet@baylibre.com, khilman@baylibre.com Subject: [RFC 09/11] dt-bindings: arm: amlogic: add SM1 bindings Date: Mon, 1 Jul 2019 12:47:03 +0200 Message-Id: <20190701104705.18271-10-narmstrong@baylibre.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190701104705.18271-1-narmstrong@baylibre.com> References: <20190701104705.18271-1-narmstrong@baylibre.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190701_034735_977171_EDB9F142 X-CRM114-Status: GOOD ( 11.19 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Neil Armstrong Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Add bindings for the new Amlogic SM1 SoC Family. It a derivative of the G12A SoC Family with : - Cortex-A55 core instead of A53 - more power domains - a neural network co-processor - a CSI input and image processor Signed-off-by: Neil Armstrong --- Documentation/devicetree/bindings/arm/amlogic.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/amlogic.yaml b/Documentation/devicetree/bindings/arm/amlogic.yaml index 325c6fd3566d..0b419fd0bac2 100644 --- a/Documentation/devicetree/bindings/arm/amlogic.yaml +++ b/Documentation/devicetree/bindings/arm/amlogic.yaml @@ -141,4 +141,7 @@ properties: - hardkernel,odroid-n2 - const: amlogic,g12b + - description: Boards with the Amlogic Meson SM1 S905X3 SoC + items: + - const: amlogic,sm1 ... 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[176.150.251.154]) by smtp.gmail.com with ESMTPSA id d24sm11658802wra.43.2019.07.01.03.47.34 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 01 Jul 2019 03:47:34 -0700 (PDT) From: Neil Armstrong To: jbrunet@baylibre.com, khilman@baylibre.com Subject: [RFC 10/11] dt-bindings: arm: amlogic: add SEI Robotics SEI610 bindings Date: Mon, 1 Jul 2019 12:47:04 +0200 Message-Id: <20190701104705.18271-11-narmstrong@baylibre.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190701104705.18271-1-narmstrong@baylibre.com> References: <20190701104705.18271-1-narmstrong@baylibre.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190701_034737_115929_A8A4E305 X-CRM114-Status: GOOD ( 10.27 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Neil Armstrong Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Add the compatible for the Amlogic SM1 Based SEI610 board. Signed-off-by: Neil Armstrong --- Documentation/devicetree/bindings/arm/amlogic.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/amlogic.yaml b/Documentation/devicetree/bindings/arm/amlogic.yaml index 0b419fd0bac2..ebf707165d73 100644 --- a/Documentation/devicetree/bindings/arm/amlogic.yaml +++ b/Documentation/devicetree/bindings/arm/amlogic.yaml @@ -143,5 +143,7 @@ properties: - description: Boards with the Amlogic Meson SM1 S905X3 SoC items: + - enum: + - seirobotics,sei610 - const: amlogic,sm1 ... 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[176.150.251.154]) by smtp.gmail.com with ESMTPSA id d24sm11658802wra.43.2019.07.01.03.47.35 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 01 Jul 2019 03:47:35 -0700 (PDT) From: Neil Armstrong To: jbrunet@baylibre.com, khilman@baylibre.com Subject: [RFC 11/11] arm64: dts: add support for SM1 based SEI Robotics SEI610 Date: Mon, 1 Jul 2019 12:47:05 +0200 Message-Id: <20190701104705.18271-12-narmstrong@baylibre.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190701104705.18271-1-narmstrong@baylibre.com> References: <20190701104705.18271-1-narmstrong@baylibre.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190701_034737_961435_B619953C X-CRM114-Status: GOOD ( 19.08 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Neil Armstrong Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Add support for the Amlogic SM1 Based SEI610 board. The SM1 SoC is a derivative of the G12A SoC Family with : - Cortex-A55 core instead of A53 - more power domains, including USB & PCIe - a neural network co-processor (NNA) - a CSI input and image processor - some changes in the audio complex, thus not yet enabled The SEI610 board is a derivative of the SEI510 board with : - removed ADC based touch button, replaced with 3x GPIO buttons - physical switch disabling on-board MICs - USB-C port for USB 2.0 OTG - On-board FTDI USB2SERIAL port for Linux console Signed-off-by: Neil Armstrong --- arch/arm64/boot/dts/amlogic/Makefile | 1 + .../boot/dts/amlogic/meson-sm1-sei610.dts | 329 ++++++++++++++++++ arch/arm64/boot/dts/amlogic/meson-sm1.dtsi | 77 ++++ 3 files changed, 407 insertions(+) create mode 100644 arch/arm64/boot/dts/amlogic/meson-sm1-sei610.dts create mode 100644 arch/arm64/boot/dts/amlogic/meson-sm1.dtsi diff --git a/arch/arm64/boot/dts/amlogic/Makefile b/arch/arm64/boot/dts/amlogic/Makefile index 07b861fe5fa5..9a852802a4cc 100644 --- a/arch/arm64/boot/dts/amlogic/Makefile +++ b/arch/arm64/boot/dts/amlogic/Makefile @@ -32,3 +32,4 @@ dtb-$(CONFIG_ARCH_MESON) += meson-gxm-q200.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxm-q201.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxm-rbox-pro.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxm-vega-s96.dtb +dtb-$(CONFIG_ARCH_MESON) += meson-sm1-sei610.dtb diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1-sei610.dts b/arch/arm64/boot/dts/amlogic/meson-sm1-sei610.dts new file mode 100644 index 000000000000..31559075fade --- /dev/null +++ b/arch/arm64/boot/dts/amlogic/meson-sm1-sei610.dts @@ -0,0 +1,329 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 BayLibre SAS. All rights reserved. + */ + +/dts-v1/; + +#include "meson-sm1.dtsi" +#include +#include +#include +#include + +/ { + compatible = "seirobotics,sei610", "amlogic,sm1"; + model = "SEI Robotics SEI610"; + + aliases { + serial0 = &uart_AO; + ethernet0 = ðmac; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + emmc_pwrseq: emmc-pwrseq { + compatible = "mmc-pwrseq-emmc"; + reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>; + }; + + gpio-keys { + compatible = "gpio-keys-polled"; + poll-interval = <100>; + + key1 { + label = "A"; + linux,code = ; + gpios = <&gpio GPIOH_6 GPIO_ACTIVE_LOW>; + }; + + key2 { + label = "B"; + linux,code = ; + gpios = <&gpio GPIOH_7 GPIO_ACTIVE_LOW>; + }; + + key3 { + label = "C"; + linux,code = ; + gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_LOW>; + }; + }; + + hdmi-connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_connector_in: endpoint { + remote-endpoint = <&hdmi_tx_tmds_out>; + }; + }; + }; + + leds { + compatible = "gpio-leds"; + + bluetooth { + label = "sei610:blue:bt"; + gpios = <&gpio GPIOC_7 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>; + default-state = "off"; + }; + }; + + pwmleds { + compatible = "pwm-leds"; + + power { + label = "sei610:red:power"; + pwms = <&pwm_AO_ab 0 30518 0>; + max-brightness = <255>; + linux,default-trigger = "default-on"; + active-low; + }; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x40000000>; + }; + + ao_5v: regulator-ao_5v { + compatible = "regulator-fixed"; + regulator-name = "AO_5V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&dc_in>; + regulator-always-on; + }; + + dc_in: regulator-dc_in { + compatible = "regulator-fixed"; + regulator-name = "DC_IN"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + emmc_1v8: regulator-emmc_1v8 { + compatible = "regulator-fixed"; + regulator-name = "EMMC_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vddao_3v3>; + regulator-always-on; + }; + + vddao_3v3: regulator-vddao_3v3 { + compatible = "regulator-fixed"; + regulator-name = "VDDAO_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&dc_in>; + regulator-always-on; + }; + + /* Used by Tuner, RGB Led & IR Emitter LED array */ + vddao_3v3_t: regultor-vddao_3v3_t { + compatible = "regulator-fixed"; + regulator-name = "VDDAO_3V3_T"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vddao_3v3>; + gpio = <&gpio GPIOH_8 GPIO_OPEN_DRAIN>; + enable-active-low; + regulator-always-on; + }; + + vddio_ao1v8: regulator-vddio_ao1v8 { + compatible = "regulator-fixed"; + regulator-name = "VDDIO_AO1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vddao_3v3>; + regulator-always-on; + }; + + reserved-memory { + /* TEE Reserved Memory */ + bl32_reserved: bl32@5000000 { + reg = <0x0 0x05300000 0x0 0x2000000>; + no-map; + }; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>; + clocks = <&wifi32k>; + clock-names = "ext_clock"; + }; + + wifi32k: wifi32k { + compatible = "pwm-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */ + }; +}; + +&cec_AO { + pinctrl-0 = <&cec_ao_a_h_pins>; + pinctrl-names = "default"; + status = "disabled"; + hdmi-phandle = <&hdmi_tx>; +}; + +&cecb_AO { + pinctrl-0 = <&cec_ao_b_h_pins>; + pinctrl-names = "default"; + status = "okay"; + hdmi-phandle = <&hdmi_tx>; +}; + +ðmac { + status = "okay"; + phy-handle = <&internal_ephy>; + phy-mode = "rmii"; +}; + +&hdmi_tx { + status = "okay"; + pinctrl-0 = <&hdmitx_hpd_pins>, <&hdmitx_ddc_pins>; + pinctrl-names = "default"; +}; + +&hdmi_tx_tmds_port { + hdmi_tx_tmds_out: endpoint { + remote-endpoint = <&hdmi_connector_in>; + }; +}; + +&i2c3 { + status = "okay"; + pinctrl-0 = <&i2c3_sda_a_pins>, <&i2c3_sck_a_pins>; + pinctrl-names = "default"; +}; + +&ir { + status = "okay"; + pinctrl-0 = <&remote_input_ao_pins>; + pinctrl-names = "default"; +}; + +&pwm_AO_ab { + status = "okay"; + pinctrl-0 = <&pwm_ao_a_pins>; + pinctrl-names = "default"; + clocks = <&xtal>; + clock-names = "clkin0"; +}; + +&pwm_ef { + status = "okay"; + pinctrl-0 = <&pwm_e_pins>; + pinctrl-names = "default"; + clocks = <&xtal>; + clock-names = "clkin0"; +}; + +&saradc { + status = "okay"; + vref-supply = <&vddio_ao1v8>; +}; + +/* SDIO */ +&sd_emmc_a { + status = "okay"; + pinctrl-0 = <&sdio_pins>; + pinctrl-1 = <&sdio_clk_gate_pins>; + pinctrl-names = "default", "clk-gate"; + #address-cells = <1>; + #size-cells = <0>; + + bus-width = <4>; + cap-sd-highspeed; + sd-uhs-sdr50; + max-frequency = <100000000>; + + non-removable; + disable-wp; + + mmc-pwrseq = <&sdio_pwrseq>; + + vmmc-supply = <&vddao_3v3>; + vqmmc-supply = <&vddio_ao1v8>; + + brcmf: wifi@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + }; +}; + +/* SD card */ +&sd_emmc_b { + status = "okay"; + pinctrl-0 = <&sdcard_c_pins>; + pinctrl-1 = <&sdcard_clk_gate_c_pins>; + pinctrl-names = "default", "clk-gate"; + + bus-width = <4>; + cap-sd-highspeed; + max-frequency = <50000000>; + disable-wp; + + cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_LOW>; + vmmc-supply = <&vddao_3v3>; + vqmmc-supply = <&vddao_3v3>; +}; + +/* eMMC */ +&sd_emmc_c { + status = "okay"; + pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>; + pinctrl-1 = <&emmc_clk_gate_pins>; + pinctrl-names = "default", "clk-gate"; + + bus-width = <8>; + cap-mmc-highspeed; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + max-frequency = <200000000>; + non-removable; + disable-wp; + + mmc-pwrseq = <&emmc_pwrseq>; + vmmc-supply = <&vddao_3v3>; + vqmmc-supply = <&emmc_1v8>; +}; + +&uart_A { + status = "okay"; + pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>; + pinctrl-names = "default"; + uart-has-rtscts; + + bluetooth { + compatible = "brcm,bcm43438-bt"; + shutdown-gpios = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>; + max-speed = <2000000>; + clocks = <&wifi32k>; + clock-names = "lpo"; + vbat-supply = <&vddao_3v3>; + vddio-supply = <&vddio_ao1v8>; + }; +}; + +/* Exposed via the on-board USB to Serial FT232RL IC */ +&uart_AO { + status = "okay"; + pinctrl-0 = <&uart_ao_a_pins>; + pinctrl-names = "default"; +}; + +&usb { + status = "okay"; + dr_mode = "otg"; +}; diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi b/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi new file mode 100644 index 000000000000..7b4f6fdd28c7 --- /dev/null +++ b/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi @@ -0,0 +1,77 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 BayLibre, SAS + * Author: Neil Armstrong + */ + +#include "meson-g12-common.dtsi" +#include + +/ { + compatible = "amlogic,sm1"; + + cpus { + #address-cells = <0x2>; + #size-cells = <0x0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0 0x0>; + enable-method = "psci"; + next-level-cache = <&l2>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0 0x1>; + enable-method = "psci"; + next-level-cache = <&l2>; + }; + + cpu2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0 0x2>; + enable-method = "psci"; + next-level-cache = <&l2>; + }; + + cpu3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0 0x3>; + enable-method = "psci"; + next-level-cache = <&l2>; + }; + + l2: l2-cache0 { + compatible = "cache"; + }; + }; +}; + +&cecb_AO { + compatible = "amlogic,meson-sm1-ao-cec"; +}; + +&clk_msr { + compatible = "amlogic,meson-sm1-clk-measure"; +}; + +&pwrc_vpu { + compatible = "amlogic,meson-sm1-pwrc-vpu"; +}; + +&rti { + pwrc: power-controller { + compatible = "amlogic,meson-sm1-pwrc"; + #power-domain-cells = <1>; + amlogic,hhi-sysctrl = <&hhi>; + }; +}; + +&usb { + power-domains = <&pwrc PWRC_SM1_USB_ID>; +};