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Mon, 1 Jul 2019 13:11:49 +0000 (GMT) From: Lukasz Luba To: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org Cc: mturquette@baylibre.com, sboyd@kernel.org, b.zolnierkie@samsung.com, krzk@kernel.org, kgene@kernel.org, cw00.choi@samsung.com, kyungmin.park@samsung.com, m.szyprowski@samsung.com, s.nawrocki@samsung.com, myungjoo.ham@samsung.com, keescook@chromium.org, tony@atomide.com, jroedel@suse.de, treding@nvidia.com, digetx@gmail.com, gregkh@linuxfoundation.org, willy.mh.wolff.ml@gmail.com, Lukasz Luba Subject: [PATCH v11 1/9] dt-bindings: ddr: rename lpddr2 directory Date: Mon, 1 Jul 2019 15:11:30 +0200 Message-Id: <20190701131138.22666-2-l.luba@partner.samsung.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190701131138.22666-1-l.luba@partner.samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA0VSe0xNcRzvd889j66Ojhv6Spi72RTKa/Mzr5jHWWvLPGa0xqWzy+om9/RA ZjcpSsliSmopo9xqvW5P0pOolBSaykx5RCLXbUsW3e7Bf5/f5/H7fPbbjyGUfaQTcyQwWNAF qgNUlEJe+nC0dUkS5eS79KLJDhcm55P45Y8PJE5vaCVxznAfwpE38yl8uSlNhlsuaHFC32cC t7UV0PjJmUEav9I74+G41yTuqEylsCm+AeHktvsynNfQS+P2pi24OyKbwvWD50g8/qJQjqs7 PXH32FQ88ugt8nDkR8yJcv5rVxTNX9e3y/mKlF6aLzLEUHx1Wi7Nx0cOUXzt0D0Zf9FoQHxx czhvKpq7fco+xVo/IeBIqKBzX39AcdhQayCCzrLHc7NKCD2qmhKLbBngVoL5fRQZixSMkstG UP/+FmU9/ECQaRySFBOC/pHHsr+R2yl3JSELQUlhp/xf5E7SOzoWMQzFuUG54ZglMJ1LRnD9 406Lh+DKCPjS3YMsggO3CRoGByaxnFsAmT0Rkw0stwE6mh5Q1rZ5kFNQQ1iwLecBz8y9k/uA i2cg+kyLNGkzdEV3SAEH+NRopK3YGX5XpEseEfTxGciKT0FfQprkWQP1je2kZTTBuUB+pbuV 3ghZEdeQhQZuKnR9mWahiQmYWJpEWGkWzkcrre6FYIx7KhXNhKzcq9LlPPRkjEovehlBTP+A 7BKal/K/7AZCBuQohIhajSCuCBTC3ES1VgwJ1LgdOqotQhNfr3m80VyO7v86WIc4BqnsWH0P +CpJdah4QluHgCFU09nq7Fm+StZPfeKkoDu6XxcSIIh1aDYjVzmy4TZvfJScRh0s+AtCkKD7 q8oYWyc9UhQrnFIDzDHerl6h4zXmtEe7ORefbwl7qnzveJvKF/sYNAmG8zVzSuy9y0572fuv jvhQ4dm/a757qjebtzq4q1i3TQi6sKjt5ydjnCwqbK+yMHQj0vgl7nq5aUaMyWt0h50s7Ar7 3CZxzLnz+fJBel21zXciaeXWxQWlLrGrRqtWqeTiYfUyV0Inqv8AhDEx1XYDAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrGIsWRmVeSWpSXmKPExsVy+t/xu7rT2KRiDVpvsFlsnLGe1eL6l+es FvOPnGO1WP3xMaNF8+L1bBaTT81lsjjTnWvR//g1s8X58xvYLc42vWG3uNUgY/Gx5x6rxeVd c9gsPvceYbSYcX4fk8XaI3fZLS6ecrW43biCzeLwm3ZWi3/XNrJY7L/iZXH7N5/FtxOPGB3E Pb59ncTi8f5GK7vH7IaLLB47Z91l99i0qpPNY//cNewevc3v2DwOvtvD5NG3ZRWjx+bT1R6f N8kFcEfp2RTll5akKmTkF5fYKkUbWhjpGVpa6BmZWOoZGpvHWhmZKunb2aSk5mSWpRbp2yXo Zaw6uIq5oIW3Ys3yrcwNjHu5uxg5OSQETCSWzdrN2sXIxSEksJRR4vzh7YwQCTGJSfu2s0PY whJ/rnWxQRR9YpR49302UIKDg01AT2LHqkKQuIjAHEaJn13bGEEcZoGzzBK7V7xhAukWFnCS OPLmJdhUFgFViUV3GsHivAL2EpdPHWWD2CAvsXrDAWYQm1PAQeLS17tgcSGgmnWLbzBOYORb wMiwilEktbQ4Nz232EivODG3uDQvXS85P3cTIzAOtx37uWUHY9e74EOMAhyMSjy8GrckYoVY E8uKK3MPMUpwMCuJ8O5fIRkrxJuSWFmVWpQfX1Sak1p8iNEU6KiJzFKiyfnAFJFXEm9oamhu YWlobmxubGahJM7bIXAwRkggPbEkNTs1tSC1CKaPiYNTqoFxSmBForxVYdgi8edfoyczzlkp lGMtn7T0zplnGa+9lmavaD8uu9tJafexRyWfltTLKPZPEoz6ItykqBBi/E/RKeDHoWmhylXT whZuuMFs9Cvyd57D8bqT93YevBChznDosoXkouuTJ1nv2D3T9jXXo0XWp2YkyiUq//+0/HE/ w4Wgd+HnbrPVKLEUZyQaajEXFScCAPeoG9rZAgAA X-CMS-MailID: 20190701131150eucas1p158e1d6065775d48edabfc360cbb882b1 X-Msg-Generator: CA X-RootMTR: 20190701131150eucas1p158e1d6065775d48edabfc360cbb882b1 X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20190701131150eucas1p158e1d6065775d48edabfc360cbb882b1 References: <20190701131138.22666-1-l.luba@partner.samsung.com> Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Change directory name to be ready for new types of memories. Reviewed-by: Rob Herring Signed-off-by: Lukasz Luba --- .../devicetree/bindings/{lpddr2 => ddr}/lpddr2-timings.txt | 0 Documentation/devicetree/bindings/{lpddr2 => ddr}/lpddr2.txt | 2 +- 2 files changed, 1 insertion(+), 1 deletion(-) rename Documentation/devicetree/bindings/{lpddr2 => ddr}/lpddr2-timings.txt (100%) rename Documentation/devicetree/bindings/{lpddr2 => ddr}/lpddr2.txt (96%) diff --git a/Documentation/devicetree/bindings/lpddr2/lpddr2-timings.txt b/Documentation/devicetree/bindings/ddr/lpddr2-timings.txt similarity index 100% rename from Documentation/devicetree/bindings/lpddr2/lpddr2-timings.txt rename to Documentation/devicetree/bindings/ddr/lpddr2-timings.txt diff --git a/Documentation/devicetree/bindings/lpddr2/lpddr2.txt b/Documentation/devicetree/bindings/ddr/lpddr2.txt similarity index 96% rename from Documentation/devicetree/bindings/lpddr2/lpddr2.txt rename to Documentation/devicetree/bindings/ddr/lpddr2.txt index 58354a075e13..ddd40121e6f6 100644 --- a/Documentation/devicetree/bindings/lpddr2/lpddr2.txt +++ b/Documentation/devicetree/bindings/ddr/lpddr2.txt @@ -36,7 +36,7 @@ Child nodes: "lpddr2-timings" provides AC timing parameters of the device for a given speed-bin. The user may provide the timings for as many speed-bins as is required. Please see Documentation/devicetree/ - bindings/lpddr2/lpddr2-timings.txt for more information on "lpddr2-timings" + bindings/ddr/lpddr2-timings.txt for more information on "lpddr2-timings" Example: From patchwork Mon Jul 1 13:11:31 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lukasz Luba X-Patchwork-Id: 11025919 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 50F2F18E8 for ; Mon, 1 Jul 2019 13:12:37 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 30654285DA for ; Mon, 1 Jul 2019 13:12:37 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 2474D2875E; Mon, 1 Jul 2019 13:12:37 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 6BF41285DA for ; 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Mon, 1 Jul 2019 13:11:50 +0000 (GMT) From: Lukasz Luba To: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org Cc: mturquette@baylibre.com, sboyd@kernel.org, b.zolnierkie@samsung.com, krzk@kernel.org, kgene@kernel.org, cw00.choi@samsung.com, kyungmin.park@samsung.com, m.szyprowski@samsung.com, s.nawrocki@samsung.com, myungjoo.ham@samsung.com, keescook@chromium.org, tony@atomide.com, jroedel@suse.de, treding@nvidia.com, digetx@gmail.com, gregkh@linuxfoundation.org, willy.mh.wolff.ml@gmail.com, Lukasz Luba Subject: [PATCH v11 2/9] dt-bindings: ddr: add LPDDR3 memories Date: Mon, 1 Jul 2019 15:11:31 +0200 Message-Id: <20190701131138.22666-3-l.luba@partner.samsung.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190701131138.22666-1-l.luba@partner.samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA0VSeyxVcRzvd8/TrWuny/JLFu6iSHq331YrvbZTy9bW+iOxOupQy0X3oIf+ uHVR5KZodSOJiF3qInmVt8WShJJn7tBLyorbeirH0frv8/08vp/tuy+NKc2EPX04OIzXBHNB KlKOFz/63rLkKmnvt+xSzUpUYDAR6OX4WwKl1T8lUO7nQYB0t0wkSnqcKkNPzqtRwuAHDLW0 5FOo+cwIhbq1Duhz/CsCtZdfJ9GYvh4gQ0ulDN2p76NQ6+OtqOd0DonqRs4SaKKjAEdVz7ej np/W6GvjAPCyY79aEnF2tDOaYlO0rThbltxHsYXGWJKtSs2jWL3uE8nWfHooYy8UGQF7rymS HSucv3Omj3zdQT7ocASvWbp+v/yQ3tBEhha4Hv89/IvSgv75cYCmIbMKdk+cjANyWsnkAPhC Z6KkYXxyGM2QScMYgNHjWjIOWE0lvjcPkJKQDaAuY4gShanIQOlucS3JeMJS41GRtmUMAKa8 2yX6MaYEgx97eoEo2DDrYW9U4lQWZ1xgXXU+LmYVzAbY1Xlc6nKEufnVmIitGC/YZumb6oXM JRqOtBsxybQFmoeTcQnbwOGGIkrCDvBPWZpMwgLU6tOBhE/BwYTUac9aWNfQSoi9GOMGTeVL JXojvNt+m5QuZA07P84WaWwSJhZfxSRaAc/FKCX3IlgU/2y6aA7MzrsyvZyFhgT99D2TAKyq tOAXgWPy/7KbABiBHR8uqAN5YWUwf8xT4NRCeHCg54EQdSGY/LumiQZLKaj85V8LGBqoZim0 vdBPSXARwgl1LYA0prJVVOXM9VMqDnInTvKakH2a8CBeqAXzaFxlp4icYd6rZAK5MP4Iz4fy mn+qjLay1wKrTQE6H7Oz056KGVr/ELe6yMxGeZnTlcx034BvaaOuxOotsc07PBzzeu/Hfpib 77xtcWhH1+vGNYLZZoX1hazyEaLExZzq5GH5Ur1g7E3lun5b/FrF+ze6xHPeKEPD+XJtP9xu XH7l7lrsmBUz5B2VUmwi8+w2b461XdjDnHpQFKPChUPccndMI3B/ARVusy1zAwAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrKIsWRmVeSWpSXmKPExsVy+t/xu7rT2aRiDQ5eZLbYOGM9q8X1L89Z LeYfOcdqsfrjY0aL5sXr2Swmn5rLZHGmO9ei//FrZovz5zewW5xtesNucatBxuJjzz1Wi8u7 5rBZfO49wmgx4/w+Jou1R+6yW1w85Wpxu3EFm8XhN+2sFv+ubWSx2H/Fy+L2bz6LbyceMTqI e3z7OonF4/2NVnaP2Q0XWTx2zrrL7rFpVSebx/65a9g9epvfsXkcfLeHyaNvyypGj82nqz0+ b5IL4I7SsynKLy1JVcjILy6xVYo2tDDSM7S00DMysdQzNDaPtTIyVdK3s0lJzcksSy3St0vQ y+idcZqtYKNaxd9Xf9gbGO/LdTFyckgImEj8PPuIrYuRi0NIYCmjxLNz81khEmISk/ZtZ4ew hSX+XOuCKvrEKHH0/n7mLkYODjYBPYkdqwpB4iICcxglfnZtYwRxmAXOMkvsXvGGCaRbWMBO 4k7LJLBJLAKqEocPbGABaeYVsJe4eaMCYoG8xOoNB5hBbE4BB4lLX++ygdhCQCXrFt9gnMDI t4CRYRWjSGppcW56brGhXnFibnFpXrpecn7uJkZgFG479nPzDsZLG4MPMQpwMCrx8GrckogV Yk0sK67MPcQowcGsJMK7f4VkrBBvSmJlVWpRfnxRaU5q8SFGU6CbJjJLiSbnAxNEXkm8oamh uYWlobmxubGZhZI4b4fAwRghgfTEktTs1NSC1CKYPiYOTqkGxqm+h3OFa2U69ntI/MzYv6dl 3rTJjVx33N4runROszo8+0bP+q+6NRo79/tfOFr9Knids1PtubOTaj2Mmu4ebb3M/WT2/KcP 7nR5VQlcdzQI8T/Iv3DZTQHfLxO1s04cvsL9mnf50QvGWSGHC0XNfpx02b35/c3jC98l53J/ Zqpoby5wnbv+3mklluKMREMt5qLiRABO4naY2AIAAA== X-CMS-MailID: 20190701131151eucas1p2b9f0982ed2d285d212964d7857e6ed8a X-Msg-Generator: CA X-RootMTR: 20190701131151eucas1p2b9f0982ed2d285d212964d7857e6ed8a X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20190701131151eucas1p2b9f0982ed2d285d212964d7857e6ed8a References: <20190701131138.22666-1-l.luba@partner.samsung.com> Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Specifies the AC timing parameters of the LPDDR3 memory device. Reviewed-by: Rob Herring Signed-off-by: Lukasz Luba --- .../bindings/ddr/lpddr3-timings.txt | 58 +++++++++++ .../devicetree/bindings/ddr/lpddr3.txt | 97 +++++++++++++++++++ 2 files changed, 155 insertions(+) create mode 100644 Documentation/devicetree/bindings/ddr/lpddr3-timings.txt create mode 100644 Documentation/devicetree/bindings/ddr/lpddr3.txt diff --git a/Documentation/devicetree/bindings/ddr/lpddr3-timings.txt b/Documentation/devicetree/bindings/ddr/lpddr3-timings.txt new file mode 100644 index 000000000000..84705e50a3fd --- /dev/null +++ b/Documentation/devicetree/bindings/ddr/lpddr3-timings.txt @@ -0,0 +1,58 @@ +* AC timing parameters of LPDDR3 memories for a given speed-bin. + +The structures are based on LPDDR2 and extended where needed. + +Required properties: +- compatible : Should be "jedec,lpddr3-timings" +- min-freq : minimum DDR clock frequency for the speed-bin. Type is +- reg : maximum DDR clock frequency for the speed-bin. Type is + +Optional properties: + +The following properties represent AC timing parameters from the memory +data-sheet of the device for a given speed-bin. All these properties are +of type and the default unit is ps (pico seconds). +- tRFC +- tRRD +- tRPab +- tRPpb +- tRCD +- tRC +- tRAS +- tWTR +- tWR +- tRTP +- tW2W-C2C +- tR2R-C2C +- tFAW +- tXSR +- tXP +- tCKE +- tCKESR +- tMRD + +Example: + +timings_samsung_K3QF2F20DB_800mhz: lpddr3-timings@800000000 { + compatible = "jedec,lpddr3-timings"; + reg = <800000000>; /* workaround: it shows max-freq */ + min-freq = <100000000>; + tRFC = <65000>; + tRRD = <6000>; + tRPab = <12000>; + tRPpb = <12000>; + tRCD = <10000>; + tRC = <33750>; + tRAS = <23000>; + tWTR = <3750>; + tWR = <7500>; + tRTP = <3750>; + tW2W-C2C = <0>; + tR2R-C2C = <0>; + tFAW = <25000>; + tXSR = <70000>; + tXP = <3750>; + tCKE = <3750>; + tCKESR = <3750>; + tMRD = <7000>; +}; diff --git a/Documentation/devicetree/bindings/ddr/lpddr3.txt b/Documentation/devicetree/bindings/ddr/lpddr3.txt new file mode 100644 index 000000000000..3b2485b84b3f --- /dev/null +++ b/Documentation/devicetree/bindings/ddr/lpddr3.txt @@ -0,0 +1,97 @@ +* LPDDR3 SDRAM memories compliant to JEDEC JESD209-3C + +Required properties: +- compatible : Should be - "jedec,lpddr3" +- density : representing density in Mb (Mega bits) +- io-width : representing bus width. Possible values are 8, 16, 32, 64 +- #address-cells: Must be set to 1 +- #size-cells: Must be set to 0 + +Optional properties: + +The following optional properties represent the minimum value of some AC +timing parameters of the DDR device in terms of number of clock cycles. +These values shall be obtained from the device data-sheet. +- tRFC-min-tck +- tRRD-min-tck +- tRPab-min-tck +- tRPpb-min-tck +- tRCD-min-tck +- tRC-min-tck +- tRAS-min-tck +- tWTR-min-tck +- tWR-min-tck +- tRTP-min-tck +- tW2W-C2C-min-tck +- tR2R-C2C-min-tck +- tWL-min-tck +- tDQSCK-min-tck +- tRL-min-tck +- tFAW-min-tck +- tXSR-min-tck +- tXP-min-tck +- tCKE-min-tck +- tCKESR-min-tck +- tMRD-min-tck + +Child nodes: +- The lpddr3 node may have one or more child nodes of type "lpddr3-timings". + "lpddr3-timings" provides AC timing parameters of the device for + a given speed-bin. Please see Documentation/devicetree/ + bindings/ddr/lpddr3-timings.txt for more information on "lpddr3-timings" + +Example: + +samsung_K3QF2F20DB: lpddr3 { + compatible = "Samsung,K3QF2F20DB", "jedec,lpddr3"; + density = <16384>; + io-width = <32>; + #address-cells = <1>; + #size-cells = <0>; + + tRFC-min-tck = <17>; + tRRD-min-tck = <2>; + tRPab-min-tck = <2>; + tRPpb-min-tck = <2>; + tRCD-min-tck = <3>; + tRC-min-tck = <6>; + tRAS-min-tck = <5>; + tWTR-min-tck = <2>; + tWR-min-tck = <7>; + tRTP-min-tck = <2>; + tW2W-C2C-min-tck = <0>; + tR2R-C2C-min-tck = <0>; + tWL-min-tck = <8>; + tDQSCK-min-tck = <5>; + tRL-min-tck = <14>; + tFAW-min-tck = <5>; + tXSR-min-tck = <12>; + tXP-min-tck = <2>; + tCKE-min-tck = <2>; + tCKESR-min-tck = <2>; + tMRD-min-tck = <5>; + + timings_samsung_K3QF2F20DB_800mhz: lpddr3-timings@800000000 { + compatible = "jedec,lpddr3-timings"; + reg = <800000000>; /* workaround: it shows max-freq */ + min-freq = <100000000>; + tRFC = <65000>; + tRRD = <6000>; + tRPab = <12000>; + tRPpb = <12000>; + tRCD = <10000>; + tRC = <33750>; + tRAS = <23000>; + tWTR = <3750>; + tWR = <7500>; + tRTP = <3750>; + tW2W-C2C = <0>; + tR2R-C2C = <0>; + tFAW = <25000>; + tXSR = <70000>; + tXP = <3750>; + tCKE = <3750>; + tCKESR = <3750>; + tMRD = <7000>; + }; +} From patchwork Mon Jul 1 13:11:32 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lukasz Luba X-Patchwork-Id: 11025927 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 97EF813B1 for ; Mon, 1 Jul 2019 13:12:42 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 8B8992873C for ; Mon, 1 Jul 2019 13:12:42 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 7FE7B28754; Mon, 1 Jul 2019 13:12:42 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id B950928715 for ; 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Mon, 1 Jul 2019 13:11:51 +0000 (GMT) From: Lukasz Luba To: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org Cc: mturquette@baylibre.com, sboyd@kernel.org, b.zolnierkie@samsung.com, krzk@kernel.org, kgene@kernel.org, cw00.choi@samsung.com, kyungmin.park@samsung.com, m.szyprowski@samsung.com, s.nawrocki@samsung.com, myungjoo.ham@samsung.com, keescook@chromium.org, tony@atomide.com, jroedel@suse.de, treding@nvidia.com, digetx@gmail.com, gregkh@linuxfoundation.org, willy.mh.wolff.ml@gmail.com, Lukasz Luba Subject: [PATCH v11 3/9] drivers: memory: extend of_memory by LPDDR3 support Date: Mon, 1 Jul 2019 15:11:32 +0200 Message-Id: <20190701131138.22666-4-l.luba@partner.samsung.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190701131138.22666-1-l.luba@partner.samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA0VSe0hTURzu7D59zG5L9KQ9YBGUkGUYHCjMQuFmIpGSPVi18jarzdmuj8yE mZnls7SHaKJh5JyWtkw3k8wHWWqaFb61bERSpvgMUSrnnfXf9/se5/udw6ExiZlwoc+ERXCa MLlSStrila9m2zZnky6yrVm/tqMn2WUE6pr6RqD8xjYClYybAUooLCNRVnOeCLWmqFCG+QeG 2tvLKfT28giFerWr0XjqIIE+VN8j0WRaI0DZ7S9E6FHjAIU6mn1RX7yORA0jSQT63fkER7Uf /VDfnAOaef0FeDuzM9OZODvWnUixudoOnDXlDFCsQX+dZGvzSik2LWGUZOtGa0RseoUesE9b YtlJw9r9dkdsd4ZwyjNRnGaL1wnb0FtdZiI8cd+Fz+UdpBbovZKBDQ0ZT1hdZKKSgS0tYXQA JiY/xoVhCsCetglMGCYBNKUaRUuRyqp0kSAUAagfnCX/RW5eubUw0DTJuEOj/rwl4MhkA5g7 HGjxYEwVBn/29QOLsJLxh/qnA5QF48wGWNZZhFmwmNkFC559ooS2dbCk/OUib8N4w/fTA4tl kEmjYUnNPC6YfODttjprYCX83lRhxavhH1O+dW0eatPuAwFfguaMPKtnB2xo6iAsS2PMJlhW vUWgd8PhMcst6QXsALt/rrDQ2ALMrLyLCbQYXrsqEdwbYUXqO2uREywqvWM9nIWG5HwgPE8W gL13xogbYF3O/7ICAPTAmYvkVQqO3xbGRbvzchUfGaZwP6VWGcDC12v53TRlBNXzJ+sBQwOp vVjbD2USQh7Fx6jqAaQxqaO4VrdKJhGHyGMuchr1cU2kkuPrgSuNS53Fscs+H5UwCnkEd47j wjnNkiqibVy0QPZgzcR1xd7g5V41b2rclGb+yCVqqNjN9XXdiaFYXx043G+X+sjx6/MA9TAK cBdj/geOB0kiv6fI5g+tt+/1PRhca2xVlAbOqDxOj3a/aKBxZXTSlJoNkDzc40BinkHHhntm HeMKi5dl/VD72Y8nxSmKAxiDzifCKd5mLgY/K8X5ULmHG6bh5X8BkSkRq3YDAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrGIsWRmVeSWpSXmKPExsVy+t/xu7oz2KRiDd6eY7LYOGM9q8X1L89Z LeYfOcdqsfrjY0aL5sXr2Swmn5rLZHGmO9ei//FrZovz5zewW5xtesNucatBxuJjzz1Wi8u7 5rBZfO49wmgx4/w+Jou1R+6yW1w85Wpxu3EFm8XhN+2sFv+ubWSx2H/Fy+L2bz6LbyceMTqI e3z7OonF4/2NVnaP2Q0XWTx2zrrL7rFpVSebx/65a9g9epvfsXkcfLeHyaNvyypGj82nqz0+ b5IL4I7SsynKLy1JVcjILy6xVYo2tDDSM7S00DMysdQzNDaPtTIyVdK3s0lJzcksSy3St0vQ y5hy/TFrQat3xYMNF9kaGFfZdTFyckgImEhs297H1MXIxSEksJRR4uyUwywQCTGJSfu2s0PY whJ/rnWxQRR9YpT4ums5UBEHB5uAnsSOVYUgcRGBOYwSP7u2MYI4zAJnmSV2r3jDBNItLOAj sWrzXbBJLAKqEuuvLWcGsXkF7CUWbL0PtUFeYvWGA2BxTgEHiUtf77KB2EJANesW32CcwMi3 gJFhFaNIamlxbnpusZFecWJucWleul5yfu4mRmAcbjv2c8sOxq53wYcYBTgYlXh4NW5JxAqx JpYVV+YeYpTgYFYS4d2/QjJWiDclsbIqtSg/vqg0J7X4EKMp0FETmaVEk/OBKSKvJN7Q1NDc wtLQ3Njc2MxCSZy3Q+BgjJBAemJJanZqakFqEUwfEwenVANjnMMULX6V4KrUnMB7DqtXv3ol ofv5vPN00cSPl5/3djcuCdirvvdB72PtwDn/S/MYN69Vso/QFJoX6CIXMStJjmNbxPNXfCvz Hy8WXiz4/8hdgQkfV0fnFPy3lfuZldncwdAuLvAkKlc4+uDCyMSm5mV/PP2Frtw0/d09rWEC Y9W0d/um5zYrsRRnJBpqMRcVJwIAU/C9H9kCAAA= X-CMS-MailID: 20190701131152eucas1p2c5ac5f1611fd07e3b7a4ad289abe3e81 X-Msg-Generator: CA X-RootMTR: 20190701131152eucas1p2c5ac5f1611fd07e3b7a4ad289abe3e81 X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20190701131152eucas1p2c5ac5f1611fd07e3b7a4ad289abe3e81 References: <20190701131138.22666-1-l.luba@partner.samsung.com> Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The patch adds AC timings information needed to support LPDDR3 and memory controllers. The structure is used in of_memory and currently in Exynos 5422 DMC. Add parsing data needed for LPDDR3 support. It is currently used in Exynos5422 Dynamic Memory Controller. Acked-by: Krzysztof Kozlowski Signed-off-by: Lukasz Luba --- drivers/memory/of_memory.c | 149 +++++++++++++++++++++++++++++++++++++ drivers/memory/of_memory.h | 18 +++++ include/memory/jedec_ddr.h | 61 +++++++++++++++ 3 files changed, 228 insertions(+) diff --git a/drivers/memory/of_memory.c b/drivers/memory/of_memory.c index 2f5ed7366eec..3227903edae4 100644 --- a/drivers/memory/of_memory.c +++ b/drivers/memory/of_memory.c @@ -2,6 +2,7 @@ * OpenFirmware helpers for memory drivers * * Copyright (C) 2012 Texas Instruments, Inc. + * Copyright (C) 2019 Samsung Electronics Co., Ltd. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -152,3 +153,151 @@ const struct lpddr2_timings *of_get_ddr_timings(struct device_node *np_ddr, return lpddr2_jedec_timings; } EXPORT_SYMBOL(of_get_ddr_timings); + +/** + * of_lpddr3_get_min_tck() - extract min timing values for lpddr3 + * @np: pointer to ddr device tree node + * @device: device requesting for min timing values + * + * Populates the lpddr3_min_tck structure by extracting data + * from device tree node. Returns a pointer to the populated + * structure. If any error in populating the structure, returns NULL. + */ +const struct lpddr3_min_tck *of_lpddr3_get_min_tck(struct device_node *np, + struct device *dev) +{ + int ret = 0; + struct lpddr3_min_tck *min; + + min = devm_kzalloc(dev, sizeof(*min), GFP_KERNEL); + if (!min) + goto default_min_tck; + + ret |= of_property_read_u32(np, "tRFC-min-tck", &min->tRFC); + ret |= of_property_read_u32(np, "tRRD-min-tck", &min->tRRD); + ret |= of_property_read_u32(np, "tRPab-min-tck", &min->tRPab); + ret |= of_property_read_u32(np, "tRPpb-min-tck", &min->tRPpb); + ret |= of_property_read_u32(np, "tRCD-min-tck", &min->tRCD); + ret |= of_property_read_u32(np, "tRC-min-tck", &min->tRC); + ret |= of_property_read_u32(np, "tRAS-min-tck", &min->tRAS); + ret |= of_property_read_u32(np, "tWTR-min-tck", &min->tWTR); + ret |= of_property_read_u32(np, "tWR-min-tck", &min->tWR); + ret |= of_property_read_u32(np, "tRTP-min-tck", &min->tRTP); + ret |= of_property_read_u32(np, "tW2W-C2C-min-tck", &min->tW2W_C2C); + ret |= of_property_read_u32(np, "tR2R-C2C-min-tck", &min->tR2R_C2C); + ret |= of_property_read_u32(np, "tWL-min-tck", &min->tWL); + ret |= of_property_read_u32(np, "tDQSCK-min-tck", &min->tDQSCK); + ret |= of_property_read_u32(np, "tRL-min-tck", &min->tRL); + ret |= of_property_read_u32(np, "tFAW-min-tck", &min->tFAW); + ret |= of_property_read_u32(np, "tXSR-min-tck", &min->tXSR); + ret |= of_property_read_u32(np, "tXP-min-tck", &min->tXP); + ret |= of_property_read_u32(np, "tCKE-min-tck", &min->tCKE); + ret |= of_property_read_u32(np, "tCKESR-min-tck", &min->tCKESR); + ret |= of_property_read_u32(np, "tMRD-min-tck", &min->tMRD); + + if (ret) { + dev_warn(dev, "%s: errors while parsing min-tck values\n", + __func__); + devm_kfree(dev, min); + goto default_min_tck; + } + + return min; + +default_min_tck: + dev_warn(dev, "%s: using default min-tck values\n", __func__); + return NULL; +} +EXPORT_SYMBOL(of_lpddr3_get_min_tck); + +static int of_lpddr3_do_get_timings(struct device_node *np, + struct lpddr3_timings *tim) +{ + int ret; + + /* The 'reg' param required since DT has changed, used as 'max-freq' */ + ret = of_property_read_u32(np, "reg", &tim->max_freq); + ret |= of_property_read_u32(np, "min-freq", &tim->min_freq); + ret |= of_property_read_u32(np, "tRFC", &tim->tRFC); + ret |= of_property_read_u32(np, "tRRD", &tim->tRRD); + ret |= of_property_read_u32(np, "tRPab", &tim->tRPab); + ret |= of_property_read_u32(np, "tRPpb", &tim->tRPpb); + ret |= of_property_read_u32(np, "tRCD", &tim->tRCD); + ret |= of_property_read_u32(np, "tRC", &tim->tRC); + ret |= of_property_read_u32(np, "tRAS", &tim->tRAS); + ret |= of_property_read_u32(np, "tWTR", &tim->tWTR); + ret |= of_property_read_u32(np, "tWR", &tim->tWR); + ret |= of_property_read_u32(np, "tRTP", &tim->tRTP); + ret |= of_property_read_u32(np, "tW2W-C2C", &tim->tW2W_C2C); + ret |= of_property_read_u32(np, "tR2R-C2C", &tim->tR2R_C2C); + ret |= of_property_read_u32(np, "tFAW", &tim->tFAW); + ret |= of_property_read_u32(np, "tXSR", &tim->tXSR); + ret |= of_property_read_u32(np, "tXP", &tim->tXP); + ret |= of_property_read_u32(np, "tCKE", &tim->tCKE); + ret |= of_property_read_u32(np, "tCKESR", &tim->tCKESR); + ret |= of_property_read_u32(np, "tMRD", &tim->tMRD); + + return ret; +} + +/** + * of_lpddr3_get_ddr_timings() - extracts the lpddr3 timings and updates no of + * frequencies available. + * @np_ddr: Pointer to ddr device tree node + * @dev: Device requesting for ddr timings + * @device_type: Type of ddr + * @nr_frequencies: No of frequencies available for ddr + * (updated by this function) + * + * Populates lpddr3_timings structure by extracting data from device + * tree node. Returns pointer to populated structure. If any error + * while populating, returns NULL. + */ +const struct lpddr3_timings +*of_lpddr3_get_ddr_timings(struct device_node *np_ddr, struct device *dev, + u32 device_type, u32 *nr_frequencies) +{ + struct lpddr3_timings *timings = NULL; + u32 arr_sz = 0, i = 0; + struct device_node *np_tim; + char *tim_compat = NULL; + + switch (device_type) { + case DDR_TYPE_LPDDR3: + tim_compat = "jedec,lpddr3-timings"; + break; + default: + dev_warn(dev, "%s: un-supported memory type\n", __func__); + } + + for_each_child_of_node(np_ddr, np_tim) + if (of_device_is_compatible(np_tim, tim_compat)) + arr_sz++; + + if (arr_sz) + timings = devm_kcalloc(dev, arr_sz, sizeof(*timings), + GFP_KERNEL); + + if (!timings) + goto default_timings; + + for_each_child_of_node(np_ddr, np_tim) { + if (of_device_is_compatible(np_tim, tim_compat)) { + if (of_lpddr3_do_get_timings(np_tim, &timings[i])) { + devm_kfree(dev, timings); + goto default_timings; + } + i++; + } + } + + *nr_frequencies = arr_sz; + + return timings; + +default_timings: + dev_warn(dev, "%s: using default timings\n", __func__); + *nr_frequencies = 0; + return NULL; +} +EXPORT_SYMBOL(of_lpddr3_get_ddr_timings); diff --git a/drivers/memory/of_memory.h b/drivers/memory/of_memory.h index ef2514f553d3..b532044830f4 100644 --- a/drivers/memory/of_memory.h +++ b/drivers/memory/of_memory.h @@ -18,6 +18,11 @@ extern const struct lpddr2_min_tck *of_get_min_tck(struct device_node *np, extern const struct lpddr2_timings *of_get_ddr_timings(struct device_node *np_ddr, struct device *dev, u32 device_type, u32 *nr_frequencies); +extern const struct lpddr3_min_tck + *of_lpddr3_get_min_tck(struct device_node *np, struct device *dev); +extern const struct lpddr3_timings + *of_lpddr3_get_ddr_timings(struct device_node *np_ddr, + struct device *dev, u32 device_type, u32 *nr_frequencies); #else static inline const struct lpddr2_min_tck *of_get_min_tck(struct device_node *np, struct device *dev) @@ -31,6 +36,19 @@ static inline const struct lpddr2_timings { return NULL; } + +static inline const struct lpddr3_min_tck + *of_lpddr3_get_min_tck(struct device_node *np, struct device *dev) +{ + return NULL; +} + +static inline const struct lpddr3_timings + *of_lpddr3_get_ddr_timings(struct device_node *np_ddr, + struct device *dev, u32 device_type, u32 *nr_frequencies) +{ + return NULL; +} #endif /* CONFIG_OF && CONFIG_DDR */ #endif /* __LINUX_MEMORY_OF_REG_ */ diff --git a/include/memory/jedec_ddr.h b/include/memory/jedec_ddr.h index ddad0f870e5d..675670a8c597 100644 --- a/include/memory/jedec_ddr.h +++ b/include/memory/jedec_ddr.h @@ -32,6 +32,7 @@ #define DDR_TYPE_LPDDR2_S4 3 #define DDR_TYPE_LPDDR2_S2 4 #define DDR_TYPE_LPDDR2_NVM 5 +#define DDR_TYPE_LPDDR3 6 /* DDR IO width */ #define DDR_IO_WIDTH_4 1 @@ -172,4 +173,64 @@ extern const struct lpddr2_timings lpddr2_jedec_timings[NUM_DDR_TIMING_TABLE_ENTRIES]; extern const struct lpddr2_min_tck lpddr2_jedec_min_tck; +/* + * Structure for timings for LPDDR3 based on LPDDR2 plus additional fields. + * All parameters are in pico seconds(ps) unless explicitly indicated + * with a suffix like tRAS_max_ns below + */ +struct lpddr3_timings { + u32 max_freq; + u32 min_freq; + u32 tRFC; + u32 tRRD; + u32 tRPab; + u32 tRPpb; + u32 tRCD; + u32 tRC; + u32 tRAS; + u32 tWTR; + u32 tWR; + u32 tRTP; + u32 tW2W_C2C; + u32 tR2R_C2C; + u32 tWL; + u32 tDQSCK; + u32 tRL; + u32 tFAW; + u32 tXSR; + u32 tXP; + u32 tCKE; + u32 tCKESR; + u32 tMRD; +}; + +/* + * Min value for some parameters in terms of number of tCK cycles(nCK) + * Please set to zero parameters that are not valid for a given memory + * type + */ +struct lpddr3_min_tck { + u32 tRFC; + u32 tRRD; + u32 tRPab; + u32 tRPpb; + u32 tRCD; + u32 tRC; + u32 tRAS; + u32 tWTR; + u32 tWR; + u32 tRTP; + u32 tW2W_C2C; + u32 tR2R_C2C; + u32 tWL; + u32 tDQSCK; + u32 tRL; + u32 tFAW; + u32 tXSR; + u32 tXP; + u32 tCKE; + u32 tCKESR; + u32 tMRD; +}; + #endif /* __LINUX_JEDEC_DDR_H */ From patchwork Mon Jul 1 13:11:33 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lukasz Luba X-Patchwork-Id: 11025883 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 1E058746 for ; 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Mon, 1 Jul 2019 13:11:52 +0000 (GMT) From: Lukasz Luba To: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org Cc: mturquette@baylibre.com, sboyd@kernel.org, b.zolnierkie@samsung.com, krzk@kernel.org, kgene@kernel.org, cw00.choi@samsung.com, kyungmin.park@samsung.com, m.szyprowski@samsung.com, s.nawrocki@samsung.com, myungjoo.ham@samsung.com, keescook@chromium.org, tony@atomide.com, jroedel@suse.de, treding@nvidia.com, digetx@gmail.com, gregkh@linuxfoundation.org, willy.mh.wolff.ml@gmail.com, Lukasz Luba Subject: [PATCH v11 4/9] dt-bindings: memory-controllers: add Exynos5422 DMC device description Date: Mon, 1 Jul 2019 15:11:33 +0200 Message-Id: <20190701131138.22666-5-l.luba@partner.samsung.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190701131138.22666-1-l.luba@partner.samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA0WSaUwTURSFfZ2lA1IdC5EnopBGEpWwRX88g1EUMeNuYoJGJTLCBIi0aIe6 JxaIyC4B1II0gGLEFlLAqiCEpUVZqiIqLiDEiAkuBUUEY8SFcar+O+/e79xzc/MoTD5IeFBx qkROrWLjFaQzfvPut26/QtIjItCYhlCNzkSgZ1+GCVTS9oBAxrEhgFIum0iU36WXoHuZSnR2 6AOGururpeh+sl2K+rSeaCxrkECPbxeTaDy7DSBdd5MEVbUNSFFPVxjqT6ogkdV+hkA/n9bg qPnJRtT/fRaa7HgNQtyZyYk8nPn4/LSUuajtwZn6ogEpU2tIJ5lmfaWUyU4ZJZnW0UYJk2M2 AOa67QQzXrtw+8zdziujufi4w5w6YFWkc6w5KfpgjtfR+mu9hBYMz8sAFAXp5bChjskATpSc rgCwZVKVAZyn9RcAK1MaCPExDmBSfodUoARDr6kWFxtXATSNNpL/LMnDLzBhLEn7wzrDIcHg RusAvPh2h8Bg9C0MjvS/BALjSrNwyLpXkDjtA78aTwq4jF4NizsNjiwvaKxuwQTtRIfARxMD f6IgnU3BfPsIEKF10PI0lxS1K3zfbnaYPeGv+hKJqHmozS5z8Cfh0Fm9gwmG1vYeQtgBo5dA 0+0AsbwG5nVacPFAs+DzkTlCGZuWeTcvYGJZBtNS5SK9GJqzHjqC5sKrlecdwxlYYLMD8Tj5 AKb2ppO5wKvof1gpAAbgzml4ZQzHL1NxR/x5VslrVDH+UQnKWjD962w/2yfqQNPUfgugKaBw kWlfwgg5wR7mjyktAFKYwk3WXDEvQi6LZo8d59QJ+9SaeI63gPkUrnCXnZjxao+cjmETuQMc d5BT/+1KKCcPLQj3cOFLw6+UKx82jCFb5JFQPq0v6p1LyXvdjZ15vuUXYkL0pTxahBK2jfho 2LJG+dY7p3LX+wXbQk8fqnq1IPBc2Ir9rde4tVN8s2ITferzmy0uPzRmb/9dn4ILOyKswd+C CjIvbejZPJvwHlMYY6s1R61PPPU+urjXKXa97+AWBc7HskFLMTXP/gZzYVR3cQMAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrCIsWRmVeSWpSXmKPExsVy+t/xu7oz2KRiDaZctLHYOGM9q8X1L89Z LeYfOcdqsfrjY0aL5sXr2Swmn5rLZHGmO9ei//FrZovz5zewW5xtesNucatBxuJjzz1Wi8u7 5rBZfO49wmgx4/w+Jou1R+6yW1w85Wpxu3EFm8XhN+2sFv+ubWSx2H/Fy+L2bz6LbyceMTqI e3z7OonF4/2NVnaP2Q0XWTx2zrrL7rFpVSebx/65a9g9epvfsXkcfLeHyaNvyypGj82nqz0+ b5IL4I7SsynKLy1JVcjILy6xVYo2tDDSM7S00DMysdQzNDaPtTIyVdK3s0lJzcksSy3St0vQ y9jSmFLQJ1+xc+VV1gbG55JdjJwcEgImElfXb2LpYuTiEBJYyihx6d1RdoiEmMSkfduhbGGJ P9e62CCKPjFKfFl0i7WLkYODTUBPYseqQpC4iMAcRomfXdsYQRxmgbPMErtXvGEC6RYWiJfo /r6PBaSBRUBV4vvqGpAwr4C9xJyTq6AWyEus3nCAGcTmFHCQuPT1LhuILQRUs27xDcYJjHwL GBlWMYqklhbnpucWG+oVJ+YWl+al6yXn525iBMbgtmM/N+9gvLQx+BCjAAejEg+vxi2JWCHW xLLiytxDjBIczEoivPtXSMYK8aYkVlalFuXHF5XmpBYfYjQFumkis5Rocj4wPeSVxBuaGppb WBqaG5sbm1koifN2CByMERJITyxJzU5NLUgtgulj4uCUamCMe3xB8OwK1brgY5fv+L0TVF82 bapDj7+Kyfo8lyZLhoO7FnO+i8kuK3J92SzBX/Pw4tuXgZLX0suu/ozz5OW0q5znJHnf7O37 kEfSjEGdC8UFeIP3nk69toLN51vNlqJPFpyKl7X1DBz3fHzF1vJocu7yTW+2BQv66Xnf+Lcu 5PxMq9fC9o5KLMUZiYZazEXFiQDR1YUA1wIAAA== X-CMS-MailID: 20190701131153eucas1p100567483c17b63e4707c21c63f780437 X-Msg-Generator: CA X-RootMTR: 20190701131153eucas1p100567483c17b63e4707c21c63f780437 X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20190701131153eucas1p100567483c17b63e4707c21c63f780437 References: <20190701131138.22666-1-l.luba@partner.samsung.com> Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The patch adds description for DT binding for a new Exynos5422 Dynamic Memory Controller device. Acked-by: Krzysztof Kozlowski Reviewed-by: Rob Herring Signed-off-by: Lukasz Luba --- .../memory-controllers/exynos5422-dmc.txt | 73 +++++++++++++++++++ 1 file changed, 73 insertions(+) create mode 100644 Documentation/devicetree/bindings/memory-controllers/exynos5422-dmc.txt diff --git a/Documentation/devicetree/bindings/memory-controllers/exynos5422-dmc.txt b/Documentation/devicetree/bindings/memory-controllers/exynos5422-dmc.txt new file mode 100644 index 000000000000..02aeb3b5a820 --- /dev/null +++ b/Documentation/devicetree/bindings/memory-controllers/exynos5422-dmc.txt @@ -0,0 +1,73 @@ +* Exynos5422 frequency and voltage scaling for Dynamic Memory Controller device + +The Samsung Exynos5422 SoC has DMC (Dynamic Memory Controller) to which the DRAM +memory chips are connected. The driver is to monitor the controller in runtime +and switch frequency and voltage. To monitor the usage of the controller in +runtime, the driver uses the PPMU (Platform Performance Monitoring Unit), which +is able to measure the current load of the memory. +When 'userspace' governor is used for the driver, an application is able to +switch the DMC and memory frequency. + +Required properties for DMC device for Exynos5422: +- compatible: Should be "samsung,exynos5422-dmc". +- clocks : list of clock specifiers, must contain an entry for each + required entry in clock-names for CLK_FOUT_SPLL, CLK_MOUT_SCLK_SPLL, + CLK_FF_DOUT_SPLL2, CLK_FOUT_BPLL, CLK_MOUT_BPLL, CLK_SCLK_BPLL, + CLK_MOUT_MX_MSPLL_CCORE, CLK_MOUT_MX_MSPLL_CCORE_PHY, CLK_MOUT_MCLK_CDREX, +- clock-names : should include "fout_spll", "mout_sclk_spll", "ff_dout_spll2", + "fout_bpll", "mout_bpll", "sclk_bpll", "mout_mx_mspll_ccore", + "mout_mclk_cdrex" entries +- devfreq-events : phandles for PPMU devices connected to this DMC. +- vdd-supply : phandle for voltage regulator which is connected. +- reg : registers of two CDREX controllers. +- operating-points-v2 : phandle for OPPs described in v2 definition. +- device-handle : phandle of the connected DRAM memory device. For more + information please refer to documentation file: + Documentation/devicetree/bindings/ddr/lpddr3.txt +- devfreq-events : phandles of the PPMU events used by the controller. +- samsung,syscon-clk : phandle of the clock register set used by the controller, + these registers are used for enabling a 'pause' feature and are not + exposed by clock framework but they must be used in a safe way. + The register offsets are in the driver code and specyfic for this SoC + type. + +Example: + + ppmu_dmc0_0: ppmu@10d00000 { + compatible = "samsung,exynos-ppmu"; + reg = <0x10d00000 0x2000>; + clocks = <&clock CLK_PCLK_PPMU_DREX0_0>; + clock-names = "ppmu"; + events { + ppmu_event_dmc0_0: ppmu-event3-dmc0_0 { + event-name = "ppmu-event3-dmc0_0"; + }; + }; + }; + + dmc: memory-controller@10c20000 { + compatible = "samsung,exynos5422-dmc"; + reg = <0x10c20000 0x100>, <0x10c30000 0x100>, + clocks = <&clock CLK_FOUT_SPLL>, + <&clock CLK_MOUT_SCLK_SPLL>, + <&clock CLK_FF_DOUT_SPLL2>, + <&clock CLK_FOUT_BPLL>, + <&clock CLK_MOUT_BPLL>, + <&clock CLK_SCLK_BPLL>, + <&clock CLK_MOUT_MX_MSPLL_CCORE>, + <&clock CLK_MOUT_MCLK_CDREX>, + clock-names = "fout_spll", + "mout_sclk_spll", + "ff_dout_spll2", + "fout_bpll", + "mout_bpll", + "sclk_bpll", + "mout_mx_mspll_ccore", + "mout_mclk_cdrex", + operating-points-v2 = <&dmc_opp_table>; + devfreq-events = <&ppmu_event3_dmc0_0>, <&ppmu_event3_dmc0_1>, + <&ppmu_event3_dmc1_0>, <&ppmu_event3_dmc1_1>; + device-handle = <&samsung_K3QF2F20DB>; + vdd-supply = <&buck1_reg>; + samsung,syscon-clk = <&clock>; + }; From patchwork Mon Jul 1 13:11:34 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lukasz Luba X-Patchwork-Id: 11025911 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 93C96746 for ; Mon, 1 Jul 2019 13:12:26 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 7DE6D285B9 for ; Mon, 1 Jul 2019 13:12:26 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 6E317208C2; Mon, 1 Jul 2019 13:12:26 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 1B9B0285B9 for ; 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Mon, 1 Jul 2019 13:11:52 +0000 (GMT) From: Lukasz Luba To: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org Cc: mturquette@baylibre.com, sboyd@kernel.org, b.zolnierkie@samsung.com, krzk@kernel.org, kgene@kernel.org, cw00.choi@samsung.com, kyungmin.park@samsung.com, m.szyprowski@samsung.com, s.nawrocki@samsung.com, myungjoo.ham@samsung.com, keescook@chromium.org, tony@atomide.com, jroedel@suse.de, treding@nvidia.com, digetx@gmail.com, gregkh@linuxfoundation.org, willy.mh.wolff.ml@gmail.com, Lukasz Luba Subject: [PATCH v11 5/9] drivers: memory: add DMC driver for Exynos5422 Date: Mon, 1 Jul 2019 15:11:34 +0200 Message-Id: <20190701131138.22666-6-l.luba@partner.samsung.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190701131138.22666-1-l.luba@partner.samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA0VSa1BMYRj27bnsqaw5tqZeacTGuIzC6Mdn3IfGGb8MP8xkmiyOMtote1SK GZtUpBXtTJpVklLpMlvbDiqK2qTIFiap7TKaRigmXVxK2D1r/Hue532e933mm48h5EOUN3NM fZLXqJURCtqVvPvkh9XfQHuHrJ3uXIwrs4wUfjPxnsK5lhcULh0bRDgx30hjfWuOBD+/pMLp g58IbLVWSHHbuREp7tb64LG0Pgq/qsmm8bjOgnCWtU6Cyy29UtzRGoR7Eopp3DiSQuHZzkoS 17/ejXum5+Gpp+/QNi9uajKD5L50JUm569oOkqs29Eo5U8lFmqvPKZNyusTPNPf48wMJd9lc griqZ6e5cdOiPW7BrpuO8BHHYnjNmi0HXcNtpUY6qr1Fcio7aYDUooo0SSpyYYANhPqvv6Sp yJWRs8UITMWDpEgmEKRfm6JFMo6g32gnYsQ4nOB0FSHIbJn4H6mqTKBSEcPQbADcLzlhD3iw WQiuD++zewj2HgGjPTZkH7izu+CX5aqjCMkug8ymLIcuY7fC5LkmZ0FfKK14RNixC7sNXk72 OioBq2NgKEErFU07obC2jRKxO3xsNjt1H/hdnetcJIBWl4dEfAYG03Ocno3Q2NzhKE2wK8FY s0aUt0NBe61DBnYedI3Ot8vEX5hx9xohyjK4kCwX3SvAnNbuPOQJRWWZzuUc1J23OZ9HjyCp po++gnwN/4/dRKgEefHRgiqMF9ar+dgAQakSotVhAYcjVSb09/M9m22evI/qZg41IJZBirky rQ1C5JQyRohTNSBgCIWHrL54QYhcdkQZF89rIkM10RG80IAWMqTCS3Z6zsABORumPMkf5/ko XvNvKmFcvLVov/9CfZuF1hfGbr/dtTq0yJDR2G9Ynhof1a2em7Iizi/3hppDb20f9t8YHhFm zirLX+U/HMrb4Rf3Tc56JkssqGDs1u3QBWaf5Ei3oe/80s5sSb9J314X4Db68bghaOO3O+qZ zZ4bmMSfZ6Y8YjP2Rjcs8ek/2qUzzxEap4OtgQpSCFeuW0VoBOUfWA4gB3gDAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrBIsWRmVeSWpSXmKPExsVy+t/xu7oz2aRiDaY+s7bYOGM9q8X1L89Z LeYfOcdqsfrjY0aL5sXr2Swmn5rLZHGmO9ei//FrZovz5zewW5xtesNucatBxuJjzz1Wi8u7 5rBZfO49wmgx4/w+Jou1R+6yW1w85Wpxu3EFm8XhN+2sFv+ubWSx2H/Fy+L2bz6LbyceMTqI e3z7OonF4/2NVnaP2Q0XWTx2zrrL7rFpVSebx/65a9g9epvfsXkcfLeHyaNvyypGj82nqz0+ b5IL4I7SsynKLy1JVcjILy6xVYo2tDDSM7S00DMysdQzNDaPtTIyVdK3s0lJzcksSy3St0vQ y7izej1bwYWTTBVzWh+wNDBu6GHqYuTkkBAwkVj/opGli5GLQ0hgKaPEwbMz2SESYhKT9m2H soUl/lzrYoMo+sQocWzzPMYuRg4ONgE9iR2rCkHiIgJzGCV+dm1jBHGYBc4yS+xe8QZshbCA u8TfIxPBbBYBVYlpR2cwgti8AvYSX5uOQp0hL7F6wwFmEJtTwEHi0te7bCC2EFDNusU3GCcw 8i1gZFjFKJJaWpybnltspFecmFtcmpeul5yfu4kRGIvbjv3csoOx613wIUYBDkYlHl6NWxKx QqyJZcWVuYcYJTiYlUR496+QjBXiTUmsrEotyo8vKs1JLT7EaAp01ERmKdHkfGCayCuJNzQ1 NLewNDQ3Njc2s1AS5+0QOBgjJJCeWJKanZpakFoE08fEwSnVwNhzvaHY4Drjw8nup89tWCvt m7xzVePq6RpbbP+LXn8yX9ZOROb3ulCbSa4pzXI6Jx9rqJsFbXJZYfSy96FOjnmKv8HEl1Z/ rZs/XeLKZRG8v8z+14Sl181feNxVOJsnv+TKppWqArlvSvcH5t8suJ4Vl8n6v0XW4YxxnkFE 1f2bYvEv3GTyuJRYijMSDbWYi4oTAdVjrETbAgAA X-CMS-MailID: 20190701131154eucas1p2e7bab2f0d0e510372fd9f1f1755a5d30 X-Msg-Generator: CA X-RootMTR: 20190701131154eucas1p2e7bab2f0d0e510372fd9f1f1755a5d30 X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20190701131154eucas1p2e7bab2f0d0e510372fd9f1f1755a5d30 References: <20190701131138.22666-1-l.luba@partner.samsung.com> Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch adds driver for Exynos5422 Dynamic Memory Controller. The driver provides support for dynamic frequency and voltage scaling for DMC and DRAM. It supports changing timings of DRAM running with different frequency. There is also an algorithm to calculate timigns based on memory description provided in DT. The patch also contains needed MAINTAINERS file update. Signed-off-by: Lukasz Luba --- MAINTAINERS | 8 + drivers/memory/samsung/Kconfig | 13 + drivers/memory/samsung/Makefile | 1 + drivers/memory/samsung/exynos5422-dmc.c | 1257 +++++++++++++++++++++++ 4 files changed, 1279 insertions(+) create mode 100644 drivers/memory/samsung/exynos5422-dmc.c diff --git a/MAINTAINERS b/MAINTAINERS index 5cfbea4ce575..126cc64f2245 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -4827,6 +4827,14 @@ F: include/linux/dma-direct.h F: include/linux/dma-mapping.h F: include/linux/dma-noncoherent.h +DMC FREQUENCY DRIVER FOR SAMSUNG EXYNOS5422 +M: Lukasz Luba +L: linux-pm@vger.kernel.org +L: linux-samsung-soc@vger.kernel.org +S: Maintained +F: drivers/memory/samsung/exynos5422-dmc.c +F: Documentation/devicetree/bindings/memory-controllers/exynos5422-dmc.txt + DME1737 HARDWARE MONITOR DRIVER M: Juerg Haefliger L: linux-hwmon@vger.kernel.org diff --git a/drivers/memory/samsung/Kconfig b/drivers/memory/samsung/Kconfig index 79ce7ea58903..e42a0fe8f3f1 100644 --- a/drivers/memory/samsung/Kconfig +++ b/drivers/memory/samsung/Kconfig @@ -7,6 +7,19 @@ config SAMSUNG_MC if SAMSUNG_MC +config EXYNOS5422_DMC + tristate "EXYNOS5422 Dynamic Memory Controller driver" + depends on ARCH_EXYNOS || (COMPILE_TEST && HAS_IOMEM) + depends on DDR + depends on DEVFREQ_GOV_SIMPLE_ONDEMAND + depends on (PM_DEVFREQ && PM_DEVFREQ_EVENT) + help + This adds driver for Exynos5422 DMC (Dynamic Memory Controller). + The driver provides support for Dynamic Voltage and Frequency Scaling in + DMC and DRAM. It also supports changing timings of DRAM running with + different frequency. The timings are calculated based on DT memory + information. + config EXYNOS_SROM bool "Exynos SROM controller driver" if COMPILE_TEST depends on (ARM && ARCH_EXYNOS) || (COMPILE_TEST && HAS_IOMEM) diff --git a/drivers/memory/samsung/Makefile b/drivers/memory/samsung/Makefile index 00587be66211..ea071be21c44 100644 --- a/drivers/memory/samsung/Makefile +++ b/drivers/memory/samsung/Makefile @@ -1,2 +1,3 @@ # SPDX-License-Identifier: GPL-2.0 +obj-$(CONFIG_EXYNOS5422_DMC) += exynos5422-dmc.o obj-$(CONFIG_EXYNOS_SROM) += exynos-srom.o diff --git a/drivers/memory/samsung/exynos5422-dmc.c b/drivers/memory/samsung/exynos5422-dmc.c new file mode 100644 index 000000000000..a0bb988af277 --- /dev/null +++ b/drivers/memory/samsung/exynos5422-dmc.c @@ -0,0 +1,1257 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2019 Samsung Electronics Co., Ltd. + * Author: Lukasz Luba + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "../of_memory.h" + +#define EXYNOS5_DREXI_TIMINGAREF (0x0030) +#define EXYNOS5_DREXI_TIMINGROW0 (0x0034) +#define EXYNOS5_DREXI_TIMINGDATA0 (0x0038) +#define EXYNOS5_DREXI_TIMINGPOWER0 (0x003C) +#define EXYNOS5_DREXI_TIMINGROW1 (0x00E4) +#define EXYNOS5_DREXI_TIMINGDATA1 (0x00E8) +#define EXYNOS5_DREXI_TIMINGPOWER1 (0x00EC) +#define CDREX_PAUSE (0x2091c) +#define CDREX_LPDDR3PHY_CON3 (0x20a20) +#define CDREX_LPDDR3PHY_CLKM_SRC (0x20700) +#define EXYNOS5_TIMING_SET_SWI BIT(28) +#define USE_MX_MSPLL_TIMINGS (1) +#define USE_BPLL_TIMINGS (0) +#define EXYNOS5_AREF_NORMAL (0x2e) + +/** + * struct dmc_opp_table - Operating level desciption + * + * Covers frequency and voltage settings of the DMC operating mode. + */ +struct dmc_opp_table { + u32 freq_hz; + u32 volt_uv; +}; + +/** + * struct exynos5_dmc - main structure describing DMC device + * + * The main structure for the Dynamic Memory Controller which covers clocks, + * memory regions, HW information, parameters and current operating mode. + */ +struct exynos5_dmc { + struct device *dev; + struct devfreq *df; + struct devfreq_simple_ondemand_data gov_data; + void __iomem *base_drexi0; + void __iomem *base_drexi1; + struct regmap *clk_regmap; + struct mutex lock; + unsigned long curr_rate; + unsigned long curr_volt; + unsigned long bypass_rate; + struct dmc_opp_table *opp; + struct dmc_opp_table opp_bypass; + int opp_count; + u32 timings_arr_size; + u32 *timing_row; + u32 *timing_data; + u32 *timing_power; + const struct lpddr3_timings *timings; + const struct lpddr3_min_tck *min_tck; + u32 bypass_timing_row; + u32 bypass_timing_data; + u32 bypass_timing_power; + struct regulator *vdd_mif; + struct clk *fout_spll; + struct clk *fout_bpll; + struct clk *mout_spll; + struct clk *mout_bpll; + struct clk *mout_mclk_cdrex; + struct clk *mout_mx_mspll_ccore; + struct clk *mx_mspll_ccore_phy; + struct clk *mout_mx_mspll_ccore_phy; + struct devfreq_event_dev **counter; + int num_counters; +}; + +#define TIMING_FIELD(t_name, t_bit_beg, t_bit_end) \ + { .name = t_name, .bit_beg = t_bit_beg, .bit_end = t_bit_end } + +#define TIMING_VAL2REG(timing, t_val) \ +({ \ + u32 __val; \ + __val = (t_val) << (timing)->bit_beg; \ + __val; \ +}) + +struct timing_reg { + char *name; + int bit_beg; + int bit_end; + unsigned int val; +}; + +static const struct timing_reg timing_row[] = { + TIMING_FIELD("tRFC", 24, 31), + TIMING_FIELD("tRRD", 20, 23), + TIMING_FIELD("tRP", 16, 19), + TIMING_FIELD("tRCD", 12, 15), + TIMING_FIELD("tRC", 6, 11), + TIMING_FIELD("tRAS", 0, 5), +}; + +static const struct timing_reg timing_data[] = { + TIMING_FIELD("tWTR", 28, 31), + TIMING_FIELD("tWR", 24, 27), + TIMING_FIELD("tRTP", 20, 23), + TIMING_FIELD("tW2W-C2C", 14, 14), + TIMING_FIELD("tR2R-C2C", 12, 12), + TIMING_FIELD("WL", 8, 11), + TIMING_FIELD("tDQSCK", 4, 7), + TIMING_FIELD("RL", 0, 3), +}; + +static const struct timing_reg timing_power[] = { + TIMING_FIELD("tFAW", 26, 31), + TIMING_FIELD("tXSR", 16, 25), + TIMING_FIELD("tXP", 8, 15), + TIMING_FIELD("tCKE", 4, 7), + TIMING_FIELD("tMRD", 0, 3), +}; + +#define TIMING_COUNT (ARRAY_SIZE(timing_row) + ARRAY_SIZE(timing_data) + \ + ARRAY_SIZE(timing_power)) + +static int exynos5_counters_set_event(struct exynos5_dmc *dmc) +{ + int i, ret; + + for (i = 0; i < dmc->num_counters; i++) { + if (!dmc->counter[i]) + continue; + ret = devfreq_event_set_event(dmc->counter[i]); + if (ret < 0) + return ret; + } + return 0; +} + +static int exynos5_counters_enable_edev(struct exynos5_dmc *dmc) +{ + int i, ret; + + for (i = 0; i < dmc->num_counters; i++) { + if (!dmc->counter[i]) + continue; + ret = devfreq_event_enable_edev(dmc->counter[i]); + if (ret < 0) + return ret; + } + return 0; +} + +static int exynos5_counters_disable_edev(struct exynos5_dmc *dmc) +{ + int i, ret; + + for (i = 0; i < dmc->num_counters; i++) { + if (!dmc->counter[i]) + continue; + ret = devfreq_event_disable_edev(dmc->counter[i]); + if (ret < 0) + return ret; + } + return 0; +} + +/** + * find_target_freq_id() - Finds requested frequency in local DMC configuration + * @dmc: device for which the information is checked + * @target_rate: requested frequency in KHz + * + * Seeks in the local DMC driver structure for the requested frequency value + * and returns index or error value. + */ +static int find_target_freq_idx(struct exynos5_dmc *dmc, + unsigned long target_rate) +{ + int i; + + for (i = dmc->opp_count - 1; i >= 0; i--) + if (dmc->opp[i].freq_hz <= target_rate) + return i; + + return -EINVAL; +} + +/** + * exynos5_switch_timing_regs() - Changes bank register set for DRAM timings + * @dmc: device for which the new settings is going to be applied + * @set: boolean variable passing set value + * + * Changes the register set, which holds timing parameters. + * There is two register sets: 0 and 1. The register set 0 + * is used in normal operation when the clock is provided from main PLL. + * The bank register set 1 is used when the main PLL frequency is going to be + * changed and the clock is taken from alternative, stable source. + * This function switches between these banks according to the + * currently used clock source. + */ +static void exynos5_switch_timing_regs(struct exynos5_dmc *dmc, bool set) +{ + unsigned int reg; + int ret; + + ret = regmap_read(dmc->clk_regmap, CDREX_LPDDR3PHY_CON3, ®); + + if (set) + reg |= EXYNOS5_TIMING_SET_SWI; + else + reg &= ~EXYNOS5_TIMING_SET_SWI; + + regmap_write(dmc->clk_regmap, CDREX_LPDDR3PHY_CON3, reg); +} + +/** + * exynos5_init_freq_table() - Initialized PM OPP framework + * @dmc: DMC device for which the frequencies are used for OPP init + * @profile: devfreq device's profile + * + * Populate the devfreq device's OPP table based on current frequency, voltage. + */ +static int exynos5_init_freq_table(struct exynos5_dmc *dmc, + struct devfreq_dev_profile *profile) +{ + int i, ret; + int idx; + unsigned long freq; + + ret = dev_pm_opp_of_add_table(dmc->dev); + if (ret < 0) { + dev_err(dmc->dev, "Failed to get OPP table\n"); + return ret; + } + + dmc->opp_count = dev_pm_opp_get_opp_count(dmc->dev); + + dmc->opp = devm_kmalloc_array(dmc->dev, dmc->opp_count, + sizeof(struct dmc_opp_table), GFP_KERNEL); + if (!dmc->opp) + goto err_opp; + + idx = dmc->opp_count - 1; + for (i = 0, freq = ULONG_MAX; i < dmc->opp_count; i++, freq--) { + struct dev_pm_opp *opp; + + opp = dev_pm_opp_find_freq_floor(dmc->dev, &freq); + if (IS_ERR(opp)) + goto err_free_tables; + + dmc->opp[idx - i].freq_hz = freq; + dmc->opp[idx - i].volt_uv = dev_pm_opp_get_voltage(opp); + + dev_pm_opp_put(opp); + } + + return 0; + +err_free_tables: + kfree(dmc->opp); +err_opp: + dev_pm_opp_of_remove_table(dmc->dev); + + return -EINVAL; +} + +/** + * exynos5_set_bypass_dram_timings() - Low-level changes of the DRAM timings + * @dmc: device for which the new settings is going to be applied + * @param: DRAM parameters which passes timing data + * + * Low-level function for changing timings for DRAM memory clocking from + * 'bypass' clock source (fixed frequency @400MHz). + * It uses timing bank registers set 1. + */ +static void exynos5_set_bypass_dram_timings(struct exynos5_dmc *dmc) +{ + writel(EXYNOS5_AREF_NORMAL, + dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGAREF); + + writel(dmc->bypass_timing_row, + dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGROW1); + writel(dmc->bypass_timing_row, + dmc->base_drexi1 + EXYNOS5_DREXI_TIMINGROW1); + writel(dmc->bypass_timing_data, + dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGDATA1); + writel(dmc->bypass_timing_data, + dmc->base_drexi1 + EXYNOS5_DREXI_TIMINGDATA1); + writel(dmc->bypass_timing_power, + dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGPOWER1); + writel(dmc->bypass_timing_power, + dmc->base_drexi1 + EXYNOS5_DREXI_TIMINGPOWER1); +} + +/** + * exynos5_dram_change_timings() - Low-level changes of the DRAM final timings + * @dmc: device for which the new settings is going to be applied + * @target_rate: target frequency of the DMC + * + * Low-level function for changing timings for DRAM memory operating from main + * clock source (BPLL), which can have different frequencies. Thus, each + * frequency must have corresponding timings register values in order to keep + * the needed delays. + * It uses timing bank registers set 0. + */ +static int exynos5_dram_change_timings(struct exynos5_dmc *dmc, + unsigned long target_rate) +{ + int idx; + + for (idx = dmc->opp_count - 1; idx >= 0; idx--) + if (dmc->opp[idx].freq_hz <= target_rate) + break; + + if (idx < 0) + return -EINVAL; + + writel(EXYNOS5_AREF_NORMAL, + dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGAREF); + + writel(dmc->timing_row[idx], + dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGROW0); + writel(dmc->timing_row[idx], + dmc->base_drexi1 + EXYNOS5_DREXI_TIMINGROW0); + writel(dmc->timing_data[idx], + dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGDATA0); + writel(dmc->timing_data[idx], + dmc->base_drexi1 + EXYNOS5_DREXI_TIMINGDATA0); + writel(dmc->timing_power[idx], + dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGPOWER0); + writel(dmc->timing_power[idx], + dmc->base_drexi1 + EXYNOS5_DREXI_TIMINGPOWER0); + + return 0; +} + +/** + * exynos5_dmc_align_target_voltage() - Sets the final voltage for the DMC + * @dmc: device for which it is going to be set + * @target_volt: new voltage which is chosen to be final + * + * Function tries to align voltage to the safe level for 'normal' mode. + * It checks the need of higher voltage and changes the value. The target + * voltage might be lower that currently set and still the system will be + * stable. + */ +static int exynos5_dmc_align_target_voltage(struct exynos5_dmc *dmc, + unsigned long target_volt) +{ + int ret = 0; + + if (dmc->curr_volt <= target_volt) + return 0; + + ret = regulator_set_voltage(dmc->vdd_mif, target_volt, + target_volt); + if (!ret) + dmc->curr_volt = target_volt; + + return ret; +} + +/** + * exynos5_dmc_align_bypass_voltage() - Sets the voltage for the DMC + * @dmc: device for which it is going to be set + * @target_volt: new voltage which is chosen to be final + * + * Function tries to align voltage to the safe level for the 'bypass' mode. + * It checks the need of higher voltage and changes the value. + * The target voltage must not be less than currently needed, because + * for current frequency the device might become unstable. + */ +static int exynos5_dmc_align_bypass_voltage(struct exynos5_dmc *dmc, + unsigned long target_volt) +{ + int ret = 0; + unsigned long bypass_volt = dmc->opp_bypass.volt_uv; + + target_volt = max(bypass_volt, target_volt); + + if (dmc->curr_volt >= target_volt) + return 0; + + ret = regulator_set_voltage(dmc->vdd_mif, target_volt, + target_volt); + if (!ret) + dmc->curr_volt = target_volt; + + return ret; +} + +/** + * exynos5_dmc_align_bypass_dram_timings() - Chooses and sets DRAM timings + * @dmc: device for which it is going to be set + * @target_rate: new frequency which is chosen to be final + * + * Function changes the DRAM timings for the temporary 'bypass' mode. + */ +static int exynos5_dmc_align_bypass_dram_timings(struct exynos5_dmc *dmc, + unsigned long target_rate) +{ + int idx = find_target_freq_idx(dmc, target_rate); + + if (idx < 0) + return -EINVAL; + + exynos5_set_bypass_dram_timings(dmc); + + return 0; +} + +/** + * exynos5_dmc_switch_to_bypass_configuration() - Switching to temporary clock + * @dmc: DMC device for which the switching is going to happen + * @target_rate: new frequency which is going to be set as a final + * @target_volt: new voltage which is going to be set as a final + * + * Function configures DMC and clocks for operating in temporary 'bypass' mode. + * This mode is used only temporary but if required, changes voltage and timings + * for DRAM chips. It switches the main clock to stable clock source for the + * period of the main PLL reconfiguration. + */ +static int +exynos5_dmc_switch_to_bypass_configuration(struct exynos5_dmc *dmc, + unsigned long target_rate, + unsigned long target_volt) +{ + int ret; + + /* + * Having higher voltage for a particular frequency does not harm + * the chip. Use it for the temporary frequency change when one + * voltage manipulation might be avoided. + */ + ret = exynos5_dmc_align_bypass_voltage(dmc, target_volt); + if (ret) + return ret; + + /* + * Longer delays for DRAM does not cause crash, the opposite does. + */ + ret = exynos5_dmc_align_bypass_dram_timings(dmc, target_rate); + if (ret) + return ret; + + /* + * Delays are long enough, so use them for the new coming clock. + */ + exynos5_switch_timing_regs(dmc, USE_MX_MSPLL_TIMINGS); + + return ret; +} + +/** + * exynos5_dmc_change_freq_and_volt() - Changes voltage and frequency of the DMC + * using safe procedure + * @dmc: device for which the frequency is going to be changed + * @target_rate: requested new frequency + * @target_volt: requested voltage which corresponds to the new frequency + * + * The DMC frequency change procedure requires a few steps. + * The main requirement is to change the clock source in the clk mux + * for the time of main clock PLL locking. The assumption is that the + * alternative clock source set as parent is stable. + * The second parent's clock frequency is fixed to 400MHz, it is named 'bypass' + * clock. This requires alignment in DRAM timing parameters for the new + * T-period. There is two bank sets for keeping DRAM + * timings: set 0 and set 1. The set 0 is used when main clock source is + * chosen. The 2nd set of regs is used for 'bypass' clock. Switching between + * the two bank sets is part of the process. + * The voltage must also be aligned to the minimum required level. There is + * this intermediate step with switching to 'bypass' parent clock source. + * if the old voltage is lower, it requires an increase of the voltage level. + * The complexity of the voltage manipulation is hidden in low level function. + * In this function there is last alignment of the voltage level at the end. + */ +static int +exynos5_dmc_change_freq_and_volt(struct exynos5_dmc *dmc, + unsigned long target_rate, + unsigned long target_volt) +{ + int ret; + + ret = exynos5_dmc_switch_to_bypass_configuration(dmc, target_rate, + target_volt); + if (ret) + return ret; + + /* + * Voltage is set at least to a level needed for this frequency, + * so switching clock source is safe now. + */ + clk_prepare_enable(dmc->fout_spll); + clk_prepare_enable(dmc->mout_spll); + clk_prepare_enable(dmc->mout_mx_mspll_ccore); + + ret = clk_set_parent(dmc->mout_mclk_cdrex, dmc->mout_mx_mspll_ccore); + if (ret) + goto disable_clocks; + + /* + * We are safe to increase the timings for current bypass frequency. + * Thanks to this the settings will be ready for the upcoming clock + * source change. + */ + exynos5_dram_change_timings(dmc, target_rate); + + clk_set_rate(dmc->fout_bpll, target_rate); + + exynos5_switch_timing_regs(dmc, USE_BPLL_TIMINGS); + + ret = clk_set_parent(dmc->mout_mclk_cdrex, dmc->mout_bpll); + if (ret) + goto disable_clocks; + + /* + * Make sure if the voltage is not from 'bypass' settings and align to + * the right level for power efficiency. + */ + ret = exynos5_dmc_align_target_voltage(dmc, target_volt); + +disable_clocks: + clk_disable_unprepare(dmc->mout_mx_mspll_ccore); + clk_disable_unprepare(dmc->mout_spll); + clk_disable_unprepare(dmc->fout_spll); + + return ret; +} + +/** + * exynos5_dmc_get_volt_freq() - Gets the frequency and voltage from the OPP + * table. + * @dmc: device for which the frequency is going to be changed + * @freq: requested frequency in KHz + * @target_rate: returned frequency which is the same or lower than + * requested + * @target_volt: returned voltage which corresponds to the returned + * frequency + * + * Function gets requested frequency and checks OPP framework for needed + * frequency and voltage. It populates the values 'target_rate' and + * 'target_volt' or returns error value when OPP framework fails. + */ +static int exynos5_dmc_get_volt_freq(struct exynos5_dmc *dmc, + unsigned long *freq, + unsigned long *target_rate, + unsigned long *target_volt, u32 flags) +{ + struct dev_pm_opp *opp; + + opp = devfreq_recommended_opp(dmc->dev, freq, flags); + if (IS_ERR(opp)) + return PTR_ERR(opp); + + *target_rate = dev_pm_opp_get_freq(opp); + *target_volt = dev_pm_opp_get_voltage(opp); + dev_pm_opp_put(opp); + + return 0; +} + +/** + * exynos5_dmc_target() - Function responsible for changing frequency of DMC + * @dev: device for which the frequency is going to be changed + * @freq: requested frequency in KHz + * @flags: flags provided for this frequency change request + * + * An entry function provided to the devfreq framework which provides frequency + * change of the DMC. The function gets the possible rate from OPP table based + * on requested frequency. It calls the next function responsible for the + * frequency and voltage change. In case of failure, does not set 'curr_rate' + * and returns error value to the framework. + */ +static int exynos5_dmc_target(struct device *dev, unsigned long *freq, + u32 flags) +{ + struct exynos5_dmc *dmc = dev_get_drvdata(dev); + unsigned long target_rate = 0; + unsigned long target_volt = 0; + int ret; + + ret = exynos5_dmc_get_volt_freq(dmc, freq, &target_rate, &target_volt, + flags); + + if (ret) + return ret; + + if (target_rate == dmc->curr_rate) + return 0; + + mutex_lock(&dmc->lock); + + ret = exynos5_dmc_change_freq_and_volt(dmc, target_rate, target_volt); + + if (ret) { + mutex_unlock(&dmc->lock); + return ret; + } + + dmc->curr_rate = target_rate; + + mutex_unlock(&dmc->lock); + return 0; +} + +/** + * exynos5_counters_get() - Gets the performance counters values. + * @dmc: device for which the counters are going to be checked + * @load_count: variable which is populated with counter value + * @total_count: variable which is used as 'wall clock' reference + * + * Function which provides performance counters values. It sums up counters for + * two DMC channels. The 'total_count' is used as a reference and max value. + * The ratio 'load_count/total_count' shows the busy percentage [0%, 100%]. + */ +static int exynos5_counters_get(struct exynos5_dmc *dmc, + unsigned long *load_count, + unsigned long *total_count) +{ + unsigned long total = 0; + struct devfreq_event_data event; + int ret, i; + + *load_count = 0; + + /* Take into account only read+write counters, but stop all */ + for (i = 0; i < dmc->num_counters; i++) { + if (!dmc->counter[i]) + continue; + + ret = devfreq_event_get_event(dmc->counter[i], &event); + if (ret < 0) + return ret; + + *load_count += event.load_count; + + if (total < event.total_count) + total = event.total_count; + } + + *total_count = total; + + return 0; +} + +/** + * exynos5_dmc_get_status() - Read current DMC performance statistics. + * @dev: device for which the statistics are requested + * @stat: structure which has statistic fields + * + * Function reads the DMC performance counters and calculates 'busy_time' + * and 'total_time'. To protect from overflow, the values are shifted right + * by 10. After read out the counters are setup to count again. + */ +static int exynos5_dmc_get_status(struct device *dev, + struct devfreq_dev_status *stat) +{ + struct exynos5_dmc *dmc = dev_get_drvdata(dev); + unsigned long load, total; + int ret; + + ret = exynos5_counters_get(dmc, &load, &total); + if (ret < 0) + return -EINVAL; + + /* To protect from overflow in calculation ratios, divide by 1024 */ + stat->busy_time = load >> 10; + stat->total_time = total >> 10; + + ret = exynos5_counters_set_event(dmc); + if (ret < 0) { + dev_err(dev, "could not set event counter\n"); + return ret; + } + + return 0; +} + +/** + * exynos5_dmc_get_cur_freq() - Function returns current DMC frequency + * @dev: device for which the framework checks operating frequency + * @freq: returned frequency value + * + * It returns the currently used frequency of the DMC. The real operating + * frequency might be lower when the clock source value could not be divided + * to the requested value. + */ +static int exynos5_dmc_get_cur_freq(struct device *dev, unsigned long *freq) +{ + struct exynos5_dmc *dmc = dev_get_drvdata(dev); + + mutex_lock(&dmc->lock); + *freq = dmc->curr_rate; + mutex_unlock(&dmc->lock); + + return 0; +} + +/** + * exynos5_dmc_df_profile - Devfreq governor's profile structure + * + * It provides to the devfreq framework needed functions and polling period. + */ +static struct devfreq_dev_profile exynos5_dmc_df_profile = { + .polling_ms = 500, + .target = exynos5_dmc_target, + .get_dev_status = exynos5_dmc_get_status, + .get_cur_freq = exynos5_dmc_get_cur_freq, +}; + +/** + * exynos5_dmc_align_initial_frequency() - Align initial frequency value + * @dmc: device for which the frequency is going to be set + * @bootloader_init_freq: initial frequency set by the bootloader in KHz + * + * The initial bootloader frequency, which is present during boot, might be + * different that supported frequency values in the driver. It is possible + * due to different PLL settings or used PLL as a source. + * This function provides the 'initial_freq' for the devfreq framework + * statistics engine which supports only registered values. Thus, some alignment + * must be made. + */ +unsigned long +exynos5_dmc_align_init_freq(struct exynos5_dmc *dmc, + unsigned long bootloader_init_freq) +{ + unsigned long aligned_freq; + int idx; + + idx = find_target_freq_idx(dmc, bootloader_init_freq); + if (idx >= 0) + aligned_freq = dmc->opp[idx].freq_hz; + else + aligned_freq = dmc->opp[dmc->opp_count - 1].freq_hz; + + return aligned_freq; +} + +/** + * create_timings_aligned() - Create register values and align with standard + * @dmc: device for which the frequency is going to be set + * @idx: speed bin in the OPP table + * @clk_period_ps: the period of the clock, known as tCK + * + * The function calculates timings and creates a register value ready for + * a frequency transition. The register contains a few timings. They are + * shifted by a known offset. The timing value is calculated based on memory + * specyfication: minimal time required and minimal cycles required. + */ +static int create_timings_aligned(struct exynos5_dmc *dmc, u32 *reg_timing_row, + u32 *reg_timing_data, u32 *reg_timing_power, + u32 clk_period_ps) +{ + u32 val; + const struct timing_reg *reg; + + if (clk_period_ps == 0) + return -EINVAL; + + *reg_timing_row = 0; + *reg_timing_data = 0; + *reg_timing_power = 0; + + val = dmc->timings->tRFC / clk_period_ps; + val += dmc->timings->tRFC % clk_period_ps ? 1 : 0; + val = max(val, dmc->min_tck->tRFC); + reg = &timing_row[0]; + *reg_timing_row |= TIMING_VAL2REG(reg, val); + + val = dmc->timings->tRRD / clk_period_ps; + val += dmc->timings->tRRD % clk_period_ps ? 1 : 0; + val = max(val, dmc->min_tck->tRRD); + reg = &timing_row[1]; + *reg_timing_row |= TIMING_VAL2REG(reg, val); + + val = dmc->timings->tRPab / clk_period_ps; + val += dmc->timings->tRPab % clk_period_ps ? 1 : 0; + val = max(val, dmc->min_tck->tRPab); + reg = &timing_row[2]; + *reg_timing_row |= TIMING_VAL2REG(reg, val); + + val = dmc->timings->tRCD / clk_period_ps; + val += dmc->timings->tRCD % clk_period_ps ? 1 : 0; + val = max(val, dmc->min_tck->tRCD); + reg = &timing_row[3]; + *reg_timing_row |= TIMING_VAL2REG(reg, val); + + val = dmc->timings->tRC / clk_period_ps; + val += dmc->timings->tRC % clk_period_ps ? 1 : 0; + val = max(val, dmc->min_tck->tRC); + reg = &timing_row[4]; + *reg_timing_row |= TIMING_VAL2REG(reg, val); + + val = dmc->timings->tRAS / clk_period_ps; + val += dmc->timings->tRAS % clk_period_ps ? 1 : 0; + val = max(val, dmc->min_tck->tRAS); + reg = &timing_row[5]; + *reg_timing_row |= TIMING_VAL2REG(reg, val); + + /* data related timings */ + val = dmc->timings->tWTR / clk_period_ps; + val += dmc->timings->tWTR % clk_period_ps ? 1 : 0; + val = max(val, dmc->min_tck->tWTR); + reg = &timing_data[0]; + *reg_timing_data |= TIMING_VAL2REG(reg, val); + + val = dmc->timings->tWR / clk_period_ps; + val += dmc->timings->tWR % clk_period_ps ? 1 : 0; + val = max(val, dmc->min_tck->tWR); + reg = &timing_data[1]; + *reg_timing_data |= TIMING_VAL2REG(reg, val); + + val = dmc->timings->tRTP / clk_period_ps; + val += dmc->timings->tRTP % clk_period_ps ? 1 : 0; + val = max(val, dmc->min_tck->tRTP); + reg = &timing_data[2]; + *reg_timing_data |= TIMING_VAL2REG(reg, val); + + val = dmc->timings->tW2W_C2C / clk_period_ps; + val += dmc->timings->tW2W_C2C % clk_period_ps ? 1 : 0; + val = max(val, dmc->min_tck->tW2W_C2C); + reg = &timing_data[3]; + *reg_timing_data |= TIMING_VAL2REG(reg, val); + + val = dmc->timings->tR2R_C2C / clk_period_ps; + val += dmc->timings->tR2R_C2C % clk_period_ps ? 1 : 0; + val = max(val, dmc->min_tck->tR2R_C2C); + reg = &timing_data[4]; + *reg_timing_data |= TIMING_VAL2REG(reg, val); + + val = dmc->timings->tWL / clk_period_ps; + val += dmc->timings->tWL % clk_period_ps ? 1 : 0; + val = max(val, dmc->min_tck->tWL); + reg = &timing_data[5]; + *reg_timing_data |= TIMING_VAL2REG(reg, val); + + val = dmc->timings->tDQSCK / clk_period_ps; + val += dmc->timings->tDQSCK % clk_period_ps ? 1 : 0; + val = max(val, dmc->min_tck->tDQSCK); + reg = &timing_data[6]; + *reg_timing_data |= TIMING_VAL2REG(reg, val); + + val = dmc->timings->tRL / clk_period_ps; + val += dmc->timings->tRL % clk_period_ps ? 1 : 0; + val = max(val, dmc->min_tck->tRL); + reg = &timing_data[7]; + *reg_timing_data |= TIMING_VAL2REG(reg, val); + + /* power related timings */ + val = dmc->timings->tFAW / clk_period_ps; + val += dmc->timings->tFAW % clk_period_ps ? 1 : 0; + val = max(val, dmc->min_tck->tXP); + reg = &timing_power[0]; + *reg_timing_power |= TIMING_VAL2REG(reg, val); + + val = dmc->timings->tXSR / clk_period_ps; + val += dmc->timings->tXSR % clk_period_ps ? 1 : 0; + val = max(val, dmc->min_tck->tXSR); + reg = &timing_power[1]; + *reg_timing_power |= TIMING_VAL2REG(reg, val); + + val = dmc->timings->tXP / clk_period_ps; + val += dmc->timings->tXP % clk_period_ps ? 1 : 0; + val = max(val, dmc->min_tck->tXP); + reg = &timing_power[2]; + *reg_timing_power |= TIMING_VAL2REG(reg, val); + + val = dmc->timings->tCKE / clk_period_ps; + val += dmc->timings->tCKE % clk_period_ps ? 1 : 0; + val = max(val, dmc->min_tck->tCKE); + reg = &timing_power[3]; + *reg_timing_power |= TIMING_VAL2REG(reg, val); + + val = dmc->timings->tMRD / clk_period_ps; + val += dmc->timings->tMRD % clk_period_ps ? 1 : 0; + val = max(val, dmc->min_tck->tMRD); + reg = &timing_power[4]; + *reg_timing_power |= TIMING_VAL2REG(reg, val); + + return 0; +} + +/** + * of_get_dram_timings() - helper function for parsing DT settings for DRAM + * @dmc: device for which the frequency is going to be set + * + * The function parses DT entries with DRAM information. + */ +static int of_get_dram_timings(struct exynos5_dmc *dmc) +{ + int ret = 0; + int idx; + struct device_node *np_ddr; + u32 freq_mhz, clk_period_ps; + + np_ddr = of_parse_phandle(dmc->dev->of_node, "device-handle", 0); + if (!np_ddr) { + dev_warn(dmc->dev, "could not find 'device-handle' in DT\n"); + return -EINVAL; + } + + dmc->timing_row = devm_kmalloc_array(dmc->dev, TIMING_COUNT, + sizeof(u32), GFP_KERNEL); + if (!dmc->timing_row) + return -ENOMEM; + + dmc->timing_data = devm_kmalloc_array(dmc->dev, TIMING_COUNT, + sizeof(u32), GFP_KERNEL); + if (!dmc->timing_data) + return -ENOMEM; + + dmc->timing_power = devm_kmalloc_array(dmc->dev, TIMING_COUNT, + sizeof(u32), GFP_KERNEL); + if (!dmc->timing_power) + return -ENOMEM; + + dmc->timings = of_lpddr3_get_ddr_timings(np_ddr, dmc->dev, + DDR_TYPE_LPDDR3, + &dmc->timings_arr_size); + if (!dmc->timings) { + of_node_put(np_ddr); + dev_warn(dmc->dev, "could not get timings from DT\n"); + return -EINVAL; + } + + dmc->min_tck = of_lpddr3_get_min_tck(np_ddr, dmc->dev); + if (!dmc->min_tck) { + of_node_put(np_ddr); + dev_warn(dmc->dev, "could not get tck from DT\n"); + return -EINVAL; + } + + /* Sorted array of OPPs with frequency ascending */ + for (idx = 0; idx < dmc->opp_count; idx++) { + freq_mhz = dmc->opp[idx].freq_hz / 1000000; + clk_period_ps = 1000000 / freq_mhz; + + ret = create_timings_aligned(dmc, &dmc->timing_row[idx], + &dmc->timing_data[idx], + &dmc->timing_power[idx], + clk_period_ps); + } + + of_node_put(np_ddr); + + /* Take the highest frequency's timings as 'bypass' */ + dmc->bypass_timing_row = dmc->timing_row[idx - 1]; + dmc->bypass_timing_data = dmc->timing_data[idx - 1]; + dmc->bypass_timing_power = dmc->timing_power[idx - 1]; + + return ret; +} + +/** + * exynos5_dmc_init_clks() - Initialize clocks needed for DMC operation. + * @dmc: DMC structure containing needed fields + * + * Get the needed clocks defined in DT device, enable and set the right parents. + * Read current frequency and initialize the initial rate for governor. + */ +static int exynos5_dmc_init_clks(struct exynos5_dmc *dmc) +{ + int ret; + unsigned long target_volt = 0; + unsigned long target_rate = 0; + unsigned int tmp; + + dmc->fout_spll = devm_clk_get(dmc->dev, "fout_spll"); + if (IS_ERR(dmc->fout_spll)) + return PTR_ERR(dmc->fout_spll); + + dmc->fout_bpll = devm_clk_get(dmc->dev, "fout_bpll"); + if (IS_ERR(dmc->fout_bpll)) + return PTR_ERR(dmc->fout_bpll); + + dmc->mout_mclk_cdrex = devm_clk_get(dmc->dev, "mout_mclk_cdrex"); + if (IS_ERR(dmc->mout_mclk_cdrex)) + return PTR_ERR(dmc->mout_mclk_cdrex); + + dmc->mout_bpll = devm_clk_get(dmc->dev, "mout_bpll"); + if (IS_ERR(dmc->mout_bpll)) + return PTR_ERR(dmc->mout_bpll); + + dmc->mout_mx_mspll_ccore = devm_clk_get(dmc->dev, + "mout_mx_mspll_ccore"); + if (IS_ERR(dmc->mout_mx_mspll_ccore)) + return PTR_ERR(dmc->mout_mx_mspll_ccore); + + dmc->mout_spll = devm_clk_get(dmc->dev, "ff_dout_spll2"); + if (IS_ERR(dmc->mout_spll)) { + dmc->mout_spll = devm_clk_get(dmc->dev, "mout_sclk_spll"); + if (IS_ERR(dmc->mout_spll)) + return PTR_ERR(dmc->mout_spll); + } + + /* + * Convert frequency to KHz values and set it for the governor. + */ + dmc->curr_rate = clk_get_rate(dmc->mout_mclk_cdrex); + dmc->curr_rate = exynos5_dmc_align_init_freq(dmc, dmc->curr_rate); + exynos5_dmc_df_profile.initial_freq = dmc->curr_rate; + + ret = exynos5_dmc_get_volt_freq(dmc, &dmc->curr_rate, &target_rate, + &target_volt, 0); + if (ret) + return ret; + + dmc->curr_volt = target_volt; + + clk_set_parent(dmc->mout_mx_mspll_ccore, dmc->mout_spll); + + dmc->bypass_rate = clk_get_rate(dmc->mout_mx_mspll_ccore); + + clk_prepare_enable(dmc->fout_bpll); + clk_prepare_enable(dmc->mout_bpll); + + /* + * Some bootloaders do not set clock routes correctly. + * Stop one path in clocks to PHY. + */ + regmap_read(dmc->clk_regmap, CDREX_LPDDR3PHY_CLKM_SRC, &tmp); + tmp &= ~(BIT(1) | BIT(0)); + regmap_write(dmc->clk_regmap, CDREX_LPDDR3PHY_CLKM_SRC, tmp); + + return 0; +} + +/** + * exynos5_performance_counters_init() - Initializes performance DMC's counters + * @dmc: DMC for which it does the setup + * + * Initialization of performance counters in DMC for estimating usage. + * The counter's values are used for calculation of a memory bandwidth and based + * on that the governor changes the frequency. + * The counters are not used when the governor is GOVERNOR_USERSPACE. + */ +static int exynos5_performance_counters_init(struct exynos5_dmc *dmc) +{ + int counters_size; + int ret, i; + + dmc->num_counters = devfreq_event_get_edev_count(dmc->dev); + if (dmc->num_counters < 0) { + dev_err(dmc->dev, "could not get devfreq-event counters\n"); + return dmc->num_counters; + } + + counters_size = sizeof(struct devfreq_event_dev) * dmc->num_counters; + dmc->counter = devm_kzalloc(dmc->dev, counters_size, GFP_KERNEL); + if (!dmc->counter) + return -ENOMEM; + + for (i = 0; i < dmc->num_counters; i++) { + dmc->counter[i] = + devfreq_event_get_edev_by_phandle(dmc->dev, i); + if (IS_ERR_OR_NULL(dmc->counter[i])) + return -EPROBE_DEFER; + } + + ret = exynos5_counters_enable_edev(dmc); + if (ret < 0) { + dev_err(dmc->dev, "could not enable event counter\n"); + return ret; + } + + ret = exynos5_counters_set_event(dmc); + if (ret < 0) { + exynos5_counters_disable_edev(dmc); + dev_err(dmc->dev, "counld not set event counter\n"); + return ret; + } + + return 0; +} + +/** + * exynos5_dmc_set_pause_on_switching() - Controls a pause feature in DMC + * @dmc: device which is used for changing this feature + * @set: a boolean state passing enable/disable request + * + * There is a need of pausing DREX DMC when divider or MUX in clock tree + * changes its configuration. In such situation access to the memory is blocked + * in DMC automatically. This feature is used when clock frequency change + * request appears and touches clock tree. + */ +static inline int exynos5_dmc_set_pause_on_switching(struct exynos5_dmc *dmc) +{ + unsigned int val; + int ret; + + ret = regmap_read(dmc->clk_regmap, CDREX_PAUSE, &val); + if (ret) + return ret; + + val |= 1UL; + regmap_write(dmc->clk_regmap, CDREX_PAUSE, val); + + return 0; +} + +/** + * exynos5_dmc_probe() - Probe function for the DMC driver + * @pdev: platform device for which the driver is going to be initialized + * + * Initialize basic components: clocks, regulators, performance counters, etc. + * Read out product version and based on the information setup + * internal structures for the controller (frequency and voltage) and for DRAM + * memory parameters: timings for each operating frequency. + * Register new devfreq device for controlling DVFS of the DMC. + */ +static int exynos5_dmc_probe(struct platform_device *pdev) +{ + int ret = 0; + struct device *dev = &pdev->dev; + struct device_node *np = dev->of_node; + struct exynos5_dmc *dmc; + struct resource *res; + + dmc = devm_kzalloc(dev, sizeof(*dmc), GFP_KERNEL); + if (!dmc) + return -ENOMEM; + + mutex_init(&dmc->lock); + + dmc->dev = dev; + platform_set_drvdata(pdev, dmc); + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + dmc->base_drexi0 = devm_ioremap_resource(dev, res); + if (IS_ERR(dmc->base_drexi0)) + return PTR_ERR(dmc->base_drexi0); + + res = platform_get_resource(pdev, IORESOURCE_MEM, 1); + dmc->base_drexi1 = devm_ioremap_resource(dev, res); + if (IS_ERR(dmc->base_drexi1)) + return PTR_ERR(dmc->base_drexi1); + + dmc->clk_regmap = syscon_regmap_lookup_by_phandle(np, + "samsung,syscon-clk"); + if (IS_ERR(dmc->clk_regmap)) + return PTR_ERR(dmc->clk_regmap); + + ret = exynos5_init_freq_table(dmc, &exynos5_dmc_df_profile); + if (ret) { + dev_warn(dev, "couldn't initialize frequency settings\n"); + return ret; + } + + dmc->vdd_mif = devm_regulator_get(dev, "vdd"); + if (IS_ERR(dmc->vdd_mif)) { + ret = PTR_ERR(dmc->vdd_mif); + return ret; + } + + ret = exynos5_dmc_init_clks(dmc); + if (ret) + return ret; + + ret = of_get_dram_timings(dmc); + if (ret) { + dev_warn(dev, "couldn't initialize timings settings\n"); + goto remove_clocks; + } + + ret = exynos5_performance_counters_init(dmc); + if (ret) { + dev_warn(dev, "couldn't probe performance counters\n"); + goto remove_clocks; + } + + ret = exynos5_dmc_set_pause_on_switching(dmc); + if (ret) { + dev_warn(dev, "couldn't get access to PAUSE register\n"); + goto err_devfreq_add; + } + + /* + * Setup default thresholds for the devfreq governor. + * The values are chosen based on experiments. + */ + dmc->gov_data.upthreshold = 30; + dmc->gov_data.downdifferential = 5; + + dmc->df = devm_devfreq_add_device(dev, &exynos5_dmc_df_profile, + DEVFREQ_GOV_SIMPLE_ONDEMAND, + &dmc->gov_data); + + if (IS_ERR(dmc->df)) { + ret = PTR_ERR(dmc->df); + goto err_devfreq_add; + } + + dev_info(dev, "DMC initialized\n"); + + return 0; + +err_devfreq_add: + exynos5_counters_disable_edev(dmc); +remove_clocks: + clk_disable_unprepare(dmc->mout_bpll); + clk_disable_unprepare(dmc->fout_bpll); + + return ret; +} + +/** + * exynos5_dmc_remove() - Remove function for the platform device + * @pdev: platform device which is going to be removed + * + * The function relies on 'devm' framework function which automatically + * clean the device's resources. It just calls explicitly disable function for + * the performance counters. + */ +static int exynos5_dmc_remove(struct platform_device *pdev) +{ + struct exynos5_dmc *dmc = dev_get_drvdata(&pdev->dev); + + exynos5_counters_disable_edev(dmc); + + clk_disable_unprepare(dmc->mout_bpll); + clk_disable_unprepare(dmc->fout_bpll); + + dev_pm_opp_remove_table(dmc->dev); + + return 0; +} + +static const struct of_device_id exynos5_dmc_of_match[] = { + { .compatible = "samsung,exynos5422-dmc", }, + { }, +}; +MODULE_DEVICE_TABLE(of, exynos5_dmc_of_match); + +static struct platform_driver exynos5_dmc_platdrv = { + .probe = exynos5_dmc_probe, + .remove = exynos5_dmc_remove, + .driver = { + .name = "exynos5-dmc", + .of_match_table = exynos5_dmc_of_match, + }, +}; +module_platform_driver(exynos5_dmc_platdrv); +MODULE_DESCRIPTION("Driver for Exynos5422 Dynamic Memory Controller dynamic frequency and voltage change"); +MODULE_LICENSE("GPL v2"); +MODULE_AUTHOR("Lukasz Luba"); From patchwork Mon Jul 1 13:11:35 2019 Content-Type: text/plain; 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Mon, 1 Jul 2019 13:11:53 +0000 (GMT) From: Lukasz Luba To: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org Cc: mturquette@baylibre.com, sboyd@kernel.org, b.zolnierkie@samsung.com, krzk@kernel.org, kgene@kernel.org, cw00.choi@samsung.com, kyungmin.park@samsung.com, m.szyprowski@samsung.com, s.nawrocki@samsung.com, myungjoo.ham@samsung.com, keescook@chromium.org, tony@atomide.com, jroedel@suse.de, treding@nvidia.com, digetx@gmail.com, gregkh@linuxfoundation.org, willy.mh.wolff.ml@gmail.com, Lukasz Luba Subject: [PATCH v11 6/9] ARM: dts: exynos: add chipid label and syscon compatible Date: Mon, 1 Jul 2019 15:11:35 +0200 Message-Id: <20190701131138.22666-7-l.luba@partner.samsung.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190701131138.22666-1-l.luba@partner.samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA0VSZ0xTURjl9k2qxWcx9hNXUjcqDtBcRwQSTV5c0fADoyFa5AWItGgfKKjB KnFTNDUqggRwBGSVUWXEsBUDSEVRlCEGElFAFKEYByrl1fjv3DO+892byxLKLsqNDdVFCHqd JkxNy8kHj783Lk2i3QKW3zV54vwEM4VbhnsonFLTSOGswW6EY2+baXylLlmGGy5q8aXuPgJb rXkMfnqqn8Gthhl4MO4thV+U3qTxkLEG4QRrmQzn1HQwuKluE247mUHj6v6zFP79Kp/E5c2b cdtPFzzypAv5qPgRm4nkP78+zfBJhiaSL0nsYPiCzPM0X56czfDG2AGarxx4KOPjLZmIL6w/ xg8VzNoxYbd8fZAQFnpY0C/bsE8eUvfIRhxsoKOaU23IgCzUBeTMAucFOT2d6AKSs0ouA0FJ fDxjF5TcMIKs0ROSMITANFJJ/ksUxd8gJCEdwUfzN0Y6jCVONb8cc7EszXlAceYhe2AKl4Ag 6YOf3UNwRQR8amtHdsGV84PPLQ3jdSQ3D4pexI03KDhvOJt9hpDaZkNWXsU4duZ84Lmtg7YP As7IQlqK2bHSRrjfmujArtBba2EkPAP+lKTIJCyCwZiGJHwcui8lOzzroLq2ibIvTXCLwFy6 TKJ9oaJxdPwuwLnA60+T7TQxBk0PrhMSrYBzZ5SSeyFY4p45iqZCevY1x3Aeinvek9LzXEHQ Z2ghL6PZif/LUhHKRCohUtQGC6KnTjjiIWq0YqQu2GN/uLYAjf28+t+1tmJU9iuwCnEsUk9U GNohQElpDovR2ioELKGeoijPmBagVARpoo8K+vC9+sgwQaxC01lSrVIcc3q3R8kFayKEA4Jw UND/U2Wss5sBha0soTaFL+i8EzXXW5W72G3Ozug3Mbd8+4ZGmydZf5jcff1jvmzp9brxM8pF 7ntdljjTM33rtltRLUHnnDy8nQLeq5y+lfv0ybOvFg7Mj1i13TPX2B7q3rV29en78/YSIeY1 IaaL9Rml1l1LCmOHd/T7m2RNlq861zvDFXk+Ffvu+QWqSTFEs8Kd0Iuavx5UxVd1AwAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrGIsWRmVeSWpSXmKPExsVy+t/xu7qz2KRiDb59s7LYOGM9q8X1L89Z LeYfOcdqsfrjY0aL5sXr2Swmn5rLZHGmO9ei//FrZovz5zewW5xtesNucatBxuJjzz1Wi8u7 5rBZfO49wmgx4/w+Jou1R+6yW1w85Wpxu3EFm8XhN+2sFv+ubWSx2H/Fy+L2bz6LbyceMTqI e3z7OonF4/2NVnaP2Q0XWTx2zrrL7rFpVSebx/65a9g9epvfsXkcfLeHyaNvyypGj82nqz0+ b5IL4I7SsynKLy1JVcjILy6xVYo2tDDSM7S00DMysdQzNDaPtTIyVdK3s0lJzcksSy3St0vQ yzh19CtzwRm2iisLvjI2MG5h7WLk5JAQMJHY3jeTuYuRi0NIYCmjxKT3y6ESYhKT9m1nh7CF Jf5c62KDKPrEKHHp7jvGLkYODjYBPYkdqwpB4iICcxglfnZtYwRxmAXOMkvsXvGGCaRbWCBQ Yu+zB2A2i4CqxPbLPSwgNq+AvUT7mjZmiA3yEqs3HACzOQUcJC59vcsGYgsB1axbfINxAiPf AkaGVYwiqaXFuem5xUZ6xYm5xaV56XrJ+bmbGIFxuO3Yzy07GLveBR9iFOBgVOLh1bglESvE mlhWXJl7iFGCg1lJhHf/CslYId6UxMqq1KL8+KLSnNTiQ4ymQEdNZJYSTc4Hpoi8knhDU0Nz C0tDc2NzYzMLJXHeDoGDMUIC6YklqdmpqQWpRTB9TBycUg2MG9XO6e7V1lvzdkrSGg2TD1du ZQffzw5nMNS8t0VOs/zKief5k1/+Za9Pu636+HDMJf1/Sx9Yrw24Exa1qLjM7cWDA0lHXy4T XVDNyPNyAuN0pdeePgZaelU1c/M+rl0Y++7JGzG76+bFax8U582KncQu9nMav1gYN/ciEdHZ spsPRT3REpSoUGIpzkg01GIuKk4EAPVNaMfZAgAA X-CMS-MailID: 20190701131155eucas1p1f51297a17dd902fc431f62234ef5e677 X-Msg-Generator: CA X-RootMTR: 20190701131155eucas1p1f51297a17dd902fc431f62234ef5e677 X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20190701131155eucas1p1f51297a17dd902fc431f62234ef5e677 References: <20190701131138.22666-1-l.luba@partner.samsung.com> Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add the chipid label which allows to use it in phandle from other device. Use syscon in compatible to get the regmap of the device register set. The chipid is used in DMC during initialization to compare compatibility. Signed-off-by: Lukasz Luba --- arch/arm/boot/dts/exynos5.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/exynos5.dtsi b/arch/arm/boot/dts/exynos5.dtsi index 67f9b4504a42..4801ca759feb 100644 --- a/arch/arm/boot/dts/exynos5.dtsi +++ b/arch/arm/boot/dts/exynos5.dtsi @@ -35,8 +35,8 @@ #size-cells = <1>; ranges; - chipid@10000000 { - compatible = "samsung,exynos4210-chipid"; + chipid: chipid@10000000 { + compatible = "samsung,exynos4210-chipid", "syscon"; reg = <0x10000000 0x100>; }; From patchwork Mon Jul 1 13:11:36 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lukasz Luba X-Patchwork-Id: 11025899 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 6093318E8 for ; Mon, 1 Jul 2019 13:12:17 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 52062262F2 for ; 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Mon, 1 Jul 2019 13:11:56 +0000 (GMT) Received: from eusmgms2.samsung.com (unknown [182.198.249.180]) by eusmtrp2.samsung.com (KnoxPortal) with ESMTP id 20190701131156eusmtrp2f30a8ab7bc5324a759c65690cd51445a~tSqR5S2G-0788807888eusmtrp2I; Mon, 1 Jul 2019 13:11:56 +0000 (GMT) X-AuditID: cbfec7f5-b8fff700000010e5-e2-5d1a069c9bfd Received: from eusmtip1.samsung.com ( [203.254.199.221]) by eusmgms2.samsung.com (EUCPMTA) with SMTP id A6.EA.04140.B960A1D5; Mon, 1 Jul 2019 14:11:55 +0100 (BST) Received: from AMDC3778.DIGITAL.local (unknown [106.120.51.20]) by eusmtip1.samsung.com (KnoxPortal) with ESMTPA id 20190701131154eusmtip1b0515db8510e5218f7f1f0d6dbdfffc5~tSqQ7MOtP2637626376eusmtip1f; Mon, 1 Jul 2019 13:11:54 +0000 (GMT) From: Lukasz Luba To: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org Cc: mturquette@baylibre.com, sboyd@kernel.org, b.zolnierkie@samsung.com, krzk@kernel.org, kgene@kernel.org, cw00.choi@samsung.com, kyungmin.park@samsung.com, m.szyprowski@samsung.com, s.nawrocki@samsung.com, myungjoo.ham@samsung.com, keescook@chromium.org, tony@atomide.com, jroedel@suse.de, treding@nvidia.com, digetx@gmail.com, gregkh@linuxfoundation.org, willy.mh.wolff.ml@gmail.com, Lukasz Luba Subject: [PATCH v11 7/9] ARM: dts: exynos: add syscon to clock compatible Date: Mon, 1 Jul 2019 15:11:36 +0200 Message-Id: <20190701131138.22666-8-l.luba@partner.samsung.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190701131138.22666-1-l.luba@partner.samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA0VSa0hTYRju29k5O1vNjlPyyyJhIVTQVpTwRdKFkk7+qQj6UYiteTBzW7WT qWU1q5Uzl6WQ4jQNoca01Lm8dfGeUbqlhYpuUi4wzQtmapmtmmfVv+d93uf5nvd9+UhMMogH k3GaM4xWo1BJCRG/6sV3+/p8Ijhqg21Ajipyy3DU83UIR4UtdhyVTLoBulJcRqDsVwU81H5D jTLdnzHkcJQLUMflUQHq061EkxkDOHpbl0+gKWMLQLmO5zz0sMUlQJ2vIlB/qplAzaPXceTp ruCj+neRqP+HH5p5OQh2BNEz01l8eqJXL6BNuk4+XZvnEtBWi4Gg6wtKBbTxyjhBN44/5dE3 bRZAV74+T09ZV+1ffFgUHsOo4s4yWvm2o6LjE44e/JRdmGTMvMvXAT2ZDoQkpDZDW/8Qlg5E pIQyA1hcYSK44iuA7c5UHldMAThX8AVPB+SC5VE1yfEPAPzRXM7753A1OAiviKBksMZy2hsR SOUCaPp00KvBqGoMjvU7gbcRQO2F1xrtmBfzqVDoGnmDe7GY2g478k0Cbr4QWFLesKARUjtg 17RrYTxIGUhYaPmIcaLd8Krd7DMEwJE2mw+vhL9qC3kcZqHOeA9wOAW6Mwt8mq2wua1zYTOM WgvL6uQcvRMWtg4DbmE/2Dvm76WxPzCrKgfjaDFMuybh1GugLeONL2gZfFB6x/c4DfPHG3Hu PNkA6h/piVsgJO9/WBEAFhDEJLDqWIbdpGESZaxCzSZoYmXKk2or+PPzXnvapmvA8/ljTYAi gXSJWOeEURJccZZNVjcBSGLSQHG9eXmURByjSD7HaE9GaxNUDNsEVpB8aZD4/KL3RyRUrOIM E88wpxjt3y6PFAbrgCY6cD5SDz4sCc3xn+1rzWhyZu+rfKxsdog3b3JFC4pUq7uIXdKsWTTc vSu04bbEfWfA/OL0hYjwpVPOud2JtDKgcVnSoU+aNKvsy8gBS9j3sPuRaYaJWdU3V9/FLeF7 KnufpdcCXZcyRSm/dMJQ4vngKf2ZE188N/9kLE4WZZDy2eOKjeswLav4DYwHaPB1AwAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrKIsWRmVeSWpSXmKPExsVy+t/xu7qz2aRiDTbvsbDYOGM9q8X1L89Z LeYfOcdqsfrjY0aL5sXr2Swmn5rLZHGmO9ei//FrZovz5zewW5xtesNucatBxuJjzz1Wi8u7 5rBZfO49wmgx4/w+Jou1R+6yW1w85Wpxu3EFm8XhN+2sFv+ubWSx2H/Fy+L2bz6LbyceMTqI e3z7OonF4/2NVnaP2Q0XWTx2zrrL7rFpVSebx/65a9g9epvfsXkcfLeHyaNvyypGj82nqz0+ b5IL4I7SsynKLy1JVcjILy6xVYo2tDDSM7S00DMysdQzNDaPtTIyVdK3s0lJzcksSy3St0vQ y3h//jprwTnOit7+eSwNjK0cXYwcHBICJhLrtgOZXBxCAksZJU4eucLUxcgJFBeTmLRvOzuE LSzx51oXG0TRJ0aJrdO7WECa2QT0JHasKgSJiwjMYZT42bWNEcRhFjjLLLF7xRuwScICnhJt B88xg9gsAqoSd19dYAWxeQXsJc7OmQ21QV5i9YYDYDWcAg4Sl77eZQOxhYBq1i2+wTiBkW8B I8MqRpHU0uLc9NxiI73ixNzi0rx0veT83E2MwCjcduznlh2MXe+CDzEKcDAq8fBq3JKIFWJN LCuuzD3EKMHBrCTCu3+FZKwQb0piZVVqUX58UWlOavEhRlOgoyYyS4km5wMTRF5JvKGpobmF paG5sbmxmYWSOG+HwMEYIYH0xJLU7NTUgtQimD4mDk6pBkbVImcO9wsRLGadhXzOAudEJ4RF +SSXL9fcPyObJ/qX9J+vXeKri2d8svE3CJF3m6vzuJ1nj1lUkaKhyW7bbxe9nLd67NzZzmU0 cWf9s2mZrnobNtvu5mufu6bg3Kbf2g78n2wLmfquf6zfcDph9m8Z6/Xqy9LqrKfF7t39L7mZ y3aFz+dbe5VYijMSDbWYi4oTAY24bwjYAgAA X-CMS-MailID: 20190701131156eucas1p2b43f31c138c4afdd8a8cd07bb9d04a20 X-Msg-Generator: CA X-RootMTR: 20190701131156eucas1p2b43f31c138c4afdd8a8cd07bb9d04a20 X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20190701131156eucas1p2b43f31c138c4afdd8a8cd07bb9d04a20 References: <20190701131138.22666-1-l.luba@partner.samsung.com> Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP In order to get the clock by phandle and use it with regmap it needs to be compatible with syscon. The DMC driver uses two registers from clock register set and needs the regmap of them. Signed-off-by: Lukasz Luba --- arch/arm/boot/dts/exynos5420.dtsi | 2 +- arch/arm/boot/dts/exynos5800.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi index 5fb2326875dc..d153617ff1a3 100644 --- a/arch/arm/boot/dts/exynos5420.dtsi +++ b/arch/arm/boot/dts/exynos5420.dtsi @@ -173,7 +173,7 @@ }; clock: clock-controller@10010000 { - compatible = "samsung,exynos5420-clock"; + compatible = "samsung,exynos5420-clock", "syscon"; reg = <0x10010000 0x30000>; #clock-cells = <1>; }; diff --git a/arch/arm/boot/dts/exynos5800.dtsi b/arch/arm/boot/dts/exynos5800.dtsi index 57d3b319fd65..0a2b3287ed92 100644 --- a/arch/arm/boot/dts/exynos5800.dtsi +++ b/arch/arm/boot/dts/exynos5800.dtsi @@ -17,7 +17,7 @@ }; &clock { - compatible = "samsung,exynos5800-clock"; + compatible = "samsung,exynos5800-clock", "syscon"; }; &cluster_a15_opp_table { From patchwork Mon Jul 1 13:11:37 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lukasz Luba X-Patchwork-Id: 11025893 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 5C3B113B1 for ; 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Mon, 1 Jul 2019 13:11:55 +0000 (GMT) From: Lukasz Luba To: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org Cc: mturquette@baylibre.com, sboyd@kernel.org, b.zolnierkie@samsung.com, krzk@kernel.org, kgene@kernel.org, cw00.choi@samsung.com, kyungmin.park@samsung.com, m.szyprowski@samsung.com, s.nawrocki@samsung.com, myungjoo.ham@samsung.com, keescook@chromium.org, tony@atomide.com, jroedel@suse.de, treding@nvidia.com, digetx@gmail.com, gregkh@linuxfoundation.org, willy.mh.wolff.ml@gmail.com, Lukasz Luba Subject: [PATCH v11 8/9] ARM: dts: exynos: add DMC device for exynos5422 Date: Mon, 1 Jul 2019 15:11:37 +0200 Message-Id: <20190701131138.22666-9-l.luba@partner.samsung.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190701131138.22666-1-l.luba@partner.samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA0VSaUwTYRD163a322rNWhCmeGAajUoCheiPL4EIRk02/iJqjEeIVtkgkRbs CqLyo0rwxgM8agFBDdIUSIWiCLFyHwJaQSOkHB4YFYsHQolHAtJu1X9v3rx5bzIZmlC8IYPo RN1BTq/TJKkomfh+68+noQVUUFz4B+ciXGG0krh34gOJC5ufkrh0bBjhzNtWCud2FIhw11kt vjDsIrDDcVeCnxwflWCnYSEeOzdE4ue1+RQez25G2Oh4JMLlzYMS3N2xAfcfM1O4afQkiade Vohx3YuNuP/3XDzZ/hbFBLKT7hwx+7UvS8LmGbrFbI1pUMJWWk5TbF1BmYTNzvxCsQ1fHorY 81UWxNo6j7LjlYtjZ++QRcVzSYlpnF69Zrdsnz1TmfJOnd7iqCcMKHvpGSSlgVkNV+x20Rkk oxWMGUHVSC8pFBMIrOVGSijGEYzXFBN/R4ZfVftUJQgKrUOifyOuruKZgqYpJgweWA54BvwZ I4K8j5s9GoKpJuBz/wDyNPwYFq5b8r2uYmYZNExPe7GciQbXHatISAuG0rv1Xl7KxECPe9C7 EjCnaXDebPaGAbMeit2+7fzgU1uVRMALYbqm0OfDgyH7JhJwBgxfKPBpIqGprZv02BDMSrDW qgV6LWRdy0WC+1zo+zzPQxMzMOf+NUKg5XDqhEJQr4Cqc898QQFQUnbVZ85CxZuXvuvkIrht Oi65iIJN/8OKELKgQC6V1yZwfISOOxTGa7R8qi4hbG+ythLNPF7nVNv3B8jds6cRMTRSzZEb BiBOQWrS+MPaRgQ0ofKX15mVcQp5vObwEU6fvEufmsTxjWgBLVYFyo/Oer1TwSRoDnL7OS6F 0//timhp0MwXSO2LK7Q2AyQt+TEGRoezZY8yqlA6tNSkIZV3lseczY31d66LzVsecNVtVubn tD8skkcFv92wVnwguu995/bMX/D1Ul/1DbrTZLqluDzR5Jr+tmWbq0M9v9VmVwfZzt+yhQdv yUCV5hHZJt2CkLR+51YqMl2bHrrq8b2wtliVmN+niQgh9LzmDy6lFw90AwAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrKIsWRmVeSWpSXmKPExsVy+t/xu7pz2KRiDV4fNrHYOGM9q8X1L89Z LeYfOcdqsfrjY0aL5sXr2Swmn5rLZHGmO9ei//FrZovz5zewW5xtesNucatBxuJjzz1Wi8u7 5rBZfO49wmgx4/w+Jou1R+6yW1w85Wpxu3EFm8XhN+2sFv+ubWSx2H/Fy+L2bz6LbyceMTqI e3z7OonF4/2NVnaP2Q0XWTx2zrrL7rFpVSebx/65a9g9epvfsXkcfLeHyaNvyypGj82nqz0+ b5IL4I7SsynKLy1JVcjILy6xVYo2tDDSM7S00DMysdQzNDaPtTIyVdK3s0lJzcksSy3St0vQ y9jbLFnwRL/i6PkDzA2MvSpdjJwcEgImEo/vb2ftYuTiEBJYyihx7cNLJoiEmMSkfdvZIWxh iT/Xutggij4xSqzr7AIq4uBgE9CT2LGqECQuIjCHUeJn1zZGEIdZ4CyzxO4Vb8AmCQt4SMxc NYcZxGYRUJU4+P8/mM0rYC/xetl6qG3yEqs3HACLcwo4SFz6epcNxBYCqlm3+AbjBEa+BYwM qxhFUkuLc9Nziw31ihNzi0vz0vWS83M3MQKjcNuxn5t3MF7aGHyIUYCDUYmHV+OWRKwQa2JZ cWXuIUYJDmYlEd79KyRjhXhTEiurUovy44tKc1KLDzGaAh01kVlKNDkfmCDySuINTQ3NLSwN zY3Njc0slMR5OwQOxggJpCeWpGanphakFsH0MXFwSjUwzsmc5l7Z8UP66aeS0h37pZ1Wv7ht 8tA8LoSjtv9Oinqlg3Ht7VmBz1zOnbj1cLeuwdbbG7jZFOw2bvzxU+h9xhfmSdOdQ86Y97T0 tHusyW7PmtPN6HchR/jmFsebz59kcvT15QU0ZLIw7BOLYkqdECPJXX2isEnv5UKPk8oyDHGL reRiHz5VYinOSDTUYi4qTgQA6nIDVNgCAAA= X-CMS-MailID: 20190701131156eucas1p22e9d3919bd70875cabd410c925c3a52c X-Msg-Generator: CA X-RootMTR: 20190701131156eucas1p22e9d3919bd70875cabd410c925c3a52c X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20190701131156eucas1p22e9d3919bd70875cabd410c925c3a52c References: <20190701131138.22666-1-l.luba@partner.samsung.com> Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add description of Dynamic Memory Controller and PPMU counters. They are used by exynos5422-dmc driver. There is a definition of the memory chip, which is then used during calculation of timings for each OPP. The algorithm in the driver needs these two sets to bound the timings. Signed-off-by: Lukasz Luba --- arch/arm/boot/dts/exynos5420.dtsi | 71 +++++++++++ arch/arm/boot/dts/exynos5422-odroid-core.dtsi | 116 ++++++++++++++++++ 2 files changed, 187 insertions(+) diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi index d153617ff1a3..9dbfe400cdd2 100644 --- a/arch/arm/boot/dts/exynos5420.dtsi +++ b/arch/arm/boot/dts/exynos5420.dtsi @@ -235,6 +235,29 @@ status = "disabled"; }; + dmc: memory-controller@10c20000 { + compatible = "samsung,exynos5422-dmc"; + reg = <0x10c20000 0x100>, <0x10c30000 0x100>; + clocks = <&clock CLK_FOUT_SPLL>, + <&clock CLK_MOUT_SCLK_SPLL>, + <&clock CLK_FF_DOUT_SPLL2>, + <&clock CLK_FOUT_BPLL>, + <&clock CLK_MOUT_BPLL>, + <&clock CLK_SCLK_BPLL>, + <&clock CLK_MOUT_MX_MSPLL_CCORE>, + <&clock CLK_MOUT_MCLK_CDREX>; + clock-names = "fout_spll", + "mout_sclk_spll", + "ff_dout_spll2", + "fout_bpll", + "mout_bpll", + "sclk_bpll", + "mout_mx_mspll_ccore", + "mout_mclk_cdrex"; + samsung,syscon-clk = <&clock>; + status = "disabled"; + }; + nocp_mem0_0: nocp@10ca1000 { compatible = "samsung,exynos5420-nocp"; reg = <0x10CA1000 0x200>; @@ -271,6 +294,54 @@ status = "disabled"; }; + ppmu_dmc0_0: ppmu@10d00000 { + compatible = "samsung,exynos-ppmu"; + reg = <0x10d00000 0x2000>; + clocks = <&clock CLK_PCLK_PPMU_DREX0_0>; + clock-names = "ppmu"; + events { + ppmu_event3_dmc0_0: ppmu-event3-dmc0_0 { + event-name = "ppmu-event3-dmc0_0"; + }; + }; + }; + + ppmu_dmc0_1: ppmu@10d10000 { + compatible = "samsung,exynos-ppmu"; + reg = <0x10d10000 0x2000>; + clocks = <&clock CLK_PCLK_PPMU_DREX0_1>; + clock-names = "ppmu"; + events { + ppmu_event3_dmc0_1: ppmu-event3-dmc0_1 { + event-name = "ppmu-event3-dmc0_1"; + }; + }; + }; + + ppmu_dmc1_0: ppmu@10d60000 { + compatible = "samsung,exynos-ppmu"; + reg = <0x10d60000 0x2000>; + clocks = <&clock CLK_PCLK_PPMU_DREX1_0>; + clock-names = "ppmu"; + events { + ppmu_event3_dmc1_0: ppmu-event3-dmc1_0 { + event-name = "ppmu-event3-dmc1_0"; + }; + }; + }; + + ppmu_dmc1_1: ppmu@10d70000 { + compatible = "samsung,exynos-ppmu"; + reg = <0x10d70000 0x2000>; + clocks = <&clock CLK_PCLK_PPMU_DREX1_1>; + clock-names = "ppmu"; + events { + ppmu_event3_dmc1_1: ppmu-event3-dmc1_1 { + event-name = "ppmu-event3-dmc1_1"; + }; + }; + }; + gsc_pd: power-domain@10044000 { compatible = "samsung,exynos4210-pd"; reg = <0x10044000 0x20>; diff --git a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi index 25d95de15c9b..30e569c13ee7 100644 --- a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi +++ b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi @@ -34,6 +34,97 @@ clock-frequency = <24000000>; }; }; + + dmc_opp_table: opp_table2 { + compatible = "operating-points-v2"; + + opp00 { + opp-hz = /bits/ 64 <165000000>; + opp-microvolt = <875000>; + }; + opp01 { + opp-hz = /bits/ 64 <206000000>; + opp-microvolt = <875000>; + }; + opp02 { + opp-hz = /bits/ 64 <275000000>; + opp-microvolt = <875000>; + }; + opp03 { + opp-hz = /bits/ 64 <413000000>; + opp-microvolt = <887500>; + }; + opp04 { + opp-hz = /bits/ 64 <543000000>; + opp-microvolt = <937500>; + }; + opp05 { + opp-hz = /bits/ 64 <633000000>; + opp-microvolt = <1012500>; + }; + opp06 { + opp-hz = /bits/ 64 <728000000>; + opp-microvolt = <1037500>; + }; + opp07 { + opp-hz = /bits/ 64 <825000000>; + opp-microvolt = <1050000>; + }; + }; + + samsung_K3QF2F20DB: lpddr3 { + compatible = "samsung,K3QF2F20DB", "jedec,lpddr3"; + density = <16384>; + io-width = <32>; + #address-cells = <1>; + #size-cells = <0>; + + tRFC-min-tck = <17>; + tRRD-min-tck = <2>; + tRPab-min-tck = <2>; + tRPpb-min-tck = <2>; + tRCD-min-tck = <3>; + tRC-min-tck = <6>; + tRAS-min-tck = <5>; + tWTR-min-tck = <2>; + tWR-min-tck = <7>; + tRTP-min-tck = <2>; + tW2W-C2C-min-tck = <0>; + tR2R-C2C-min-tck = <0>; + tWL-min-tck = <8>; + tDQSCK-min-tck = <5>; + tRL-min-tck = <14>; + tFAW-min-tck = <5>; + tXSR-min-tck = <12>; + tXP-min-tck = <2>; + tCKE-min-tck = <2>; + tCKESR-min-tck = <2>; + tMRD-min-tck = <5>; + + timings_samsung_K3QF2F20DB_800mhz: lpddr3-timings@800000000 { + compatible = "jedec,lpddr3-timings"; + reg = <800000000>; /* workaround: it shows max-freq */ + min-freq = <100000000>; + tRFC = <65000>; + tRRD = <6000>; + tRPab = <12000>; + tRPpb = <12000>; + tRCD = <10000>; + tRC = <33750>; + tRAS = <23000>; + tWTR = <3750>; + tWR = <7500>; + tRTP = <3750>; + tW2W-C2C = <0>; + tR2R-C2C = <0>; + tFAW = <25000>; + tXSR = <70000>; + tXP = <3750>; + tCKE = <3750>; + tCKESR = <3750>; + tMRD = <7000>; + }; + }; }; &adc { @@ -132,6 +223,15 @@ cpu-supply = <&buck2_reg>; }; +&dmc { + devfreq-events = <&ppmu_event3_dmc0_0>, <&ppmu_event3_dmc0_1>, + <&ppmu_event3_dmc1_0>, <&ppmu_event3_dmc1_1>; + device-handle = <&samsung_K3QF2F20DB>; + operating-points-v2 = <&dmc_opp_table>; + vdd-supply = <&buck1_reg>; + status = "okay"; +}; + &hsi2c_4 { status = "okay"; @@ -540,6 +640,22 @@ }; }; +&ppmu_dmc0_0 { + status = "okay"; +}; + +&ppmu_dmc0_1 { + status = "okay"; +}; + +&ppmu_dmc1_0 { + status = "okay"; +}; + +&ppmu_dmc1_1 { + status = "okay"; +}; + &tmu_cpu0 { vtmu-supply = <&ldo7_reg>; }; From patchwork Mon Jul 1 13:11:38 2019 Content-Type: text/plain; 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Mon, 1 Jul 2019 13:11:56 +0000 (GMT) From: Lukasz Luba To: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org Cc: mturquette@baylibre.com, sboyd@kernel.org, b.zolnierkie@samsung.com, krzk@kernel.org, kgene@kernel.org, cw00.choi@samsung.com, kyungmin.park@samsung.com, m.szyprowski@samsung.com, s.nawrocki@samsung.com, myungjoo.ham@samsung.com, keescook@chromium.org, tony@atomide.com, jroedel@suse.de, treding@nvidia.com, digetx@gmail.com, gregkh@linuxfoundation.org, willy.mh.wolff.ml@gmail.com, Lukasz Luba Subject: [PATCH v11 9/9] ARM: exynos_defconfig: enable DMC driver Date: Mon, 1 Jul 2019 15:11:38 +0200 Message-Id: <20190701131138.22666-10-l.luba@partner.samsung.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190701131138.22666-1-l.luba@partner.samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA0WSe0hTURzHO7tPzeVtiZ5MFJZFVmpW1IkiFAwuQRD2tJJaeVHRTdvVfAUt pVLTfFam+cgi56N8NEyl8knLRzkrU1yGuswyK8w0hmRt3kn/fc73+/2d7zmHQ2OSEcKRDlFE ckqFLExKWuN1z4097oWkY8CmwZR1qCa3ikD9v8YJVNT+ikAVUwaAEu9WkSi7s0CEuq/KUbrh K4Z6eqop9DJhkkKDKic0lfqBQG8ab5NoOq0doNyeZyL0oH2IQr2de5D+oppEbZNXCDT/rgZH TW/3Iv3cMjT7YhR4O7CzM1k4+2PgEsXmq3pxtiFviGJry5NJtqmgkmLTEr+TbMv3JyL2mqYc sI+64tnpWuf9S49Z7wrkwkLOcUrP3aesg2815+ARf4gY3Vw2pQJ3iBRgRUNmK0wwaExsTUsY NYAZn4cWDAnzC8D+nAjBmAawNOkuuThRaLhPCkYpgPPDbSJhYZrQDv+mUgBNk4wHrC8/ax6w Y3IBzP98wJzBmMcY/KZ/D8zGCsYHDnwxUmbGmTWwrmpUZGYx4w11mhlMaHOBFdXNC2xl0l/P DC00QyaZhk19lZZL+MIBoxEIvAJOaDWUwE7wb0ORSGAeqtLuWDLnoSG9wJLZCdu0vYT50Bjj BqsaPQXZB+r0H3GzDJllcODbcrOMmTCr7iYmyGKYdFkipNdBTarOUmQPSytvWDZn4bi6jBIe NBvAT3qfDOCS97+rGIBy4MBF8fIgjvdScNEevEzORymCPM6Ey2uB6eN1zWt/1oOZ16dbAUMD qY1Y9R4GSAjZOT5W3gogjUntxE3qlQEScaAsNo5Thp9URoVxfCtYReNSB3H8kuHjEiZIFsmF clwEp1x0RbSVowrkrc5rrRw7FOPkb6codna9l9lnsxl/Ol5S7Gd/9DAaLBNv3qDWcW62k598 u/0f8tjs9f0fqidatAcjjcszjXHx0SPNJTd18WBtuo0/6zcy1ebO+jA5218eWTraHJd7YpvL xjHke/RR5IWSkyEdE/tcU0Kfde2IRlvGwi/E2Xbkc1KcD5Z5rceUvOwfq2NeqXQDAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrGIsWRmVeSWpSXmKPExsVy+t/xu7pz2aRiDV5uM7bYOGM9q8X1L89Z LeYfOcdqsfrjY0aL5sXr2Swmn5rLZHGmO9ei//FrZovz5zewW5xtesNucatBxuJjzz1Wi8u7 5rBZfO49wmgx4/w+Jou1R+6yW1w85Wpxu3EFm8XhN+2sFv+ubWSx2H/Fy+L2bz6LbyceMTqI e3z7OonF4/2NVnaP2Q0XWTx2zrrL7rFpVSebx/65a9g9epvfsXkcfLeHyaNvyypGj82nqz0+ b5IL4I7SsynKLy1JVcjILy6xVYo2tDDSM7S00DMysdQzNDaPtTIyVdK3s0lJzcksSy3St0vQ y5h5YApLwV/Wigu/J7M3MC5k7WLk5JAQMJGY93gZWxcjF4eQwFJGiTfrjrNDJMQkJu3bDmUL S/y51gVV9IlRonP2A6BuDg42AT2JHasKQeIiAnMYJX52bWMEcZgFzjJL7F7xhgmkW1jAUeLG y59gk1gEVCW2rX8EFucVcJC4sOUrM8QGeYnVGw6A2ZxA8Utf77KB2EIC9hLrFt9gnMDIt4CR YRWjSGppcW56brGhXnFibnFpXrpecn7uJkZgHG479nPzDsZLG4MPMQpwMCrx8GrckogVYk0s K67MPcQowcGsJMK7f4VkrBBvSmJlVWpRfnxRaU5q8SFGU6CjJjJLiSbnA1NEXkm8oamhuYWl obmxubGZhZI4b4fAwRghgfTEktTs1NSC1CKYPiYOTqkGRsFQs88h66S+8FSWSXzZ17Q5tI7f d6XAA8eFNs5/fsZ/Ffv4as7Mj5H6HvN+XxLpOSFjb3UydUpJi99Gj8TZrj+Kg7d+kfi0+WNp 1Nfl8rpC2ce6c1RL8tndFR/uYlOY0RH6+67+BIs3rumndr3yMag5e42JXVa293sFJ6vzi0U7 wo+4J64xUGIpzkg01GIuKk4EAD86CovZAgAA X-CMS-MailID: 20190701131158eucas1p2392cc10dfabbd2628c160d0aa3abecb8 X-Msg-Generator: CA X-RootMTR: 20190701131158eucas1p2392cc10dfabbd2628c160d0aa3abecb8 X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20190701131158eucas1p2392cc10dfabbd2628c160d0aa3abecb8 References: <20190701131138.22666-1-l.luba@partner.samsung.com> Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Enable driver for Exynos5422 Dynamic Memory Controller supporting dynamic frequency and voltage scaling in Exynos5422 SoCs. Signed-off-by: Lukasz Luba --- arch/arm/configs/exynos_defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/configs/exynos_defconfig b/arch/arm/configs/exynos_defconfig index c95c54284da2..4e7e52786174 100644 --- a/arch/arm/configs/exynos_defconfig +++ b/arch/arm/configs/exynos_defconfig @@ -290,6 +290,8 @@ CONFIG_DEVFREQ_GOV_PERFORMANCE=y CONFIG_DEVFREQ_GOV_POWERSAVE=y CONFIG_DEVFREQ_GOV_USERSPACE=y CONFIG_ARM_EXYNOS_BUS_DEVFREQ=y +CONFIG_EXYNOS5422_DMC=y +CONFIG_DDR=y CONFIG_DEVFREQ_EVENT_EXYNOS_NOCP=y CONFIG_EXYNOS_IOMMU=y CONFIG_EXTCON=y