From patchwork Sat Sep 1 20:12:28 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergei Shtylyov X-Patchwork-Id: 10584895 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 45EB617DE for ; Sat, 1 Sep 2018 20:12:36 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 3736E29F88 for ; Sat, 1 Sep 2018 20:12:36 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 2AED429F8B; Sat, 1 Sep 2018 20:12:36 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 1FA2529F8A for ; Sat, 1 Sep 2018 20:12:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726976AbeIBAZi (ORCPT ); Sat, 1 Sep 2018 20:25:38 -0400 Received: from mail-lf1-f53.google.com ([209.85.167.53]:34763 "EHLO mail-lf1-f53.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726986AbeIBAZi (ORCPT ); Sat, 1 Sep 2018 20:25:38 -0400 Received: by mail-lf1-f53.google.com with SMTP id c29-v6so6279084lfj.1 for ; Sat, 01 Sep 2018 13:12:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=cogentembedded-com.20150623.gappssmtp.com; s=20150623; h=from:subject:to:references:organization:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=EY7w41sN8isFyhfj0NaSatPS+uaV0PtkuzS9yIASz7E=; b=hzYjGXZw1TEA0sW6c4tIAloOcqripAM56QM3E8HClmLs0mZpuBXFzsMVmoxaW0m3aC sI4KqnsjmU0b092XPYiL8pe2x5BxKkv+P8KjvDBNBM5Ddm7H5dSlnsfL7zhe8SaK0xJx bS8G1M088rBHp+VOa3LzFt3xrxbTmxiPc2LHCzYxJA+wl238WimfXk7pm787gSBN/Uka Hvu2rarMTa06iXndiVN1g277oPHX+43Rh+8QYXOUWITHnI2D5wf2tbzSu2EITTav32Ji 4R+GQYEVWYJgtW3xa9tAZzbEmh+0vJwpMxSEyy2j6HeDOflLGoJfTUaUQcfxrNmVnWut q/wQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:subject:to:references:organization :message-id:date:user-agent:mime-version:in-reply-to :content-language:content-transfer-encoding; bh=EY7w41sN8isFyhfj0NaSatPS+uaV0PtkuzS9yIASz7E=; b=dP6ESwUSHqcwL9+eu+Gw+IJjSHj0bJBk93OwJDvxhXpL2PrtjWG0bGKsSZ1kSA7/ic +9SgTkMiRFDXKjy2W4vhlaAVLjjXp5RxMp3dYc/uolR9hMzhI3Q9jUMhmRTiy3xFG5+q DWRTanES8YwVArKtJXg/80+7DTIsIC0zv0C9+hx9lbM2hZEmWkcOwBoJEyGzeDdzqaVo 4x3adGfEQCk8u5VrfRPSOoGuy60kh3FTN8xN64x/aMofS4pTO4ClB2o2UrLO9rB/aj1I CklU2V0IlSDXY0n3HLB6K1kA+nnTqq5hYARfhCXTEoaUauNR1LmXanpZtvrvrv1B00CE diFg== X-Gm-Message-State: APzg51DzgLvcdD25RPzOD+ES4EDNZRDeMHaO/kGDw93sxRAeOd5vp4l1 EtHgk7x03uNBMrRux2pCUQCSxBtbl0M= X-Google-Smtp-Source: ANB0VdZntj9jn/N8W0CLi9796zwwUPWmeqxl0m2eW9FfVxJ57ba2fwdEhgBOdiXU+Q6XBae98u2Z4g== X-Received: by 2002:a19:3fcd:: with SMTP id m196-v6mr845102lfa.11.1535832751225; Sat, 01 Sep 2018 13:12:31 -0700 (PDT) Received: from wasted.cogentembedded.com ([31.173.80.63]) by smtp.gmail.com with ESMTPSA id w200-v6sm2561041lff.71.2018.09.01.13.12.28 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 01 Sep 2018 13:12:29 -0700 (PDT) From: Sergei Shtylyov Subject: [PATCH v2] clk: renesas: r8a77970: add SD0H/SD0 clocks for SDHI To: "linux-renesas-soc@vger.kernel.org" , Michael Turquette , Stephen Boyd , Geert Uytterhoeven , linux-clk@vger.kernel.org References: <5b7895ac-11c1-ac2d-837b-56726bc6226a@cogentembedded.com> Organization: Cogent Embedded Message-ID: <4f401a77-ae41-5a6e-3e10-51dad300e183@cogentembedded.com> Date: Sat, 1 Sep 2018 23:12:28 +0300 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.2.1 MIME-Version: 1.0 In-Reply-To: <5b7895ac-11c1-ac2d-837b-56726bc6226a@cogentembedded.com> Content-Language: en-MW Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP On R-Car V3M (AKA R8A77970), the SD0CKCR is laid out differently than on the other R-Car gen3 SoCs. In fact, the layout is the same as on R-Car gen2 SoCs, so we'll need to copy the divisor tables from the R-Car gen2 driver. We'll also need to support the SoC specific clock types, thus we're adding CLK_TYPE_GEN3_SOC_BASE at the end of 'enum rcar_gen3_clk_types', declare SD0H/SDH clocks in 'enum r8a77970_clk_types', and handle those clocks in the overridden cpg_clk_register() method; then, finally, add the SD-IF module clock (derived from the SD0 clock). Signed-off-by: Sergei Shtylyov Reviewed-by: Geert Uytterhoeven --- This patch is against the 'clk-renesas' branch of Geert's 'renesas-drivers.git' repo. Changes in version 2: - made r8a77970_cpg_clk_register() *static*; - #define'd CPG_SD0CKCR and used it instead of the bare number. drivers/clk/renesas/r8a77970-cpg-mssr.c | 66 +++++++++++++++++++++++++++++++- drivers/clk/renesas/rcar-gen3-cpg.h | 3 + 2 files changed, 67 insertions(+), 2 deletions(-) Index: renesas-drivers/drivers/clk/renesas/r8a77970-cpg-mssr.c =================================================================== --- renesas-drivers.orig/drivers/clk/renesas/r8a77970-cpg-mssr.c +++ renesas-drivers/drivers/clk/renesas/r8a77970-cpg-mssr.c @@ -1,7 +1,7 @@ /* * r8a77970 Clock Pulse Generator / Module Standby and Software Reset * - * Copyright (C) 2017 Cogent Embedded Inc. + * Copyright (C) 2017-2018 Cogent Embedded Inc. * * Based on r8a7795-cpg-mssr.c * @@ -12,6 +12,7 @@ * the Free Software Foundation; version 2 of the License. */ +#include #include #include #include @@ -22,6 +23,13 @@ #include "renesas-cpg-mssr.h" #include "rcar-gen3-cpg.h" +#define CPG_SD0CKCR 0x0074 + +enum r8a77970_clk_types { + CLK_TYPE_R8A77970_SD0H = CLK_TYPE_GEN3_SOC_BASE, + CLK_TYPE_R8A77970_SD0, +}; + enum clk_ids { /* Core Clock Outputs exported to DT */ LAST_DT_CORE_CLK = R8A77970_CLK_OSC, @@ -42,6 +50,20 @@ enum clk_ids { MOD_CLK_BASE }; +static spinlock_t cpg_lock; + +static const struct clk_div_table cpg_sd0h_div_table[] = { + { 0, 2 }, { 1, 3 }, { 2, 4 }, { 3, 6 }, + { 4, 8 }, { 5, 12 }, { 6, 16 }, { 7, 18 }, + { 8, 24 }, { 10, 36 }, { 11, 48 }, { 0, 0 }, +}; + +static const struct clk_div_table cpg_sd0_div_table[] = { + { 4, 8 }, { 5, 12 }, { 6, 16 }, { 7, 18 }, + { 8, 24 }, { 10, 36 }, { 11, 48 }, { 12, 10 }, + { 0, 0 }, +}; + static const struct cpg_core_clk r8a77970_core_clks[] __initconst = { /* External Clock Inputs */ DEF_INPUT("extal", CLK_EXTAL), @@ -68,6 +90,10 @@ static const struct cpg_core_clk r8a7797 DEF_FIXED("s2d2", R8A77970_CLK_S2D2, CLK_PLL1_DIV2, 12, 1), DEF_FIXED("s2d4", R8A77970_CLK_S2D4, CLK_PLL1_DIV2, 24, 1), + DEF_BASE("sd0h", R8A77970_CLK_SD0H, CLK_TYPE_R8A77970_SD0H, + CLK_PLL1_DIV2), + DEF_BASE("sd0", R8A77970_CLK_SD0, CLK_TYPE_R8A77970_SD0, CLK_PLL1_DIV2), + DEF_FIXED("cl", R8A77970_CLK_CL, CLK_PLL1_DIV2, 48, 1), DEF_FIXED("cp", R8A77970_CLK_CP, CLK_EXTAL, 2, 1), @@ -92,6 +118,7 @@ static const struct mssr_mod_clk r8a7797 DEF_MOD("mfis", 213, R8A77970_CLK_S2D2), DEF_MOD("sys-dmac2", 217, R8A77970_CLK_S2D1), DEF_MOD("sys-dmac1", 218, R8A77970_CLK_S2D1), + DEF_MOD("sd-if", 314, R8A77970_CLK_SD0), DEF_MOD("rwdt", 402, R8A77970_CLK_R), DEF_MOD("intc-ex", 407, R8A77970_CLK_CP), DEF_MOD("intc-ap", 408, R8A77970_CLK_S2D1), @@ -173,11 +200,46 @@ static int __init r8a77970_cpg_mssr_init if (error) return error; + spin_lock_init(&cpg_lock); + cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)]; return rcar_gen3_cpg_init(cpg_pll_config, CLK_EXTALR, cpg_mode); } +static struct clk * __init r8a77970_cpg_clk_register(struct device *dev, + const struct cpg_core_clk *core, const struct cpg_mssr_info *info, + struct clk **clks, void __iomem *base, + struct raw_notifier_head *notifiers) +{ + const struct clk_div_table *table; + const struct clk *parent; + unsigned int shift; + + switch (core->type) { + case CLK_TYPE_R8A77970_SD0H: + table = cpg_sd0h_div_table; + shift = 8; + break; + case CLK_TYPE_R8A77970_SD0: + table = cpg_sd0_div_table; + shift = 4; + break; + default: + return rcar_gen3_cpg_clk_register(dev, core, info, clks, base, + notifiers); + } + + parent = clks[core->parent]; + if (IS_ERR(parent)) + return ERR_CAST(parent); + + return clk_register_divider_table(NULL, core->name, + __clk_get_name(parent), 0, + base + CPG_SD0CKCR, + shift, 4, 0, table, &cpg_lock); +} + const struct cpg_mssr_info r8a77970_cpg_mssr_info __initconst = { /* Core Clocks */ .core_clks = r8a77970_core_clks, @@ -196,5 +258,5 @@ const struct cpg_mssr_info r8a77970_cpg_ /* Callbacks */ .init = r8a77970_cpg_mssr_init, - .cpg_clk_register = rcar_gen3_cpg_clk_register, + .cpg_clk_register = r8a77970_cpg_clk_register, }; Index: renesas-drivers/drivers/clk/renesas/rcar-gen3-cpg.h =================================================================== --- renesas-drivers.orig/drivers/clk/renesas/rcar-gen3-cpg.h +++ renesas-drivers/drivers/clk/renesas/rcar-gen3-cpg.h @@ -25,6 +25,9 @@ enum rcar_gen3_clk_types { CLK_TYPE_GEN3_Z2, CLK_TYPE_GEN3_OSC, /* OSC EXTAL predivider and fixed divider */ CLK_TYPE_GEN3_RCKSEL, /* Select parent/divider using RCKCR.CKSEL */ + + /* SoC specific definitions start here */ + CLK_TYPE_GEN3_SOC_BASE, }; #define DEF_GEN3_SD(_name, _id, _parent, _offset) \