From patchwork Wed Jul 10 18:37:12 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Janakarajan Natarajan X-Patchwork-Id: 11038799 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 633FA14C0 for ; Wed, 10 Jul 2019 18:37:22 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 5847E284DC for ; Wed, 10 Jul 2019 18:37:22 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 4B331289DC; Wed, 10 Jul 2019 18:37:22 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id DEEC2284DC for ; Wed, 10 Jul 2019 18:37:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728183AbfGJShV (ORCPT ); Wed, 10 Jul 2019 14:37:21 -0400 Received: from mail-eopbgr740045.outbound.protection.outlook.com ([40.107.74.45]:40544 "EHLO NAM01-BN3-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1728162AbfGJShS (ORCPT ); Wed, 10 Jul 2019 14:37:18 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amdcloud.onmicrosoft.com; s=selector1-amdcloud-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=1EuYjhv0K981eq+CHQGYecMhyIdmi6r6HsOp6EUH6sg=; b=rU0PuqznwLpfkwvTBg8Fy9PfPIWcRJBbcNBLOXqQbIwCTH9NM6bf2tm9Q/UjVq9sANT0AfykQ11FkXr4YuFCLCfxuZnyyQCBWSKCeG5z5+rHyMiBYZWLO7TYZZCg67J+dD0Q/aemByYf3OIP549nXME4NRyzhGKMpaJR/bOL3So= Received: from SN6PR12MB2736.namprd12.prod.outlook.com (52.135.107.27) by SN6PR12MB2846.namprd12.prod.outlook.com (52.135.103.161) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2052.20; Wed, 10 Jul 2019 18:37:14 +0000 Received: from SN6PR12MB2736.namprd12.prod.outlook.com ([fe80::a475:e612:8e1e:ed28]) by SN6PR12MB2736.namprd12.prod.outlook.com ([fe80::a475:e612:8e1e:ed28%3]) with mapi id 15.20.2052.020; Wed, 10 Jul 2019 18:37:14 +0000 From: "Natarajan, Janakarajan" To: "linux-acpi@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "linux-pm@vger.kernel.org" , "devel@acpica.org" CC: "Rafael J . Wysocki" , Len Brown , Viresh Kumar , Robert Moore , Erik Schmauss , "Ghannam, Yazen" , "Natarajan, Janakarajan" Subject: [PATCHv3 1/6] acpi/cppc: Add macros for CPPC register checks Thread-Topic: [PATCHv3 1/6] acpi/cppc: Add macros for CPPC register checks Thread-Index: AQHVN059RHJ8UgAi2UmQapw4p1j2fg== Date: Wed, 10 Jul 2019 18:37:12 +0000 Message-ID: <668aa711c3c455e926c066a27cb62720399fb2df.1562781484.git.Janakarajan.Natarajan@amd.com> References: In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: SN4PR0201CA0064.namprd02.prod.outlook.com (2603:10b6:803:20::26) To SN6PR12MB2736.namprd12.prod.outlook.com (2603:10b6:805:77::27) authentication-results: spf=none (sender IP is ) smtp.mailfrom=Janakarajan.Natarajan@amd.com; x-ms-exchange-messagesentrepresentingtype: 1 x-mailer: git-send-email 2.17.1 x-originating-ip: [165.204.78.2] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 519148af-081f-4840-79ed-08d705659fca x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: BCL:0;PCL:0;RULEID:(2390118)(7020095)(4652040)(8989299)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(5600148)(711020)(4605104)(1401327)(4618075)(2017052603328)(7193020);SRVR:SN6PR12MB2846; x-ms-traffictypediagnostic: SN6PR12MB2846: x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:4941; x-forefront-prvs: 0094E3478A x-forefront-antispam-report: SFV:NSPM;SFS:(10009020)(4636009)(346002)(366004)(396003)(136003)(376002)(39860400002)(199004)(189003)(6512007)(14454004)(71190400001)(71200400001)(7736002)(25786009)(26005)(186003)(102836004)(76176011)(52116002)(486006)(50226002)(6436002)(64756008)(66446008)(53936002)(386003)(99286004)(6506007)(2201001)(66946007)(66476007)(8676002)(305945005)(81166006)(68736007)(6116002)(8936002)(81156014)(86362001)(3846002)(66556008)(6486002)(110136005)(316002)(2501003)(11346002)(446003)(2616005)(5660300002)(256004)(4326008)(36756003)(476003)(118296001)(478600001)(2906002)(66066001)(54906003);DIR:OUT;SFP:1101;SCL:1;SRVR:SN6PR12MB2846;H:SN6PR12MB2736.namprd12.prod.outlook.com;FPR:;SPF:None;LANG:en;PTR:InfoNoRecords;A:1;MX:1; received-spf: None (protection.outlook.com: amd.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: +RaGSnKTBl89QJVfOEsOCET37Yq9J8a3Bh0ECgh3YcbWl+8Lg+iNIqCIVKLxaN5bbnnq8/dgVQGhFADfysO+nN8ZnLX301bbYe9iBBApJc0NvjTiK1LVLiXpfsA+GxVq1K7lCfLfqT2vt5buBqNCfoejsSZIGAfDoJntMYebnJ/AxxBMlNuuoXGPZCH2xewhewA6k6TxEs6H4uT7lNOyP7F6jj5Io634nV6rpkJ0CkX/4C5lbJd/CBen+Pr/TgCUIfdBD02+vkDkuBHJb713/9NjKFcczy2plLNRGmXIfMce7RgOMc+hHdjyY698CvLKNeXbfs78F9K37xNw9wCPkt/+6eQf5u44DQoPrmPwqidf42uPYlYDBpEbvUNSQvWuzrGehqwu4EYoTT6AK/V1kmwnIi/PADImgKhJrk8wNY4= MIME-Version: 1.0 X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: 519148af-081f-4840-79ed-08d705659fca X-MS-Exchange-CrossTenant-originalarrivaltime: 10 Jul 2019 18:37:13.0355 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: jnataraj@amd.com X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN6PR12MB2846 Sender: linux-acpi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-acpi@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Introduce two macros to help with checking the support for optional CPPC registers. CPC_SUP_BUFFER_ONLY ensures that an expected BUFFER only register has a register type of ACPI_TYPE_BUFFER and is not NULL. REG_SUPPORTED decides which check to perform based the expected type of the CPPC register. Signed-off-by: Janakarajan Natarajan --- drivers/acpi/cppc_acpi.c | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/drivers/acpi/cppc_acpi.c b/drivers/acpi/cppc_acpi.c index 15f103d7532b..c43de65531ae 100644 --- a/drivers/acpi/cppc_acpi.c +++ b/drivers/acpi/cppc_acpi.c @@ -111,6 +111,14 @@ static DEFINE_PER_CPU(struct cpc_desc *, cpc_desc_ptr); #define CPC_SUPPORTED(cpc) ((cpc)->type == ACPI_TYPE_INTEGER ? \ !!(cpc)->cpc_entry.int_value : \ !IS_NULL_REG(&(cpc)->cpc_entry.reg)) + +/* + * Evaluates to True if an optional cpc field is supported and is + * BUFFER only + */ +#define CPC_SUP_BUFFER_ONLY(cpc) ((cpc)->type == ACPI_TYPE_BUFFER && \ + !IS_NULL_REG(&(cpc)->cpc_entry.reg)) + /* * Arbitrary Retries in case the remote processor is slow to respond * to PCC commands. Keeping it high enough to cover emulators where @@ -705,6 +713,26 @@ static bool is_cppc_supported(int revision, int num_ent) * } */ +static bool is_buf_only(int reg_idx) +{ + switch (reg_idx) { + case HIGHEST_PERF: + case NOMINAL_PERF: + case LOW_NON_LINEAR_PERF: + case LOWEST_PERF: + case CTR_WRAP_TIME: + case AUTO_SEL_ENABLE: + case REFERENCE_PERF: + return false; + default: + return true; + } +} + +#define REG_SUPPORTED(cpc, idx) (is_buf_only(idx) ? \ + CPC_SUP_BUFFER_ONLY(&cpc->cpc_regs[idx]) : \ + CPC_SUPPORTED(&cpc->cpc_regs[idx])) + /** * acpi_cppc_processor_probe - Search for per CPU _CPC objects. * @pr: Ptr to acpi_processor containing this CPU's logical ID. From patchwork Wed Jul 10 18:37:13 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Janakarajan Natarajan X-Patchwork-Id: 11038815 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 19D1C112C for ; Wed, 10 Jul 2019 18:37:48 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 0F308288F6 for ; Wed, 10 Jul 2019 18:37:48 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 0332B289DC; Wed, 10 Jul 2019 18:37:47 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 8D19B289D6 for ; Wed, 10 Jul 2019 18:37:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728313AbfGJShl (ORCPT ); Wed, 10 Jul 2019 14:37:41 -0400 Received: from mail-eopbgr740045.outbound.protection.outlook.com ([40.107.74.45]:40544 "EHLO NAM01-BN3-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1728168AbfGJShW (ORCPT ); Wed, 10 Jul 2019 14:37:22 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amdcloud.onmicrosoft.com; s=selector1-amdcloud-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=4G1+O/qT6Yvto1oKEvQiiFZ3riOC1p6vsSY6aymBSmI=; b=YBVg0daAD/JJTDOkkH2XCeBIC/xODiC+ToZfwLRGL6mDplwCZETIJi7KOWts+at4/KiVqaQmAwAeTtqfc6Imh3CJUsYWDHzoiF8rfC+iiGjfa5M0pAssoQQE+I+LapNoh8+4zebK3DOR1XMx+XUg5RWo8iB83tO7ZBxMOMEGnOw= Received: from SN6PR12MB2736.namprd12.prod.outlook.com (52.135.107.27) by SN6PR12MB2846.namprd12.prod.outlook.com (52.135.103.161) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2052.20; Wed, 10 Jul 2019 18:37:15 +0000 Received: from SN6PR12MB2736.namprd12.prod.outlook.com ([fe80::a475:e612:8e1e:ed28]) by SN6PR12MB2736.namprd12.prod.outlook.com ([fe80::a475:e612:8e1e:ed28%3]) with mapi id 15.20.2052.020; Wed, 10 Jul 2019 18:37:14 +0000 From: "Natarajan, Janakarajan" To: "linux-acpi@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "linux-pm@vger.kernel.org" , "devel@acpica.org" CC: "Rafael J . Wysocki" , Len Brown , Viresh Kumar , Robert Moore , Erik Schmauss , "Ghannam, Yazen" , "Natarajan, Janakarajan" Subject: [PATCHv3 2/6] acpi/cppc: Ensure only supported CPPC sysfs entries are created Thread-Topic: [PATCHv3 2/6] acpi/cppc: Ensure only supported CPPC sysfs entries are created Thread-Index: AQHVN05+WQrgmSia/kKIgKq6JMN9/g== Date: Wed, 10 Jul 2019 18:37:13 +0000 Message-ID: <10d1f1e3ad8d6faeaa7ca70ac800ffea371f8707.1562781484.git.Janakarajan.Natarajan@amd.com> References: In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: SN4PR0201CA0064.namprd02.prod.outlook.com (2603:10b6:803:20::26) To SN6PR12MB2736.namprd12.prod.outlook.com (2603:10b6:805:77::27) authentication-results: spf=none (sender IP is ) smtp.mailfrom=Janakarajan.Natarajan@amd.com; x-ms-exchange-messagesentrepresentingtype: 1 x-mailer: git-send-email 2.17.1 x-originating-ip: [165.204.78.2] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 39218fcf-a9c2-46b6-0877-08d70565a054 x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: BCL:0;PCL:0;RULEID:(2390118)(7020095)(4652040)(8989299)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(5600148)(711020)(4605104)(1401327)(4618075)(2017052603328)(7193020);SRVR:SN6PR12MB2846; x-ms-traffictypediagnostic: SN6PR12MB2846: x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:2803; x-forefront-prvs: 0094E3478A x-forefront-antispam-report: SFV:NSPM;SFS:(10009020)(4636009)(346002)(366004)(396003)(136003)(376002)(39860400002)(199004)(189003)(6512007)(14454004)(71190400001)(71200400001)(7736002)(25786009)(26005)(186003)(102836004)(76176011)(52116002)(486006)(50226002)(6436002)(64756008)(66446008)(53936002)(386003)(99286004)(6506007)(2201001)(66946007)(66476007)(8676002)(305945005)(81166006)(68736007)(6116002)(8936002)(81156014)(86362001)(3846002)(66556008)(6486002)(110136005)(316002)(2501003)(11346002)(446003)(2616005)(5660300002)(256004)(4326008)(36756003)(476003)(118296001)(478600001)(2906002)(66066001)(54906003);DIR:OUT;SFP:1101;SCL:1;SRVR:SN6PR12MB2846;H:SN6PR12MB2736.namprd12.prod.outlook.com;FPR:;SPF:None;LANG:en;PTR:InfoNoRecords;A:1;MX:1; received-spf: None (protection.outlook.com: amd.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: ouLVYekNv7eZc3awB7XnDkToPy6uaXsmrUkpNxu9Jxipmxzg2Sq0iXTnSnFg0+prnRdgDlJh5dUgcQ9j8wEMQluQsEp/8q3WMOvc7hXZdnnRRwnzTduudfvUCD1CAPDtBFZPXqtoqkU1eCysOglE5HOrH/PPkdnYoKJRhsFEmzZAYffReQTgcZaWz7C1SJ57SCekZOMCQXpB8bFXa2c5mjQ3EXpaO+jf2Mf15eCs6ucpkjFFlycLT4RjY6IzQ9jomBOrTqEbWOuxLVZVWnp2uxOUxVLiLxSKrMwkMV1lSSInEsuxUg4mSBwBJk5rWwZh9LzLtwrb81VvZsB6J9P75IkFJ6B78OwXk3Wv0VhoTbPXvpCr4QtkUtHpan9jUzc7DhLl+L5ikkyZzATnIMblix1VfDDzyFywSSEYsYy94NA= MIME-Version: 1.0 X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: 39218fcf-a9c2-46b6-0877-08d70565a054 X-MS-Exchange-CrossTenant-originalarrivaltime: 10 Jul 2019 18:37:13.8980 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: jnataraj@amd.com X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN6PR12MB2846 Sender: linux-acpi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-acpi@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add attributes only for registers that are supported by the platform. This prevents unsupported, optional registers from having sysfs entries created. Signed-off-by: Janakarajan Natarajan --- drivers/acpi/cppc_acpi.c | 82 +++++++++++++++++++++++++++++++++------- 1 file changed, 68 insertions(+), 14 deletions(-) diff --git a/drivers/acpi/cppc_acpi.c b/drivers/acpi/cppc_acpi.c index c43de65531ae..53a9dc9960b6 100644 --- a/drivers/acpi/cppc_acpi.c +++ b/drivers/acpi/cppc_acpi.c @@ -183,22 +183,8 @@ static ssize_t show_feedback_ctrs(struct kobject *kobj, } define_one_cppc_ro(feedback_ctrs); -static struct attribute *cppc_attrs[] = { - &feedback_ctrs.attr, - &reference_perf.attr, - &wraparound_time.attr, - &highest_perf.attr, - &lowest_perf.attr, - &lowest_nonlinear_perf.attr, - &nominal_perf.attr, - &nominal_freq.attr, - &lowest_freq.attr, - NULL -}; - static struct kobj_type cppc_ktype = { .sysfs_ops = &kobj_sysfs_ops, - .default_attrs = cppc_attrs, }; static int check_pcc_chan(int pcc_ss_id, bool chk_err_bit) @@ -733,6 +719,69 @@ static bool is_buf_only(int reg_idx) CPC_SUP_BUFFER_ONLY(&cpc->cpc_regs[idx]) : \ CPC_SUPPORTED(&cpc->cpc_regs[idx])) +static int is_mandatory_reg(int reg_idx) +{ + switch (reg_idx) { + case HIGHEST_PERF: + case NOMINAL_PERF: + case LOW_NON_LINEAR_PERF: + case LOWEST_PERF: + case REFERENCE_CTR: + case DELIVERED_CTR: + return 1; + } + + return 0; +} + +#define MANDATORY_REG_CNT 6 + +static int set_cppc_attrs(struct cpc_desc *cpc, int entries) +{ + int i, attr_i = 0, opt_reg_cnt; + static struct attribute **cppc_attrs; + + cppc_attrs = kcalloc(entries, sizeof(*cppc_attrs), GFP_KERNEL); + if (!cppc_attrs) + return -ENOMEM; + + /* Set optional regs */ + opt_reg_cnt = entries - MANDATORY_REG_CNT; + for (i = 0; i < MAX_CPC_REG_ENT && attr_i < opt_reg_cnt; i++) { + if (is_mandatory_reg(i) || !REG_SUPPORTED(cpc, i)) + continue; + + switch (i) { + case NOMINAL_FREQ: + cppc_attrs[attr_i++] = &nominal_freq.attr; + break; + case LOWEST_FREQ: + cppc_attrs[attr_i++] = &lowest_freq.attr; + break; + case REFERENCE_PERF: + cppc_attrs[attr_i++] = &reference_perf.attr; + break; + case CTR_WRAP_TIME: + cppc_attrs[attr_i++] = &wraparound_time.attr; + break; + } + } + + /* Set mandatory regs */ + cppc_attrs[attr_i++] = &highest_perf.attr; + cppc_attrs[attr_i++] = &nominal_perf.attr; + cppc_attrs[attr_i++] = &lowest_nonlinear_perf.attr; + cppc_attrs[attr_i++] = &lowest_perf.attr; + + /* Set feedback_ctr sysfs entry */ + cppc_attrs[attr_i] = &feedback_ctrs.attr; + + /* Set kobj_type member */ + cppc_ktype.default_attrs = cppc_attrs; + + return 0; +} + /** * acpi_cppc_processor_probe - Search for per CPU _CPC objects. * @pr: Ptr to acpi_processor containing this CPU's logical ID. @@ -887,6 +936,10 @@ int acpi_cppc_processor_probe(struct acpi_processor *pr) /* Plug PSD data into this CPU's CPC descriptor. */ per_cpu(cpc_desc_ptr, pr->id) = cpc_ptr; + ret = set_cppc_attrs(cpc_ptr, num_ent - 2); + if (ret) + goto out_free; + ret = kobject_init_and_add(&cpc_ptr->kobj, &cppc_ktype, &cpu_dev->kobj, "acpi_cppc"); if (ret) { @@ -948,6 +1001,7 @@ void acpi_cppc_processor_exit(struct acpi_processor *pr) iounmap(addr); } + kfree(cppc_ktype.default_attrs); kobject_put(&cpc_ptr->kobj); kfree(cpc_ptr); } From patchwork Wed Jul 10 18:37:14 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Janakarajan Natarajan X-Patchwork-Id: 11038823 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id E55E5112C for ; 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Wysocki" , Len Brown , Viresh Kumar , Robert Moore , Erik Schmauss , "Ghannam, Yazen" , "Ghannam, Yazen" , "Natarajan, Janakarajan" Subject: [PATCHv3 3/6] acpi/cppc: Rework cppc_set_perf() to use cppc_regs index Thread-Topic: [PATCHv3 3/6] acpi/cppc: Rework cppc_set_perf() to use cppc_regs index Thread-Index: AQHVN05+ZGHRO/MraUWKit0+yoLPzQ== Date: Wed, 10 Jul 2019 18:37:14 +0000 Message-ID: <9bc091f450bea98454685e6118a37d0b32b7db96.1562781484.git.Janakarajan.Natarajan@amd.com> References: In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: SN4PR0201CA0064.namprd02.prod.outlook.com (2603:10b6:803:20::26) To SN6PR12MB2736.namprd12.prod.outlook.com (2603:10b6:805:77::27) authentication-results: spf=none (sender IP is ) smtp.mailfrom=Janakarajan.Natarajan@amd.com; x-ms-exchange-messagesentrepresentingtype: 1 x-mailer: git-send-email 2.17.1 x-originating-ip: [165.204.78.2] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 567b6f4d-c86d-4e51-aa56-08d70565a100 x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: BCL:0;PCL:0;RULEID:(2390118)(7020095)(4652040)(8989299)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(5600148)(711020)(4605104)(1401327)(4618075)(2017052603328)(7193020);SRVR:SN6PR12MB2621; x-ms-traffictypediagnostic: SN6PR12MB2621: x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:8273; x-forefront-prvs: 0094E3478A x-forefront-antispam-report: SFV:NSPM;SFS:(10009020)(4636009)(346002)(396003)(39860400002)(366004)(376002)(136003)(199004)(189003)(50226002)(4326008)(81156014)(81166006)(71200400001)(14454004)(71190400001)(476003)(11346002)(446003)(68736007)(2616005)(6116002)(3846002)(486006)(256004)(305945005)(7736002)(478600001)(14444005)(25786009)(5660300002)(36756003)(2906002)(76176011)(53936002)(66476007)(66556008)(64756008)(66066001)(66446008)(6512007)(2501003)(8936002)(118296001)(6436002)(6486002)(8676002)(66946007)(316002)(52116002)(102836004)(2201001)(6506007)(99286004)(26005)(386003)(86362001)(110136005)(54906003)(186003);DIR:OUT;SFP:1101;SCL:1;SRVR:SN6PR12MB2621;H:SN6PR12MB2736.namprd12.prod.outlook.com;FPR:;SPF:None;LANG:en;PTR:InfoNoRecords;A:1;MX:1; received-spf: None (protection.outlook.com: amd.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: vfxzYu+k6u5t8q5E8xnFOoFbhQpwHoFvWKPeEN/xUuW/2NwFaR6SQxWgYmrkxNHJ3165vq6aSK/tcHwFNEaMIqAaWKkXvqto7oaMMqLx4nKVVHmPnfkqoSluM88OXBKmLsXKICHkwz8vKgnkVxiCaf2JEYZZ1H5BD8Oj0GVvro5yu2/x07vj2hxBt3Qyh+iZQXlZVUwXL6WngrIRVivIhHmwRuQ+ZWf/g92QGVqLxRz+rDKgQ9fg+KztIensggFV6JIX6v1IIXJmhoX6r/JrA0qbq57UK4O6Zr0n7Ng99U84f+3g5CTyELuicerKrEYPam5stmRRXOhKdIYyi74qCaQ3Q49KIp4wj8e4hpBjKDLFs8JFcK2jAsU2yfNEBochiH0l/KrSWUBsE1KBVWikLi82txsuPX/7mKh3otIYp0c= MIME-Version: 1.0 X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: 567b6f4d-c86d-4e51-aa56-08d70565a100 X-MS-Exchange-CrossTenant-originalarrivaltime: 10 Jul 2019 18:37:15.0034 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: jnataraj@amd.com X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN6PR12MB2621 Sender: linux-acpi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-acpi@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Yazen Ghannam The cppc_set_perf() currently only works for DESIRED_PERF. To make it generic, pass in the index of the register being accessed. Also, rename cppc_set_perf() to cppc_set_reg(). This is in preparation for it to be used for more than just the DESIRED_PERF register. Signed-off-by: Yazen Ghannam [ carved out into a patch, cleaned up, productized ] Signed-off-by: Janakarajan Natarajan --- drivers/acpi/cppc_acpi.c | 36 ++++++++++++++++++++++------------ drivers/cpufreq/cppc_cpufreq.c | 6 +++--- include/acpi/cppc_acpi.h | 2 +- 3 files changed, 28 insertions(+), 16 deletions(-) diff --git a/drivers/acpi/cppc_acpi.c b/drivers/acpi/cppc_acpi.c index 53a9dc9960b6..c13dacea4a8b 100644 --- a/drivers/acpi/cppc_acpi.c +++ b/drivers/acpi/cppc_acpi.c @@ -56,7 +56,7 @@ struct cppc_pcc_data { /* * Lock to provide controlled access to the PCC channel. * - * For performance critical usecases(currently cppc_set_perf) + * For performance-critical usecases(currently cppc_set_reg) * We need to take read_lock and check if channel belongs to OSPM * before reading or writing to PCC subspace * We need to take write_lock before transferring the channel @@ -1341,26 +1341,38 @@ int cppc_get_perf_ctrs(int cpunum, struct cppc_perf_fb_ctrs *perf_fb_ctrs) EXPORT_SYMBOL_GPL(cppc_get_perf_ctrs); /** - * cppc_set_perf - Set a CPU's performance controls. - * @cpu: CPU for which to set performance controls. + * cppc_set_reg - Set the CPUs control register. + * @cpu: CPU for which to set the register. * @perf_ctrls: ptr to cppc_perf_ctrls. See cppc_acpi.h + * @reg_idx: Index of the register being accessed * * Return: 0 for success, -ERRNO otherwise. */ -int cppc_set_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls) +int cppc_set_reg(int cpu, struct cppc_perf_ctrls *perf_ctrls, + enum cppc_regs reg_idx) { struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpu); - struct cpc_register_resource *desired_reg; int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu); struct cppc_pcc_data *pcc_ss_data = NULL; + struct cpc_register_resource *reg; int ret = 0; + u32 value; if (!cpc_desc) { pr_debug("No CPC descriptor for CPU:%d\n", cpu); return -ENODEV; } - desired_reg = &cpc_desc->cpc_regs[DESIRED_PERF]; + switch (reg_idx) { + case DESIRED_PERF: + value = perf_ctrls->desired_perf; + break; + default: + pr_debug("CPC register index #%d not writeable\n", reg_idx); + return -EINVAL; + } + + reg = &cpc_desc->cpc_regs[reg_idx]; /* * This is Phase-I where we want to write to CPC registers @@ -1369,7 +1381,7 @@ int cppc_set_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls) * Since read_lock can be acquired by multiple CPUs simultaneously we * achieve that goal here */ - if (CPC_IN_PCC(desired_reg)) { + if (CPC_IN_PCC(reg)) { if (pcc_ss_id < 0) { pr_debug("Invalid pcc_ss_id\n"); return -ENODEV; @@ -1396,14 +1408,14 @@ int cppc_set_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls) * Skip writing MIN/MAX until Linux knows how to come up with * useful values. */ - cpc_write(cpu, desired_reg, perf_ctrls->desired_perf); + cpc_write(cpu, reg, value); - if (CPC_IN_PCC(desired_reg)) + if (CPC_IN_PCC(reg)) up_read(&pcc_ss_data->pcc_lock); /* END Phase-I */ /* * This is Phase-II where we transfer the ownership of PCC to Platform * - * Short Summary: Basically if we think of a group of cppc_set_perf + * Short Summary: Basically if we think of a group of cppc_set_reg * requests that happened in short overlapping interval. The last CPU to * come out of Phase-I will enter Phase-II and ring the doorbell. * @@ -1446,7 +1458,7 @@ int cppc_set_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls) * case during a CMD_READ and if there are pending writes it delivers * the write command before servicing the read command */ - if (CPC_IN_PCC(desired_reg)) { + if (CPC_IN_PCC(reg)) { if (down_write_trylock(&pcc_ss_data->pcc_lock)) {/* BEGIN Phase-II */ /* Update only if there are pending write commands */ if (pcc_ss_data->pending_pcc_write_cmd) @@ -1462,7 +1474,7 @@ int cppc_set_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls) } return ret; } -EXPORT_SYMBOL_GPL(cppc_set_perf); +EXPORT_SYMBOL_GPL(cppc_set_reg); /** * cppc_get_transition_latency - returns frequency transition latency in ns diff --git a/drivers/cpufreq/cppc_cpufreq.c b/drivers/cpufreq/cppc_cpufreq.c index 8d8da763adc5..81e9dff03c92 100644 --- a/drivers/cpufreq/cppc_cpufreq.c +++ b/drivers/cpufreq/cppc_cpufreq.c @@ -207,7 +207,7 @@ static int cppc_cpufreq_set_target(struct cpufreq_policy *policy, freqs.new = target_freq; cpufreq_freq_transition_begin(policy, &freqs); - ret = cppc_set_perf(cpu->cpu, &cpu->perf_ctrls); + ret = cppc_set_reg(cpu->cpu, &cpu->perf_ctrls, DESIRED_PERF); cpufreq_freq_transition_end(policy, &freqs, ret != 0); if (ret) @@ -231,7 +231,7 @@ static void cppc_cpufreq_stop_cpu(struct cpufreq_policy *policy) cpu->perf_ctrls.desired_perf = cpu->perf_caps.lowest_perf; - ret = cppc_set_perf(cpu_num, &cpu->perf_ctrls); + ret = cppc_set_reg(cpu_num, &cpu->perf_ctrls, DESIRED_PERF); if (ret) pr_debug("Err setting perf value:%d on CPU:%d. ret:%d\n", cpu->perf_caps.lowest_perf, cpu_num, ret); @@ -344,7 +344,7 @@ static int cppc_cpufreq_cpu_init(struct cpufreq_policy *policy) cpu->perf_caps.highest_perf); cpu->perf_ctrls.desired_perf = cpu->perf_caps.highest_perf; - ret = cppc_set_perf(cpu_num, &cpu->perf_ctrls); + ret = cppc_set_reg(cpu_num, &cpu->perf_ctrls, DESIRED_PERF); if (ret) pr_debug("Err setting perf value:%d on CPU:%d. ret:%d\n", cpu->perf_caps.highest_perf, cpu_num, ret); diff --git a/include/acpi/cppc_acpi.h b/include/acpi/cppc_acpi.h index a6a9373ab863..f229e903525d 100644 --- a/include/acpi/cppc_acpi.h +++ b/include/acpi/cppc_acpi.h @@ -135,7 +135,7 @@ struct cppc_cpudata { extern int cppc_get_desired_perf(int cpunum, u64 *desired_perf); extern int cppc_get_perf_ctrs(int cpu, struct cppc_perf_fb_ctrs *perf_fb_ctrs); -extern int cppc_set_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls); +extern int cppc_set_reg(int cpu, struct cppc_perf_ctrls *perf_ctrls, enum cppc_regs reg_idx); extern int cppc_get_perf_caps(int cpu, struct cppc_perf_caps *caps); extern int acpi_get_psd_map(struct cppc_cpudata **); extern unsigned int cppc_get_transition_latency(int cpu); From patchwork Wed Jul 10 18:37:16 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Janakarajan Natarajan X-Patchwork-Id: 11038817 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 5773617EF for ; Wed, 10 Jul 2019 18:37:48 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 4A628287E7 for ; Wed, 10 Jul 2019 18:37:48 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 3ECEF289EA; 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Wysocki" , Len Brown , Viresh Kumar , Robert Moore , Erik Schmauss , "Ghannam, Yazen" , "Ghannam, Yazen" , "Natarajan, Janakarajan" Subject: [PATCHv3 4/6] acpi/cppc: Add support for optional CPPC registers Thread-Topic: [PATCHv3 4/6] acpi/cppc: Add support for optional CPPC registers Thread-Index: AQHVN05/uCAmzktiqUqe1+5kYIkwWA== Date: Wed, 10 Jul 2019 18:37:16 +0000 Message-ID: <296ef9c218d1ef240c33c3beb68b7caef4d77940.1562781484.git.Janakarajan.Natarajan@amd.com> References: In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: SN4PR0201CA0064.namprd02.prod.outlook.com (2603:10b6:803:20::26) To SN6PR12MB2736.namprd12.prod.outlook.com (2603:10b6:805:77::27) authentication-results: spf=none (sender IP is ) smtp.mailfrom=Janakarajan.Natarajan@amd.com; x-ms-exchange-messagesentrepresentingtype: 1 x-mailer: git-send-email 2.17.1 x-originating-ip: [165.204.78.2] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 8ca2853d-6ea4-4df8-e5b8-08d70565a194 x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: BCL:0;PCL:0;RULEID:(2390118)(7020095)(4652040)(8989299)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(5600148)(711020)(4605104)(1401327)(4618075)(2017052603328)(7193020);SRVR:SN6PR12MB2749; x-ms-traffictypediagnostic: SN6PR12MB2749: x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:6790; x-forefront-prvs: 0094E3478A x-forefront-antispam-report: SFV:NSPM;SFS:(10009020)(4636009)(366004)(136003)(376002)(346002)(396003)(39860400002)(199004)(189003)(66476007)(66946007)(5660300002)(66556008)(81166006)(2906002)(54906003)(64756008)(50226002)(36756003)(186003)(6486002)(6506007)(386003)(316002)(110136005)(102836004)(2501003)(14454004)(8936002)(68736007)(66446008)(2201001)(99286004)(7736002)(446003)(478600001)(118296001)(305945005)(52116002)(53936002)(76176011)(6512007)(8676002)(86362001)(256004)(11346002)(486006)(25786009)(14444005)(476003)(2616005)(3846002)(6436002)(26005)(6116002)(71200400001)(71190400001)(81156014)(4326008)(66066001);DIR:OUT;SFP:1101;SCL:1;SRVR:SN6PR12MB2749;H:SN6PR12MB2736.namprd12.prod.outlook.com;FPR:;SPF:None;LANG:en;PTR:InfoNoRecords;A:1;MX:1; received-spf: None (protection.outlook.com: amd.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: HunOsVXhHnQo16/AYrvVECL0KbHRuFbL6TjfYNms1zZ2m0zbEoOt0+0vQH3hJtE6UUHi/9coxShgVdhikFU6c0d2zMvINlvjRBV023Ll5tyd1yJmqaZ1VKKDc4JSzospAgNuNBcUAlQ4jwKvsmJfzjgGu9BThe+/tMyFYNDqBzgoNiOefOFC+ZjKpbOrC2dHpyuCpWeRhzOaYj2wMnSj/maeEeolAP+71dzP6eXipGay5rl+hpBSwiKfTeb4BqFzdlIblT5kWOc4iWc2sCegUlwr2N/VBfZS83FhM7Fx6p19s8LYvCEVagbvXkfFE94IZ9u7cy9bnpFyl8jeRRKUjdcNlh/AZHidCeO5cl8qOFRJOlugl9OCognEJUnAbUBmF5QGHy83xsnUpPUEn5LKIqN73Vxe8mtrAkGPP/lmHuA= MIME-Version: 1.0 X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: 8ca2853d-6ea4-4df8-e5b8-08d70565a194 X-MS-Exchange-CrossTenant-originalarrivaltime: 10 Jul 2019 18:37:16.3196 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: jnataraj@amd.com X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN6PR12MB2749 Sender: linux-acpi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-acpi@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Yazen Ghannam Newer AMD processors support a subset of the optional CPPC registers. Add support for these optional registers. Signed-off-by: Yazen Ghannam [ carved out into a patch, cleaned up, productized ] Signed-off-by: Janakarajan Natarajan --- drivers/acpi/cppc_acpi.c | 88 +++++++++++++++++++++++++++++++++++++--- include/acpi/cppc_acpi.h | 3 ++ 2 files changed, 86 insertions(+), 5 deletions(-) diff --git a/drivers/acpi/cppc_acpi.c b/drivers/acpi/cppc_acpi.c index c13dacea4a8b..b24e54263efb 100644 --- a/drivers/acpi/cppc_acpi.c +++ b/drivers/acpi/cppc_acpi.c @@ -1367,6 +1367,18 @@ int cppc_set_reg(int cpu, struct cppc_perf_ctrls *perf_ctrls, case DESIRED_PERF: value = perf_ctrls->desired_perf; break; + case MAX_PERF: + value = perf_ctrls->max_perf; + break; + case MIN_PERF: + value = perf_ctrls->min_perf; + break; + case ENERGY_PERF: + value = perf_ctrls->energy_perf; + break; + case AUTO_SEL_ENABLE: + value = perf_ctrls->auto_sel_enable; + break; default: pr_debug("CPC register index #%d not writeable\n", reg_idx); return -EINVAL; @@ -1404,11 +1416,8 @@ int cppc_set_reg(int cpu, struct cppc_perf_ctrls *perf_ctrls, cpc_desc->write_cmd_status = 0; } - /* - * Skip writing MIN/MAX until Linux knows how to come up with - * useful values. - */ - cpc_write(cpu, reg, value); + if (CPC_SUPPORTED(reg)) + cpc_write(cpu, reg, value); if (CPC_IN_PCC(reg)) up_read(&pcc_ss_data->pcc_lock); /* END Phase-I */ @@ -1476,6 +1485,75 @@ int cppc_set_reg(int cpu, struct cppc_perf_ctrls *perf_ctrls, } EXPORT_SYMBOL_GPL(cppc_set_reg); +int cppc_get_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls) +{ + struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpu); + struct cpc_register_resource *desired_reg, *max_reg, *min_reg; + struct cpc_register_resource *energy_reg, *auto_sel_enable_reg; + int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu); + u64 desired, max, min, energy, auto_sel_enable; + struct cppc_pcc_data *pcc_ss_data = NULL; + int ret = 0, regs_in_pcc = 0; + + if (!cpc_desc) { + pr_debug("No CPC descriptor for CPU: %d\n", cpu); + return -ENODEV; + } + + desired_reg = &cpc_desc->cpc_regs[DESIRED_PERF]; + max_reg = &cpc_desc->cpc_regs[MAX_PERF]; + min_reg = &cpc_desc->cpc_regs[MIN_PERF]; + energy_reg = &cpc_desc->cpc_regs[ENERGY_PERF]; + auto_sel_enable_reg = &cpc_desc->cpc_regs[AUTO_SEL_ENABLE]; + + /* Check if any of the perf registers are in PCC */ + if (CPC_IN_PCC(desired_reg) || CPC_IN_PCC(max_reg) || + CPC_IN_PCC(min_reg) || CPC_IN_PCC(energy_reg) || + CPC_IN_PCC(auto_sel_enable_reg)) { + pcc_ss_data = pcc_data[pcc_ss_id]; + down_write(&pcc_ss_data->pcc_lock); + regs_in_pcc = 1; + + /*Ring doorbell once to update PCC subspace */ + if (send_pcc_cmd(pcc_ss_id, CMD_READ) < 0) { + ret = -EIO; + goto out_err; + } + } + + /* desired_perf is the only mandatory value in perf_ctrls */ + if (cpc_read(cpu, desired_reg, &desired)) + ret = -EFAULT; + + if (CPC_SUP_BUFFER_ONLY(max_reg) && cpc_read(cpu, max_reg, &max)) + ret = -EFAULT; + + if (CPC_SUP_BUFFER_ONLY(min_reg) && cpc_read(cpu, min_reg, &min)) + ret = -EFAULT; + + if (CPC_SUP_BUFFER_ONLY(energy_reg) && + cpc_read(cpu, energy_reg, &energy)) + ret = -EFAULT; + + if (CPC_SUPPORTED(auto_sel_enable_reg) && + cpc_read(cpu, auto_sel_enable_reg, &auto_sel_enable)) + ret = -EFAULT; + + if (!ret) { + perf_ctrls->desired_perf = desired; + perf_ctrls->max_perf = max; + perf_ctrls->min_perf = min; + perf_ctrls->energy_perf = energy; + perf_ctrls->auto_sel_enable = auto_sel_enable; + } + +out_err: + if (regs_in_pcc) + up_write(&pcc_ss_data->pcc_lock); + return ret; +} +EXPORT_SYMBOL_GPL(cppc_get_perf); + /** * cppc_get_transition_latency - returns frequency transition latency in ns * diff --git a/include/acpi/cppc_acpi.h b/include/acpi/cppc_acpi.h index f229e903525d..80720b246c51 100644 --- a/include/acpi/cppc_acpi.h +++ b/include/acpi/cppc_acpi.h @@ -113,6 +113,8 @@ struct cppc_perf_ctrls { u32 max_perf; u32 min_perf; u32 desired_perf; + u32 auto_sel_enable; + u32 energy_perf; }; struct cppc_perf_fb_ctrs { @@ -136,6 +138,7 @@ struct cppc_cpudata { extern int cppc_get_desired_perf(int cpunum, u64 *desired_perf); extern int cppc_get_perf_ctrs(int cpu, struct cppc_perf_fb_ctrs *perf_fb_ctrs); extern int cppc_set_reg(int cpu, struct cppc_perf_ctrls *perf_ctrls, enum cppc_regs reg_idx); +extern int cppc_get_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls); extern int cppc_get_perf_caps(int cpu, struct cppc_perf_caps *caps); extern int acpi_get_psd_map(struct cppc_cpudata **); extern unsigned int cppc_get_transition_latency(int cpu); From patchwork Wed Jul 10 18:37:17 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Janakarajan Natarajan X-Patchwork-Id: 11038811 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 143C814C0 for ; Wed, 10 Jul 2019 18:37:42 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 04F0B284DC for ; Wed, 10 Jul 2019 18:37:42 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id ED0E7289EC; Wed, 10 Jul 2019 18:37:41 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 70A19289D6 for ; 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Wysocki" , Len Brown , Viresh Kumar , Robert Moore , Erik Schmauss , "Ghannam, Yazen" , "Ghannam, Yazen" , "Natarajan, Janakarajan" Subject: [PATCHv3 5/6] acpi/cppc: Add support for CPPC Enable register Thread-Topic: [PATCHv3 5/6] acpi/cppc: Add support for CPPC Enable register Thread-Index: AQHVN06A9flMOYmKH0yRLd2nLrnssw== Date: Wed, 10 Jul 2019 18:37:17 +0000 Message-ID: <40c32db191fa023f7f8f1e48d58565a22b8fcbd6.1562781484.git.Janakarajan.Natarajan@amd.com> References: In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: SN4PR0201CA0064.namprd02.prod.outlook.com (2603:10b6:803:20::26) To SN6PR12MB2736.namprd12.prod.outlook.com (2603:10b6:805:77::27) authentication-results: spf=none (sender IP is ) smtp.mailfrom=Janakarajan.Natarajan@amd.com; x-ms-exchange-messagesentrepresentingtype: 1 x-mailer: git-send-email 2.17.1 x-originating-ip: [165.204.78.2] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: d0749c57-ff40-4eae-c3bb-08d70565a249 x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: BCL:0;PCL:0;RULEID:(2390118)(7020095)(4652040)(8989299)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(5600148)(711020)(4605104)(1401327)(4618075)(2017052603328)(7193020);SRVR:SN6PR12MB2749; x-ms-traffictypediagnostic: SN6PR12MB2749: x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:8273; x-forefront-prvs: 0094E3478A x-forefront-antispam-report: SFV:NSPM;SFS:(10009020)(4636009)(366004)(136003)(376002)(346002)(396003)(39860400002)(199004)(189003)(66476007)(66946007)(5660300002)(66556008)(81166006)(2906002)(54906003)(64756008)(50226002)(36756003)(186003)(6486002)(6506007)(386003)(316002)(110136005)(102836004)(2501003)(14454004)(8936002)(68736007)(66446008)(2201001)(99286004)(7736002)(446003)(478600001)(118296001)(305945005)(52116002)(53936002)(76176011)(6512007)(8676002)(86362001)(256004)(11346002)(486006)(25786009)(14444005)(476003)(2616005)(3846002)(6436002)(26005)(6116002)(71200400001)(71190400001)(81156014)(6666004)(4326008)(66066001);DIR:OUT;SFP:1101;SCL:1;SRVR:SN6PR12MB2749;H:SN6PR12MB2736.namprd12.prod.outlook.com;FPR:;SPF:None;LANG:en;PTR:InfoNoRecords;A:1;MX:1; received-spf: None (protection.outlook.com: amd.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: PXxgfJXmR4zEpUVENmUVVCP5kW1ZM6VWbFYkECRBjD27EkNYi7KkMcMTiJ2b5ufhKKXVAfcdf3LAZxzz2WEZgwjOCI9R1yUJqL8T1PQN1iO8Xkgv4ZlpwJeqvbLjgzX/bZdii5Y8j+KPCOiCLRJnM/tx60v3e3hgWbniH+qQNHBfW0AeA2WKj8lcNkwThu4OUeYQ2jBjw6HTUgVk8qFBQrn/MXf0iNxJBxQSSOIrnKHlNqmvrEawqYDqUoKWMbcdruI3eOcVwXIQz+P3mVXwqSc+301NmtTAHQ9dGxVL2K3QxmRI3Xu0LhdzlOdmqEw6VVa6JhR1QTIho+cYZYRuZ/dWoFpE2Uin069PB2yDvCqGCHA3qD8c8JpclyKet6V8X7YZwMSiKs3f8Ost2fHpo6af1LZSu0H/HJ9zBHTAblU= MIME-Version: 1.0 X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: d0749c57-ff40-4eae-c3bb-08d70565a249 X-MS-Exchange-CrossTenant-originalarrivaltime: 10 Jul 2019 18:37:17.5259 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: jnataraj@amd.com X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN6PR12MB2749 Sender: linux-acpi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-acpi@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Yazen Ghannam To enable CPPC on a processor, the OS should write a value "1" to the CPPC Enable register. Add support for this register. Since we have a new variable "enable" in cppc_perf_ctrls, rename it and the associated functions i.e. cppc_perf_ctrls->cppc_ctrls and cppc_get_perf()->cppc_get_ctrls(). Signed-off-by: Yazen Ghannam [ carved out into a patch, cleaned up, productized ] Signed-off-by: Janakarajan Natarajan --- drivers/acpi/cppc_acpi.c | 44 ++++++++++++++++++++++++---------------- include/acpi/cppc_acpi.h | 10 +++++---- 2 files changed, 33 insertions(+), 21 deletions(-) diff --git a/drivers/acpi/cppc_acpi.c b/drivers/acpi/cppc_acpi.c index b24e54263efb..3199433e3f71 100644 --- a/drivers/acpi/cppc_acpi.c +++ b/drivers/acpi/cppc_acpi.c @@ -1343,12 +1343,12 @@ EXPORT_SYMBOL_GPL(cppc_get_perf_ctrs); /** * cppc_set_reg - Set the CPUs control register. * @cpu: CPU for which to set the register. - * @perf_ctrls: ptr to cppc_perf_ctrls. See cppc_acpi.h + * @ctrls: ptr to cppc_ctrls. See cppc_acpi.h * @reg_idx: Index of the register being accessed * * Return: 0 for success, -ERRNO otherwise. */ -int cppc_set_reg(int cpu, struct cppc_perf_ctrls *perf_ctrls, +int cppc_set_reg(int cpu, struct cppc_ctrls *ctrls, enum cppc_regs reg_idx) { struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpu); @@ -1364,20 +1364,23 @@ int cppc_set_reg(int cpu, struct cppc_perf_ctrls *perf_ctrls, } switch (reg_idx) { + case ENABLE: + value = ctrls->enable; + break; case DESIRED_PERF: - value = perf_ctrls->desired_perf; + value = ctrls->desired_perf; break; case MAX_PERF: - value = perf_ctrls->max_perf; + value = ctrls->max_perf; break; case MIN_PERF: - value = perf_ctrls->min_perf; + value = ctrls->min_perf; break; case ENERGY_PERF: - value = perf_ctrls->energy_perf; + value = ctrls->energy_perf; break; case AUTO_SEL_ENABLE: - value = perf_ctrls->auto_sel_enable; + value = ctrls->auto_sel_enable; break; default: pr_debug("CPC register index #%d not writeable\n", reg_idx); @@ -1485,13 +1488,14 @@ int cppc_set_reg(int cpu, struct cppc_perf_ctrls *perf_ctrls, } EXPORT_SYMBOL_GPL(cppc_set_reg); -int cppc_get_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls) +int cppc_get_ctrls(int cpu, struct cppc_ctrls *ctrls) { struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpu); struct cpc_register_resource *desired_reg, *max_reg, *min_reg; struct cpc_register_resource *energy_reg, *auto_sel_enable_reg; + struct cpc_register_resource *enable_reg; int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu); - u64 desired, max, min, energy, auto_sel_enable; + u64 desired, max, min, energy, auto_sel_enable, enable; struct cppc_pcc_data *pcc_ss_data = NULL; int ret = 0, regs_in_pcc = 0; @@ -1500,6 +1504,7 @@ int cppc_get_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls) return -ENODEV; } + enable_reg = &cpc_desc->cpc_regs[ENABLE]; desired_reg = &cpc_desc->cpc_regs[DESIRED_PERF]; max_reg = &cpc_desc->cpc_regs[MAX_PERF]; min_reg = &cpc_desc->cpc_regs[MIN_PERF]; @@ -1509,7 +1514,7 @@ int cppc_get_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls) /* Check if any of the perf registers are in PCC */ if (CPC_IN_PCC(desired_reg) || CPC_IN_PCC(max_reg) || CPC_IN_PCC(min_reg) || CPC_IN_PCC(energy_reg) || - CPC_IN_PCC(auto_sel_enable_reg)) { + CPC_IN_PCC(auto_sel_enable_reg) || CPC_IN_PCC(enable_reg)) { pcc_ss_data = pcc_data[pcc_ss_id]; down_write(&pcc_ss_data->pcc_lock); regs_in_pcc = 1; @@ -1521,10 +1526,14 @@ int cppc_get_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls) } } - /* desired_perf is the only mandatory value in perf_ctrls */ + /* desired_perf is the only mandatory value in ctrls */ if (cpc_read(cpu, desired_reg, &desired)) ret = -EFAULT; + if (CPC_SUP_BUFFER_ONLY(enable_reg) && + cpc_read(cpu, enable_reg, &enable)) + ret = -EFAULT; + if (CPC_SUP_BUFFER_ONLY(max_reg) && cpc_read(cpu, max_reg, &max)) ret = -EFAULT; @@ -1540,11 +1549,12 @@ int cppc_get_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls) ret = -EFAULT; if (!ret) { - perf_ctrls->desired_perf = desired; - perf_ctrls->max_perf = max; - perf_ctrls->min_perf = min; - perf_ctrls->energy_perf = energy; - perf_ctrls->auto_sel_enable = auto_sel_enable; + ctrls->enable = enable; + ctrls->desired_perf = desired; + ctrls->max_perf = max; + ctrls->min_perf = min; + ctrls->energy_perf = energy; + ctrls->auto_sel_enable = auto_sel_enable; } out_err: @@ -1552,7 +1562,7 @@ int cppc_get_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls) up_write(&pcc_ss_data->pcc_lock); return ret; } -EXPORT_SYMBOL_GPL(cppc_get_perf); +EXPORT_SYMBOL_GPL(cppc_get_ctrls); /** * cppc_get_transition_latency - returns frequency transition latency in ns diff --git a/include/acpi/cppc_acpi.h b/include/acpi/cppc_acpi.h index 80720b246c51..e6cd2a487874 100644 --- a/include/acpi/cppc_acpi.h +++ b/include/acpi/cppc_acpi.h @@ -109,7 +109,8 @@ struct cppc_perf_caps { u32 nominal_freq; }; -struct cppc_perf_ctrls { +struct cppc_ctrls { + bool enable; u32 max_perf; u32 min_perf; u32 desired_perf; @@ -128,17 +129,18 @@ struct cppc_perf_fb_ctrs { struct cppc_cpudata { int cpu; struct cppc_perf_caps perf_caps; - struct cppc_perf_ctrls perf_ctrls; + struct cppc_ctrls ctrls; struct cppc_perf_fb_ctrs perf_fb_ctrs; struct cpufreq_policy *cur_policy; unsigned int shared_type; cpumask_var_t shared_cpu_map; }; +extern int cppc_get_enable(int cpu); extern int cppc_get_desired_perf(int cpunum, u64 *desired_perf); extern int cppc_get_perf_ctrs(int cpu, struct cppc_perf_fb_ctrs *perf_fb_ctrs); -extern int cppc_set_reg(int cpu, struct cppc_perf_ctrls *perf_ctrls, enum cppc_regs reg_idx); -extern int cppc_get_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls); +extern int cppc_set_reg(int cpu, struct cppc_ctrls *ctrls, enum cppc_regs reg_idx); +extern int cppc_get_ctrls(int cpu, struct cppc_ctrls *ctrls); extern int cppc_get_perf_caps(int cpu, struct cppc_perf_caps *caps); extern int acpi_get_psd_map(struct cppc_cpudata **); extern unsigned int cppc_get_transition_latency(int cpu); From patchwork Wed Jul 10 18:37:18 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Janakarajan Natarajan X-Patchwork-Id: 11038807 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 55FE717EF for ; Wed, 10 Jul 2019 18:37:35 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 493EB288F6 for ; Wed, 10 Jul 2019 18:37:35 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 3C735289AD; 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Wysocki" , Len Brown , Viresh Kumar , Robert Moore , Erik Schmauss , "Ghannam, Yazen" , "Natarajan, Janakarajan" Subject: [PATCHv3 6/6] drivers/cpufreq: Add a CPUFreq driver for AMD processors (Fam17h and later) Thread-Topic: [PATCHv3 6/6] drivers/cpufreq: Add a CPUFreq driver for AMD processors (Fam17h and later) Thread-Index: AQHVN06AuI3rG5PgEkGK1o9FtbMXtQ== Date: Wed, 10 Jul 2019 18:37:18 +0000 Message-ID: References: In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: SN4PR0201CA0064.namprd02.prod.outlook.com (2603:10b6:803:20::26) To SN6PR12MB2736.namprd12.prod.outlook.com (2603:10b6:805:77::27) authentication-results: spf=none (sender IP is ) smtp.mailfrom=Janakarajan.Natarajan@amd.com; x-ms-exchange-messagesentrepresentingtype: 1 x-mailer: git-send-email 2.17.1 x-originating-ip: [165.204.78.2] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: eb687ae8-0adf-46f9-e3a8-08d70565a2f2 x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: BCL:0;PCL:0;RULEID:(2390118)(7020095)(4652040)(8989299)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(5600148)(711020)(4605104)(1401327)(4618075)(2017052603328)(7193020);SRVR:SN6PR12MB2639; x-ms-traffictypediagnostic: SN6PR12MB2639: x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:8882; x-forefront-prvs: 0094E3478A x-forefront-antispam-report: SFV:NSPM;SFS:(10009020)(4636009)(39860400002)(396003)(136003)(366004)(346002)(376002)(189003)(199004)(11346002)(446003)(99286004)(3846002)(6436002)(6116002)(2501003)(6666004)(66066001)(71200400001)(71190400001)(316002)(476003)(25786009)(2616005)(6506007)(386003)(76176011)(486006)(36756003)(14454004)(66946007)(305945005)(6486002)(64756008)(66446008)(66476007)(8936002)(66556008)(81156014)(81166006)(54906003)(53936002)(186003)(2201001)(8676002)(26005)(4326008)(50226002)(118296001)(52116002)(102836004)(68736007)(86362001)(6512007)(5660300002)(2906002)(256004)(14444005)(110136005)(7736002)(478600001);DIR:OUT;SFP:1101;SCL:1;SRVR:SN6PR12MB2639;H:SN6PR12MB2736.namprd12.prod.outlook.com;FPR:;SPF:None;LANG:en;PTR:InfoNoRecords;MX:1;A:1; received-spf: None (protection.outlook.com: amd.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: PZtyf9U8T0BLfvcrdIyhtTmd6AyTWWCc4m1S+ANTibJneEYOfLLPipa7iM0taupgi/b0UOZg4jHM1RIFsYO7to2GuZ2dFqmwGi2qQnM2L3MCjbbckHqtq71tv4usmzrzqDojJlp/DpML1rOD2RAtHbd/O3r4taDm32Q6XUI8A4jVWOOO/D9aIzu/G69joE0SDI3k8HrLH8RvYeVx2220o3mUoZQ2MdNWK+sZQSSo2qWEcDuKK7jOuls4J09R9S2KSpOkDhM6+gB/qW8haRG27E5fHJzYQAZSvlYVA0lerK0RkxdR9usToQ+PSXqeQTRkqDH3Ca8mP+VWWwXPu6Ep5Zkty8VqYtvdP6iB9PidS+ZCdjywlqpRZan2eETBKkMfS64MqKB6DfB4NnHNr/IXlp3+uinu6kE4ZtDCUOtVDvo= MIME-Version: 1.0 X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: eb687ae8-0adf-46f9-e3a8-08d70565a2f2 X-MS-Exchange-CrossTenant-originalarrivaltime: 10 Jul 2019 18:37:18.4644 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: jnataraj@amd.com X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN6PR12MB2639 Sender: linux-acpi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-acpi@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add a new CPUFreq driver which exposes sysfs entries to control the platform. To make use of this driver use a kernel commandline option. Ex: amd_cpufreq=enable - Enable AMD CPUFreq driver for Fam17h and later Also, place amd-cpufreq before acpi-cpufreq in the Makefile to give it higher priority. Signed-off-by: Janakarajan Natarajan --- drivers/cpufreq/Kconfig.x86 | 14 ++ drivers/cpufreq/Makefile | 4 +- drivers/cpufreq/amd-cpufreq.c | 233 ++++++++++++++++++++++++++++++++++ 3 files changed, 250 insertions(+), 1 deletion(-) create mode 100644 drivers/cpufreq/amd-cpufreq.c diff --git a/drivers/cpufreq/Kconfig.x86 b/drivers/cpufreq/Kconfig.x86 index dfa6457deaf6..01c7c5b5486a 100644 --- a/drivers/cpufreq/Kconfig.x86 +++ b/drivers/cpufreq/Kconfig.x86 @@ -32,6 +32,20 @@ config X86_PCC_CPUFREQ If in doubt, say N. +config X86_AMD_CPUFREQ + tristate "AMD CPUFreq driver" + depends on ACPI_PROCESSOR + select ACPI_CPPC_LIB + help + This adds a CPUFreq driver which uses CPPC methods + as described in the ACPI v6.1 spec for newer (>= Fam17h) + AMD processors. + + When this driver is enabled it will become preferred to + the acpi-cpufreq driver. + + If in doubt, say N. + config X86_ACPI_CPUFREQ tristate "ACPI Processor P-States driver" depends on ACPI_PROCESSOR diff --git a/drivers/cpufreq/Makefile b/drivers/cpufreq/Makefile index 689b26c6f949..b2837ed9aff2 100644 --- a/drivers/cpufreq/Makefile +++ b/drivers/cpufreq/Makefile @@ -22,8 +22,10 @@ obj-$(CONFIG_CPUFREQ_DT_PLATDEV) += cpufreq-dt-platdev.o # Link order matters. K8 is preferred to ACPI because of firmware bugs in early # K8 systems. This is still the case but acpi-cpufreq errors out so that # powernow-k8 can load then. ACPI is preferred to all other hardware-specific drivers. -# speedstep-* is preferred over p4-clockmod. +# speedstep-* is preferred over p4-clockmod. amd-cpufreq is preferred to acpi-cpufreq +# for Fam17h or newer AMD processors. For others, acpi-cpufreq will be used. +obj-$(CONFIG_X86_AMD_CPUFREQ) += amd-cpufreq.o obj-$(CONFIG_X86_ACPI_CPUFREQ) += acpi-cpufreq.o obj-$(CONFIG_X86_POWERNOW_K8) += powernow-k8.o obj-$(CONFIG_X86_PCC_CPUFREQ) += pcc-cpufreq.o diff --git a/drivers/cpufreq/amd-cpufreq.c b/drivers/cpufreq/amd-cpufreq.c new file mode 100644 index 000000000000..262c8de3be2e --- /dev/null +++ b/drivers/cpufreq/amd-cpufreq.c @@ -0,0 +1,233 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * AMD CPUFREQ driver for Family 17h or greater AMD processors. + * + * Copyright (C) 2019 Advanced Micro Devices, Inc. + * + * Author: Janakarajan Natarajan + */ +#define pr_fmt(fmt) "AMD Cpufreq: " fmt + +#include +#include +#include +#include +#include +#include +#include + +#include + +#include + +struct amd_desc { + int cpu_id; + struct cppc_ctrls ctrls; + struct kobject kobj; +}; + +struct amd_desc **all_cpu_data; + +static unsigned int cppc_enable; +module_param(cppc_enable, uint, 0644); +MODULE_PARM_DESC(cppc_enable, + "1 - enable AMD CpuFreq, create CPPC sysfs entries."); + +#define to_amd_desc(a) container_of(a, struct amd_desc, kobj) + +#define show_func(access_fn, struct_name, member_name) \ + static ssize_t show_##member_name(struct kobject *kobj, \ + struct kobj_attribute *attr, \ + char *buf) \ + { \ + struct amd_desc *desc = to_amd_desc(kobj); \ + struct struct_name st_name = {0}; \ + int ret; \ + \ + ret = access_fn(desc->cpu_id, &st_name); \ + if (ret) \ + return ret; \ + \ + return scnprintf(buf, PAGE_SIZE, "%llu\n", \ + (u64)st_name.member_name); \ + } \ + +#define store_func(struct_name, member_name, reg_idx) \ + static ssize_t store_##member_name(struct kobject *kobj, \ + struct kobj_attribute *attr, \ + const char *buf, size_t count)\ + { \ + struct amd_desc *desc = to_amd_desc(kobj); \ + struct struct_name st_name = {0}; \ + u32 val; \ + int ret; \ + \ + ret = kstrtou32(buf, 0, &val); \ + if (ret) \ + return ret; \ + \ + st_name.member_name = val; \ + \ + ret = cppc_set_reg(desc->cpu_id, &st_name, reg_idx); \ + if (ret) \ + return ret; \ + \ + return count; \ + } \ + +#define define_one_rw(struct_name, access_fn, member_name, reg_idx) \ + show_func(access_fn, struct_name, member_name) \ + store_func(struct_name, member_name, reg_idx) \ + define_one_global_rw(member_name) + +define_one_rw(cppc_ctrls, cppc_get_ctrls, enable, ENABLE); +define_one_rw(cppc_ctrls, cppc_get_ctrls, max_perf, MAX_PERF); +define_one_rw(cppc_ctrls, cppc_get_ctrls, min_perf, MIN_PERF); +define_one_rw(cppc_ctrls, cppc_get_ctrls, desired_perf, DESIRED_PERF); +define_one_rw(cppc_ctrls, cppc_get_ctrls, auto_sel_enable, AUTO_SEL_ENABLE); + +static struct attribute *amd_cpufreq_attributes[] = { + &enable.attr, + &max_perf.attr, + &min_perf.attr, + &desired_perf.attr, + &auto_sel_enable.attr, + NULL +}; + +static const struct attribute_group amd_cpufreq_attr_group = { + .attrs = amd_cpufreq_attributes, +}; + +static struct kobj_type amd_cpufreq_type = { + .sysfs_ops = &kobj_sysfs_ops, + .default_attrs = amd_cpufreq_attributes, +}; + +static int amd_cpufreq_cpu_init(struct cpufreq_policy *policy) +{ + return 0; +} + +static int amd_cpufreq_cpu_exit(struct cpufreq_policy *policy) +{ + return 0; +} + +static int amd_cpufreq_cpu_verify(struct cpufreq_policy *policy) +{ + return 0; +} + +static int amd_cpufreq_cpu_target_index(struct cpufreq_policy *policy, + unsigned int index) +{ + return 0; +} + +static struct cpufreq_driver amd_cpufreq_driver = { + .name = "amd_cpufreq", + .init = amd_cpufreq_cpu_init, + .exit = amd_cpufreq_cpu_exit, + .verify = amd_cpufreq_cpu_verify, + .target_index = amd_cpufreq_cpu_target_index, +}; + +static void amd_cpufreq_sysfs_delete_params(void) +{ + int i; + + for_each_possible_cpu(i) { + if (all_cpu_data[i]) { + kobject_del(&all_cpu_data[i]->kobj); + kfree(all_cpu_data[i]); + } + } + + kfree(all_cpu_data); +} + +static int __init amd_cpufreq_sysfs_expose_params(void) +{ + struct device *cpu_dev; + int i, ret; + + all_cpu_data = kcalloc(num_possible_cpus(), sizeof(void *), + GFP_KERNEL); + + if (!all_cpu_data) + return -ENOMEM; + + for_each_possible_cpu(i) { + all_cpu_data[i] = kzalloc(sizeof(struct amd_desc), GFP_KERNEL); + if (!all_cpu_data[i]) { + ret = -ENOMEM; + goto free; + } + + all_cpu_data[i]->cpu_id = i; + cpu_dev = get_cpu_device(i); + ret = kobject_init_and_add(&all_cpu_data[i]->kobj, &amd_cpufreq_type, + &cpu_dev->kobj, "amd_cpufreq"); + if (ret) + goto free; + } + + return 0; +free: + amd_cpufreq_sysfs_delete_params(); + return ret; +} + +static int __init amd_cpufreq_init(void) +{ + int ret = 0; + + /* + * Use only if: + * - AMD, + * - Family 17h (or) newer and, + * - Explicitly enabled + */ + if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD || + boot_cpu_data.x86 < 0x17 || !cppc_enable) + return -ENODEV; + + ret = cpufreq_register_driver(&amd_cpufreq_driver); + if (ret) { + pr_info("Failed to register driver\n"); + goto out; + } + + ret = amd_cpufreq_sysfs_expose_params(); + if (ret) { + pr_info("Could not create sysfs entries\n"); + cpufreq_unregister_driver(&amd_cpufreq_driver); + goto out; + } + + pr_info("Using amd-cpufreq driver\n"); + return ret; + +out: + return ret; +} + +static void __exit amd_cpufreq_exit(void) +{ + amd_cpufreq_sysfs_delete_params(); + cpufreq_unregister_driver(&amd_cpufreq_driver); +} + +static const struct acpi_device_id amd_acpi_ids[] __used = { + {ACPI_PROCESSOR_DEVICE_HID, }, + {} +}; + +device_initcall(amd_cpufreq_init); +module_exit(amd_cpufreq_exit); +MODULE_DEVICE_TABLE(acpi, amd_acpi_ids); + +MODULE_AUTHOR("Janakarajan Natarajan"); +MODULE_DESCRIPTION("AMD CPUFreq driver based on ACPI CPPC v6.1 spec"); +MODULE_LICENSE("GPL");