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DIR:OUT; SFP:1101; SCL:1; SRVR:AM0PR04MB4356; H:AM0PR04MB4481.eurprd04.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; A:1; MX:1; received-spf: None (protection.outlook.com: nxp.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: AtzLDsRvqKTXNVTLt/FmlK5BH5wNFAutUrF7UpeiSwI4o2wlHXFh30G1CKoPeuZEhEpEExiELlF5gd2FsUAja5nufRfT+Szxd3bnBPwNZXz/MDNXf6l7Nwx4KZ6p906VSamBviJ8H4xyTz6/XQI0gm/5LSRog/7l0EHkVB5tayjbCWgxXyOdX2uKgDe7038IC/kjAgBUCs4wUOVquB4kZe3UANdy2Xj26ZWYZzO+WIqDhF3dg7QSDuhQunStlRha6BZDajmYeq6ciSM+m4aAoah6izoFnosYoB4zR0omCMvcXZasKjQ3pOl9K81iHrOUJP+Xqqs56e3rFWOp982A4R8ke/wMwiUOFKwyAtfeTWmmGKHVqOb+s5O9DoYsMBGn44mesxGNHHl7hTsaBkVn/p+v7gUCqKWeu8vsYp7LULc= MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 075c2886-9846-4998-d6be-08d7090c9ecc X-MS-Exchange-CrossTenant-originalarrivaltime: 15 Jul 2019 10:10:10.8164 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: peng.fan@nxp.com X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM0PR04MB4356 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190715_031012_158405_EDE659E5 X-CRM114-Status: GOOD ( 17.79 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "devicetree@vger.kernel.org" , Peng Fan , "linux-kernel@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , dl-linux-imx Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP From: Peng Fan The ARM SMC/HVC mailbox binding describes a firmware interface to trigger actions in software layers running in the EL2 or EL3 exception levels. The term "ARM" here relates to the SMC instruction as part of the ARM instruction set, not as a standard endorsed by ARM Ltd. Signed-off-by: Peng Fan --- V3: Convert to yaml Drop interrupt Introudce transports to indicate mem/reg The func id is still kept as optional, because like SCMI it only cares about message. V2: Introduce interrupts as a property. .../devicetree/bindings/mailbox/arm-smc.yaml | 124 +++++++++++++++++++++ 1 file changed, 124 insertions(+) create mode 100644 Documentation/devicetree/bindings/mailbox/arm-smc.yaml diff --git a/Documentation/devicetree/bindings/mailbox/arm-smc.yaml b/Documentation/devicetree/bindings/mailbox/arm-smc.yaml new file mode 100644 index 000000000000..da9b1a03bc4e --- /dev/null +++ b/Documentation/devicetree/bindings/mailbox/arm-smc.yaml @@ -0,0 +1,124 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mailbox/arm-smc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ARM SMC Mailbox Interface + +maintainers: + - Peng Fan + +description: | + This mailbox uses the ARM smc (secure monitor call) and hvc (hypervisor + call) instruction to trigger a mailbox-connected activity in firmware, + executing on the very same core as the caller. By nature this operation + is synchronous and this mailbox provides no way for asynchronous messages + to be delivered the other way round, from firmware to the OS, but + asynchronous notification could also be supported. However the value of + r0/w0/x0 the firmware returns after the smc call is delivered as a received + message to the mailbox framework, so a synchronous communication can be + established, for a asynchronous notification, no value will be returned. + The exact meaning of both the action the mailbox triggers as well as the + return value is defined by their users and is not subject to this binding. + + One use case of this mailbox is the SCMI interface, which uses shared memory + to transfer commands and parameters, and a mailbox to trigger a function + call. This allows SoCs without a separate management processor (or when + such a processor is not available or used) to use this standardized + interface anyway. + + This binding describes no hardware, but establishes a firmware interface. + Upon receiving an SMC using one of the described SMC function identifiers, + the firmware is expected to trigger some mailbox connected functionality. + The communication follows the ARM SMC calling convention. + Firmware expects an SMC function identifier in r0 or w0. The supported + identifiers are passed from consumers, or listed in the the arm,func-ids + properties as described below. The firmware can return one value in + the first SMC result register, it is expected to be an error value, + which shall be propagated to the mailbox client. + + Any core which supports the SMC or HVC instruction can be used, as long as + a firmware component running in EL3 or EL2 is handling these calls. + +properties: + compatible: + const: arm,smc-mbox + + "#mbox-cells": + const: 1 + + arm,num-chans: + description: The number of channels supported. + $ref: /schemas/types.yaml#/definitions/uint32 + + method: + items: + - enum: + - smc + - hvc + + transports: + items: + - enum: + - mem + - reg + + arm,func-ids: + description: | + An array of 32-bit values specifying the function IDs used by each + mailbox channel. Those function IDs follow the ARM SMC calling + convention standard [1]. + + There is one identifier per channel and the number of supported + channels is determined by the length of this array. + minItems: 0 + maxItems: 4096 # Should be enough? + +required: + - compatible + - "#mbox-cells" + - arm,num-chans + - transports + - method + +examples: + - | + sram@910000 { + compatible = "mmio-sram"; + reg = <0x0 0x93f000 0x0 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x0 0x93f000 0x1000>; + + cpu_scp_lpri: scp-shmem@0 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0x200>; + }; + + cpu_scp_hpri: scp-shmem@200 { + compatible = "arm,scmi-shmem"; + reg = <0x200 0x200>; + }; + }; + + firmware { + smc_mbox: mailbox { + #mbox-cells = <1>; + compatible = "arm,smc-mbox"; + method = "smc"; + arm,num-chans = <0x2>; + transports = "mem"; + /* Optional */ + arm,func-ids = <0xc20000fe>, <0xc20000ff>; + }; + + scmi { + compatible = "arm,scmi"; + mboxes = <&mailbox 0 &mailbox 1>; + mbox-names = "tx", "rx"; + shmem = <&cpu_scp_lpri &cpu_scp_hpri>; + }; + }; + +... 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DIR:OUT; SFP:1101; SCL:1; SRVR:AM0PR04MB4356; H:AM0PR04MB4481.eurprd04.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; A:1; MX:1; received-spf: None (protection.outlook.com: nxp.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: WnxRCi7HKfjgsjNMsgnWSLx0wapE8ru1SsOF2cd2lOmG7MZIte8rDIKoK5tXsUlEWkQA3EiokDxs5AL8X0xcFJUYvp07IA8D5ZGNgoWFO7gyVUhXCcQxKLyX4aS4Vi6C+kfMwK4eAqHhbiK8OIPDPyh3tPIXFd+XKfQNrdV62RhfYE4L6+/o8iCW5+4JLB2pEzhjE+/M/skvPWuTnxDeUElAgxQiNThH0T1PGvcZcClrzL5rt2SghmhGSJbASqwuSF6DQAcY/Fh/wl8vuQt0IC59ObU7VTJK0Rb4N/locZBZCfWesPZov2e2d71e0UMLy7R84ejeCqirbKg/Z6zWb2ArYDr4vpBXsrlRtcoolC86s+rZ6jKYZtO9UX08xwMyIF+46DO+CpDoaf7ZsVnSH3zZA4ilKIgqyNhcJITStmA= MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: cc9e7fb9-d82b-4123-cf43-08d7090ca117 X-MS-Exchange-CrossTenant-originalarrivaltime: 15 Jul 2019 10:10:14.5223 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: peng.fan@nxp.com X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM0PR04MB4356 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190715_031017_982343_8D43E6F4 X-CRM114-Status: GOOD ( 18.40 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "devicetree@vger.kernel.org" , Peng Fan , "linux-kernel@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , dl-linux-imx Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP From: Peng Fan This mailbox driver implements a mailbox which signals transmitted data via an ARM smc (secure monitor call) instruction. The mailbox receiver is implemented in firmware and can synchronously return data when it returns execution to the non-secure world again. An asynchronous receive path is not implemented. This allows the usage of a mailbox to trigger firmware actions on SoCs which either don't have a separate management processor or on which such a core is not available. A user of this mailbox could be the SCP interface. Modified from Andre Przywara's v2 patch https://lore.kernel.org/patchwork/patch/812999/ Cc: Andre Przywara Signed-off-by: Peng Fan --- V3: Drop interrupt. Introduce transports for mem/reg usage. Add chan-id for mem usage. V2: Add interrupts notification support. drivers/mailbox/Kconfig | 7 ++ drivers/mailbox/Makefile | 2 + drivers/mailbox/arm-smc-mailbox.c | 215 ++++++++++++++++++++++++++++++++++++++ 3 files changed, 224 insertions(+) create mode 100644 drivers/mailbox/arm-smc-mailbox.c diff --git a/drivers/mailbox/Kconfig b/drivers/mailbox/Kconfig index 595542bfae85..c3bd0f1ddcd8 100644 --- a/drivers/mailbox/Kconfig +++ b/drivers/mailbox/Kconfig @@ -15,6 +15,13 @@ config ARM_MHU The controller has 3 mailbox channels, the last of which can be used in Secure mode only. +config ARM_SMC_MBOX + tristate "Generic ARM smc mailbox" + depends on OF && HAVE_ARM_SMCCC + help + Generic mailbox driver which uses ARM smc calls to call into + firmware for triggering mailboxes. + config IMX_MBOX tristate "i.MX Mailbox" depends on ARCH_MXC || COMPILE_TEST diff --git a/drivers/mailbox/Makefile b/drivers/mailbox/Makefile index c22fad6f696b..93918a84c91b 100644 --- a/drivers/mailbox/Makefile +++ b/drivers/mailbox/Makefile @@ -7,6 +7,8 @@ obj-$(CONFIG_MAILBOX_TEST) += mailbox-test.o obj-$(CONFIG_ARM_MHU) += arm_mhu.o +obj-$(CONFIG_ARM_SMC_MBOX) += arm-smc-mailbox.o + obj-$(CONFIG_IMX_MBOX) += imx-mailbox.o obj-$(CONFIG_ARMADA_37XX_RWTM_MBOX) += armada-37xx-rwtm-mailbox.o diff --git a/drivers/mailbox/arm-smc-mailbox.c b/drivers/mailbox/arm-smc-mailbox.c new file mode 100644 index 000000000000..76a2ae11ee4d --- /dev/null +++ b/drivers/mailbox/arm-smc-mailbox.c @@ -0,0 +1,215 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2016,2017 ARM Ltd. + * Copyright 2019 NXP + */ + +#include +#include +#include +#include +#include +#include +#include + +#define ARM_SMC_MBOX_MEM_TRANS BIT(0) + +struct arm_smc_chan_data { + u32 function_id; + u32 chan_id; + u32 flags; +}; + +struct arm_smccc_mbox_cmd { + unsigned long a0, a1, a2, a3, a4, a5, a6, a7; +}; + +typedef unsigned long (smc_mbox_fn)(unsigned long, unsigned long, + unsigned long, unsigned long, + unsigned long, unsigned long, + unsigned long, unsigned long); +static smc_mbox_fn *invoke_smc_mbox_fn; + +static int arm_smc_send_data(struct mbox_chan *link, void *data) +{ + struct arm_smc_chan_data *chan_data = link->con_priv; + struct arm_smccc_mbox_cmd *cmd = data; + unsigned long ret; + u32 function_id; + u32 chan_id; + + if (chan_data->flags & ARM_SMC_MBOX_MEM_TRANS) { + if (chan_data->function_id != UINT_MAX) + function_id = chan_data->function_id; + else + function_id = cmd->a0; + chan_id = chan_data->chan_id; + ret = invoke_smc_mbox_fn(function_id, chan_id, 0, 0, 0, 0, + 0, 0); + } else { + ret = invoke_smc_mbox_fn(cmd->a0, cmd->a1, cmd->a2, cmd->a3, + cmd->a4, cmd->a5, cmd->a6, cmd->a7); + } + + mbox_chan_received_data(link, (void *)ret); + + return 0; +} + +static unsigned long __invoke_fn_hvc(unsigned long function_id, + unsigned long arg0, unsigned long arg1, + unsigned long arg2, unsigned long arg3, + unsigned long arg4, unsigned long arg5, + unsigned long arg6) +{ + struct arm_smccc_res res; + + arm_smccc_hvc(function_id, arg0, arg1, arg2, arg3, arg4, + arg5, arg6, &res); + return res.a0; +} + +static unsigned long __invoke_fn_smc(unsigned long function_id, + unsigned long arg0, unsigned long arg1, + unsigned long arg2, unsigned long arg3, + unsigned long arg4, unsigned long arg5, + unsigned long arg6) +{ + struct arm_smccc_res res; + + arm_smccc_smc(function_id, arg0, arg1, arg2, arg3, arg4, + arg5, arg6, &res); + return res.a0; +} + +static const struct mbox_chan_ops arm_smc_mbox_chan_ops = { + .send_data = arm_smc_send_data, +}; + +static int arm_smc_mbox_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct mbox_controller *mbox; + struct arm_smc_chan_data *chan_data; + const char *method; + bool mem_trans = false; + int ret, i; + u32 val; + + if (!of_property_read_u32(dev->of_node, "arm,num-chans", &val)) { + if (!val) { + dev_err(dev, "invalid arm,num-chans value %u\n", val); + return -EINVAL; + } + } else { + return -EINVAL; + } + + if (!of_property_read_string(dev->of_node, "transports", &method)) { + if (!strcmp("mem", method)) { + mem_trans = true; + } else if (!strcmp("reg", method)) { + mem_trans = false; + } else { + dev_warn(dev, "invalid \"transports\" property: %s\n", + method); + + return -EINVAL; + } + } else { + return -EINVAL; + } + + if (!of_property_read_string(dev->of_node, "method", &method)) { + if (!strcmp("hvc", method)) { + invoke_smc_mbox_fn = __invoke_fn_hvc; + } else if (!strcmp("smc", method)) { + invoke_smc_mbox_fn = __invoke_fn_smc; + } else { + dev_warn(dev, "invalid \"method\" property: %s\n", + method); + + return -EINVAL; + } + } else { + return -EINVAL; + } + + mbox = devm_kzalloc(dev, sizeof(*mbox), GFP_KERNEL); + if (!mbox) + return -ENOMEM; + + mbox->num_chans = val; + mbox->chans = devm_kcalloc(dev, mbox->num_chans, sizeof(*mbox->chans), + GFP_KERNEL); + if (!mbox->chans) + return -ENOMEM; + + chan_data = devm_kcalloc(dev, mbox->num_chans, sizeof(*chan_data), + GFP_KERNEL); + if (!chan_data) + return -ENOMEM; + + for (i = 0; i < mbox->num_chans; i++) { + u32 function_id; + + ret = of_property_read_u32_index(dev->of_node, + "arm,func-ids", i, + &function_id); + if (ret) + chan_data[i].function_id = UINT_MAX; + + else + chan_data[i].function_id = function_id; + + chan_data[i].chan_id = i; + + if (mem_trans) + chan_data[i].flags |= ARM_SMC_MBOX_MEM_TRANS; + mbox->chans[i].con_priv = &chan_data[i]; + } + + mbox->txdone_poll = false; + mbox->txdone_irq = false; + mbox->ops = &arm_smc_mbox_chan_ops; + mbox->dev = dev; + + platform_set_drvdata(pdev, mbox); + + ret = devm_mbox_controller_register(dev, mbox); + if (ret) + return ret; + + dev_info(dev, "ARM SMC mailbox enabled with %d chan%s.\n", + mbox->num_chans, mbox->num_chans == 1 ? "" : "s"); + + return ret; +} + +static int arm_smc_mbox_remove(struct platform_device *pdev) +{ + struct mbox_controller *mbox = platform_get_drvdata(pdev); + + mbox_controller_unregister(mbox); + return 0; +} + +static const struct of_device_id arm_smc_mbox_of_match[] = { + { .compatible = "arm,smc-mbox", }, + {}, +}; +MODULE_DEVICE_TABLE(of, arm_smc_mbox_of_match); + +static struct platform_driver arm_smc_mbox_driver = { + .driver = { + .name = "arm-smc-mbox", + .of_match_table = arm_smc_mbox_of_match, + }, + .probe = arm_smc_mbox_probe, + .remove = arm_smc_mbox_remove, +}; +module_platform_driver(arm_smc_mbox_driver); + +MODULE_AUTHOR("Andre Przywara "); +MODULE_DESCRIPTION("Generic ARM smc mailbox driver"); +MODULE_LICENSE("GPL v2");