From patchwork Mon Jul 15 18:20:56 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 11044657 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 2263B138D for ; Mon, 15 Jul 2019 18:21:36 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 12A8A2849D for ; Mon, 15 Jul 2019 18:21:36 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 06BF0284C8; Mon, 15 Jul 2019 18:21:36 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 66A52284BD for ; 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/* PI_41 PI_CS_MAP:RW:24:4 */ clrsetbits_le32(&denali_pi[41], 0xf << 24, cs_map << 24); - if ((sdram_ch->rank == 1) && (sdram_params->base.dramtype == DDR3)) + if (sdram_ch->rank == 1 && sdram_params->base.dramtype == DDR3) writel(0x2EC7FFFF, &denali_pi[34]); } @@ -166,10 +166,10 @@ static void set_ds_odt(const struct chan_info *chan, u32 reg_value; if (sdram_params->base.dramtype == LPDDR4) { - tsel_rd_select_p = PHY_DRV_ODT_Hi_Z; + tsel_rd_select_p = PHY_DRV_ODT_HI_Z; tsel_wr_select_p = PHY_DRV_ODT_40; ca_tsel_wr_select_p = PHY_DRV_ODT_40; - tsel_idle_select_p = PHY_DRV_ODT_Hi_Z; + tsel_idle_select_p = PHY_DRV_ODT_HI_Z; tsel_rd_select_n = PHY_DRV_ODT_240; tsel_wr_select_n = PHY_DRV_ODT_40; @@ -181,10 +181,10 @@ static void set_ds_odt(const struct chan_info *chan, ca_tsel_wr_select_p = PHY_DRV_ODT_48; tsel_idle_select_p = PHY_DRV_ODT_240; - tsel_rd_select_n = PHY_DRV_ODT_Hi_Z; + tsel_rd_select_n = PHY_DRV_ODT_HI_Z; tsel_wr_select_n = PHY_DRV_ODT_34_3; ca_tsel_wr_select_n = PHY_DRV_ODT_48; - tsel_idle_select_n = PHY_DRV_ODT_Hi_Z; + tsel_idle_select_n = PHY_DRV_ODT_HI_Z; } else { tsel_rd_select_p = PHY_DRV_ODT_240; tsel_wr_select_p = PHY_DRV_ODT_34_3; @@ -294,7 +294,7 @@ static void set_ds_odt(const struct chan_info *chan, } static int phy_io_config(const struct chan_info *chan, - const struct rk3399_sdram_params *sdram_params) + const struct rk3399_sdram_params *sdram_params) { u32 *denali_phy = chan->publ->denali_phy; u32 vref_mode_dq, vref_value_dq, vref_mode_ac, vref_value_ac; @@ -423,7 +423,6 @@ static int phy_io_config(const struct chan_info *chan, /* PHY_939 PHY_PAD_CS_DRIVE */ clrsetbits_le32(&denali_phy[939], 0x7 << 14, mode_sel << 14); - /* speed setting */ if (sdram_params->base.ddr_freq < 400) speed = 0x0; @@ -492,7 +491,7 @@ static int pctl_cfg(const struct chan_info *chan, u32 channel, setbits_le32(&denali_pi[0], START); setbits_le32(&denali_ctl[0], START); - /* Wating for phy DLL lock */ + /* Waiting for phy DLL lock */ while (1) { tmp = readl(&denali_phy[920]); tmp1 = readl(&denali_phy[921]); @@ -547,12 +546,12 @@ static int pctl_cfg(const struct chan_info *chan, u32 channel, /* PHY_DLL_RST_EN */ clrsetbits_le32(&denali_phy[957], 0x3 << 24, 0x2 << 24); - /* Wating for PHY and DRAM init complete */ + /* Waiting for PHY and DRAM init complete */ tmp = get_timer(0); do { if (get_timer(tmp) > timeout_ms) { pr_err("DRAM (%s): phy failed to lock within %ld ms\n", - __func__, timeout_ms); + __func__, timeout_ms); return -ETIME; } } while (!(readl(&denali_ctl[203]) & (1 << 3))); @@ -569,7 +568,7 @@ static void select_per_cs_training_index(const struct chan_info *chan, u32 *denali_phy = chan->publ->denali_phy; /* PHY_84 PHY_PER_CS_TRAINING_EN_0 1bit offset_16 */ - if ((readl(&denali_phy[84])>>16) & 1) { + if ((readl(&denali_phy[84]) >> 16) & 1) { /* * PHY_8/136/264/392 * phy_per_cs_training_index_X 1bit offset_24 @@ -646,7 +645,7 @@ static int data_training_ca(const struct chan_info *chan, u32 channel, if ((((tmp >> 11) & 0x1) == 0x1) && (((tmp >> 13) & 0x1) == 0x1) && (((tmp >> 5) & 0x1) == 0x0) && - (obs_err == 0)) + obs_err == 0) break; else if ((((tmp >> 5) & 0x1) == 0x1) || (obs_err == 1)) @@ -700,7 +699,7 @@ static int data_training_wl(const struct chan_info *chan, u32 channel, if ((((tmp >> 10) & 0x1) == 0x1) && (((tmp >> 13) & 0x1) == 0x1) && (((tmp >> 4) & 0x1) == 0x0) && - (obs_err == 0)) + obs_err == 0) break; else if ((((tmp >> 4) & 0x1) == 0x1) || (obs_err == 1)) @@ -759,7 +758,7 @@ static int data_training_rg(const struct chan_info *chan, u32 channel, if ((((tmp >> 9) & 0x1) == 0x1) && (((tmp >> 13) & 0x1) == 0x1) && (((tmp >> 3) & 0x1) == 0x0) && - (obs_err == 0)) + obs_err == 0) break; else if ((((tmp >> 3) & 0x1) == 0x1) || (obs_err == 1)) @@ -955,8 +954,10 @@ static void dram_all_config(struct dram_info *dram, sys_reg |= (info->rank - 1) << SYS_REG_RANK_SHIFT(channel); sys_reg |= (info->col - 9) << SYS_REG_COL_SHIFT(channel); sys_reg |= info->bk == 3 ? 0 : 1 << SYS_REG_BK_SHIFT(channel); - sys_reg |= (info->cs0_row - 13) << SYS_REG_CS0_ROW_SHIFT(channel); - sys_reg |= (info->cs1_row - 13) << SYS_REG_CS1_ROW_SHIFT(channel); + sys_reg |= (info->cs0_row - 13) << + SYS_REG_CS0_ROW_SHIFT(channel); + sys_reg |= (info->cs1_row - 13) << + SYS_REG_CS1_ROW_SHIFT(channel); sys_reg |= (2 >> info->bw) << SYS_REG_BW_SHIFT(channel); sys_reg |= (2 >> info->dbw) << SYS_REG_DBW_SHIFT(channel); @@ -991,7 +992,7 @@ static void dram_all_config(struct dram_info *dram, } static int switch_to_phy_index1(struct dram_info *dram, - const struct rk3399_sdram_params *sdram_params) + const struct rk3399_sdram_params *sdram_params) { u32 channel; u32 *denali_phy; @@ -1026,7 +1027,7 @@ static int switch_to_phy_index1(struct dram_info *dram, denali_phy = dram->chan[channel].publ->denali_phy; clrsetbits_le32(&denali_phy[896], (0x3 << 8) | 1, 1 << 8); ret = data_training(&dram->chan[channel], channel, - sdram_params, PI_FULL_TRAINING); + sdram_params, PI_FULL_TRAINING); if (ret) { debug("index1 training failed\n"); return ret; @@ -1116,8 +1117,8 @@ static int conv_of_platdata(struct udevice *dev) int ret; ret = regmap_init_mem_platdata(dev, dtplat->reg, - ARRAY_SIZE(dtplat->reg) / 2, - &plat->map); + ARRAY_SIZE(dtplat->reg) / 2, + &plat->map); if (ret) return ret; @@ -1199,8 +1200,8 @@ static int rk3399_dmc_probe(struct udevice *dev) priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF); debug("%s: pmugrf=%p\n", __func__, priv->pmugrf); priv->info.base = CONFIG_SYS_SDRAM_BASE; - priv->info.size = rockchip_sdram_size( - (phys_addr_t)&priv->pmugrf->os_reg2); + priv->info.size = + rockchip_sdram_size((phys_addr_t)&priv->pmugrf->os_reg2); #endif return 0; } @@ -1218,7 +1219,6 @@ static struct ram_ops rk3399_dmc_ops = { .get_info = rk3399_dmc_get_info, }; - static const struct udevice_id rk3399_dmc_ids[] = { { .compatible = "rockchip,rk3399-dmc" }, { } From patchwork Mon Jul 15 18:20:57 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 11044659 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 6D3ED112C for ; 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Mon, 15 Jul 2019 11:21:27 -0700 (PDT) Received: from localhost.localdomain ([49.206.201.107]) by smtp.gmail.com with ESMTPSA id l15sm18152405pgf.5.2019.07.15.11.21.24 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 15 Jul 2019 11:21:27 -0700 (PDT) From: Jagan Teki To: Simon Glass , Philipp Tomsich , Kever Yang , YouMin Chen , u-boot@lists.denx.de Subject: [PATCH v3 02/15] ram: rk3399: Some trivial code fixes Date: Mon, 15 Jul 2019 23:50:57 +0530 Message-Id: <20190715182110.21336-3-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.18.0.321.gffc6fa0e3 In-Reply-To: <20190715182110.21336-1-jagan@amarulasolutions.com> References: <20190715182110.21336-1-jagan@amarulasolutions.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190715_112128_999095_6A7D64CA X-CRM114-Status: GOOD ( 13.11 ) X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-rockchip@lists.infradead.org, gajjar04akash@gmail.com, linux-amarula@amarulasolutions.com, Jagan Teki , Manivannan Sadhasivam Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+patchwork-linux-rockchip=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP - Add proper spaces in data training, rk3399_dmc_init, pctl_cfg - Order include files - Move macro after include files Signed-off-by: Jagan Teki Reviewed-by: Kever Yang --- drivers/ram/rockchip/sdram_rk3399.c | 60 +++++++++++++++++++++-------- 1 file changed, 43 insertions(+), 17 deletions(-) diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c index 541e4a4b1e..733864f5d2 100644 --- a/drivers/ram/rockchip/sdram_rk3399.c +++ b/drivers/ram/rockchip/sdram_rk3399.c @@ -14,14 +14,27 @@ #include #include #include -#include -#include #include #include #include +#include +#include #include #include +#define PRESET_SGRF_HOLD(n) ((0x1 << (6 + 16)) | ((n) << 6)) +#define PRESET_GPIO0_HOLD(n) ((0x1 << (7 + 16)) | ((n) << 7)) +#define PRESET_GPIO1_HOLD(n) ((0x1 << (8 + 16)) | ((n) << 8)) + +#define PHY_DRV_ODT_HI_Z 0x0 +#define PHY_DRV_ODT_240 0x1 +#define PHY_DRV_ODT_120 0x8 +#define PHY_DRV_ODT_80 0x9 +#define PHY_DRV_ODT_60 0xc +#define PHY_DRV_ODT_48 0xd +#define PHY_DRV_ODT_40 0xe +#define PHY_DRV_ODT_34_3 0xf + struct chan_info { struct rk3399_ddr_pctl_regs *pctl; struct rk3399_ddr_pi_regs *pi; @@ -43,19 +56,6 @@ struct dram_info { struct rk3399_pmugrf_regs *pmugrf; }; -#define PRESET_SGRF_HOLD(n) ((0x1 << (6 + 16)) | ((n) << 6)) -#define PRESET_GPIO0_HOLD(n) ((0x1 << (7 + 16)) | ((n) << 7)) -#define PRESET_GPIO1_HOLD(n) ((0x1 << (8 + 16)) | ((n) << 8)) - -#define PHY_DRV_ODT_HI_Z 0x0 -#define PHY_DRV_ODT_240 0x1 -#define PHY_DRV_ODT_120 0x8 -#define PHY_DRV_ODT_80 0x9 -#define PHY_DRV_ODT_60 0xc -#define PHY_DRV_ODT_48 0xd -#define PHY_DRV_ODT_40 0xe -#define PHY_DRV_ODT_34_3 0xf - #if defined(CONFIG_TPL_BUILD) || \ (!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD)) @@ -473,8 +473,10 @@ static int pctl_cfg(const struct chan_info *chan, u32 channel, copy_to_reg(&denali_ctl[1], ¶ms_ctl[1], sizeof(struct rk3399_ddr_pctl_regs) - 4); writel(params_ctl[0], &denali_ctl[0]); + copy_to_reg(denali_pi, &sdram_params->pi_regs.denali_pi[0], sizeof(struct rk3399_ddr_pi_regs)); + /* rank count need to set for init */ set_memory_map(chan, channel, sdram_params); @@ -620,8 +622,10 @@ static int data_training_ca(const struct chan_info *chan, u32 channel, for (i = 0; i < rank; i++) { select_per_cs_training_index(chan, i); + /* PI_100 PI_CALVL_EN:RW:8:2 */ clrsetbits_le32(&denali_pi[100], 0x3 << 8, 0x2 << 8); + /* PI_92 PI_CALVL_REQ:WR:16:1,PI_CALVL_CS:RW:24:2 */ clrsetbits_le32(&denali_pi[92], (0x1 << 16) | (0x3 << 24), @@ -651,9 +655,11 @@ static int data_training_ca(const struct chan_info *chan, u32 channel, (obs_err == 1)) return -EIO; } + /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */ writel(0x00003f7c, (&denali_pi[175])); } + clrbits_le32(&denali_pi[100], 0x3 << 8); return 0; @@ -670,8 +676,10 @@ static int data_training_wl(const struct chan_info *chan, u32 channel, for (i = 0; i < rank; i++) { select_per_cs_training_index(chan, i); + /* PI_60 PI_WRLVL_EN:RW:8:2 */ clrsetbits_le32(&denali_pi[60], 0x3 << 8, 0x2 << 8); + /* PI_59 PI_WRLVL_REQ:WR:8:1,PI_WRLVL_CS:RW:16:2 */ clrsetbits_le32(&denali_pi[59], (0x1 << 8) | (0x3 << 16), @@ -705,6 +713,7 @@ static int data_training_wl(const struct chan_info *chan, u32 channel, (obs_err == 1)) return -EIO; } + /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */ writel(0x00003f7c, (&denali_pi[175])); } @@ -726,8 +735,10 @@ static int data_training_rg(const struct chan_info *chan, u32 channel, for (i = 0; i < rank; i++) { select_per_cs_training_index(chan, i); + /* PI_80 PI_RDLVL_GATE_EN:RW:24:2 */ clrsetbits_le32(&denali_pi[80], 0x3 << 24, 0x2 << 24); + /* * PI_74 PI_RDLVL_GATE_REQ:WR:16:1 * PI_RDLVL_CS:RW:24:2 @@ -764,9 +775,11 @@ static int data_training_rg(const struct chan_info *chan, u32 channel, (obs_err == 1)) return -EIO; } + /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */ writel(0x00003f7c, (&denali_pi[175])); } + clrbits_le32(&denali_pi[80], 0x3 << 24); return 0; @@ -781,8 +794,10 @@ static int data_training_rl(const struct chan_info *chan, u32 channel, for (i = 0; i < rank; i++) { select_per_cs_training_index(chan, i); + /* PI_80 PI_RDLVL_EN:RW:16:2 */ clrsetbits_le32(&denali_pi[80], 0x3 << 16, 0x2 << 16); + /* PI_74 PI_RDLVL_REQ:WR:8:1,PI_RDLVL_CS:RW:24:2 */ clrsetbits_le32(&denali_pi[74], (0x1 << 8) | (0x3 << 24), @@ -805,9 +820,11 @@ static int data_training_rl(const struct chan_info *chan, u32 channel, else if (((tmp >> 2) & 0x1) == 0x1) return -EIO; } + /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */ writel(0x00003f7c, (&denali_pi[175])); } + clrbits_le32(&denali_pi[80], 0x3 << 16); return 0; @@ -822,13 +839,16 @@ static int data_training_wdql(const struct chan_info *chan, u32 channel, for (i = 0; i < rank; i++) { select_per_cs_training_index(chan, i); + /* * disable PI_WDQLVL_VREF_EN before wdq leveling? * PI_181 PI_WDQLVL_VREF_EN:RW:8:1 */ clrbits_le32(&denali_pi[181], 0x1 << 8); + /* PI_124 PI_WDQLVL_EN:RW:16:2 */ clrsetbits_le32(&denali_pi[124], 0x3 << 16, 0x2 << 16); + /* PI_121 PI_WDQLVL_REQ:WR:8:1,PI_WDQLVL_CS:RW:16:2 */ clrsetbits_le32(&denali_pi[121], (0x1 << 8) | (0x3 << 16), @@ -845,9 +865,11 @@ static int data_training_wdql(const struct chan_info *chan, u32 channel, else if (((tmp >> 6) & 0x1) == 0x1) return -EIO; } + /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */ writel(0x00003f7c, (&denali_pi[175])); } + clrbits_le32(&denali_pi[124], 0x3 << 16); return 0; @@ -938,6 +960,7 @@ static void dram_all_config(struct dram_info *dram, sys_reg |= sdram_params->base.dramtype << SYS_REG_DDRTYPE_SHIFT; sys_reg |= (sdram_params->base.num_channels - 1) << SYS_REG_NUM_CH_SHIFT; + for (channel = 0, idx = 0; (idx < sdram_params->base.num_channels) && (channel < 2); channel++) { @@ -1164,6 +1187,7 @@ static int rk3399_dmc_init(struct udevice *dev) priv->chan[1].publ, priv->chan[1].msch); debug("cru %p, cic %p, grf %p, sgrf %p, pmucru %p\n", priv->cru, priv->cic, priv->pmugrf, priv->pmusgrf, priv->pmucru); + #if CONFIG_IS_ENABLED(OF_PLATDATA) ret = clk_get_by_index_platdata(dev, 0, dtplat->clocks, &priv->ddr_clk); #else @@ -1173,14 +1197,16 @@ static int rk3399_dmc_init(struct udevice *dev) printf("%s clk get failed %d\n", __func__, ret); return ret; } + ret = clk_set_rate(&priv->ddr_clk, params->base.ddr_freq * MHz); if (ret < 0) { printf("%s clk set failed %d\n", __func__, ret); return ret; } + ret = sdram_init(priv, params); if (ret < 0) { - printf("%s DRAM init failed%d\n", __func__, ret); + printf("%s DRAM init failed %d\n", __func__, ret); return ret; } @@ -1198,7 +1224,7 @@ static int rk3399_dmc_probe(struct udevice *dev) struct dram_info *priv = dev_get_priv(dev); priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF); - debug("%s: pmugrf=%p\n", __func__, priv->pmugrf); + debug("%s: pmugrf = %p\n", __func__, priv->pmugrf); priv->info.base = CONFIG_SYS_SDRAM_BASE; priv->info.size = rockchip_sdram_size((phys_addr_t)&priv->pmugrf->os_reg2); From patchwork Mon Jul 15 18:20:58 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 11044661 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 258BB112C for ; Mon, 15 Jul 2019 18:21:40 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 154CD2849D for ; Mon, 15 Jul 2019 18:21:40 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 093C4284C8; Mon, 15 Jul 2019 18:21:40 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id EF5382849D for ; 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No functionality change. Signed-off-by: Jagan Teki Reviewed-by: Kever Yang --- drivers/ram/rockchip/sdram_rk3399.c | 160 ++++++++++++++-------------- 1 file changed, 78 insertions(+), 82 deletions(-) diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c index 733864f5d2..c918c2e588 100644 --- a/drivers/ram/rockchip/sdram_rk3399.c +++ b/drivers/ram/rockchip/sdram_rk3399.c @@ -111,10 +111,9 @@ static void phy_dll_bypass_set(struct rk3399_ddr_publ_regs *ddr_publ_regs, } static void set_memory_map(const struct chan_info *chan, u32 channel, - const struct rk3399_sdram_params *sdram_params) + const struct rk3399_sdram_params *params) { - const struct rk3399_sdram_channel *sdram_ch = - &sdram_params->ch[channel]; + const struct rk3399_sdram_channel *sdram_ch = ¶ms->ch[channel]; u32 *denali_ctl = chan->pctl->denali_ctl; u32 *denali_pi = chan->pi->denali_pi; u32 cs_map; @@ -150,12 +149,12 @@ static void set_memory_map(const struct chan_info *chan, u32 channel, ((16 - row) << 24)); /* PI_41 PI_CS_MAP:RW:24:4 */ clrsetbits_le32(&denali_pi[41], 0xf << 24, cs_map << 24); - if (sdram_ch->rank == 1 && sdram_params->base.dramtype == DDR3) + if (sdram_ch->rank == 1 && params->base.dramtype == DDR3) writel(0x2EC7FFFF, &denali_pi[34]); } static void set_ds_odt(const struct chan_info *chan, - const struct rk3399_sdram_params *sdram_params) + const struct rk3399_sdram_params *params) { u32 *denali_phy = chan->publ->denali_phy; @@ -165,7 +164,7 @@ static void set_ds_odt(const struct chan_info *chan, u32 tsel_idle_select_n, tsel_wr_select_n, tsel_rd_select_n; u32 reg_value; - if (sdram_params->base.dramtype == LPDDR4) { + if (params->base.dramtype == LPDDR4) { tsel_rd_select_p = PHY_DRV_ODT_HI_Z; tsel_wr_select_p = PHY_DRV_ODT_40; ca_tsel_wr_select_p = PHY_DRV_ODT_40; @@ -175,7 +174,7 @@ static void set_ds_odt(const struct chan_info *chan, tsel_wr_select_n = PHY_DRV_ODT_40; ca_tsel_wr_select_n = PHY_DRV_ODT_40; tsel_idle_select_n = PHY_DRV_ODT_240; - } else if (sdram_params->base.dramtype == LPDDR3) { + } else if (params->base.dramtype == LPDDR3) { tsel_rd_select_p = PHY_DRV_ODT_240; tsel_wr_select_p = PHY_DRV_ODT_34_3; ca_tsel_wr_select_p = PHY_DRV_ODT_48; @@ -197,7 +196,7 @@ static void set_ds_odt(const struct chan_info *chan, tsel_idle_select_n = PHY_DRV_ODT_240; } - if (sdram_params->base.odt == 1) + if (params->base.odt == 1) tsel_rd_en = 1; else tsel_rd_en = 0; @@ -294,7 +293,7 @@ static void set_ds_odt(const struct chan_info *chan, } static int phy_io_config(const struct chan_info *chan, - const struct rk3399_sdram_params *sdram_params) + const struct rk3399_sdram_params *params) { u32 *denali_phy = chan->publ->denali_phy; u32 vref_mode_dq, vref_value_dq, vref_mode_ac, vref_value_ac; @@ -304,14 +303,14 @@ static int phy_io_config(const struct chan_info *chan, u32 speed; /* vref setting */ - if (sdram_params->base.dramtype == LPDDR4) { + if (params->base.dramtype == LPDDR4) { /* LPDDR4 */ vref_mode_dq = 0x6; vref_value_dq = 0x1f; vref_mode_ac = 0x6; vref_value_ac = 0x1f; - } else if (sdram_params->base.dramtype == LPDDR3) { - if (sdram_params->base.odt == 1) { + } else if (params->base.dramtype == LPDDR3) { + if (params->base.odt == 1) { vref_mode_dq = 0x5; /* LPDDR3 ODT */ drv_value = (readl(&denali_phy[6]) >> 12) & 0xf; odt_value = (readl(&denali_phy[6]) >> 4) & 0xf; @@ -370,7 +369,7 @@ static int phy_io_config(const struct chan_info *chan, } vref_mode_ac = 0x2; vref_value_ac = 0x1f; - } else if (sdram_params->base.dramtype == DDR3) { + } else if (params->base.dramtype == DDR3) { /* DDR3L */ vref_mode_dq = 0x1; vref_value_dq = 0x1f; @@ -397,11 +396,11 @@ static int phy_io_config(const struct chan_info *chan, /* PHY_915 PHY_PAD_VREF_CTRL_AC 12bits offset_16 */ clrsetbits_le32(&denali_phy[915], 0xfff << 16, reg_value << 16); - if (sdram_params->base.dramtype == LPDDR4) + if (params->base.dramtype == LPDDR4) mode_sel = 0x6; - else if (sdram_params->base.dramtype == LPDDR3) + else if (params->base.dramtype == LPDDR3) mode_sel = 0x0; - else if (sdram_params->base.dramtype == DDR3) + else if (params->base.dramtype == DDR3) mode_sel = 0x1; else return -EINVAL; @@ -424,11 +423,11 @@ static int phy_io_config(const struct chan_info *chan, clrsetbits_le32(&denali_phy[939], 0x7 << 14, mode_sel << 14); /* speed setting */ - if (sdram_params->base.ddr_freq < 400) + if (params->base.ddr_freq < 400) speed = 0x0; - else if (sdram_params->base.ddr_freq < 800) + else if (params->base.ddr_freq < 800) speed = 0x1; - else if (sdram_params->base.ddr_freq < 1200) + else if (params->base.ddr_freq < 1200) speed = 0x2; else speed = 0x3; @@ -454,13 +453,13 @@ static int phy_io_config(const struct chan_info *chan, } static int pctl_cfg(const struct chan_info *chan, u32 channel, - const struct rk3399_sdram_params *sdram_params) + const struct rk3399_sdram_params *params) { u32 *denali_ctl = chan->pctl->denali_ctl; u32 *denali_pi = chan->pi->denali_pi; u32 *denali_phy = chan->publ->denali_phy; - const u32 *params_ctl = sdram_params->pctl_regs.denali_ctl; - const u32 *params_phy = sdram_params->phy_regs.denali_phy; + const u32 *params_ctl = params->pctl_regs.denali_ctl; + const u32 *params_phy = params->phy_regs.denali_phy; u32 tmp, tmp1, tmp2; u32 pwrup_srefresh_exit; int ret; @@ -474,15 +473,15 @@ static int pctl_cfg(const struct chan_info *chan, u32 channel, sizeof(struct rk3399_ddr_pctl_regs) - 4); writel(params_ctl[0], &denali_ctl[0]); - copy_to_reg(denali_pi, &sdram_params->pi_regs.denali_pi[0], + copy_to_reg(denali_pi, ¶ms->pi_regs.denali_pi[0], sizeof(struct rk3399_ddr_pi_regs)); /* rank count need to set for init */ - set_memory_map(chan, channel, sdram_params); + set_memory_map(chan, channel, params); - writel(sdram_params->phy_regs.denali_phy[910], &denali_phy[910]); - writel(sdram_params->phy_regs.denali_phy[911], &denali_phy[911]); - writel(sdram_params->phy_regs.denali_phy[912], &denali_phy[912]); + writel(params->phy_regs.denali_phy[910], &denali_phy[910]); + writel(params->phy_regs.denali_phy[911], &denali_phy[911]); + writel(params->phy_regs.denali_phy[912], &denali_phy[912]); pwrup_srefresh_exit = readl(&denali_ctl[68]) & PWRUP_SREFRESH_EXIT; clrbits_le32(&denali_ctl[68], PWRUP_SREFRESH_EXIT); @@ -513,7 +512,7 @@ static int pctl_cfg(const struct chan_info *chan, u32 channel, copy_to_reg(&denali_phy[512], ¶ms_phy[512], (549 - 512 + 1) * 4); copy_to_reg(&denali_phy[640], ¶ms_phy[640], (677 - 640 + 1) * 4); copy_to_reg(&denali_phy[768], ¶ms_phy[768], (805 - 768 + 1) * 4); - set_ds_odt(chan, sdram_params); + set_ds_odt(chan, params); /* * phy_dqs_tsel_wr_timing_X 8bits DENALI_PHY_84/212/340/468 offset_8 @@ -541,7 +540,7 @@ static int pctl_cfg(const struct chan_info *chan, u32 channel, tmp = (readl(&denali_phy[467]) >> 16) & 0xff; clrsetbits_le32(&denali_phy[467], 0xff << 16, (tmp + 0x10) << 16); - ret = phy_io_config(chan, sdram_params); + ret = phy_io_config(chan, params); if (ret) return ret; @@ -612,13 +611,13 @@ static void override_write_leveling_value(const struct chan_info *chan) } static int data_training_ca(const struct chan_info *chan, u32 channel, - const struct rk3399_sdram_params *sdram_params) + const struct rk3399_sdram_params *params) { u32 *denali_pi = chan->pi->denali_pi; u32 *denali_phy = chan->publ->denali_phy; u32 i, tmp; u32 obs_0, obs_1, obs_2, obs_err = 0; - u32 rank = sdram_params->ch[channel].rank; + u32 rank = params->ch[channel].rank; for (i = 0; i < rank; i++) { select_per_cs_training_index(chan, i); @@ -666,13 +665,13 @@ static int data_training_ca(const struct chan_info *chan, u32 channel, } static int data_training_wl(const struct chan_info *chan, u32 channel, - const struct rk3399_sdram_params *sdram_params) + const struct rk3399_sdram_params *params) { u32 *denali_pi = chan->pi->denali_pi; u32 *denali_phy = chan->publ->denali_phy; u32 i, tmp; u32 obs_0, obs_1, obs_2, obs_3, obs_err = 0; - u32 rank = sdram_params->ch[channel].rank; + u32 rank = params->ch[channel].rank; for (i = 0; i < rank; i++) { select_per_cs_training_index(chan, i); @@ -725,13 +724,13 @@ static int data_training_wl(const struct chan_info *chan, u32 channel, } static int data_training_rg(const struct chan_info *chan, u32 channel, - const struct rk3399_sdram_params *sdram_params) + const struct rk3399_sdram_params *params) { u32 *denali_pi = chan->pi->denali_pi; u32 *denali_phy = chan->publ->denali_phy; u32 i, tmp; u32 obs_0, obs_1, obs_2, obs_3, obs_err = 0; - u32 rank = sdram_params->ch[channel].rank; + u32 rank = params->ch[channel].rank; for (i = 0; i < rank; i++) { select_per_cs_training_index(chan, i); @@ -786,11 +785,11 @@ static int data_training_rg(const struct chan_info *chan, u32 channel, } static int data_training_rl(const struct chan_info *chan, u32 channel, - const struct rk3399_sdram_params *sdram_params) + const struct rk3399_sdram_params *params) { u32 *denali_pi = chan->pi->denali_pi; u32 i, tmp; - u32 rank = sdram_params->ch[channel].rank; + u32 rank = params->ch[channel].rank; for (i = 0; i < rank; i++) { select_per_cs_training_index(chan, i); @@ -831,11 +830,11 @@ static int data_training_rl(const struct chan_info *chan, u32 channel, } static int data_training_wdql(const struct chan_info *chan, u32 channel, - const struct rk3399_sdram_params *sdram_params) + const struct rk3399_sdram_params *params) { u32 *denali_pi = chan->pi->denali_pi; u32 i, tmp; - u32 rank = sdram_params->ch[channel].rank; + u32 rank = params->ch[channel].rank; for (i = 0; i < rank; i++) { select_per_cs_training_index(chan, i); @@ -876,7 +875,7 @@ static int data_training_wdql(const struct chan_info *chan, u32 channel, } static int data_training(const struct chan_info *chan, u32 channel, - const struct rk3399_sdram_params *sdram_params, + const struct rk3399_sdram_params *params, u32 training_flag) { u32 *denali_phy = chan->publ->denali_phy; @@ -885,14 +884,14 @@ static int data_training(const struct chan_info *chan, u32 channel, setbits_le32(&denali_phy[927], (1 << 22)); if (training_flag == PI_FULL_TRAINING) { - if (sdram_params->base.dramtype == LPDDR4) { + if (params->base.dramtype == LPDDR4) { training_flag = PI_CA_TRAINING | PI_WRITE_LEVELING | PI_READ_GATE_TRAINING | PI_READ_LEVELING | PI_WDQ_LEVELING; - } else if (sdram_params->base.dramtype == LPDDR3) { + } else if (params->base.dramtype == LPDDR3) { training_flag = PI_CA_TRAINING | PI_WRITE_LEVELING | PI_READ_GATE_TRAINING; - } else if (sdram_params->base.dramtype == DDR3) { + } else if (params->base.dramtype == DDR3) { training_flag = PI_WRITE_LEVELING | PI_READ_GATE_TRAINING | PI_READ_LEVELING; @@ -901,23 +900,23 @@ static int data_training(const struct chan_info *chan, u32 channel, /* ca training(LPDDR4,LPDDR3 support) */ if ((training_flag & PI_CA_TRAINING) == PI_CA_TRAINING) - data_training_ca(chan, channel, sdram_params); + data_training_ca(chan, channel, params); /* write leveling(LPDDR4,LPDDR3,DDR3 support) */ if ((training_flag & PI_WRITE_LEVELING) == PI_WRITE_LEVELING) - data_training_wl(chan, channel, sdram_params); + data_training_wl(chan, channel, params); /* read gate training(LPDDR4,LPDDR3,DDR3 support) */ if ((training_flag & PI_READ_GATE_TRAINING) == PI_READ_GATE_TRAINING) - data_training_rg(chan, channel, sdram_params); + data_training_rg(chan, channel, params); /* read leveling(LPDDR4,LPDDR3,DDR3 support) */ if ((training_flag & PI_READ_LEVELING) == PI_READ_LEVELING) - data_training_rl(chan, channel, sdram_params); + data_training_rl(chan, channel, params); /* wdq leveling(LPDDR4 support) */ if ((training_flag & PI_WDQ_LEVELING) == PI_WDQ_LEVELING) - data_training_wdql(chan, channel, sdram_params); + data_training_wdql(chan, channel, params); /* PHY_927 PHY_PAD_DQS_DRIVE RPULL offset_22 */ clrbits_le32(&denali_phy[927], (1 << 22)); @@ -926,7 +925,7 @@ static int data_training(const struct chan_info *chan, u32 channel, } static void set_ddrconfig(const struct chan_info *chan, - const struct rk3399_sdram_params *sdram_params, + const struct rk3399_sdram_params *params, unsigned char channel, u32 ddrconfig) { /* only need to set ddrconfig */ @@ -934,14 +933,14 @@ static void set_ddrconfig(const struct chan_info *chan, unsigned int cs0_cap = 0; unsigned int cs1_cap = 0; - cs0_cap = (1 << (sdram_params->ch[channel].cs0_row - + sdram_params->ch[channel].col - + sdram_params->ch[channel].bk - + sdram_params->ch[channel].bw - 20)); - if (sdram_params->ch[channel].rank > 1) - cs1_cap = cs0_cap >> (sdram_params->ch[channel].cs0_row - - sdram_params->ch[channel].cs1_row); - if (sdram_params->ch[channel].row_3_4) { + cs0_cap = (1 << (params->ch[channel].cs0_row + + params->ch[channel].col + + params->ch[channel].bk + + params->ch[channel].bw - 20)); + if (params->ch[channel].rank > 1) + cs1_cap = cs0_cap >> (params->ch[channel].cs0_row + - params->ch[channel].cs1_row); + if (params->ch[channel].row_3_4) { cs0_cap = cs0_cap * 3 / 4; cs1_cap = cs1_cap * 3 / 4; } @@ -952,24 +951,22 @@ static void set_ddrconfig(const struct chan_info *chan, } static void dram_all_config(struct dram_info *dram, - const struct rk3399_sdram_params *sdram_params) + const struct rk3399_sdram_params *params) { u32 sys_reg = 0; unsigned int channel, idx; - sys_reg |= sdram_params->base.dramtype << SYS_REG_DDRTYPE_SHIFT; - sys_reg |= (sdram_params->base.num_channels - 1) - << SYS_REG_NUM_CH_SHIFT; + sys_reg |= params->base.dramtype << SYS_REG_DDRTYPE_SHIFT; + sys_reg |= (params->base.num_channels - 1) << SYS_REG_NUM_CH_SHIFT; for (channel = 0, idx = 0; - (idx < sdram_params->base.num_channels) && (channel < 2); + (idx < params->base.num_channels) && (channel < 2); channel++) { - const struct rk3399_sdram_channel *info = - &sdram_params->ch[channel]; + const struct rk3399_sdram_channel *info = ¶ms->ch[channel]; struct rk3399_msch_regs *ddr_msch_regs; const struct rk3399_msch_timings *noc_timing; - if (sdram_params->ch[channel].col == 0) + if (params->ch[channel].col == 0) continue; idx++; sys_reg |= info->row_3_4 << SYS_REG_ROW_3_4_SHIFT(channel); @@ -985,7 +982,7 @@ static void dram_all_config(struct dram_info *dram, sys_reg |= (2 >> info->dbw) << SYS_REG_DBW_SHIFT(channel); ddr_msch_regs = dram->chan[channel].msch; - noc_timing = &sdram_params->ch[channel].noc_timings; + noc_timing = ¶ms->ch[channel].noc_timings; writel(noc_timing->ddrtiminga0, &ddr_msch_regs->ddrtiminga0); writel(noc_timing->ddrtimingb0, @@ -998,14 +995,14 @@ static void dram_all_config(struct dram_info *dram, &ddr_msch_regs->ddrmode); /* rank 1 memory clock disable (dfi_dram_clk_disable = 1) */ - if (sdram_params->ch[channel].rank == 1) + if (params->ch[channel].rank == 1) setbits_le32(&dram->chan[channel].pctl->denali_ctl[276], 1 << 17); } writel(sys_reg, &dram->pmugrf->os_reg2); rk_clrsetreg(&dram->pmusgrf->soc_con4, 0x1f << 10, - sdram_params->base.stride << 10); + params->base.stride << 10); /* reboot hold register set */ writel(PRESET_SGRF_HOLD(0) | PRESET_GPIO0_HOLD(1) | @@ -1015,11 +1012,11 @@ static void dram_all_config(struct dram_info *dram, } static int switch_to_phy_index1(struct dram_info *dram, - const struct rk3399_sdram_params *sdram_params) + const struct rk3399_sdram_params *params) { u32 channel; u32 *denali_phy; - u32 ch_count = sdram_params->base.num_channels; + u32 ch_count = params->base.num_channels; int ret; int i = 0; @@ -1050,7 +1047,7 @@ static int switch_to_phy_index1(struct dram_info *dram, denali_phy = dram->chan[channel].publ->denali_phy; clrsetbits_le32(&denali_phy[896], (0x3 << 8) | 1, 1 << 8); ret = data_training(&dram->chan[channel], channel, - sdram_params, PI_FULL_TRAINING); + params, PI_FULL_TRAINING); if (ret) { debug("index1 training failed\n"); return ret; @@ -1061,10 +1058,10 @@ static int switch_to_phy_index1(struct dram_info *dram, } static int sdram_init(struct dram_info *dram, - const struct rk3399_sdram_params *sdram_params) + const struct rk3399_sdram_params *params) { - unsigned char dramtype = sdram_params->base.dramtype; - unsigned int ddr_freq = sdram_params->base.ddr_freq; + unsigned char dramtype = params->base.dramtype; + unsigned int ddr_freq = params->base.ddr_freq; int channel; debug("Starting SDRAM initialization...\n"); @@ -1082,10 +1079,10 @@ static int sdram_init(struct dram_info *dram, phy_dll_bypass_set(publ, ddr_freq); - if (channel >= sdram_params->base.num_channels) + if (channel >= params->base.num_channels) continue; - if (pctl_cfg(chan, channel, sdram_params) != 0) { + if (pctl_cfg(chan, channel, params) != 0) { printf("pctl_cfg fail, reset\n"); return -EIO; } @@ -1094,17 +1091,16 @@ static int sdram_init(struct dram_info *dram, if (dramtype == LPDDR3) udelay(10); - if (data_training(chan, channel, - sdram_params, PI_FULL_TRAINING)) { + if (data_training(chan, channel, params, PI_FULL_TRAINING)) { printf("SDRAM initialization failed, reset\n"); return -EIO; } - set_ddrconfig(chan, sdram_params, channel, - sdram_params->ch[channel].ddrconfig); + set_ddrconfig(chan, params, channel, + params->ch[channel].ddrconfig); } - dram_all_config(dram, sdram_params); - switch_to_phy_index1(dram, sdram_params); + dram_all_config(dram, params); + switch_to_phy_index1(dram, params); debug("Finish SDRAM initialization...\n"); return 0; From patchwork Mon Jul 15 18:20:59 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 11044663 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 782E2112C for ; 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Mon, 15 Jul 2019 11:21:34 -0700 (PDT) Received: from localhost.localdomain ([49.206.201.107]) by smtp.gmail.com with ESMTPSA id l15sm18152405pgf.5.2019.07.15.11.21.31 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 15 Jul 2019 11:21:34 -0700 (PDT) From: Jagan Teki To: Simon Glass , Philipp Tomsich , Kever Yang , YouMin Chen , u-boot@lists.denx.de Subject: [PATCH v3 04/15] ram: rk3399: Handle pctl_cfg return type Date: Mon, 15 Jul 2019 23:50:59 +0530 Message-Id: <20190715182110.21336-5-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.18.0.321.gffc6fa0e3 In-Reply-To: <20190715182110.21336-1-jagan@amarulasolutions.com> References: <20190715182110.21336-1-jagan@amarulasolutions.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190715_112135_803535_78D97B62 X-CRM114-Status: GOOD ( 11.69 ) X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-rockchip@lists.infradead.org, gajjar04akash@gmail.com, linux-amarula@amarulasolutions.com, Jagan Teki , Manivannan Sadhasivam Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+patchwork-linux-rockchip=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Add proper return type handling of pctl_cfg with meaningful print statement. Signed-off-by: Jagan Teki Reviewed-by: Kever Yang --- drivers/ram/rockchip/sdram_rk3399.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c index c918c2e588..de5d8c1b5f 100644 --- a/drivers/ram/rockchip/sdram_rk3399.c +++ b/drivers/ram/rockchip/sdram_rk3399.c @@ -1063,6 +1063,7 @@ static int sdram_init(struct dram_info *dram, unsigned char dramtype = params->base.dramtype; unsigned int ddr_freq = params->base.ddr_freq; int channel; + int ret; debug("Starting SDRAM initialization...\n"); @@ -1082,9 +1083,10 @@ static int sdram_init(struct dram_info *dram, if (channel >= params->base.num_channels) continue; - if (pctl_cfg(chan, channel, params) != 0) { - printf("pctl_cfg fail, reset\n"); - return -EIO; + ret = pctl_cfg(chan, channel, params); + if (ret < 0) { + printf("%s: pctl config failed\n", __func__); + return ret; } /* LPDDR2/LPDDR3 need to wait DAI complete, max 10us */ From patchwork Mon Jul 15 18:21:00 2019 Content-Type: text/plain; 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No functionality change. Signed-off-by: Jagan Teki Signed-off-by: YouMin Chen Reviewed-by: Kever Yang --- drivers/ram/rockchip/sdram_rk3399.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c index de5d8c1b5f..85ff47f133 100644 --- a/drivers/ram/rockchip/sdram_rk3399.c +++ b/drivers/ram/rockchip/sdram_rk3399.c @@ -161,7 +161,7 @@ static void set_ds_odt(const struct chan_info *chan, u32 tsel_idle_en, tsel_wr_en, tsel_rd_en; u32 tsel_idle_select_p, tsel_wr_select_p, tsel_rd_select_p; u32 ca_tsel_wr_select_p, ca_tsel_wr_select_n; - u32 tsel_idle_select_n, tsel_wr_select_n, tsel_rd_select_n; + u32 tsel_idle_select_n, tsel_wr_select_dq_n, tsel_rd_select_n; u32 reg_value; if (params->base.dramtype == LPDDR4) { @@ -171,7 +171,7 @@ static void set_ds_odt(const struct chan_info *chan, tsel_idle_select_p = PHY_DRV_ODT_HI_Z; tsel_rd_select_n = PHY_DRV_ODT_240; - tsel_wr_select_n = PHY_DRV_ODT_40; + tsel_wr_select_dq_n = PHY_DRV_ODT_40; ca_tsel_wr_select_n = PHY_DRV_ODT_40; tsel_idle_select_n = PHY_DRV_ODT_240; } else if (params->base.dramtype == LPDDR3) { @@ -181,7 +181,7 @@ static void set_ds_odt(const struct chan_info *chan, tsel_idle_select_p = PHY_DRV_ODT_240; tsel_rd_select_n = PHY_DRV_ODT_HI_Z; - tsel_wr_select_n = PHY_DRV_ODT_34_3; + tsel_wr_select_dq_n = PHY_DRV_ODT_34_3; ca_tsel_wr_select_n = PHY_DRV_ODT_48; tsel_idle_select_n = PHY_DRV_ODT_HI_Z; } else { @@ -191,7 +191,7 @@ static void set_ds_odt(const struct chan_info *chan, tsel_idle_select_p = PHY_DRV_ODT_240; tsel_rd_select_n = PHY_DRV_ODT_240; - tsel_wr_select_n = PHY_DRV_ODT_34_3; + tsel_wr_select_dq_n = PHY_DRV_ODT_34_3; ca_tsel_wr_select_n = PHY_DRV_ODT_34_3; tsel_idle_select_n = PHY_DRV_ODT_240; } @@ -210,7 +210,7 @@ static void set_ds_odt(const struct chan_info *chan, * for write cycles for DQ/DM */ reg_value = tsel_rd_select_n | (tsel_rd_select_p << 0x4) | - (tsel_wr_select_n << 8) | (tsel_wr_select_p << 12) | + (tsel_wr_select_dq_n << 8) | (tsel_wr_select_p << 12) | (tsel_idle_select_n << 16) | (tsel_idle_select_p << 20); clrsetbits_le32(&denali_phy[6], 0xffffff, reg_value); clrsetbits_le32(&denali_phy[134], 0xffffff, reg_value); @@ -250,7 +250,7 @@ static void set_ds_odt(const struct chan_info *chan, /* phy_pad_fdbk_drive 23bit DENALI_PHY_924/925 */ clrsetbits_le32(&denali_phy[924], 0xff, - tsel_wr_select_n | (tsel_wr_select_p << 4)); + tsel_wr_select_dq_n | (tsel_wr_select_p << 4)); clrsetbits_le32(&denali_phy[925], 0xff, tsel_rd_select_n | (tsel_rd_select_p << 4)); From patchwork Mon Jul 15 18:21:01 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 11044667 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 7E1B7138D for ; Mon, 15 Jul 2019 18:21:48 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 7115E2849D for ; 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Mon, 15 Jul 2019 11:21:41 -0700 (PDT) Received: from localhost.localdomain ([49.206.201.107]) by smtp.gmail.com with ESMTPSA id l15sm18152405pgf.5.2019.07.15.11.21.38 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 15 Jul 2019 11:21:41 -0700 (PDT) From: Jagan Teki To: Simon Glass , Philipp Tomsich , Kever Yang , YouMin Chen , u-boot@lists.denx.de Subject: [PATCH v3 06/15] ram: rk3399: s/tsel_wr_select_p/tsel_wr_select_dq_p Date: Mon, 15 Jul 2019 23:51:01 +0530 Message-Id: <20190715182110.21336-7-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.18.0.321.gffc6fa0e3 In-Reply-To: <20190715182110.21336-1-jagan@amarulasolutions.com> References: <20190715182110.21336-1-jagan@amarulasolutions.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190715_112142_771655_4FEB9E93 X-CRM114-Status: GOOD ( 10.49 ) X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-rockchip@lists.infradead.org, gajjar04akash@gmail.com, linux-amarula@amarulasolutions.com, Jagan Teki , Manivannan Sadhasivam Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+patchwork-linux-rockchip=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Rename tsel_wr_select_p to tsel_wr_select_dq_p based on the bsp code. No functionality change. Signed-off-by: Jagan Teki Signed-off-by: YouMin Chen Reviewed-by: Kever Yang --- drivers/ram/rockchip/sdram_rk3399.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c index 85ff47f133..3ec32bdbc0 100644 --- a/drivers/ram/rockchip/sdram_rk3399.c +++ b/drivers/ram/rockchip/sdram_rk3399.c @@ -159,14 +159,14 @@ static void set_ds_odt(const struct chan_info *chan, u32 *denali_phy = chan->publ->denali_phy; u32 tsel_idle_en, tsel_wr_en, tsel_rd_en; - u32 tsel_idle_select_p, tsel_wr_select_p, tsel_rd_select_p; + u32 tsel_idle_select_p, tsel_wr_select_dq_p, tsel_rd_select_p; u32 ca_tsel_wr_select_p, ca_tsel_wr_select_n; u32 tsel_idle_select_n, tsel_wr_select_dq_n, tsel_rd_select_n; u32 reg_value; if (params->base.dramtype == LPDDR4) { tsel_rd_select_p = PHY_DRV_ODT_HI_Z; - tsel_wr_select_p = PHY_DRV_ODT_40; + tsel_wr_select_dq_p = PHY_DRV_ODT_40; ca_tsel_wr_select_p = PHY_DRV_ODT_40; tsel_idle_select_p = PHY_DRV_ODT_HI_Z; @@ -176,7 +176,7 @@ static void set_ds_odt(const struct chan_info *chan, tsel_idle_select_n = PHY_DRV_ODT_240; } else if (params->base.dramtype == LPDDR3) { tsel_rd_select_p = PHY_DRV_ODT_240; - tsel_wr_select_p = PHY_DRV_ODT_34_3; + tsel_wr_select_dq_p = PHY_DRV_ODT_34_3; ca_tsel_wr_select_p = PHY_DRV_ODT_48; tsel_idle_select_p = PHY_DRV_ODT_240; @@ -186,7 +186,7 @@ static void set_ds_odt(const struct chan_info *chan, tsel_idle_select_n = PHY_DRV_ODT_HI_Z; } else { tsel_rd_select_p = PHY_DRV_ODT_240; - tsel_wr_select_p = PHY_DRV_ODT_34_3; + tsel_wr_select_dq_p = PHY_DRV_ODT_34_3; ca_tsel_wr_select_p = PHY_DRV_ODT_34_3; tsel_idle_select_p = PHY_DRV_ODT_240; @@ -210,7 +210,7 @@ static void set_ds_odt(const struct chan_info *chan, * for write cycles for DQ/DM */ reg_value = tsel_rd_select_n | (tsel_rd_select_p << 0x4) | - (tsel_wr_select_dq_n << 8) | (tsel_wr_select_p << 12) | + (tsel_wr_select_dq_n << 8) | (tsel_wr_select_dq_p << 12) | (tsel_idle_select_n << 16) | (tsel_idle_select_p << 20); clrsetbits_le32(&denali_phy[6], 0xffffff, reg_value); clrsetbits_le32(&denali_phy[134], 0xffffff, reg_value); @@ -250,7 +250,7 @@ static void set_ds_odt(const struct chan_info *chan, /* phy_pad_fdbk_drive 23bit DENALI_PHY_924/925 */ clrsetbits_le32(&denali_phy[924], 0xff, - tsel_wr_select_dq_n | (tsel_wr_select_p << 4)); + tsel_wr_select_dq_n | (tsel_wr_select_dq_p << 4)); clrsetbits_le32(&denali_phy[925], 0xff, tsel_rd_select_n | (tsel_rd_select_p << 4)); From patchwork Mon Jul 15 18:21:02 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 11044669 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 08D4E112C for ; Mon, 15 Jul 2019 18:21:52 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id ED04D2849D for ; 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Mon, 15 Jul 2019 11:21:45 -0700 (PDT) Received: from localhost.localdomain ([49.206.201.107]) by smtp.gmail.com with ESMTPSA id l15sm18152405pgf.5.2019.07.15.11.21.41 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 15 Jul 2019 11:21:44 -0700 (PDT) From: Jagan Teki To: Simon Glass , Philipp Tomsich , Kever Yang , YouMin Chen , u-boot@lists.denx.de Subject: [PATCH v3 07/15] ram: rk3399: s/ca_tsel_wr_select_n/tsel_wr_select_ca_n Date: Mon, 15 Jul 2019 23:51:02 +0530 Message-Id: <20190715182110.21336-8-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.18.0.321.gffc6fa0e3 In-Reply-To: <20190715182110.21336-1-jagan@amarulasolutions.com> References: <20190715182110.21336-1-jagan@amarulasolutions.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190715_112145_920598_7E16B2B3 X-CRM114-Status: GOOD ( 11.35 ) X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-rockchip@lists.infradead.org, gajjar04akash@gmail.com, linux-amarula@amarulasolutions.com, Jagan Teki , Manivannan Sadhasivam Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+patchwork-linux-rockchip=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Rename ca_tsel_wr_select_n to tsel_wr_select_ca_n based on the bsp code. No functionality change. Signed-off-by: Jagan Teki Signed-off-by: YouMin Chen Reviewed-by: Kever Yang --- drivers/ram/rockchip/sdram_rk3399.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c index 3ec32bdbc0..bdb46a0128 100644 --- a/drivers/ram/rockchip/sdram_rk3399.c +++ b/drivers/ram/rockchip/sdram_rk3399.c @@ -160,7 +160,7 @@ static void set_ds_odt(const struct chan_info *chan, u32 tsel_idle_en, tsel_wr_en, tsel_rd_en; u32 tsel_idle_select_p, tsel_wr_select_dq_p, tsel_rd_select_p; - u32 ca_tsel_wr_select_p, ca_tsel_wr_select_n; + u32 ca_tsel_wr_select_p, tsel_wr_select_ca_n; u32 tsel_idle_select_n, tsel_wr_select_dq_n, tsel_rd_select_n; u32 reg_value; @@ -172,7 +172,7 @@ static void set_ds_odt(const struct chan_info *chan, tsel_rd_select_n = PHY_DRV_ODT_240; tsel_wr_select_dq_n = PHY_DRV_ODT_40; - ca_tsel_wr_select_n = PHY_DRV_ODT_40; + tsel_wr_select_ca_n = PHY_DRV_ODT_40; tsel_idle_select_n = PHY_DRV_ODT_240; } else if (params->base.dramtype == LPDDR3) { tsel_rd_select_p = PHY_DRV_ODT_240; @@ -182,7 +182,7 @@ static void set_ds_odt(const struct chan_info *chan, tsel_rd_select_n = PHY_DRV_ODT_HI_Z; tsel_wr_select_dq_n = PHY_DRV_ODT_34_3; - ca_tsel_wr_select_n = PHY_DRV_ODT_48; + tsel_wr_select_ca_n = PHY_DRV_ODT_48; tsel_idle_select_n = PHY_DRV_ODT_HI_Z; } else { tsel_rd_select_p = PHY_DRV_ODT_240; @@ -192,7 +192,7 @@ static void set_ds_odt(const struct chan_info *chan, tsel_rd_select_n = PHY_DRV_ODT_240; tsel_wr_select_dq_n = PHY_DRV_ODT_34_3; - ca_tsel_wr_select_n = PHY_DRV_ODT_34_3; + tsel_wr_select_ca_n = PHY_DRV_ODT_34_3; tsel_idle_select_n = PHY_DRV_ODT_240; } @@ -228,7 +228,7 @@ static void set_ds_odt(const struct chan_info *chan, clrsetbits_le32(&denali_phy[391], 0xffffff, reg_value); /* phy_adr_tsel_select_ 8bits DENALI_PHY_544/672/800 offset_0 */ - reg_value = ca_tsel_wr_select_n | (ca_tsel_wr_select_p << 0x4); + reg_value = tsel_wr_select_ca_n | (ca_tsel_wr_select_p << 0x4); clrsetbits_le32(&denali_phy[544], 0xff, reg_value); clrsetbits_le32(&denali_phy[672], 0xff, reg_value); clrsetbits_le32(&denali_phy[800], 0xff, reg_value); From patchwork Mon Jul 15 18:21:03 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 11044671 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 562A6112C for ; Mon, 15 Jul 2019 18:21:55 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 46E6C2849D for ; Mon, 15 Jul 2019 18:21:55 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 3841D284CE; Mon, 15 Jul 2019 18:21:55 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id CA1A92849D for ; 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No functionality change. Signed-off-by: Jagan Teki Signed-off-by: YouMin Chen Reviewed-by: Kever Yang --- drivers/ram/rockchip/sdram_rk3399.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c index bdb46a0128..8a983f9bb1 100644 --- a/drivers/ram/rockchip/sdram_rk3399.c +++ b/drivers/ram/rockchip/sdram_rk3399.c @@ -160,14 +160,14 @@ static void set_ds_odt(const struct chan_info *chan, u32 tsel_idle_en, tsel_wr_en, tsel_rd_en; u32 tsel_idle_select_p, tsel_wr_select_dq_p, tsel_rd_select_p; - u32 ca_tsel_wr_select_p, tsel_wr_select_ca_n; + u32 tsel_wr_select_ca_p, tsel_wr_select_ca_n; u32 tsel_idle_select_n, tsel_wr_select_dq_n, tsel_rd_select_n; u32 reg_value; if (params->base.dramtype == LPDDR4) { tsel_rd_select_p = PHY_DRV_ODT_HI_Z; tsel_wr_select_dq_p = PHY_DRV_ODT_40; - ca_tsel_wr_select_p = PHY_DRV_ODT_40; + tsel_wr_select_ca_p = PHY_DRV_ODT_40; tsel_idle_select_p = PHY_DRV_ODT_HI_Z; tsel_rd_select_n = PHY_DRV_ODT_240; @@ -177,7 +177,7 @@ static void set_ds_odt(const struct chan_info *chan, } else if (params->base.dramtype == LPDDR3) { tsel_rd_select_p = PHY_DRV_ODT_240; tsel_wr_select_dq_p = PHY_DRV_ODT_34_3; - ca_tsel_wr_select_p = PHY_DRV_ODT_48; + tsel_wr_select_ca_p = PHY_DRV_ODT_48; tsel_idle_select_p = PHY_DRV_ODT_240; tsel_rd_select_n = PHY_DRV_ODT_HI_Z; @@ -187,7 +187,7 @@ static void set_ds_odt(const struct chan_info *chan, } else { tsel_rd_select_p = PHY_DRV_ODT_240; tsel_wr_select_dq_p = PHY_DRV_ODT_34_3; - ca_tsel_wr_select_p = PHY_DRV_ODT_34_3; + tsel_wr_select_ca_p = PHY_DRV_ODT_34_3; tsel_idle_select_p = PHY_DRV_ODT_240; tsel_rd_select_n = PHY_DRV_ODT_240; @@ -228,7 +228,7 @@ static void set_ds_odt(const struct chan_info *chan, clrsetbits_le32(&denali_phy[391], 0xffffff, reg_value); /* phy_adr_tsel_select_ 8bits DENALI_PHY_544/672/800 offset_0 */ - reg_value = tsel_wr_select_ca_n | (ca_tsel_wr_select_p << 0x4); + reg_value = tsel_wr_select_ca_n | (tsel_wr_select_ca_p << 0x4); clrsetbits_le32(&denali_phy[544], 0xff, reg_value); clrsetbits_le32(&denali_phy[672], 0xff, reg_value); clrsetbits_le32(&denali_phy[800], 0xff, reg_value); From patchwork Mon Jul 15 18:21:04 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 11044673 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 7AD8B1510 for ; Mon, 15 Jul 2019 18:21:58 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 6BF532849D for ; Mon, 15 Jul 2019 18:21:58 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 5F04D284CE; Mon, 15 Jul 2019 18:21:58 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 041B92849D for ; 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X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-rockchip@lists.infradead.org, gajjar04akash@gmail.com, linux-amarula@amarulasolutions.com, Jagan Teki , Manivannan Sadhasivam Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+patchwork-linux-rockchip=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Order tsel* variable declarations and assignment in proper and meaningful way. No functionality change. Signed-off-by: Jagan Teki Signed-off-by: YouMin Chen Reviewed-by: Kever Yang --- drivers/ram/rockchip/sdram_rk3399.c | 37 +++++++++++++++++------------ 1 file changed, 22 insertions(+), 15 deletions(-) diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c index 8a983f9bb1..043b27737d 100644 --- a/drivers/ram/rockchip/sdram_rk3399.c +++ b/drivers/ram/rockchip/sdram_rk3399.c @@ -159,41 +159,48 @@ static void set_ds_odt(const struct chan_info *chan, u32 *denali_phy = chan->publ->denali_phy; u32 tsel_idle_en, tsel_wr_en, tsel_rd_en; - u32 tsel_idle_select_p, tsel_wr_select_dq_p, tsel_rd_select_p; - u32 tsel_wr_select_ca_p, tsel_wr_select_ca_n; - u32 tsel_idle_select_n, tsel_wr_select_dq_n, tsel_rd_select_n; + u32 tsel_idle_select_p, tsel_rd_select_p; + u32 tsel_idle_select_n, tsel_rd_select_n; + u32 tsel_wr_select_dq_p, tsel_wr_select_ca_p; + u32 tsel_wr_select_dq_n, tsel_wr_select_ca_n; u32 reg_value; if (params->base.dramtype == LPDDR4) { tsel_rd_select_p = PHY_DRV_ODT_HI_Z; - tsel_wr_select_dq_p = PHY_DRV_ODT_40; - tsel_wr_select_ca_p = PHY_DRV_ODT_40; + tsel_rd_select_n = PHY_DRV_ODT_240; + tsel_idle_select_p = PHY_DRV_ODT_HI_Z; + tsel_idle_select_n = PHY_DRV_ODT_240; - tsel_rd_select_n = PHY_DRV_ODT_240; + tsel_wr_select_dq_p = PHY_DRV_ODT_40; tsel_wr_select_dq_n = PHY_DRV_ODT_40; + + tsel_wr_select_ca_p = PHY_DRV_ODT_40; tsel_wr_select_ca_n = PHY_DRV_ODT_40; - tsel_idle_select_n = PHY_DRV_ODT_240; } else if (params->base.dramtype == LPDDR3) { tsel_rd_select_p = PHY_DRV_ODT_240; - tsel_wr_select_dq_p = PHY_DRV_ODT_34_3; - tsel_wr_select_ca_p = PHY_DRV_ODT_48; + tsel_rd_select_n = PHY_DRV_ODT_HI_Z; + tsel_idle_select_p = PHY_DRV_ODT_240; + tsel_idle_select_n = PHY_DRV_ODT_HI_Z; - tsel_rd_select_n = PHY_DRV_ODT_HI_Z; + tsel_wr_select_dq_p = PHY_DRV_ODT_34_3; tsel_wr_select_dq_n = PHY_DRV_ODT_34_3; + + tsel_wr_select_ca_p = PHY_DRV_ODT_48; tsel_wr_select_ca_n = PHY_DRV_ODT_48; - tsel_idle_select_n = PHY_DRV_ODT_HI_Z; } else { tsel_rd_select_p = PHY_DRV_ODT_240; - tsel_wr_select_dq_p = PHY_DRV_ODT_34_3; - tsel_wr_select_ca_p = PHY_DRV_ODT_34_3; + tsel_rd_select_n = PHY_DRV_ODT_240; + tsel_idle_select_p = PHY_DRV_ODT_240; + tsel_idle_select_n = PHY_DRV_ODT_240; - tsel_rd_select_n = PHY_DRV_ODT_240; + tsel_wr_select_dq_p = PHY_DRV_ODT_34_3; tsel_wr_select_dq_n = PHY_DRV_ODT_34_3; + + tsel_wr_select_ca_p = PHY_DRV_ODT_34_3; tsel_wr_select_ca_n = PHY_DRV_ODT_34_3; - tsel_idle_select_n = PHY_DRV_ODT_240; } if (params->base.odt == 1) From patchwork Mon Jul 15 18:21:05 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 11044675 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id ED0AD138D for ; Mon, 15 Jul 2019 18:22:03 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id DC2CF2849D for ; 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Mon, 15 Jul 2019 11:21:55 -0700 (PDT) Received: from localhost.localdomain ([49.206.201.107]) by smtp.gmail.com with ESMTPSA id l15sm18152405pgf.5.2019.07.15.11.21.52 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 15 Jul 2019 11:21:55 -0700 (PDT) From: Jagan Teki To: Simon Glass , Philipp Tomsich , Kever Yang , YouMin Chen , u-boot@lists.denx.de Subject: [PATCH v3 10/15] ram: rockchip: rk3399: Add cap_info structure Date: Mon, 15 Jul 2019 23:51:05 +0530 Message-Id: <20190715182110.21336-11-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.18.0.321.gffc6fa0e3 In-Reply-To: <20190715182110.21336-1-jagan@amarulasolutions.com> References: <20190715182110.21336-1-jagan@amarulasolutions.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190715_112156_097629_A4151888 X-CRM114-Status: GOOD ( 14.69 ) X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-rockchip@lists.infradead.org, gajjar04akash@gmail.com, linux-amarula@amarulasolutions.com, Jagan Teki , Manivannan Sadhasivam Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+patchwork-linux-rockchip=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Group common ddr attributes like - rank - col - bk - bw - dbw - row_3_4 - cs0_row - cs1_row - ddrconfig into a common cap_info structure for more code readability and extend if possible based on the new features. Signed-off-by: Jagan Teki Reviewed-by: Kever Yang --- .../include/asm/arch-rockchip/sdram_rk3399.h | 6 +- drivers/ram/rockchip/sdram_rk3399.c | 73 ++++++++++--------- 2 files changed, 45 insertions(+), 34 deletions(-) diff --git a/arch/arm/include/asm/arch-rockchip/sdram_rk3399.h b/arch/arm/include/asm/arch-rockchip/sdram_rk3399.h index c6a260bad8..683093d4ca 100644 --- a/arch/arm/include/asm/arch-rockchip/sdram_rk3399.h +++ b/arch/arm/include/asm/arch-rockchip/sdram_rk3399.h @@ -71,7 +71,7 @@ struct rk3399_ddr_cic_regs { /* DENALI_CTL_274 */ #define MEM_RST_VALID 1 -struct rk3399_sdram_channel { +struct sdram_cap_info { unsigned int rank; /* dram column number, 0 means this channel is invalid */ unsigned int col; @@ -89,6 +89,10 @@ struct rk3399_sdram_channel { unsigned int cs0_row; unsigned int cs1_row; unsigned int ddrconfig; +}; + +struct rk3399_sdram_channel { + struct sdram_cap_info cap_info; struct rk3399_msch_timings noc_timings; }; diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c index 043b27737d..492b0975dd 100644 --- a/drivers/ram/rockchip/sdram_rk3399.c +++ b/drivers/ram/rockchip/sdram_rk3399.c @@ -121,35 +121,36 @@ static void set_memory_map(const struct chan_info *chan, u32 channel, u32 row; /* Get row number from ddrconfig setting */ - if (sdram_ch->ddrconfig < 2 || sdram_ch->ddrconfig == 4) + if (sdram_ch->cap_info.ddrconfig < 2 || + sdram_ch->cap_info.ddrconfig == 4) row = 16; - else if (sdram_ch->ddrconfig == 3) + else if (sdram_ch->cap_info.ddrconfig == 3) row = 14; else row = 15; - cs_map = (sdram_ch->rank > 1) ? 3 : 1; - reduc = (sdram_ch->bw == 2) ? 0 : 1; + cs_map = (sdram_ch->cap_info.rank > 1) ? 3 : 1; + reduc = (sdram_ch->cap_info.bw == 2) ? 0 : 1; /* Set the dram configuration to ctrl */ - clrsetbits_le32(&denali_ctl[191], 0xF, (12 - sdram_ch->col)); + clrsetbits_le32(&denali_ctl[191], 0xF, (12 - sdram_ch->cap_info.col)); clrsetbits_le32(&denali_ctl[190], (0x3 << 16) | (0x7 << 24), - ((3 - sdram_ch->bk) << 16) | + ((3 - sdram_ch->cap_info.bk) << 16) | ((16 - row) << 24)); clrsetbits_le32(&denali_ctl[196], 0x3 | (1 << 16), cs_map | (reduc << 16)); /* PI_199 PI_COL_DIFF:RW:0:4 */ - clrsetbits_le32(&denali_pi[199], 0xF, (12 - sdram_ch->col)); + clrsetbits_le32(&denali_pi[199], 0xF, (12 - sdram_ch->cap_info.col)); /* PI_155 PI_ROW_DIFF:RW:24:3 PI_BANK_DIFF:RW:16:2 */ clrsetbits_le32(&denali_pi[155], (0x3 << 16) | (0x7 << 24), - ((3 - sdram_ch->bk) << 16) | + ((3 - sdram_ch->cap_info.bk) << 16) | ((16 - row) << 24)); /* PI_41 PI_CS_MAP:RW:24:4 */ clrsetbits_le32(&denali_pi[41], 0xf << 24, cs_map << 24); - if (sdram_ch->rank == 1 && params->base.dramtype == DDR3) + if (sdram_ch->cap_info.rank == 1 && params->base.dramtype == DDR3) writel(0x2EC7FFFF, &denali_pi[34]); } @@ -624,7 +625,7 @@ static int data_training_ca(const struct chan_info *chan, u32 channel, u32 *denali_phy = chan->publ->denali_phy; u32 i, tmp; u32 obs_0, obs_1, obs_2, obs_err = 0; - u32 rank = params->ch[channel].rank; + u32 rank = params->ch[channel].cap_info.rank; for (i = 0; i < rank; i++) { select_per_cs_training_index(chan, i); @@ -678,7 +679,7 @@ static int data_training_wl(const struct chan_info *chan, u32 channel, u32 *denali_phy = chan->publ->denali_phy; u32 i, tmp; u32 obs_0, obs_1, obs_2, obs_3, obs_err = 0; - u32 rank = params->ch[channel].rank; + u32 rank = params->ch[channel].cap_info.rank; for (i = 0; i < rank; i++) { select_per_cs_training_index(chan, i); @@ -737,7 +738,7 @@ static int data_training_rg(const struct chan_info *chan, u32 channel, u32 *denali_phy = chan->publ->denali_phy; u32 i, tmp; u32 obs_0, obs_1, obs_2, obs_3, obs_err = 0; - u32 rank = params->ch[channel].rank; + u32 rank = params->ch[channel].cap_info.rank; for (i = 0; i < rank; i++) { select_per_cs_training_index(chan, i); @@ -796,7 +797,7 @@ static int data_training_rl(const struct chan_info *chan, u32 channel, { u32 *denali_pi = chan->pi->denali_pi; u32 i, tmp; - u32 rank = params->ch[channel].rank; + u32 rank = params->ch[channel].cap_info.rank; for (i = 0; i < rank; i++) { select_per_cs_training_index(chan, i); @@ -841,7 +842,7 @@ static int data_training_wdql(const struct chan_info *chan, u32 channel, { u32 *denali_pi = chan->pi->denali_pi; u32 i, tmp; - u32 rank = params->ch[channel].rank; + u32 rank = params->ch[channel].cap_info.rank; for (i = 0; i < rank; i++) { select_per_cs_training_index(chan, i); @@ -940,14 +941,14 @@ static void set_ddrconfig(const struct chan_info *chan, unsigned int cs0_cap = 0; unsigned int cs1_cap = 0; - cs0_cap = (1 << (params->ch[channel].cs0_row - + params->ch[channel].col - + params->ch[channel].bk - + params->ch[channel].bw - 20)); - if (params->ch[channel].rank > 1) - cs1_cap = cs0_cap >> (params->ch[channel].cs0_row - - params->ch[channel].cs1_row); - if (params->ch[channel].row_3_4) { + cs0_cap = (1 << (params->ch[channel].cap_info.cs0_row + + params->ch[channel].cap_info.col + + params->ch[channel].cap_info.bk + + params->ch[channel].cap_info.bw - 20)); + if (params->ch[channel].cap_info.rank > 1) + cs1_cap = cs0_cap >> (params->ch[channel].cap_info.cs0_row + - params->ch[channel].cap_info.cs1_row); + if (params->ch[channel].cap_info.row_3_4) { cs0_cap = cs0_cap * 3 / 4; cs1_cap = cs1_cap * 3 / 4; } @@ -973,20 +974,26 @@ static void dram_all_config(struct dram_info *dram, struct rk3399_msch_regs *ddr_msch_regs; const struct rk3399_msch_timings *noc_timing; - if (params->ch[channel].col == 0) + if (params->ch[channel].cap_info.col == 0) continue; idx++; - sys_reg |= info->row_3_4 << SYS_REG_ROW_3_4_SHIFT(channel); + sys_reg |= info->cap_info.row_3_4 << + SYS_REG_ROW_3_4_SHIFT(channel); sys_reg |= 1 << SYS_REG_CHINFO_SHIFT(channel); - sys_reg |= (info->rank - 1) << SYS_REG_RANK_SHIFT(channel); - sys_reg |= (info->col - 9) << SYS_REG_COL_SHIFT(channel); - sys_reg |= info->bk == 3 ? 0 : 1 << SYS_REG_BK_SHIFT(channel); - sys_reg |= (info->cs0_row - 13) << + sys_reg |= (info->cap_info.rank - 1) << + SYS_REG_RANK_SHIFT(channel); + sys_reg |= (info->cap_info.col - 9) << + SYS_REG_COL_SHIFT(channel); + sys_reg |= info->cap_info.bk == 3 ? 0 : 1 << + SYS_REG_BK_SHIFT(channel); + sys_reg |= (info->cap_info.cs0_row - 13) << SYS_REG_CS0_ROW_SHIFT(channel); - sys_reg |= (info->cs1_row - 13) << + sys_reg |= (info->cap_info.cs1_row - 13) << SYS_REG_CS1_ROW_SHIFT(channel); - sys_reg |= (2 >> info->bw) << SYS_REG_BW_SHIFT(channel); - sys_reg |= (2 >> info->dbw) << SYS_REG_DBW_SHIFT(channel); + sys_reg |= (2 >> info->cap_info.bw) << + SYS_REG_BW_SHIFT(channel); + sys_reg |= (2 >> info->cap_info.dbw) << + SYS_REG_DBW_SHIFT(channel); ddr_msch_regs = dram->chan[channel].msch; noc_timing = ¶ms->ch[channel].noc_timings; @@ -1002,7 +1009,7 @@ static void dram_all_config(struct dram_info *dram, &ddr_msch_regs->ddrmode); /* rank 1 memory clock disable (dfi_dram_clk_disable = 1) */ - if (params->ch[channel].rank == 1) + if (params->ch[channel].cap_info.rank == 1) setbits_le32(&dram->chan[channel].pctl->denali_ctl[276], 1 << 17); } @@ -1106,7 +1113,7 @@ static int sdram_init(struct dram_info *dram, } set_ddrconfig(chan, params, channel, - params->ch[channel].ddrconfig); + params->ch[channel].cap_info.ddrconfig); } dram_all_config(dram, params); switch_to_phy_index1(dram, params); From patchwork Mon Jul 15 18:21:06 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 11044677 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 7E94A112C for ; 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Mon, 15 Jul 2019 11:21:58 -0700 (PDT) Received: from localhost.localdomain ([49.206.201.107]) by smtp.gmail.com with ESMTPSA id l15sm18152405pgf.5.2019.07.15.11.21.55 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 15 Jul 2019 11:21:58 -0700 (PDT) From: Jagan Teki To: Simon Glass , Philipp Tomsich , Kever Yang , YouMin Chen , u-boot@lists.denx.de Subject: [PATCH v3 11/15] ram: rk3399: s/rk3399_base_params/sdram_base_params Date: Mon, 15 Jul 2019 23:51:06 +0530 Message-Id: <20190715182110.21336-12-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.18.0.321.gffc6fa0e3 In-Reply-To: <20190715182110.21336-1-jagan@amarulasolutions.com> References: <20190715182110.21336-1-jagan@amarulasolutions.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190715_112200_351710_77753E27 X-CRM114-Status: GOOD ( 10.72 ) X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-rockchip@lists.infradead.org, gajjar04akash@gmail.com, linux-amarula@amarulasolutions.com, Jagan Teki , Manivannan Sadhasivam Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+patchwork-linux-rockchip=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Most of the ddr parameters are common in rk3399_base_params structure and which would reuse it in another controller like px30 in future. So, rename the structure from rk3399_base_params into sdram_base_params. Signed-off-by: Jagan Teki Signed-off-by: YouMin Chen Reviewed-by: Kever Yang --- arch/arm/include/asm/arch-rockchip/sdram_rk3399.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/include/asm/arch-rockchip/sdram_rk3399.h b/arch/arm/include/asm/arch-rockchip/sdram_rk3399.h index 683093d4ca..5614b94ecb 100644 --- a/arch/arm/include/asm/arch-rockchip/sdram_rk3399.h +++ b/arch/arm/include/asm/arch-rockchip/sdram_rk3399.h @@ -96,7 +96,7 @@ struct rk3399_sdram_channel { struct rk3399_msch_timings noc_timings; }; -struct rk3399_base_params { +struct sdram_base_params { unsigned int ddr_freq; unsigned int dramtype; unsigned int num_channels; @@ -106,7 +106,7 @@ struct rk3399_base_params { struct rk3399_sdram_params { struct rk3399_sdram_channel ch[2]; - struct rk3399_base_params base; + struct sdram_base_params base; struct rk3399_ddr_pctl_regs pctl_regs; struct rk3399_ddr_pi_regs pi_regs; struct rk3399_ddr_publ_regs phy_regs; From patchwork Mon Jul 15 18:21:07 2019 Content-Type: text/plain; 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Signed-off-by: Jagan Teki Reviewed-by: Kever Yang --- .../include/asm/arch-rockchip/sdram_common.h | 29 +++++++++++++++++++ .../include/asm/arch-rockchip/sdram_rk3399.h | 28 ------------------ 2 files changed, 29 insertions(+), 28 deletions(-) diff --git a/arch/arm/include/asm/arch-rockchip/sdram_common.h b/arch/arm/include/asm/arch-rockchip/sdram_common.h index 671c318d50..82ce3d3fc9 100644 --- a/arch/arm/include/asm/arch-rockchip/sdram_common.h +++ b/arch/arm/include/asm/arch-rockchip/sdram_common.h @@ -5,6 +5,35 @@ #ifndef _ASM_ARCH_SDRAM_COMMON_H #define _ASM_ARCH_SDRAM_COMMON_H + +struct sdram_cap_info { + unsigned int rank; + /* dram column number, 0 means this channel is invalid */ + unsigned int col; + /* dram bank number, 3:8bank, 2:4bank */ + unsigned int bk; + /* channel buswidth, 2:32bit, 1:16bit, 0:8bit */ + unsigned int bw; + /* die buswidth, 2:32bit, 1:16bit, 0:8bit */ + unsigned int dbw; + /* + * row_3_4 = 1: 6Gb or 12Gb die + * row_3_4 = 0: normal die, power of 2 + */ + unsigned int row_3_4; + unsigned int cs0_row; + unsigned int cs1_row; + unsigned int ddrconfig; +}; + +struct sdram_base_params { + unsigned int ddr_freq; + unsigned int dramtype; + unsigned int num_channels; + unsigned int stride; + unsigned int odt; +}; + /* * sys_reg bitfield struct * [31] row_3_4_ch1 diff --git a/arch/arm/include/asm/arch-rockchip/sdram_rk3399.h b/arch/arm/include/asm/arch-rockchip/sdram_rk3399.h index 5614b94ecb..65c92cf744 100644 --- a/arch/arm/include/asm/arch-rockchip/sdram_rk3399.h +++ b/arch/arm/include/asm/arch-rockchip/sdram_rk3399.h @@ -71,39 +71,11 @@ struct rk3399_ddr_cic_regs { /* DENALI_CTL_274 */ #define MEM_RST_VALID 1 -struct sdram_cap_info { - unsigned int rank; - /* dram column number, 0 means this channel is invalid */ - unsigned int col; - /* dram bank number, 3:8bank, 2:4bank */ - unsigned int bk; - /* channel buswidth, 2:32bit, 1:16bit, 0:8bit */ - unsigned int bw; - /* die buswidth, 2:32bit, 1:16bit, 0:8bit */ - unsigned int dbw; - /* - * row_3_4 = 1: 6Gb or 12Gb die - * row_3_4 = 0: normal die, power of 2 - */ - unsigned int row_3_4; - unsigned int cs0_row; - unsigned int cs1_row; - unsigned int ddrconfig; -}; - struct rk3399_sdram_channel { struct sdram_cap_info cap_info; struct rk3399_msch_timings noc_timings; }; -struct sdram_base_params { - unsigned int ddr_freq; - unsigned int dramtype; - unsigned int num_channels; - unsigned int stride; - unsigned int odt; -}; - struct rk3399_sdram_params { struct rk3399_sdram_channel ch[2]; struct sdram_base_params base; From patchwork Mon Jul 15 18:21:08 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 11044681 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id BDADC112C for ; Mon, 15 Jul 2019 18:22:12 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id AFB872849D for ; Mon, 15 Jul 2019 18:22:12 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id A103B284D2; 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Mon, 15 Jul 2019 11:22:05 -0700 (PDT) Received: from localhost.localdomain ([49.206.201.107]) by smtp.gmail.com with ESMTPSA id l15sm18152405pgf.5.2019.07.15.11.22.02 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 15 Jul 2019 11:22:05 -0700 (PDT) From: Jagan Teki To: Simon Glass , Philipp Tomsich , Kever Yang , YouMin Chen , u-boot@lists.denx.de Subject: [PATCH v3 13/15] arm: include: rockchip: Move dramtypes to common header Date: Mon, 15 Jul 2019 23:51:08 +0530 Message-Id: <20190715182110.21336-14-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.18.0.321.gffc6fa0e3 In-Reply-To: <20190715182110.21336-1-jagan@amarulasolutions.com> References: <20190715182110.21336-1-jagan@amarulasolutions.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190715_112206_553311_5388F99E X-CRM114-Status: GOOD ( 10.17 ) X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-rockchip@lists.infradead.org, gajjar04akash@gmail.com, linux-amarula@amarulasolutions.com, Jagan Teki , Manivannan Sadhasivam Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+patchwork-linux-rockchip=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP dramtype enum numbers as common across all dram controllers in rockchip, so move the eneum values in common header. Signed-off-by: Jagan Teki Reviewed-by: Kever Yang --- arch/arm/include/asm/arch-rockchip/sdram.h | 6 ------ arch/arm/include/asm/arch-rockchip/sdram_common.h | 8 ++++++++ arch/arm/include/asm/arch-rockchip/sdram_rk322x.h | 7 ------- arch/arm/include/asm/arch-rockchip/sdram_rk3399.h | 8 -------- 4 files changed, 8 insertions(+), 21 deletions(-) diff --git a/arch/arm/include/asm/arch-rockchip/sdram.h b/arch/arm/include/asm/arch-rockchip/sdram.h index bbe425deb9..9220763fa7 100644 --- a/arch/arm/include/asm/arch-rockchip/sdram.h +++ b/arch/arm/include/asm/arch-rockchip/sdram.h @@ -8,12 +8,6 @@ #ifndef _ASM_ARCH_RK3288_SDRAM_H__ #define _ASM_ARCH_RK3288_SDRAM_H__ -enum { - DDR3 = 3, - LPDDR3 = 6, - UNUSED = 0xFF, -}; - struct rk3288_sdram_channel { /* * bit width in address, eg: diff --git a/arch/arm/include/asm/arch-rockchip/sdram_common.h b/arch/arm/include/asm/arch-rockchip/sdram_common.h index 82ce3d3fc9..55abcdae77 100644 --- a/arch/arm/include/asm/arch-rockchip/sdram_common.h +++ b/arch/arm/include/asm/arch-rockchip/sdram_common.h @@ -6,6 +6,14 @@ #ifndef _ASM_ARCH_SDRAM_COMMON_H #define _ASM_ARCH_SDRAM_COMMON_H +enum { + DDR3 = 0x3, + LPDDR2 = 0x5, + LPDDR3 = 0x6, + LPDDR4 = 0x7, + UNUSED = 0xFF +}; + struct sdram_cap_info { unsigned int rank; /* dram column number, 0 means this channel is invalid */ diff --git a/arch/arm/include/asm/arch-rockchip/sdram_rk322x.h b/arch/arm/include/asm/arch-rockchip/sdram_rk322x.h index d0091a7aaf..336c5d7e8c 100644 --- a/arch/arm/include/asm/arch-rockchip/sdram_rk322x.h +++ b/arch/arm/include/asm/arch-rockchip/sdram_rk322x.h @@ -7,13 +7,6 @@ #include -enum { - DDR3 = 3, - LPDDR2 = 5, - LPDDR3 = 6, - UNUSED = 0xFF, -}; - struct rk322x_sdram_channel { /* * bit width in address, eg: diff --git a/arch/arm/include/asm/arch-rockchip/sdram_rk3399.h b/arch/arm/include/asm/arch-rockchip/sdram_rk3399.h index 65c92cf744..471702f935 100644 --- a/arch/arm/include/asm/arch-rockchip/sdram_rk3399.h +++ b/arch/arm/include/asm/arch-rockchip/sdram_rk3399.h @@ -6,14 +6,6 @@ #ifndef _ASM_ARCH_SDRAM_RK3399_H #define _ASM_ARCH_SDRAM_RK3399_H -enum { - DDR3 = 0x3, - LPDDR2 = 0x5, - LPDDR3 = 0x6, - LPDDR4 = 0x7, - UNUSED = 0xFF -}; - struct rk3399_ddr_pctl_regs { u32 denali_ctl[332]; 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X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-rockchip@lists.infradead.org, gajjar04akash@gmail.com, linux-amarula@amarulasolutions.com, Jagan Teki , Manivannan Sadhasivam Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+patchwork-linux-rockchip=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Add DDR4 enum number in common header. Signed-off-by: Jagan Teki Signed-off-by: YouMin Chen Reviewed-by: Kever Yang --- arch/arm/include/asm/arch-rockchip/sdram_common.h | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/include/asm/arch-rockchip/sdram_common.h b/arch/arm/include/asm/arch-rockchip/sdram_common.h index 55abcdae77..7ac25af327 100644 --- a/arch/arm/include/asm/arch-rockchip/sdram_common.h +++ b/arch/arm/include/asm/arch-rockchip/sdram_common.h @@ -7,6 +7,7 @@ #define _ASM_ARCH_SDRAM_COMMON_H enum { + DDR4 = 0, DDR3 = 0x3, LPDDR2 = 0x5, LPDDR3 = 0x6, From patchwork Mon Jul 15 18:21:10 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 11044685 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id BFCC5138D for ; Mon, 15 Jul 2019 18:22:18 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id B203A28496 for ; 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Mon, 15 Jul 2019 11:22:12 -0700 (PDT) Received: from localhost.localdomain ([49.206.201.107]) by smtp.gmail.com with ESMTPSA id l15sm18152405pgf.5.2019.07.15.11.22.09 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 15 Jul 2019 11:22:11 -0700 (PDT) From: Jagan Teki To: Simon Glass , Philipp Tomsich , Kever Yang , YouMin Chen , u-boot@lists.denx.de Subject: [PATCH v3 15/15] clk: rockchip: rk3399: Fix check patch warnings and checks Date: Mon, 15 Jul 2019 23:51:10 +0530 Message-Id: <20190715182110.21336-16-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.18.0.321.gffc6fa0e3 In-Reply-To: <20190715182110.21336-1-jagan@amarulasolutions.com> References: <20190715182110.21336-1-jagan@amarulasolutions.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190715_112213_052149_ECF59F2F X-CRM114-Status: GOOD ( 17.11 ) X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-rockchip@lists.infradead.org, gajjar04akash@gmail.com, linux-amarula@amarulasolutions.com, Jagan Teki , Manivannan Sadhasivam Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+patchwork-linux-rockchip=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP - CHECK: spaces preferred around that '*' - CHECK: spaces preferred around that '/' - CHECK: space preferred before that '|' - WARNING: macros should not use a trailing semicolon - CHECK: Unnecessary parentheses around 'fbdiv <= min_fbdiv' - CHECK: Unnecessary parentheses around 'parent->id == SCLK_MAC' - CHECK: Unnecessary parentheses around 'parent->dev == clk->dev' - WARNING: line over 80 characters - CHECK: Prefer kernel type 'u8' over 'uint8_t' - Add proper macro definitions arrangements Note: there are still line over 80 characters and other warnings but fixing those making code look unreadable, so I kept it as it is. Signed-off-by: Jagan Teki Reviewed-by: Kever Yang --- drivers/clk/rockchip/clk_rk3399.c | 68 ++++++++++++++----------------- 1 file changed, 31 insertions(+), 37 deletions(-) diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c index aa6a8ad1c9..5d1ad94e85 100644 --- a/drivers/clk/rockchip/clk_rk3399.c +++ b/drivers/clk/rockchip/clk_rk3399.c @@ -38,8 +38,8 @@ struct pll_div { }; #define RATE_TO_DIV(input_rate, output_rate) \ - ((input_rate) / (output_rate) - 1); -#define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) + ((input_rate) / (output_rate) - 1) +#define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) #define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\ .refdiv = _refdiv,\ @@ -53,15 +53,15 @@ static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2, 2); static const struct pll_div ppll_init_cfg = PLL_DIVISORS(PPLL_HZ, 2, 2, 1); #endif -static const struct pll_div apll_l_1600_cfg = PLL_DIVISORS(1600*MHz, 3, 1, 1); -static const struct pll_div apll_l_600_cfg = PLL_DIVISORS(600*MHz, 1, 2, 1); +static const struct pll_div apll_l_1600_cfg = PLL_DIVISORS(1600 * MHz, 3, 1, 1); +static const struct pll_div apll_l_600_cfg = PLL_DIVISORS(600 * MHz, 1, 2, 1); static const struct pll_div *apll_l_cfgs[] = { [APLL_L_1600_MHZ] = &apll_l_1600_cfg, [APLL_L_600_MHZ] = &apll_l_600_cfg, }; -static const struct pll_div apll_b_600_cfg = PLL_DIVISORS(600*MHz, 1, 2, 1); +static const struct pll_div apll_b_600_cfg = PLL_DIVISORS(600 * MHz, 1, 2, 1); static const struct pll_div *apll_b_cfgs[] = { [APLL_B_600_MHZ] = &apll_b_600_cfg, }; @@ -393,7 +393,7 @@ static int pll_para_config(u32 freq_hz, struct pll_div *div) fref_khz = ref_khz / refdiv; fbdiv = vco_khz / fref_khz; - if ((fbdiv >= max_fbdiv) || (fbdiv <= min_fbdiv)) + if (fbdiv >= max_fbdiv || fbdiv <= min_fbdiv) continue; diff_khz = vco_khz - fbdiv * fref_khz; if (fbdiv + 1 < max_fbdiv && diff_khz > fref_khz / 2) { @@ -409,7 +409,7 @@ static int pll_para_config(u32 freq_hz, struct pll_div *div) div->fbdiv = fbdiv; } - if (best_diff_khz > 4 * (MHz/KHz)) { + if (best_diff_khz > 4 * (MHz / KHz)) { printf("%s: Failed to match output frequency %u, " "difference is %u Hz,exceed 4MHZ\n", __func__, freq_hz, best_diff_khz * KHz); @@ -489,28 +489,21 @@ void rk3399_configure_cpu_b(struct rk3399_cru *cru, } #define I2C_CLK_REG_MASK(bus) \ - (I2C_DIV_CON_MASK << \ - CLK_I2C ##bus## _DIV_CON_SHIFT | \ - CLK_I2C_PLL_SEL_MASK << \ - CLK_I2C ##bus## _PLL_SEL_SHIFT) + (I2C_DIV_CON_MASK << CLK_I2C ##bus## _DIV_CON_SHIFT | \ + CLK_I2C_PLL_SEL_MASK << CLK_I2C ##bus## _PLL_SEL_SHIFT) #define I2C_CLK_REG_VALUE(bus, clk_div) \ - ((clk_div - 1) << \ - CLK_I2C ##bus## _DIV_CON_SHIFT | \ - CLK_I2C_PLL_SEL_GPLL << \ - CLK_I2C ##bus## _PLL_SEL_SHIFT) + ((clk_div - 1) << CLK_I2C ##bus## _DIV_CON_SHIFT | \ + CLK_I2C_PLL_SEL_GPLL << CLK_I2C ##bus## _PLL_SEL_SHIFT) #define I2C_CLK_DIV_VALUE(con, bus) \ - (con >> CLK_I2C ##bus## _DIV_CON_SHIFT) & \ - I2C_DIV_CON_MASK; + ((con >> CLK_I2C ##bus## _DIV_CON_SHIFT) & I2C_DIV_CON_MASK) #define I2C_PMUCLK_REG_MASK(bus) \ - (I2C_DIV_CON_MASK << \ - CLK_I2C ##bus## _DIV_CON_SHIFT) + (I2C_DIV_CON_MASK << CLK_I2C ##bus## _DIV_CON_SHIFT) #define I2C_PMUCLK_REG_VALUE(bus, clk_div) \ - ((clk_div - 1) << \ - CLK_I2C ##bus## _DIV_CON_SHIFT) + ((clk_div - 1) << CLK_I2C ##bus## _DIV_CON_SHIFT) static ulong rk3399_i2c_get_clk(struct rk3399_cru *cru, ulong clk_id) { @@ -597,9 +590,9 @@ static ulong rk3399_i2c_set_clk(struct rk3399_cru *cru, ulong clk_id, uint hz) */ struct spi_clkreg { - uint8_t reg; /* CLKSEL_CON[reg] register in CRU */ - uint8_t div_shift; - uint8_t sel_shift; + u8 reg; /* CLKSEL_CON[reg] register in CRU */ + u8 div_shift; + u8 sel_shift; }; /* @@ -678,7 +671,7 @@ static ulong rk3399_spi_set_clk(struct rk3399_cru *cru, ulong clk_id, uint hz) static ulong rk3399_vop_set_clk(struct rk3399_cru *cru, ulong clk_id, u32 hz) { struct pll_div vpll_config = {0}; - int aclk_vop = 198*MHz; + int aclk_vop = 198 * MHz; void *aclkreg_addr, *dclkreg_addr; u32 div; @@ -710,7 +703,7 @@ static ulong rk3399_vop_set_clk(struct rk3399_cru *cru, ulong clk_id, u32 hz) rkclk_set_pll(&cru->vpll_con[0], &vpll_config); rk_clrsetreg(dclkreg_addr, - DCLK_VOP_DCLK_SEL_MASK | DCLK_VOP_PLL_SEL_MASK| + DCLK_VOP_DCLK_SEL_MASK | DCLK_VOP_PLL_SEL_MASK | DCLK_VOP_DIV_CON_MASK, DCLK_VOP_DCLK_SEL_DIVOUT << DCLK_VOP_DCLK_SEL_SHIFT | DCLK_VOP_PLL_SEL_VPLL << DCLK_VOP_PLL_SEL_SHIFT | @@ -750,7 +743,7 @@ static ulong rk3399_mmc_set_clk(struct rk3399_cru *cru, ulong clk_id, ulong set_rate) { int src_clk_div; - int aclk_emmc = 198*MHz; + int aclk_emmc = 198 * MHz; switch (clk_id) { case HCLK_SDMMC: @@ -776,7 +769,7 @@ static ulong rk3399_mmc_set_clk(struct rk3399_cru *cru, break; case SCLK_EMMC: /* Select aclk_emmc source from GPLL */ - src_clk_div = DIV_ROUND_UP(GPLL_HZ , aclk_emmc); + src_clk_div = DIV_ROUND_UP(GPLL_HZ, aclk_emmc); assert(src_clk_div - 1 < 32); rk_clrsetreg(&cru->clksel_con[21], @@ -834,23 +827,23 @@ static ulong rk3399_ddr_set_clk(struct rk3399_cru *cru, /* clk_ddrc == DPLL = 24MHz / refdiv * fbdiv / postdiv1 / postdiv2 */ switch (set_rate) { - case 200*MHz: + case 200 * MHz: dpll_cfg = (struct pll_div) {.refdiv = 1, .fbdiv = 50, .postdiv1 = 6, .postdiv2 = 1}; break; - case 300*MHz: + case 300 * MHz: dpll_cfg = (struct pll_div) {.refdiv = 2, .fbdiv = 100, .postdiv1 = 4, .postdiv2 = 1}; break; - case 666*MHz: + case 666 * MHz: dpll_cfg = (struct pll_div) {.refdiv = 2, .fbdiv = 111, .postdiv1 = 2, .postdiv2 = 1}; break; - case 800*MHz: + case 800 * MHz: dpll_cfg = (struct pll_div) {.refdiv = 1, .fbdiv = 100, .postdiv1 = 3, .postdiv2 = 1}; break; - case 933*MHz: + case 933 * MHz: dpll_cfg = (struct pll_div) {.refdiv = 1, .fbdiv = 116, .postdiv1 = 3, .postdiv2 = 1}; break; @@ -916,7 +909,6 @@ static ulong rk3399_clk_get_rate(struct clk *clk) case SCLK_UART2: case SCLK_UART3: return 24000000; - break; case PCLK_HDMI_CTRL: break; case DCLK_VOP0: @@ -1014,7 +1006,8 @@ static ulong rk3399_clk_set_rate(struct clk *clk, ulong rate) return ret; } -static int __maybe_unused rk3399_gmac_set_parent(struct clk *clk, struct clk *parent) +static int __maybe_unused rk3399_gmac_set_parent(struct clk *clk, + struct clk *parent) { struct rk3399_clk_priv *priv = dev_get_priv(clk->dev); const char *clock_output_name; @@ -1024,7 +1017,7 @@ static int __maybe_unused rk3399_gmac_set_parent(struct clk *clk, struct clk *pa * If the requested parent is in the same clock-controller and * the id is SCLK_MAC ("clk_gmac"), switch to the internal clock. */ - if ((parent->dev == clk->dev) && (parent->id == SCLK_MAC)) { + if (parent->dev == clk->dev && parent->id == SCLK_MAC) { debug("%s: switching RGMII to SCLK_MAC\n", __func__); rk_clrreg(&priv->cru->clksel_con[19], BIT(4)); return 0; @@ -1049,7 +1042,8 @@ static int __maybe_unused rk3399_gmac_set_parent(struct clk *clk, struct clk *pa return -EINVAL; } -static int __maybe_unused rk3399_clk_set_parent(struct clk *clk, struct clk *parent) +static int __maybe_unused rk3399_clk_set_parent(struct clk *clk, + struct clk *parent) { switch (clk->id) { case SCLK_RMII_SRC: