From patchwork Mon Jul 15 21:39:59 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paul Cercueil X-Patchwork-Id: 11045051 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 38E4F746 for ; Mon, 15 Jul 2019 21:40:17 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 1DE5128516 for ; Mon, 15 Jul 2019 21:40:17 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 11D58284D1; Mon, 15 Jul 2019 21:40:17 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.7 required=2.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id E549E28517 for ; Mon, 15 Jul 2019 21:40:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730249AbfGOVkP (ORCPT ); Mon, 15 Jul 2019 17:40:15 -0400 Received: from outils.crapouillou.net ([89.234.176.41]:34402 "EHLO crapouillou.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730156AbfGOVkP (ORCPT ); Mon, 15 Jul 2019 17:40:15 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=crapouillou.net; s=mail; t=1563226813; h=from:from:sender:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-transfer-encoding:content-transfer-encoding: in-reply-to:references; bh=FswRZqgN/pvd1iwzddhHBmlf5FX0AHTot/eT8dI7keU=; b=jn+8EzXVNZMIYKWPAYf2H5irN0X3fraihSEH+bzKqqk6FsMRFZRe9M0X/Mm3viPitnyWrj hlBhhEFYQSe9r4wyynCknqW/TxRPFMbiInu53uA4FdfklHrU07XDnYNqLvBiklZO7J5sNC so0TqQ5wNG0Ze/iCIZ7lsZLTIzKgtnA= From: Paul Cercueil To: Ralf Baechle , Paul Burton , James Hogan Cc: od@zcrc.me, linux-mips@vger.kernel.org, linux-kernel@vger.kernel.org, Daniel Silsby , Paul Cercueil Subject: [PATCH 1/5] MIPS: Disallow CPU_SUPPORTS_HUGEPAGES for XPA,EVA Date: Mon, 15 Jul 2019 17:39:59 -0400 Message-Id: <20190715214003.9714-1-paul@crapouillou.net> MIME-Version: 1.0 Sender: linux-mips-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Daniel Silsby In preparation for 32-bit MIPS huge page support. EVA,XPA are extended-addressing modes for 32-bit MIPS systems. Because huge pages aren't currently supported in 32-bit MIPS, this doesn't take any features away from EVA,XPA-enabled systems. However, the soon-to- come 32-bit MIPS huge page support doesn't yet support them. This also disables CPU_SUPPORTS_HUGEPAGES for the small number of 32-bit MIPS CPUs from Alchemy/Netlogic that support a custom 36-bit extended addressing. It's unknown if they even support huge pages in hardware. Signed-off-by: Daniel Silsby Signed-off-by: Paul Cercueil --- arch/mips/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index d50fafd7bf3a..ff5f1314241e 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -2110,6 +2110,7 @@ config CPU_SUPPORTS_ADDRWINCFG bool config CPU_SUPPORTS_HUGEPAGES bool + depends on !(32BIT && (ARCH_PHYS_ADDR_T_64BIT || EVA)) config CPU_SUPPORTS_UNCACHED_ACCELERATED bool config MIPS_PGD_C0_CONTEXT From patchwork Mon Jul 15 21:40:00 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paul Cercueil X-Patchwork-Id: 11045053 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id BF9BB13B1 for ; Mon, 15 Jul 2019 21:40:23 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id AE765284F1 for ; Mon, 15 Jul 2019 21:40:23 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id A2C4428508; Mon, 15 Jul 2019 21:40:23 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.7 required=2.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 0670C28511 for ; Mon, 15 Jul 2019 21:40:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1732166AbfGOVkW (ORCPT ); Mon, 15 Jul 2019 17:40:22 -0400 Received: from outils.crapouillou.net ([89.234.176.41]:34440 "EHLO crapouillou.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730156AbfGOVkW (ORCPT ); Mon, 15 Jul 2019 17:40:22 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=crapouillou.net; s=mail; t=1563226816; h=from:from:sender:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=83UUyY3nqB5GEHoj6uddzuQXEXVwQHKMsV0TEqEzuE0=; b=CARzTCAL1r/TNLqqupFA0+vg0DHAG/ze2awrYvqFjHoLhyVbviCZHS/mzjrevH9iHBOnwI HaU8M2Q+PwnFrjZOzwn2U4kOs9KCGk1r+1S5hnia1EneyAbQ0krPm0ADZbbULFTNhUo0RW R5qE10amU1mt4wH7vntVjZQ3+70sE00= From: Paul Cercueil To: Ralf Baechle , Paul Burton , James Hogan Cc: od@zcrc.me, linux-mips@vger.kernel.org, linux-kernel@vger.kernel.org, Daniel Silsby , Paul Cercueil Subject: [PATCH 2/5] MIPS: Add partial 32-bit huge page support Date: Mon, 15 Jul 2019 17:40:00 -0400 Message-Id: <20190715214003.9714-2-paul@crapouillou.net> In-Reply-To: <20190715214003.9714-1-paul@crapouillou.net> References: <20190715214003.9714-1-paul@crapouillou.net> MIME-Version: 1.0 Sender: linux-mips-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Daniel Silsby This adds initial support for huge pages to 32-bit MIPS systems. Systems with extended addressing enabled (EVA,XPA,Alchemy/Netlogic) are not yet supported. With huge pages enabled, this implementation will increase page table memory overhead to match that of a 64-bit MIPS system. However, the cache-friendliness of page table walks is not affected significantly. Signed-off-by: Daniel Silsby Signed-off-by: Paul Cercueil --- arch/mips/include/asm/pgtable-32.h | 56 +++++++++++++++++++++++++--- arch/mips/include/asm/pgtable-bits.h | 4 +- arch/mips/mm/pgtable-32.c | 20 ++++++++++ 3 files changed, 73 insertions(+), 7 deletions(-) diff --git a/arch/mips/include/asm/pgtable-32.h b/arch/mips/include/asm/pgtable-32.h index 74afe8c76bdd..b0a78c9b6434 100644 --- a/arch/mips/include/asm/pgtable-32.h +++ b/arch/mips/include/asm/pgtable-32.h @@ -23,6 +23,24 @@ #include #endif +/* + * Regarding 32-bit MIPS huge page support (and the tradeoff it entails): + * + * We use the same huge page sizes as 64-bit MIPS. Assuming a 4KB page size, + * our 2-level table layout would normally have a PGD entry cover a contiguous + * 4MB virtual address region (pointing to a 4KB PTE page of 1,024 32-bit pte_t + * pointers, each pointing to a 4KB physical page). The problem is that 4MB, + * spanning both halves of a TLB EntryLo0,1 pair, requires 2MB hardware page + * support, not one of the standard supported sizes (1MB,4MB,16MB,...). + * To correct for this, when huge pages are enabled, we halve the number of + * pointers a PTE page holds, making its last half go to waste. Correspondingly, + * we double the number of PGD pages. Overall, page table memory overhead + * increases to match 64-bit MIPS, but PTE lookups remain CPU cache-friendly. + * + * NOTE: We don't yet support huge pages if extended-addressing is enabled + * (i.e. EVA, XPA, 36-bit Alchemy/Netlogic). + */ + extern int temp_tlb_entry; /* @@ -44,7 +62,12 @@ extern int add_temporary_entry(unsigned long entrylo0, unsigned long entrylo1, */ /* PGDIR_SHIFT determines what a third-level page table entry can map */ -#define PGDIR_SHIFT (2 * PAGE_SHIFT + PTE_ORDER - PTE_T_LOG2) +#if defined(CONFIG_MIPS_HUGE_TLB_SUPPORT) && !defined(CONFIG_PHYS_ADDR_T_64BIT) +# define PGDIR_SHIFT (2 * PAGE_SHIFT + PTE_ORDER - PTE_T_LOG2 - 1) +#else +# define PGDIR_SHIFT (2 * PAGE_SHIFT + PTE_ORDER - PTE_T_LOG2) +#endif + #define PGDIR_SIZE (1UL << PGDIR_SHIFT) #define PGDIR_MASK (~(PGDIR_SIZE-1)) @@ -52,14 +75,23 @@ extern int add_temporary_entry(unsigned long entrylo0, unsigned long entrylo1, * Entries per page directory level: we use two-level, so * we don't really have any PUD/PMD directory physically. */ -#define __PGD_ORDER (32 - 3 * PAGE_SHIFT + PGD_T_LOG2 + PTE_T_LOG2) +#if defined(CONFIG_MIPS_HUGE_TLB_SUPPORT) && !defined(CONFIG_PHYS_ADDR_T_64BIT) +# define __PGD_ORDER (32 - 3 * PAGE_SHIFT + PGD_T_LOG2 + PTE_T_LOG2 + 1) +#else +# define __PGD_ORDER (32 - 3 * PAGE_SHIFT + PGD_T_LOG2 + PTE_T_LOG2) +#endif + #define PGD_ORDER (__PGD_ORDER >= 0 ? __PGD_ORDER : 0) #define PUD_ORDER aieeee_attempt_to_allocate_pud #define PMD_ORDER 1 #define PTE_ORDER 0 #define PTRS_PER_PGD (USER_PTRS_PER_PGD * 2) -#define PTRS_PER_PTE ((PAGE_SIZE << PTE_ORDER) / sizeof(pte_t)) +#if defined(CONFIG_MIPS_HUGE_TLB_SUPPORT) && !defined(CONFIG_PHYS_ADDR_T_64BIT) +# define PTRS_PER_PTE ((PAGE_SIZE << PTE_ORDER) / sizeof(pte_t) / 2) +#else +# define PTRS_PER_PTE ((PAGE_SIZE << PTE_ORDER) / sizeof(pte_t)) +#endif #define USER_PTRS_PER_PGD (0x80000000UL/PGDIR_SIZE) #define FIRST_USER_ADDRESS 0UL @@ -87,7 +119,7 @@ extern int add_temporary_entry(unsigned long entrylo0, unsigned long entrylo1, extern void load_pgd(unsigned long pg_dir); -extern pte_t invalid_pte_table[PAGE_SIZE/sizeof(pte_t)]; +extern pte_t invalid_pte_table[PTRS_PER_PTE]; /* * Empty pgd/pmd entries point to the invalid_pte_table. @@ -97,7 +129,19 @@ static inline int pmd_none(pmd_t pmd) return pmd_val(pmd) == (unsigned long) invalid_pte_table; } -#define pmd_bad(pmd) (pmd_val(pmd) & ~PAGE_MASK) +static inline int pmd_bad(pmd_t pmd) +{ +#ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT + /* pmd_huge(pmd) but inline */ + if (unlikely(pmd_val(pmd) & _PAGE_HUGE)) + return 0; +#endif + + if (unlikely(pmd_val(pmd) & ~PAGE_MASK)) + return 1; + + return 0; +} static inline int pmd_present(pmd_t pmd) { @@ -146,6 +190,7 @@ static inline pte_t pfn_pte(unsigned long pfn, pgprot_t prot) #else #define pte_pfn(x) ((unsigned long)((x).pte >> _PFN_SHIFT)) #define pfn_pte(pfn, prot) __pte(((unsigned long long)(pfn) << _PFN_SHIFT) | pgprot_val(prot)) +#define pfn_pmd(pfn, prot) __pmd(((unsigned long long)(pfn) << _PFN_SHIFT) | pgprot_val(prot)) #endif #endif /* defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_CPU_MIPS32) */ @@ -159,6 +204,7 @@ static inline pte_t pfn_pte(unsigned long pfn, pgprot_t prot) #define pgd_offset_k(address) pgd_offset(&init_mm, address) #define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD-1)) +#define pmd_index(address) (((address) >> PMD_SHIFT) & (PTRS_PER_PMD-1)) /* to find an entry in a page-table-directory */ #define pgd_offset(mm, addr) ((mm)->pgd + pgd_index(addr)) diff --git a/arch/mips/include/asm/pgtable-bits.h b/arch/mips/include/asm/pgtable-bits.h index f88a48cd68b2..f3b1efd23f21 100644 --- a/arch/mips/include/asm/pgtable-bits.h +++ b/arch/mips/include/asm/pgtable-bits.h @@ -110,7 +110,7 @@ enum pgtable_bits { _PAGE_WRITE_SHIFT, _PAGE_ACCESSED_SHIFT, _PAGE_MODIFIED_SHIFT, -#if defined(CONFIG_64BIT) && defined(CONFIG_MIPS_HUGE_TLB_SUPPORT) +#if defined(CONFIG_MIPS_HUGE_TLB_SUPPORT) _PAGE_HUGE_SHIFT, #endif @@ -132,7 +132,7 @@ enum pgtable_bits { #define _PAGE_WRITE (1 << _PAGE_WRITE_SHIFT) #define _PAGE_ACCESSED (1 << _PAGE_ACCESSED_SHIFT) #define _PAGE_MODIFIED (1 << _PAGE_MODIFIED_SHIFT) -#if defined(CONFIG_64BIT) && defined(CONFIG_MIPS_HUGE_TLB_SUPPORT) +#if defined(CONFIG_MIPS_HUGE_TLB_SUPPORT) # define _PAGE_HUGE (1 << _PAGE_HUGE_SHIFT) #endif diff --git a/arch/mips/mm/pgtable-32.c b/arch/mips/mm/pgtable-32.c index e2a33adc0f29..6416a531a4c3 100644 --- a/arch/mips/mm/pgtable-32.c +++ b/arch/mips/mm/pgtable-32.c @@ -12,6 +12,7 @@ #include #include #include +#include void pgd_init(unsigned long page) { @@ -30,6 +31,25 @@ void pgd_init(unsigned long page) } } +#if defined(CONFIG_TRANSPARENT_HUGEPAGE) +pmd_t mk_pmd(struct page *page, pgprot_t prot) +{ + pmd_t pmd; + + pmd_val(pmd) = (page_to_pfn(page) << _PFN_SHIFT) | pgprot_val(prot); + + return pmd; +} + + +void set_pmd_at(struct mm_struct *mm, unsigned long addr, + pmd_t *pmdp, pmd_t pmd) +{ + *pmdp = pmd; + flush_tlb_all(); +} +#endif /* defined(CONFIG_TRANSPARENT_HUGEPAGE) */ + void __init pagetable_init(void) { unsigned long vaddr; From patchwork Mon Jul 15 21:40:01 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paul Cercueil X-Patchwork-Id: 11045055 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 5C101746 for ; Mon, 15 Jul 2019 21:40:30 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 4B2C22847E for ; Mon, 15 Jul 2019 21:40:30 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 3C0BB28511; Mon, 15 Jul 2019 21:40:30 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.7 required=2.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id E612A284F1 for ; Mon, 15 Jul 2019 21:40:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1732344AbfGOVk3 (ORCPT ); Mon, 15 Jul 2019 17:40:29 -0400 Received: from outils.crapouillou.net ([89.234.176.41]:34536 "EHLO crapouillou.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730156AbfGOVk3 (ORCPT ); Mon, 15 Jul 2019 17:40:29 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=crapouillou.net; s=mail; t=1563226819; h=from:from:sender:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=J3Y/wy/LIbFFdcKa02s8pUYwReL91haevitxXohYmJA=; b=Yk53lv9HpDhZZKCFpscWK6v05vmArVKnUVaI7SqU6sdX/EkwKaQBao+LSzpuYc3ASEgRnI s9dwgcbs4to7XP7Nmm3tIICeid0REofrIomr+VEDsOmT6g8hHNYNuEXKWCJJ+HtKGeerhx L+0IJuliYJnKZz/Lj4TowRto6oT8p+k= From: Paul Cercueil To: Ralf Baechle , Paul Burton , James Hogan Cc: od@zcrc.me, linux-mips@vger.kernel.org, linux-kernel@vger.kernel.org, Daniel Silsby , Paul Cercueil Subject: [PATCH 3/5] MIPS: Decouple CPU_SUPPORTS_HUGEPAGES from 64BIT Date: Mon, 15 Jul 2019 17:40:01 -0400 Message-Id: <20190715214003.9714-3-paul@crapouillou.net> In-Reply-To: <20190715214003.9714-1-paul@crapouillou.net> References: <20190715214003.9714-1-paul@crapouillou.net> MIME-Version: 1.0 Sender: linux-mips-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Daniel Silsby We now have partial 32-bit MIPS huge page support, so there's no need to restrict these config options only to 64-bit systems. Signed-off-by: Daniel Silsby Signed-off-by: Paul Cercueil --- arch/mips/Kconfig | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index ff5f1314241e..47d50e37faa4 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -43,7 +43,7 @@ config MIPS select HAVE_ARCH_MMAP_RND_COMPAT_BITS if MMU && COMPAT select HAVE_ARCH_SECCOMP_FILTER select HAVE_ARCH_TRACEHOOK - select HAVE_ARCH_TRANSPARENT_HUGEPAGE if CPU_SUPPORTS_HUGEPAGES && 64BIT + select HAVE_ARCH_TRANSPARENT_HUGEPAGE if CPU_SUPPORTS_HUGEPAGES select HAVE_EBPF_JIT if (!CPU_MICROMIPS) select HAVE_CONTEXT_TRACKING select HAVE_COPY_THREAD_TLS @@ -1223,7 +1223,7 @@ config SYS_SUPPORTS_LITTLE_ENDIAN config SYS_SUPPORTS_HUGETLBFS bool - depends on CPU_SUPPORTS_HUGEPAGES && 64BIT + depends on CPU_SUPPORTS_HUGEPAGES default y config MIPS_HUGE_TLB_SUPPORT From patchwork Mon Jul 15 21:40:02 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paul Cercueil X-Patchwork-Id: 11045057 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 34211746 for ; Mon, 15 Jul 2019 21:40:37 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 2206026E4A for ; Mon, 15 Jul 2019 21:40:37 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 167A62842E; Mon, 15 Jul 2019 21:40:37 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.7 required=2.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id C456E26E4A for ; Mon, 15 Jul 2019 21:40:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1732567AbfGOVkg (ORCPT ); Mon, 15 Jul 2019 17:40:36 -0400 Received: from outils.crapouillou.net ([89.234.176.41]:34574 "EHLO crapouillou.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1732540AbfGOVkg (ORCPT ); Mon, 15 Jul 2019 17:40:36 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=crapouillou.net; s=mail; t=1563226822; h=from:from:sender:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=8E40KY2beyOGUeXo3Pc5VtaYHQ9RQJpjOfirkoUufqU=; b=WkSxcw7H2EeVxgzYpRhP4paD9RCjkFv30PFANldAF2dKcu51enAWCRhpAcopF/ls6d3oZd D3jjiczhC8Oq+VyV5OA6C4/XQh/Jqkg+3C2j+0GNwkWxecjrUvDkpuhyQzZszD3j6iS/PF 101W2aec3Cl9J+L1UH+Ijwm2c+3j6Uk= From: Paul Cercueil To: Ralf Baechle , Paul Burton , James Hogan Cc: od@zcrc.me, linux-mips@vger.kernel.org, linux-kernel@vger.kernel.org, Daniel Silsby , Paul Cercueil Subject: [PATCH 4/5] MIPS: ingenic: Add support for huge pages Date: Mon, 15 Jul 2019 17:40:02 -0400 Message-Id: <20190715214003.9714-4-paul@crapouillou.net> In-Reply-To: <20190715214003.9714-1-paul@crapouillou.net> References: <20190715214003.9714-1-paul@crapouillou.net> MIME-Version: 1.0 Sender: linux-mips-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Daniel Silsby The Ingenic jz47xx SoC series of 32-bit MIPS CPUs support huge pages. Signed-off-by: Daniel Silsby Signed-off-by: Paul Cercueil --- arch/mips/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 47d50e37faa4..2a5d80c72c4e 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -384,6 +384,7 @@ config MACH_INGENIC select SYS_SUPPORTS_32BIT_KERNEL select SYS_SUPPORTS_LITTLE_ENDIAN select SYS_SUPPORTS_ZBOOT_UART16550 + select CPU_SUPPORTS_HUGEPAGES select DMA_NONCOHERENT select IRQ_MIPS_CPU select PINCTRL From patchwork Mon Jul 15 21:40:03 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paul Cercueil X-Patchwork-Id: 11045059 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 8274F746 for ; Mon, 15 Jul 2019 21:40:44 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 716AB26E3C for ; Mon, 15 Jul 2019 21:40:44 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 6621B2844B; Mon, 15 Jul 2019 21:40:44 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.7 required=2.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 176C126E3C for ; Mon, 15 Jul 2019 21:40:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1732683AbfGOVkn (ORCPT ); Mon, 15 Jul 2019 17:40:43 -0400 Received: from outils.crapouillou.net ([89.234.176.41]:34620 "EHLO crapouillou.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1732540AbfGOVkn (ORCPT ); Mon, 15 Jul 2019 17:40:43 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=crapouillou.net; s=mail; t=1563226825; h=from:from:sender:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=G7pXdTM0nJCK/U/d3udYCjSZFiGilJhkAIvapaAu+bs=; b=tYArbzcU+BsZbqywzOdgYshQPlxVtkL2u25SFcTo/S5Z/Un0vijf02p1jIKL/kBxXdaNsx Nr/lZXl5AsxOAPT3tdPFHuLtxbgDZ2LLXYtn4wCr6/dF7gTO2tX+2fXsc6sYiEsF4ToI79 0cCS9s1dBiKdlBJv9YrLPLB3xXKkGpk= From: Paul Cercueil To: Ralf Baechle , Paul Burton , James Hogan Cc: od@zcrc.me, linux-mips@vger.kernel.org, linux-kernel@vger.kernel.org, Daniel Silsby , Paul Cercueil Subject: [PATCH 5/5] MIPS: Undefine PMD_ORDER for 32-bit builds Date: Mon, 15 Jul 2019 17:40:03 -0400 Message-Id: <20190715214003.9714-5-paul@crapouillou.net> In-Reply-To: <20190715214003.9714-1-paul@crapouillou.net> References: <20190715214003.9714-1-paul@crapouillou.net> MIME-Version: 1.0 Sender: linux-mips-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Daniel Silsby During an update long ago to conform to 4-level page code, PMD_ORDER was changed from 0 to 1, despite the fact that a PMD table is not used at all in a 32-bit MIPS build. PMD_ORDER does not seem to be used in these builds. Now, it matches PUD_ORDER, a nonsense #define to give a build failure with informative error. The older commit that had redefined PMD_ORDER was commit c6e8b587718c ("Update MIPS to use the 4-level pagetable code thereby getting rid of the compacrapability headers.") Signed-off-by: Daniel Silsby Signed-off-by: Paul Cercueil --- arch/mips/include/asm/pgtable-32.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/mips/include/asm/pgtable-32.h b/arch/mips/include/asm/pgtable-32.h index b0a78c9b6434..e600570789f4 100644 --- a/arch/mips/include/asm/pgtable-32.h +++ b/arch/mips/include/asm/pgtable-32.h @@ -83,7 +83,7 @@ extern int add_temporary_entry(unsigned long entrylo0, unsigned long entrylo1, #define PGD_ORDER (__PGD_ORDER >= 0 ? __PGD_ORDER : 0) #define PUD_ORDER aieeee_attempt_to_allocate_pud -#define PMD_ORDER 1 +#define PMD_ORDER aieeee_attempt_to_allocate_pmd #define PTE_ORDER 0 #define PTRS_PER_PGD (USER_PTRS_PER_PGD * 2)