From patchwork Tue Sep 4 21:18:06 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lina Iyer X-Patchwork-Id: 10587975 X-Patchwork-Delegate: agross@codeaurora.org Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 34B6414E0 for ; Tue, 4 Sep 2018 21:18:59 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 237592A122 for ; Tue, 4 Sep 2018 21:18:59 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 161792A127; Tue, 4 Sep 2018 21:18:59 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 83EA32A122 for ; Tue, 4 Sep 2018 21:18:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727222AbeIEBpW (ORCPT ); Tue, 4 Sep 2018 21:45:22 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:50604 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726234AbeIEBpU (ORCPT ); Tue, 4 Sep 2018 21:45:20 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id AF7A560711; Tue, 4 Sep 2018 21:18:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1536095905; bh=VPIbRcMD/Lowf2hJ56+ZXNnRkH9gGZG9JvwH+BG80Rw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=PQeHKF5/z77LwBUgCNTXYUrdf43cphaCRHiemwSVOeRsTBufqz3qqhK7PCnGGj9WV eGFC5cUfCIKrO9ndThqH1bccEzAaykyPpNMOaEHlOGs8/O2TRWoVRK9YeYrkIym1Gb M4z9tDWREdqOOV7LRUKsnVdVbcavLOVmO9TFGrzw= Received: from codeaurora.org (i-global254.qualcomm.com [199.106.103.254]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: ilina@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id BF15C60711; Tue, 4 Sep 2018 21:18:23 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1536095904; bh=VPIbRcMD/Lowf2hJ56+ZXNnRkH9gGZG9JvwH+BG80Rw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=mvdNOhfRG6Vd+jlROLsjo3pZzizuPrIcFkMAjI9Kjbanv5MPVGkPCQLMLYhgbf+Go oWQJ4ZrnMXR7/caQQ7jNNB1GXgfh2T26eSZuuKw+PPLAd6rlp6fTLaiedMdCSBpAES Gd04f/Cj4fi6VSmLGLgQ35YS+2c1JrXu6rW+2gF0= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org BF15C60711 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=ilina@codeaurora.org From: Lina Iyer To: marc.zyngier@arm.com, bjorn.andersson@linaro.org, sboyd@kernel.org, evgreen@chromium.org, linus.walleij@linaro.org Cc: rplsssn@codeaurora.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, rnayak@codeaurora.org, devicetree@vger.kernel.org, andy.gross@linaro.org, dianders@chromium.org, Lina Iyer Subject: [PATCH v3 1/5] drivers: pinctrl: qcom: add wakeup capability to GPIO Date: Tue, 4 Sep 2018 15:18:06 -0600 Message-Id: <20180904211810.5506-2-ilina@codeaurora.org> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20180904211810.5506-1-ilina@codeaurora.org> References: <20180904211810.5506-1-ilina@codeaurora.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP QCOM SoC's that have Power Domain Controller (PDC) chip in the always-on domain can wakeup the SoC, when interrupts and GPIOs are routed to its interrupt controller. Only select GPIOs that are deemed wakeup capable are routed to specific PDC pins. During low power state, the pinmux interrupt controller may be non-functional but the PDC would be. The PDC can detect the wakeup GPIO is triggered and bring the TLMM to an operational state. Interrupts that are level triggered will be detected at the TLMM when the controller becomes operational. Edge interrupts however need to be replayed again. Request the corresponding PDC IRQ, when the GPIO is requested as an IRQ, but keep it disabled. During suspend, we can enable the PDC IRQ instead of the GPIO IRQ, which may or not be detected. Signed-off-by: Lina Iyer --- Changes in v3: - free action->name Changes in v2: - Remove IRQF_NO_SUSPEND and IRQF_ONE_SHOT from PDC IRQ Changes in v1: - Trigger GPIO in h/w from PDC IRQ handler - Avoid big tables for GPIO-PDC map, pick from DT instead - Use handler_data --- drivers/pinctrl/qcom/pinctrl-msm.c | 98 ++++++++++++++++++++++++++++++ 1 file changed, 98 insertions(+) diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinctrl-msm.c index 0e22f52b2a19..6527a0a9edd1 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm.c +++ b/drivers/pinctrl/qcom/pinctrl-msm.c @@ -687,11 +687,15 @@ static int msm_gpio_irq_set_type(struct irq_data *d, unsigned int type) const struct msm_pingroup *g; unsigned long flags; u32 val; + struct irq_data *pdc_irqd = irq_get_handler_data(d->irq); g = &pctrl->soc->groups[d->hwirq]; raw_spin_lock_irqsave(&pctrl->lock, flags); + if (pdc_irqd) + irq_set_irq_type(pdc_irqd->irq, type); + /* * For hw without possibility of detecting both edges */ @@ -779,9 +783,13 @@ static int msm_gpio_irq_set_wake(struct irq_data *d, unsigned int on) struct gpio_chip *gc = irq_data_get_irq_chip_data(d); struct msm_pinctrl *pctrl = gpiochip_get_data(gc); unsigned long flags; + struct irq_data *pdc_irqd = irq_get_handler_data(d->irq); raw_spin_lock_irqsave(&pctrl->lock, flags); + if (pdc_irqd) + irq_set_irq_wake(pdc_irqd->irq, on); + irq_set_irq_wake(pctrl->irq, on); raw_spin_unlock_irqrestore(&pctrl->lock, flags); @@ -863,6 +871,94 @@ static bool msm_gpio_needs_valid_mask(struct msm_pinctrl *pctrl) return device_property_read_u16_array(pctrl->dev, "gpios", NULL, 0) > 0; } +static irqreturn_t wake_irq_gpio_handler(int irq, void *data) +{ + struct irq_data *irqd = data; + struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd); + struct msm_pinctrl *pctrl = gpiochip_get_data(gc); + const struct msm_pingroup *g; + unsigned long flags; + u32 val; + + if (!irqd_is_level_type(irqd)) { + g = &pctrl->soc->groups[irqd->hwirq]; + raw_spin_lock_irqsave(&pctrl->lock, flags); + val = BIT(g->intr_status_bit); + writel(val, pctrl->regs + g->intr_status_reg); + raw_spin_unlock_irqrestore(&pctrl->lock, flags); + } + + return IRQ_HANDLED; +} + +static int msm_gpio_pdc_pin_request(struct irq_data *d) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + struct msm_pinctrl *pctrl = gpiochip_get_data(gc); + struct platform_device *pdev = to_platform_device(pctrl->dev); + const char *pin_name; + int irq; + int ret; + + pin_name = kasprintf(GFP_KERNEL, "gpio%lu", d->hwirq); + if (!pin_name) + return -ENOMEM; + + irq = platform_get_irq_byname(pdev, pin_name); + if (irq < 0) { + kfree(pin_name); + return 0; + } + + ret = request_irq(irq, wake_irq_gpio_handler, irqd_get_trigger_type(d), + pin_name, d); + if (ret) { + pr_warn("GPIO-%lu could not be set up as wakeup", d->hwirq); + kfree(pin_name); + return ret; + } + + irq_set_handler_data(d->irq, irq_get_irq_data(irq)); + disable_irq(irq); + + return 0; +} + +static int msm_gpio_pdc_pin_release(struct irq_data *d) +{ + struct irq_data *pdc_irqd = irq_get_handler_data(d->irq); + const void *name; + + if (pdc_irqd) { + irq_set_handler_data(d->irq, NULL); + name = free_irq(pdc_irqd->irq, d); + kfree(name); + } + + return 0; +} + +static int msm_gpio_irq_reqres(struct irq_data *d) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + + if (gpiochip_lock_as_irq(gc, irqd_to_hwirq(d))) { + dev_err(gc->parent, "unable to lock HW IRQ %lu for IRQ\n", + irqd_to_hwirq(d)); + return -EINVAL; + } + + return msm_gpio_pdc_pin_request(d); +} + +static void msm_gpio_irq_relres(struct irq_data *d) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + + msm_gpio_pdc_pin_release(d); + gpiochip_unlock_as_irq(gc, irqd_to_hwirq(d)); +} + static int msm_gpio_init(struct msm_pinctrl *pctrl) { struct gpio_chip *chip; @@ -887,6 +983,8 @@ static int msm_gpio_init(struct msm_pinctrl *pctrl) pctrl->irq_chip.irq_ack = msm_gpio_irq_ack; pctrl->irq_chip.irq_set_type = msm_gpio_irq_set_type; pctrl->irq_chip.irq_set_wake = msm_gpio_irq_set_wake; + pctrl->irq_chip.irq_request_resources = msm_gpio_irq_reqres; + pctrl->irq_chip.irq_release_resources = msm_gpio_irq_relres; ret = gpiochip_add_data(&pctrl->chip, pctrl); if (ret) { From patchwork Tue Sep 4 21:18:07 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lina Iyer X-Patchwork-Id: 10587973 X-Patchwork-Delegate: agross@codeaurora.org Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id C19CC175A for ; Tue, 4 Sep 2018 21:18:49 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id B22DC2A122 for ; Tue, 4 Sep 2018 21:18:49 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id A68702A12C; Tue, 4 Sep 2018 21:18:49 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 2AC802A124 for ; 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Tue, 4 Sep 2018 21:18:24 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1536095906; bh=IOlpyNDVhqTigHq264rg37LX/z4cmS2A8yYTWebqILY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ei8O880dxT6YHRnTEDKF5rKjpksFIrKTOvU93v5BSk77n+xBepVepZgLCk7Nb2Czz sfxW32DPcnkVp6kjxmHCs9BKHvd719agHNjDJGipepar5+CnoFuE8BLHtf8pMYYoqU owpBw4zjJSjEilHM2zT4x3qQrkb+FlZE6zIOcxEA= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 077CB607F7 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=ilina@codeaurora.org From: Lina Iyer To: marc.zyngier@arm.com, bjorn.andersson@linaro.org, sboyd@kernel.org, evgreen@chromium.org, linus.walleij@linaro.org Cc: rplsssn@codeaurora.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, rnayak@codeaurora.org, devicetree@vger.kernel.org, andy.gross@linaro.org, dianders@chromium.org, Lina Iyer Subject: [PATCH v3 2/5] dt-bindings: pinctrl: add wakeup capable GPIOs for SDM845 Date: Tue, 4 Sep 2018 15:18:07 -0600 Message-Id: <20180904211810.5506-3-ilina@codeaurora.org> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20180904211810.5506-1-ilina@codeaurora.org> References: <20180904211810.5506-1-ilina@codeaurora.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Update the documentation to use interrupts-extended format for specifying the TLMM summary IRQ line that is requested from GIC and the PDC interrupts corresponding to the wakeup capable GPIOs. Update the example to show PDC interrupts for the wakeup capable GPIOs for SDM845. Cc: devicetree@vger.kernel.org Signed-off-by: Lina Iyer --- Changes in v2: - Fix PDC IRQ number in example - Describe IRQ trigger type in example --- .../bindings/pinctrl/qcom,sdm845-pinctrl.txt | 104 +++++++++++++++++- 1 file changed, 101 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sdm845-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/qcom,sdm845-pinctrl.txt index 665aadb5ea28..c96417b291d1 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,sdm845-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sdm845-pinctrl.txt @@ -13,10 +13,21 @@ SDM845 platform. Value type: Definition: the base address and size of the TLMM register space. -- interrupts: +- interrupts-extended: Usage: required Value type: - Definition: should specify the TLMM summary IRQ. + Definition: should specify the TLMM summary IRQ as the first + interrupt. Optionally, wake up capable GPIOs may list + their corresponding PDC interrupts here. + +- interrupt-names: + Usage: required + Value type: + Definition: the names matching the interrupt definition in the + interrupts-extended property. The first interrupt name + must be "summary-irq" for the TLMM summary IRQ. PDC + interrupts must be described by "gpioN", where N is the + GPIO line corresponding to the PDC IRQ. - interrupt-controller: Usage: required @@ -155,11 +166,98 @@ Example: tlmm: pinctrl@3400000 { compatible = "qcom,sdm845-pinctrl"; reg = <0x03400000 0xc00000>; - interrupts = ; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; + interrupts-extended = + <&intc GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 30 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 31 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 32 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 33 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 34 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 35 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 36 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 37 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 38 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 39 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 41 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 42 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 43 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 44 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 45 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 46 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 47 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 49 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 50 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 51 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 52 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 54 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 55 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 56 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 57 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 58 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 59 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 60 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 61 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 62 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 63 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 64 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 65 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 66 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 67 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 68 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 69 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 70 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 71 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 72 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 73 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 74 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 75 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 76 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 77 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 79 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 80 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 81 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 82 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 83 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 84 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 85 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 86 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 90 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 91 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 92 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 95 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 96 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 97 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 98 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 99 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 100 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 102 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 103 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 104 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 105 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 106 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 107 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 108 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "summary-irq", + "gpio1", "gpio3", "gpio5", "gpio10", "gpio11", + "gpio20", "gpio22", "gpio24", "gpio26", "gpio30", + "gpio32", "gpio34", "gpio36", "gpio37", "gpio38", + "gpio39", "gpio40", "gpio43", "gpio44", "gpio46", + "gpio48", "gpio52", "gpio53", "gpio54", "gpio56", + "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", + "gpio62", "gpio63", "gpio64", "gpio66", "gpio68", + "gpio71", "gpio73", "gpio77", "gpio78", "gpio79", + "gpio80", "gpio84", "gpio85", "gpio86", "gpio88", + "gpio91", "gpio92", "gpio95", "gpio96", "gpio97", + "gpio101", "gpio103", "gpio104", "gpio115", "gpio116", + "gpio117", "gpio118", "gpio119", "gpio120", "gpio121", + "gpio122", "gpio123", "gpio124", "gpio125", "gpio127", + "gpio128", "gpio129", "gpio130", "gpio132", "gpio133", + "gpio145", "gpio41", "gpio89", "gpio31", "gpio49", + "gpio41", "gpio89", "gpio31", "gpio49"; qup9_active: qup9-active { mux { From patchwork Tue Sep 4 21:18:08 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lina Iyer X-Patchwork-Id: 10587971 X-Patchwork-Delegate: agross@codeaurora.org Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id A7E9F920 for ; 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b=mM+LnKp0Pt8wVudaC8aIi3RRRboAiS0kPXxOPKZLm/ez9qtMG3pFjeniHu+R8jgby +CTlzxcz5/5RqzRvHkMujeO4D/nP18+88G/TqVqFBdCOtzU/H4nb0GX30d2EKnD/2Z 2PFcsKQPUYi2NEJDDxLFafVSTZx0gjs4HpzqvgI0= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 4E9DB608BF Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=ilina@codeaurora.org From: Lina Iyer To: marc.zyngier@arm.com, bjorn.andersson@linaro.org, sboyd@kernel.org, evgreen@chromium.org, linus.walleij@linaro.org Cc: rplsssn@codeaurora.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, rnayak@codeaurora.org, devicetree@vger.kernel.org, andy.gross@linaro.org, dianders@chromium.org, Lina Iyer Subject: [PATCH v3 3/5] drivers: pinctrl: msm: enable PDC interrupt only during suspend Date: Tue, 4 Sep 2018 15:18:08 -0600 Message-Id: <20180904211810.5506-4-ilina@codeaurora.org> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20180904211810.5506-1-ilina@codeaurora.org> References: <20180904211810.5506-1-ilina@codeaurora.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP During suspend the system may power down some of the system rails. As a result, the TLMM hw block may not be operational anymore and wakeup capable GPIOs will not be detected. The PDC however will be operational and the GPIOs that are routed to the PDC as IRQs can wake the system up. To avoid being interrupted twice (for TLMM and once for PDC IRQ) when a GPIO trips, use TLMM for active and switch to PDC for suspend. When entering suspend, disable the TLMM wakeup interrupt and instead enable the PDC IRQ and revert upon resume. Signed-off-by: Lina Iyer --- Changes in v3: - Enable PDC-IRQ swap only for edge interrupts Changes in v2: - Fix PDC IRQ max port, 126 is the max supported in h/w - Use PDC hwirq in bitmap, linux numbers could be large - Setup DISABLE_UNLAZY for both TLMM and PDC IRQs --- drivers/pinctrl/qcom/pinctrl-msm.c | 73 +++++++++++++++++++++++++++++- drivers/pinctrl/qcom/pinctrl-msm.h | 3 ++ 2 files changed, 75 insertions(+), 1 deletion(-) diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinctrl-msm.c index 6527a0a9edd1..01a455f86fcd 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm.c +++ b/drivers/pinctrl/qcom/pinctrl-msm.c @@ -37,6 +37,7 @@ #include "../pinctrl-utils.h" #define MAX_NR_GPIO 300 +#define MAX_PDC_HWIRQ 126 #define PS_HOLD_OFFSET 0x820 /** @@ -51,6 +52,7 @@ * @enabled_irqs: Bitmap of currently enabled irqs. * @dual_edge_irqs: Bitmap of irqs that need sw emulated dual edge * detection. + * @pdc_hwirqs: Bitmap of wakeup capable irqs. * @soc; Reference to soc_data of platform specific data. * @regs: Base address for the TLMM register map. */ @@ -68,11 +70,15 @@ struct msm_pinctrl { DECLARE_BITMAP(dual_edge_irqs, MAX_NR_GPIO); DECLARE_BITMAP(enabled_irqs, MAX_NR_GPIO); + DECLARE_BITMAP(pdc_hwirqs, MAX_PDC_HWIRQ); const struct msm_pinctrl_soc_data *soc; void __iomem *regs; + struct irq_domain *pdc_irq_domain; }; +static bool in_suspend; + static int msm_get_groups_count(struct pinctrl_dev *pctldev) { struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); @@ -787,8 +793,13 @@ static int msm_gpio_irq_set_wake(struct irq_data *d, unsigned int on) raw_spin_lock_irqsave(&pctrl->lock, flags); - if (pdc_irqd) + if (pdc_irqd && !in_suspend) { irq_set_irq_wake(pdc_irqd->irq, on); + if (on) + set_bit(pdc_irqd->hwirq, pctrl->pdc_hwirqs); + else + clear_bit(pdc_irqd->hwirq, pctrl->pdc_hwirqs); + } irq_set_irq_wake(pctrl->irq, on); @@ -919,7 +930,12 @@ static int msm_gpio_pdc_pin_request(struct irq_data *d) } irq_set_handler_data(d->irq, irq_get_irq_data(irq)); + irq_set_handler_data(irq, d); + irq_set_status_flags(irq, IRQ_DISABLE_UNLAZY); + irq_set_status_flags(d->irq, IRQ_DISABLE_UNLAZY); disable_irq(irq); + if (!pctrl->pdc_irq_domain) + pctrl->pdc_irq_domain = irq_get_irq_data(irq)->domain; return 0; } @@ -1071,6 +1087,61 @@ static void msm_pinctrl_setup_pm_reset(struct msm_pinctrl *pctrl) } } +int __maybe_unused msm_pinctrl_suspend_late(struct device *dev) +{ + struct msm_pinctrl *pctrl = dev_get_drvdata(dev); + struct irq_data *irqd; + unsigned int irq; + int i; + + in_suspend = true; + for_each_set_bit(i, pctrl->pdc_hwirqs, MAX_PDC_HWIRQ) { + irq = irq_find_mapping(pctrl->pdc_irq_domain, i); + irqd = irq_get_handler_data(irq); + /* + * We don't know if the TLMM will be functional + * or not, during the suspend. If its functional, + * we do not want duplicate interrupts from PDC. + * Hence disable the GPIO IRQ and enable PDC IRQ + * for edge interrupt only. + */ + if (irqd_is_wakeup_set(irqd) && !irqd_is_level_type(irqd)) { + disable_irq_wake(irqd->irq); + disable_irq(irqd->irq); + enable_irq(irq); + } + } + + return 0; +} + +int __maybe_unused msm_pinctrl_resume_late(struct device *dev) +{ + struct msm_pinctrl *pctrl = dev_get_drvdata(dev); + struct irq_data *irqd, *pdc_irqd; + unsigned int irq; + int i; + + for_each_set_bit(i, pctrl->pdc_hwirqs, MAX_PDC_HWIRQ) { + irq = irq_find_mapping(pctrl->pdc_irq_domain, i); + irqd = irq_get_handler_data(irq); + pdc_irqd = irq_get_irq_data(irq); + /* + * The TLMM will be operational now, so disable + * the PDC IRQ for edge interrupts only. + */ + if (irqd_is_wakeup_set(pdc_irqd) && + !irqd_is_level_type(pdc_irqd)) { + disable_irq_nosync(irq); + enable_irq_wake(irqd->irq); + enable_irq(irqd->irq); + } + } + in_suspend = false; + + return 0; +} + int msm_pinctrl_probe(struct platform_device *pdev, const struct msm_pinctrl_soc_data *soc_data) { diff --git a/drivers/pinctrl/qcom/pinctrl-msm.h b/drivers/pinctrl/qcom/pinctrl-msm.h index 9b9feea540ff..21b56fb5dae9 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm.h +++ b/drivers/pinctrl/qcom/pinctrl-msm.h @@ -123,4 +123,7 @@ int msm_pinctrl_probe(struct platform_device *pdev, const struct msm_pinctrl_soc_data *soc_data); int msm_pinctrl_remove(struct platform_device *pdev); +int msm_pinctrl_suspend_late(struct device *dev); +int msm_pinctrl_resume_late(struct device *dev); + #endif From patchwork Tue Sep 4 21:18:09 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lina Iyer X-Patchwork-Id: 10587967 X-Patchwork-Delegate: agross@codeaurora.org Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 9CD4D920 for ; Tue, 4 Sep 2018 21:18:32 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 8D2D12A122 for ; Tue, 4 Sep 2018 21:18:32 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 80C262A127; Tue, 4 Sep 2018 21:18:32 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 1AA882A122 for ; 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Tue, 4 Sep 2018 21:18:27 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1536095908; bh=JJLAku1WEJzIGgkft3WYFW22LPq0PqPXFU9Kz0wRJhA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=oZfC8g66pBlSZRvccsugIuDdDbBKD3TXKhrJi/8Zafo3nLSm4T2xMtsBb/wj9F5Fm Ua+ol989UrYzXud6NhBHljnso+1fLfX/n/L00HkOYN+5CeMniz0IDIFeNzfNxyMeiB I3LPwK3P4r+B5a7fzbWdWRyEwL7YiARa6ig0ebcs= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 8D5F160997 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=ilina@codeaurora.org From: Lina Iyer To: marc.zyngier@arm.com, bjorn.andersson@linaro.org, sboyd@kernel.org, evgreen@chromium.org, linus.walleij@linaro.org Cc: rplsssn@codeaurora.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, rnayak@codeaurora.org, devicetree@vger.kernel.org, andy.gross@linaro.org, dianders@chromium.org, Lina Iyer Subject: [PATCH v3 4/5] drivers: pinctrl: qcom: sdm845: support GPIO wakeup from suspend Date: Tue, 4 Sep 2018 15:18:09 -0600 Message-Id: <20180904211810.5506-5-ilina@codeaurora.org> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20180904211810.5506-1-ilina@codeaurora.org> References: <20180904211810.5506-1-ilina@codeaurora.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Enable TLMM IRQs to be sensed by PDC when we enter suspend. It is possible that the TLMM may be powered off and not detect GPIOs that are configured as wake up interrupts. By hooking into suspend callbacks, we allow PDC IRQs to take over and wake up the system if wakeup interrupts are triggered. Signed-off-by: Lina Iyer --- Changes in v3: - Move the common suspend ops definition to pinctrl-msm.c --- drivers/pinctrl/qcom/pinctrl-msm.c | 5 +++++ drivers/pinctrl/qcom/pinctrl-msm.h | 2 ++ drivers/pinctrl/qcom/pinctrl-sdm845.c | 1 + 3 files changed, 8 insertions(+) diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinctrl-msm.c index 01a455f86fcd..92887c075230 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm.c +++ b/drivers/pinctrl/qcom/pinctrl-msm.c @@ -1142,6 +1142,11 @@ int __maybe_unused msm_pinctrl_resume_late(struct device *dev) return 0; } +const struct dev_pm_ops msm_pinctrl_dev_pm_ops = { + SET_LATE_SYSTEM_SLEEP_PM_OPS(msm_pinctrl_suspend_late, + msm_pinctrl_resume_late) +}; + int msm_pinctrl_probe(struct platform_device *pdev, const struct msm_pinctrl_soc_data *soc_data) { diff --git a/drivers/pinctrl/qcom/pinctrl-msm.h b/drivers/pinctrl/qcom/pinctrl-msm.h index 21b56fb5dae9..9be1baa878a3 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm.h +++ b/drivers/pinctrl/qcom/pinctrl-msm.h @@ -126,4 +126,6 @@ int msm_pinctrl_remove(struct platform_device *pdev); int msm_pinctrl_suspend_late(struct device *dev); int msm_pinctrl_resume_late(struct device *dev); +extern const struct dev_pm_ops msm_pinctrl_dev_pm_ops; + #endif diff --git a/drivers/pinctrl/qcom/pinctrl-sdm845.c b/drivers/pinctrl/qcom/pinctrl-sdm845.c index 2ab7a8885757..0c82dc403268 100644 --- a/drivers/pinctrl/qcom/pinctrl-sdm845.c +++ b/drivers/pinctrl/qcom/pinctrl-sdm845.c @@ -1301,6 +1301,7 @@ static struct platform_driver sdm845_pinctrl_driver = { .driver = { .name = "sdm845-pinctrl", .of_match_table = sdm845_pinctrl_of_match, + .pm = &msm_pinctrl_dev_pm_ops, }, .probe = sdm845_pinctrl_probe, .remove = msm_pinctrl_remove, From patchwork Tue Sep 4 21:18:10 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lina Iyer X-Patchwork-Id: 10587969 X-Patchwork-Delegate: agross@codeaurora.org Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 71B26920 for ; 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b=iUaJCxjFlxJEQrSau/g2WEHXkkg1cWp0znSg4ffr+oI+R03RepSBseDQTmZSm+8qk 4XTJxCU4Tw2McSdOK3siZ1LnT4h/g+URA6mkjp72Nh1MTPtcUwYXJ2G45po/HDYx/9 jb35vhVOr2v7SEEWpS2Yb1JxLRX7OH+RTVjyhNP0= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org CE085607DC Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=ilina@codeaurora.org From: Lina Iyer To: marc.zyngier@arm.com, bjorn.andersson@linaro.org, sboyd@kernel.org, evgreen@chromium.org, linus.walleij@linaro.org Cc: rplsssn@codeaurora.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, rnayak@codeaurora.org, devicetree@vger.kernel.org, andy.gross@linaro.org, dianders@chromium.org, Lina Iyer Subject: [PATCH v3 5/5] arm64: dts: qcom: add wake up interrupts for GPIOs for SDM845 Date: Tue, 4 Sep 2018 15:18:10 -0600 Message-Id: <20180904211810.5506-6-ilina@codeaurora.org> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20180904211810.5506-1-ilina@codeaurora.org> References: <20180904211810.5506-1-ilina@codeaurora.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP GPIOs that are wakeup capable have interrupt lines that are routed to the always-on interrupt controller (PDC) in parallel to the pinctrl. The interrupts listed here are the wake up lines corresponding to GPIOs. Signed-off-by: Lina Iyer Reviewed-by: Rob Herring --- Changes in v2: - Define IRQ trigger type in DT Changes in v1: - Use interrupt-extended for all TLMM interrupts - Define GPIO-PDC map using interrupt-names --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 152 ++++++++++++++++++++++++++- 1 file changed, 151 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 0208f8557ffa..8d87794092b0 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -712,11 +712,161 @@ tlmm: pinctrl@3400000 { compatible = "qcom,sdm845-pinctrl"; reg = <0x03400000 0xc00000>; - interrupts = ; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; + interrupts-extended = + <&intc GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 30 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 31 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 32 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 33 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 34 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 35 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 36 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 37 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 38 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 39 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 41 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 42 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 43 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 44 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 45 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 46 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 47 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 49 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 50 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 51 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 52 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 54 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 55 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 56 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 57 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 58 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 59 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 60 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 61 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 62 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 63 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 64 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 65 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 66 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 67 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 68 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 69 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 70 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 71 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 72 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 73 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 74 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 75 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 76 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 77 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 79 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 80 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 81 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 82 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 83 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 84 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 85 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 86 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 90 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 91 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 92 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 95 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 96 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 97 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 98 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 99 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 100 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 102 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 103 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 104 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 105 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 106 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 107 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 108 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "summary-irq", + "gpio1", + "gpio3", + "gpio5", + "gpio10", + "gpio11", + "gpio20", + "gpio22", + "gpio24", + "gpio26", + "gpio30", + "gpio32", + "gpio34", + "gpio36", + "gpio37", + "gpio38", + "gpio39", + "gpio40", + "gpio43", + "gpio44", + "gpio46", + "gpio48", + "gpio52", + "gpio53", + "gpio54", + "gpio56", + "gpio57", + "gpio58", + "gpio59", + "gpio60", + "gpio61", + "gpio62", + "gpio63", + "gpio64", + "gpio66", + "gpio68", + "gpio71", + "gpio73", + "gpio77", + "gpio78", + "gpio79", + "gpio80", + "gpio84", + "gpio85", + "gpio86", + "gpio88", + "gpio91", + "gpio92", + "gpio95", + "gpio96", + "gpio97", + "gpio101", + "gpio103", + "gpio104", + "gpio115", + "gpio116", + "gpio117", + "gpio118", + "gpio119", + "gpio120", + "gpio121", + "gpio122", + "gpio123", + "gpio124", + "gpio125", + "gpio127", + "gpio128", + "gpio129", + "gpio130", + "gpio132", + "gpio133", + "gpio145", + "gpio41", + "gpio89", + "gpio31", + "gpio49", + "gpio41", + "gpio89", + "gpio31", + "gpio49"; qup_i2c0_default: qup-i2c0-default { pinmux {